57 lines
1.6 KiB
C
Executable File
57 lines
1.6 KiB
C
Executable File
/*
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* hal_clk.c- Sigmastar
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*
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* Copyright (c) [2019~2020] SigmaStar Technology.
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*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License version 2 for more details.
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*
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*/
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#include "hal_clk.h"
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#include "hal_debug.h"
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#define RIU_BASE_ADDR (0x1F000000)
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#define BANK_CAL(addr) ((addr<<9) + (RIU_BASE_ADDR))
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#define BANK_CLK_GEN (BANK_CAL(0x100A))
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#if (HAL_MSG_LEVL < HAL_MSG_DBG)
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#define REGR(base,idx) ms_readw(((uint)base+(idx)*4))
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#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4))
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#else
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#define REGR(base,idx) ms_readw(((uint)base+(idx)*4))
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#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0)
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#endif
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/*******************************************************************************************************************
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* clk_hal_init
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* init device clock
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*
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* Parameters:
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* RIU_BASE_ADDR: clock base address
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*
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* Return:
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* 0: OK, othes: failed
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*/
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//<MStar Software>//CEVA PLL: 600MHz setting
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int ive_clk_hal_init(void)
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{
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u16 value;
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value = REGR(BANK_CLK_GEN, 0x52);
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value &= ~0xF8;
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value |= 0x80; //320 MHz
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REGW(BANK_CLK_GEN, 0x52, value);
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return 0;
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}
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