335 lines
9.5 KiB
C
Executable File
335 lines
9.5 KiB
C
Executable File
/*
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* irqchip.c- Sigmastar
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*
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* Copyright (c) [2019~2020] SigmaStar Technology.
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*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License version 2 for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/syscore_ops.h>
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#include <asm/mach/irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip.h>
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#include <linux/irqdesc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "irqs.h"
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#include "registers.h"
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#include "_ms_private.h"
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#include "ms_platform.h"
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#include "ms_types.h"
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/interrupt.h>
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/* _ _ _ _ _ _ _ _ _ _ */
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/* | | */
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/* | PM_SLEEP_IRQ(32) | */
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/* |_ _ _ _ _ _ _ _ _ _| */
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/* | | */
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/* | MS_FIQ (32) | */
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/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */
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/* | | */
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/* | MS_IRQ (64) | */
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/* |_ _ _ _ _ _ _ _ _ _| ms_irq */
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/* | | */
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/* | ARM_INTERNAL(32) | */
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/* |_ _ _ _ _ _ _ _ _ _| gic_spi */
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/* | | */
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/* | PPI (16) | */
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/* |_ _ _ _ _ _ _ _ _ _| */
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/* | | */
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/* | SGI (16) | */
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/* |_ _ _ _ _ _ _ _ _ _| */
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/* */
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static void ms_main_irq_ack(struct irq_data *d)
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{
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s16 ms_fiq;
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ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR;
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if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR )
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{
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SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) );
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}
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else if( ms_fiq >= GIC_SPI_MS_FIQ_NR )
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{
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pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq);
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return;
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}
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if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack)
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{
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irq_chip_ack_parent(d);
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}
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}
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static void ms_main_irq_eoi(struct irq_data *d)
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{
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s16 ms_fiq;
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ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR;
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if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR )
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{
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SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) );
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}
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else if( ms_fiq >= GIC_SPI_MS_FIQ_NR )
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{
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pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq);
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return;
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}
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irq_chip_eoi_parent(d);
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}
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static void ms_main_irq_mask(struct irq_data *d)
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{
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s16 ms_irq;
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s16 ms_fiq;
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ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR;
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ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR;
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pr_debug("[%s] hwirq %lu\n", __func__, d->hwirq);
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if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR )
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{
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SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) );
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}
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else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR )
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{
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SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) );
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}
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else
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{
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pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq);
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return;
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}
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irq_chip_mask_parent(d);
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}
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static void ms_main_irq_unmask(struct irq_data *d)
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{
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s16 ms_irq;
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s16 ms_fiq;
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ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR;
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ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR;
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if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR )
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{
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CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) );
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}
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else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR )
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{
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CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) );
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}
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else
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{
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pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq);
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return;
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}
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irq_chip_unmask_parent(d);
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}
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static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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s16 ms_irq;
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s16 ms_fiq;
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if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH)
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{
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pr_err("Not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type);
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return 0;
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}
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ms_irq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR;
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ms_fiq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR;
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if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR )
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{
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if (flow_type&IRQ_TYPE_EDGE_FALLING)
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SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) );
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else
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CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) );
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}
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else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR )
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{
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if (flow_type&IRQ_TYPE_LEVEL_LOW)
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SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) );
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else
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CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) );
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}
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else
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{
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pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq);
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return -EINVAL;
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}
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irq_chip_set_type_parent(data, flow_type);
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return 0;
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}
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struct irq_chip ms_main_intc_irqchip = {
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.name = "MS_MAIN_INTC",
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.irq_ack = ms_main_irq_ack,
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.irq_eoi = ms_main_irq_eoi,
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.irq_mask = ms_main_irq_mask,
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.irq_unmask = ms_main_irq_unmask,
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.irq_set_type = ms_main_irq_set_type,
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};
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EXPORT_SYMBOL(ms_main_intc_irqchip);
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static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec,
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unsigned long *hwirq, unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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unsigned int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != GIC_SPI)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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for (i = 0; i < nr_irqs; i++)
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{
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL);
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pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i);
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}
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs)
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{
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unsigned int i;
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for (i = 0; i < nr_irqs; i++) {
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struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
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irq_domain_reset_irq_data(d);
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}
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}
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struct irq_domain_ops ms_main_intc_domain_ops = {
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.translate = ms_main_intc_domain_translate,
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.alloc = ms_main_intc_domain_alloc,
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.free = ms_main_intc_domain_free,
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};
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static int ms_irqchip_suspend(void)
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{
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pr_debug("\nms_irqchip_suspend\n\n");
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return 0;
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}
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static void ms_irqchip_resume(void)
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{
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pr_debug("\nms_irqchip_resume\n\n");
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//Patch for disable bypass IRQ/FIQ
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{
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u32 bypass = 0;
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bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL);
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bypass |= GICC_DIS_BYPASS_MASK;
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OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE);
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}
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}
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struct syscore_ops ms_irq_syscore_ops = {
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.suspend = ms_irqchip_suspend,
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.resume = ms_irqchip_resume,
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};
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static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent)
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{
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struct irq_domain *parent_domain, *domain;
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if (!interrupt_parent)
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{
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pr_err("%s: %s no parent\n", __func__, np->name);
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return -ENODEV;
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}
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pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name);
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parent_domain = irq_find_host(interrupt_parent);
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if (!parent_domain)
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{
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pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name);
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return -ENXIO;
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}
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//Patch for disable bypass IRQ/FIQ
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{
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u32 bypass = 0;
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bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL);
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bypass |= GICC_DIS_BYPASS_MASK;
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OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE);
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}
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domain = irq_domain_add_hierarchy(parent_domain, 0,
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GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR,
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np, &ms_main_intc_domain_ops, NULL);
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if (!domain)
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{
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pr_err("%s: %s allocat domain fail\n", __func__, np->name);
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return -ENOMEM;
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}
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register_syscore_ops(&ms_irq_syscore_ops);
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return 0;
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}
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IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc);
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