133 lines
4.7 KiB
C
Vendored
133 lines
4.7 KiB
C
Vendored
/*
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* kernel_bdma.h- Sigmastar
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*
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* Copyright (c) [2019~2020] SigmaStar Technology.
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*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License version 2 for more details.
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*
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*/
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/***************************************************************************
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* kernel_bdma.h
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*--------------------------------------------------------------------------
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* Scope: BDMA related definitions
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*
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****************************************************************************/
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#ifndef __KERNEL_BDMA_H__
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#define __KERNEL_BDMA_H__
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#include "cam_os_wrapper.h"
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/****************************************************************************/
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/* BDMA registers */
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/****************************************************************************/
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typedef struct KeBdma_s
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{
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// 0x0
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u32 reg_ch0_trig :1;
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u32 :3;
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u32 reg_ch0_stop :1;
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u32 :3;
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u32 reg_src_tlb :1;
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u32 reg_dst_tlb :1;
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u32 :22;
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// 0x1
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u32 reg_ch0_queued :1;
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u32 reg_ch0_busy :1;
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u32 reg_ch0_int_bdma :1;
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u32 reg_ch0_done :1;
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u32 reg_ch0_result0 :1;
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u32 reg_xiu_bdma_ns :1;
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u32 :26;
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// 0x2
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u32 reg_ch0_src_sel :4;
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#define REG_BDMA_SRC_MIU_IMI_CH0 0 //16 bytes
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#define REG_BDMA_SRC_MIU_IMI_CH1 1 //16 bytes
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#define REG_BDMA_SRC_MEM_FILL 4 //4 bytes
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#define REG_BDMA_SRC_SPI 5 //8 bytes
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#define REG_BDMA_SRC_TSP_SRAM 10 //1 byte
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u32 reg_ch0_src_dw :3;
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#define REG_BDMA_DATA_DEPTH_1BYTE 0
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#define REG_BDMA_DATA_DEPTH_2BYTE 1
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#define REG_BDMA_DATA_DEPTH_4BYTE 2
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#define REG_BDMA_DATA_DEPTH_8BYTE 3
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#define REG_BDMA_DATA_DEPTH_16BYTE 4
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u32 :1;
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u32 reg_ch0_dst_sel :4;
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#define REG_BDMA_DST_MIU_IMI_CH0 0
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#define REG_BDMA_DST_MIU_IMI_CH1 1
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#define REG_BDMA_DST_PM51 6
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#define REG_BDMA_DST_SEC51 9
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#define REG_BDMA_DST_TSP_SRAM 10
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#define REG_BDMA_SDT_FSP 11 //4 byte
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u32 reg_ch0_dst_dw :3;
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u32 :17;
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// 0x3
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u32 reg_ch0_dec :1;
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u32 reg_ch0_int_en :1;
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u32 :2;
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u32 reg_ch0_cfg :4;
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u32 reg_ch0_flush_wd :4;
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u32 reg_ch0_replace_miu :4;
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#define REG_BDMA_CH0_MIU0 0
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#define REG_BDMA_CH0_MIU1 1
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#define REG_BDMA_CH0_IMI 2
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#define REG_BDMA_CH1_MIU0 0
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#define REG_BDMA_CH1_MIU1 4
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#define REG_BDMA_CH1_IMI 8
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u32 :16;
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// 0x4
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u32 reg_ch0_src_a0 :16;
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u32 :16;
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// 0x5
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u32 reg_ch0_src_a1 :16;
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u32 :16;
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// 0x6
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u32 reg_ch0_dst_a0 :16;
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u32 :16;
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// 0x7
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u32 reg_ch0_dst_a1 :16;
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u32 :16;
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// 0x8
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u32 reg_ch0_size0 :16;
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u32 :16;
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// 0x9
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u32 reg_ch0_size1 :16;
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u32 :16;
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// 0xA
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u32 reg_ch0_cmd0_low :16;
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u32 :16;
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// 0xB
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u32 reg_ch0_cmd0_high :16;
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u32 :16;
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// 0xC
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u32 reg_ch0_cmd1_low :16;
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u32 :16;
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// 0xD
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u32 reg_ch0_cmd1_high :16;
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u32 :16;
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// 0xE
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u32 reg_ch0_cmd2_low :16;
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u32 :16;
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// 0xF
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u32 reg_ch0_cmd2_high :16;
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u32 :16;
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} KeBdma_t;
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extern volatile KeBdma_t* const g_ptKeBdma0;
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extern volatile KeBdma_t* const g_ptKeBdma1;
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extern volatile KeBdma_t* const g_ptKeBdma2;
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extern volatile KeBdma_t* const g_ptKeBdma3;
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#endif // __KERNEL_BDMA_H__
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