629 lines
14 KiB
C
Executable File
629 lines
14 KiB
C
Executable File
/*
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* ms_chip.c- Sigmastar
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*
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* Copyright (c) [2019~2020] SigmaStar Technology.
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*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License version 2 for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/semaphore.h>
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//#include <linux/clk.h>
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//#include <linux/platform_device.h>
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//#include <linux/input.h>
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//#include <linux/proc_fs.h>
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//#include <linux/slab.h>
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//#include <linux/i2c.h>
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//#include <linux/module.h>
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//
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//#include <asm/pmu.h>
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//#include <asm/system_misc.h>
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//#include <asm/mach-types.h>
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//#include <asm/mach/arch.h>
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//#include <asm/memory.h>
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//#include <asm/io.h>
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//#include <asm/mach/map.h>
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//
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//#include <linux/irqchip/arm-gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <linux/dma-mapping.h>
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#include <asm/cacheflush.h>
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#include "mdrv_API_version.h"
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#include "_ms_private.h"
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#include "ms_platform.h"
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#include "ms_version.h"
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#include "registers.h"
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#define UNUSED(var) (void)((var) = (var))
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DEFINE_SEMAPHORE(PfModeSem);
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DEFINE_MUTEX(FCIE3_mutex);
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EXPORT_SYMBOL(FCIE3_mutex);
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static struct ms_chip chip_funcs;
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const struct MS_BIN_OPTION ms_image_size __attribute__ ((aligned (16))) =
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{
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{'#','I','M','G','_','S','Z','#'},
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{0,0,0,0,0,0,0,0}
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};
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const struct MS_BIN_OPTION ms_XIP_phys_addr __attribute__ ((aligned (16))) =
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{
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{'#','X','I','P','_','P','A','#'},
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{0,0,0,0,0,0,0,0}
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};
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static char NONE_platform_name[]="NONE";
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////const struct MS_BIN_OPTION ms_builtin_dtb_size __attribute__ ((aligned (16)))=
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////{
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//// {'#','D','T','B','_','S','Z','#'},
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//// {0,0,0,0,0,0,0,0}
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////};
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//
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//
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#ifdef CONFIG_SS_BUILTIN_DTB
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#define BUILTIN_DTB_SZ (64*1024)
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struct MS_BUILTIN_DTB
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{
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struct MS_BIN_OPTION ms_dtb;
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u8 content[BUILTIN_DTB_SZ];
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};
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struct MS_BUILTIN_DTB builtin_dtb __attribute__ ((aligned (16)))=
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{
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.ms_dtb={ {'#','M','S','_','D','T','B','#'}, {0,0,0,0,0,0,0,0}},
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};
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void *builtin_dtb_start=(void *)builtin_dtb.content;
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const u32 builtin_dtb_size=BUILTIN_DTB_SZ;
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#endif
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//MS_VERSION LX_VERSION =
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//{
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// {'M','V','X'},
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// MVXV_HEAD_VER,
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// MVXV_LIB_TYPE, //R = general release version
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// MVXV_CHIP_ID,
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// MVXV_CHANGELIST,
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// MVXV_COMP_ID,
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// {'#'},
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// {'X','V','M'},
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//};
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#if defined(MVXV_EXT)
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#define MVXV_V2 "MVX" MVXV_HEAD_VER MVXV_LIB_TYPE MVXV_CHIP_ID MVXV_CHANGELIST MVXV_COMP_ID MVXV_EXT "#XVM"
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#else
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#define MVXV_V2 "MVX" MVXV_HEAD_VER MVXV_LIB_TYPE MVXV_CHIP_ID MVXV_CHANGELIST MVXV_COMP_ID "#XVM"
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#endif
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const char* LX_VERSION=MVXV_V2;
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const char *ms_API_version=""KL_API_VERSION;
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void Chip_Flush_MIU_Pipe(void){
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chip_funcs.chip_flush_miu_pipe();
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}
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void Chip_Flush_Memory(void){
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chip_funcs.chip_flush_memory();
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}
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void Chip_Read_Memory(void){
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chip_funcs.chip_read_memory();
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}
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void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size)
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{
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chip_funcs.cache_flush_range_va_pa(u32VAddr,u32PAddr,u32Size);
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}
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void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size)
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{
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chip_funcs.cache_clean_range_va_pa(u32VAddr,u32PAddr,u32Size);
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}
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void Chip_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size)
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{
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chip_funcs.cache_flush_range(u32Addr,u32Size);
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}
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void Chip_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size)
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{
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chip_funcs.cache_clean_range(u32Addr,u32Size);
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}
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void Chip_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size)
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{
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chip_funcs.cache_invalidate_range(u32Addr,u32Size);
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}
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void Chip_Flush_CacheAll(void)
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{
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chip_funcs.cache_flush_all();
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}
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u64 Chip_Phys_to_MIU(u64 phys)
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{
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return chip_funcs.phys_to_miu(phys);
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}
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u64 Chip_MIU_to_Phys(u64 miu)
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{
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return chip_funcs.miu_to_phys(miu);
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}
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int Chip_Get_Device_ID(void)
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{
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return chip_funcs.chip_get_device_id();
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}
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int Chip_Get_Revision(void)
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{
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return chip_funcs.chip_get_revision();
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}
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int Chip_Cache_Outer_Is_Enabled(void)
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{
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return chip_funcs.cache_outer_is_enabled();
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}
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int Chip_Boot_Get_Dev_Type(void)
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{
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return (int)((MS_BOOT_DEV_TYPE)chip_funcs.chip_get_boot_dev_type());
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}
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char* Chip_Get_Platform_Name(void)
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{
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char *name=chip_funcs.chip_get_platform_name();
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if(name==NULL || strlen(name) > 15 )
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{
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//printk(KERN_ERR "platform name invalid!! must not be NULL & < 15 chars\n");
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BUG();
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}
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return name;
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}
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const char* Chip_Get_API_Version(void)
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{
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return chip_funcs.chip_get_API_version();
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}
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//u32 Chip_Get_Image_Size(void)
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//{
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// return (u32)(__le32_to_cpu(*((__le64 *)((void *)&ms_.args[0]))));
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//}
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////
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//u32 Chip_Get_DTB_Size(void)
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//{
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// return (u32)(__le32_to_cpu(*((__le64 *)((void *)&MS_DTB_SIZE.args[0]))));
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//}
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/*************************************
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* default chip function
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*************************************/
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static char* _default_Get_Platform_Name(void)
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{
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return NONE_platform_name;
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}
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static u64 _default_Phys_to_MIU(u64 phys)
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{
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return phys;
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}
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static u64 _default_MIU_to_Phys(u64 miu)
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{
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return miu;
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}
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static void _default_flush_miu_pipe(void)
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{
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}
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//
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static void _default_Flush_Memory(void)
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{
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#ifdef CONFIG_MS_L2X0_PATCH
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if(outer_cache.sync)
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outer_cache.sync();
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else
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#endif
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Chip_Flush_MIU_Pipe();
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}
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static void _default_Read_Memory(void)
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{
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#ifdef CONFIG_MS_L2X0_PATCH
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if(outer_cache.sync)
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outer_cache.sync();
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else
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#endif
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Chip_Flush_MIU_Pipe();
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}
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//DCACHE_FLUSH function
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#define SYSHAL_DCACHE_LINE_SIZE 32
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#define HAL_DCACHE_START_ADDRESS(_addr_) \
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(((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1))
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#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \
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(((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \
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~(SYSHAL_DCACHE_LINE_SIZE-1))
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void hal_dcache_flush(void *base , u32 asize)
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{
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register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base);
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register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize);
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for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE )
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__asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_));
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/* Drain write buffer */
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_addr_ = 0x00UL;
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__asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_));
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}
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static void _default_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size)
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{
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if(((void *) u32VAddr) == NULL)
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{
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printk("u32VAddr is invalid\n");
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return;
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}
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//Clean L1
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//dmac_map_area((void *)u32VAddr,u32Size,1);
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dma_sync_single_for_cpu(NULL, virt_to_dma(NULL, (void*)u32VAddr), u32Size, DMA_TO_DEVICE);
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#ifdef CONFIG_OUTER_CACHE
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#ifdef CONFIG_MS_L2X0_PATCH
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if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled
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#endif
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{
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//Clean L2 by Way
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outer_cache.clean_range(u32PAddr,u32PAddr + u32Size);
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}
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#endif
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#ifndef CONFIG_OUTER_CACHE
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Chip_Flush_MIU_Pipe();
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#endif
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}
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static void _default_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size)
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{
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if(((void *) u32VAddr) == NULL)
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{
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printk("u32VAddr is invalid\n");
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return;
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}
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//Clean & Invalid L1
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dmac_flush_range((void *)u32VAddr, (void *)(u32VAddr + u32Size));
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#ifdef CONFIG_OUTER_CACHE
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#ifdef CONFIG_MS_L2X0_PATCH
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if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled
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#endif
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{
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//Clean&Inv L2 by range
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outer_cache.flush_range(u32PAddr,u32PAddr + u32Size);
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}
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#endif
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#ifndef CONFIG_OUTER_CACHE
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Chip_Flush_MIU_Pipe();
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#endif
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}
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static void _default_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size)
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{
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if( u32Addr == (unsigned long) NULL )
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{
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printk("u32Addr is invalid\n");
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return;
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}
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//Clean L1 & Inv L1
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dmac_flush_range((const void *)u32Addr,(const void *)(u32Addr + u32Size));
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#ifdef CONFIG_OUTER_CACHE
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#ifdef CONFIG_MS_L2X0_PATCH
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if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled
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#endif
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{
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if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1 ))
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//Clean&Inv L2 by Way
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outer_cache.flush_all();
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else
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//Clean&Inv L2 by Range
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outer_cache.flush_range(__pa(u32Addr) , __pa(u32Addr) + u32Size);
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}
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#endif
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#ifndef CONFIG_OUTER_CACHE
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Chip_Flush_MIU_Pipe();
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#endif
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}
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static void _default_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size)
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{
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if( u32Addr ==(unsigned long) NULL )
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{
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printk("u32Addr is invalid\n");
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return;
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}
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//Clean L1
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//dmac_map_area((const void *)u32Addr,(size_t)u32Size,1);
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dma_sync_single_for_cpu(NULL, virt_to_dma(NULL, (void*)u32Addr), u32Size, DMA_TO_DEVICE);
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#ifdef CONFIG_OUTER_CACHE
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#ifdef CONFIG_MS_L2X0_PATCH
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if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled
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#endif
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{
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if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1))
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//Clean L2 by range
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outer_cache.flush_all();
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else
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//Clean&Inv L2 by Range
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outer_cache.clean_range(__pa(u32Addr) , __pa(u32Addr) + u32Size);
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}
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#endif
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#ifndef CONFIG_OUTER_CACHE
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Chip_Flush_MIU_Pipe();
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#endif
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}
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static void _default_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size)
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{
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if( u32Addr == (unsigned long) NULL )
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{
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printk("u32Addr is invalid\n");
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return;
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}
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#ifdef CONFIG_OUTER_CACHE
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#ifdef CONFIG_MS_L2X0_PATCH
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if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled
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#endif
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{
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if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1))
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{
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printk("%s:Input VA can't be converted to PA\n",__func__);
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}
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else
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{
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//Inv L2 by range
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outer_cache.inv_range(__pa(u32Addr) , __pa(u32Addr)+ u32Size);
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}
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}
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#endif
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//Inv L1
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//dmac_map_area((const void *)u32Addr,(size_t)u32Size,2);
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dma_sync_single_for_cpu(NULL, virt_to_dma(NULL, (void*)u32Addr), u32Size, DMA_FROM_DEVICE);
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}
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static void _default_Flush_CacheAll(void)
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{
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__cpuc_flush_icache_all();
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__cpuc_flush_kern_all();
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__cpuc_flush_user_all();
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#ifdef CONFIG_OUTER_CACHE
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#ifdef CONFIG_MS_L2X0_PATCH
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if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled
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#endif
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{
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//Clean&Inv L2 by range
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outer_cache.flush_all();
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}
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#endif
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#ifndef CONFIG_OUTER_CACHE
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Chip_Flush_MIU_Pipe();
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#endif
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}
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static int _default_Get_Revision(void)
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{
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return 0;
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}
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static int _default_Get_ID(void)
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{
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return (int)DEVICE_ID_END;
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}
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static int _default_Get_Boot_Dev_Type(void)
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{
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return (int)MS_BOOT_DEV_NONE;
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}
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static int _default_get_storage_type(void)
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{
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return (int)MS_STORAGE_UNKNOWN;
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}
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static int _default_get_package_type(void)
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{
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return 0;
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}
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static int _default_Outer_Cache_Is_Enabled(void)
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{
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return 0;
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}
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static unsigned long long _default_Get_RIU_Phys(void)
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{
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return 0;
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}
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static int _default_Get_RIU_Size(void)
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{
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return 0;
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}
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static int _default_chip_function_set(int id, int param)
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{
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UNUSED(id);
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UNUSED(param);
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//printk(KERN_ERR "CHIP_FUNCTION not yet implemented\n!!");
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return -1;
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}
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static const char* _default_chip_get_API_version(void)
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{
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return ms_API_version;
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}
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static u64 _default_chip_get_us_ticks(void)
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{
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return 0;
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}
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struct ms_chip* ms_chip_get(void)
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{
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return &chip_funcs;
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}
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void __init ms_chip_init_default(void)
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{
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chip_funcs.cache_clean_range=_default_Clean_Cache_Range;
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chip_funcs.cache_flush_range=_default_Flush_Cache_Range;
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chip_funcs.cache_flush_all=_default_Flush_CacheAll;
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chip_funcs.cache_invalidate_range=_default_Inv_Cache_Range;
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chip_funcs.cache_clean_range_va_pa=_default_Clean_Cache_Range_VA_PA;
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chip_funcs.cache_flush_range_va_pa=_default_Flush_Cache_Range_VA_PA;
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|
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chip_funcs.chip_flush_memory=_default_Flush_Memory;
|
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chip_funcs.chip_read_memory=_default_Read_Memory;
|
|
chip_funcs.chip_flush_miu_pipe=_default_flush_miu_pipe;
|
|
|
|
chip_funcs.phys_to_miu=_default_Phys_to_MIU;
|
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chip_funcs.miu_to_phys=_default_MIU_to_Phys;
|
|
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chip_funcs.chip_get_device_id=_default_Get_ID;
|
|
chip_funcs.chip_get_revision=_default_Get_Revision;
|
|
|
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chip_funcs.cache_outer_is_enabled=_default_Outer_Cache_Is_Enabled;
|
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|
|
chip_funcs.chip_get_boot_dev_type=_default_Get_Boot_Dev_Type;
|
|
chip_funcs.chip_get_platform_name=_default_Get_Platform_Name;
|
|
|
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chip_funcs.chip_get_riu_phys=_default_Get_RIU_Phys;
|
|
chip_funcs.chip_get_riu_size=_default_Get_RIU_Size;
|
|
|
|
chip_funcs.chip_function_set=_default_chip_function_set;
|
|
|
|
chip_funcs.chip_get_API_version=_default_chip_get_API_version;
|
|
|
|
chip_funcs.chip_get_storage_type=_default_get_storage_type;
|
|
chip_funcs.chip_get_package_type=_default_get_package_type;
|
|
|
|
chip_funcs.chip_get_us_ticks=_default_chip_get_us_ticks;
|
|
|
|
}
|
|
|
|
unsigned long long Chip_Get_RIU_Phys(void)
|
|
{
|
|
return chip_funcs.chip_get_riu_phys();
|
|
}
|
|
|
|
int Chip_Get_RIU_Size(void)
|
|
{
|
|
return chip_funcs.chip_get_riu_size();
|
|
}
|
|
|
|
|
|
int Chip_Function_Set(int function_id, int param)
|
|
{
|
|
return chip_funcs.chip_function_set(function_id,param);
|
|
}
|
|
|
|
int Chip_Get_Storage_Type(void)
|
|
{
|
|
return (int)chip_funcs.chip_get_storage_type();
|
|
}
|
|
|
|
int Chip_Get_Package_Type(void)
|
|
{
|
|
return (int)chip_funcs.chip_get_package_type();
|
|
}
|
|
|
|
u64 Chip_Get_US_Ticks(void)
|
|
{
|
|
return chip_funcs.chip_get_us_ticks();
|
|
}
|
|
|
|
EXPORT_SYMBOL(ms_chip_get);
|
|
|
|
EXPORT_SYMBOL(Chip_Flush_MIU_Pipe);
|
|
EXPORT_SYMBOL(v7_dma_flush_range);
|
|
EXPORT_SYMBOL(Chip_Flush_Memory);
|
|
EXPORT_SYMBOL(Chip_Read_Memory);
|
|
EXPORT_SYMBOL(Chip_Flush_Cache_Range_VA_PA);
|
|
EXPORT_SYMBOL(Chip_Clean_Cache_Range_VA_PA);
|
|
EXPORT_SYMBOL(Chip_Flush_Cache_Range);
|
|
EXPORT_SYMBOL(Chip_Clean_Cache_Range);
|
|
EXPORT_SYMBOL(Chip_Inv_Cache_Range);
|
|
EXPORT_SYMBOL(Chip_Flush_CacheAll);
|
|
EXPORT_SYMBOL(Chip_Phys_to_MIU);
|
|
EXPORT_SYMBOL(Chip_MIU_to_Phys);
|
|
|
|
EXPORT_SYMBOL(Chip_Cache_Outer_Is_Enabled);
|
|
|
|
EXPORT_SYMBOL(Chip_Get_Device_ID);
|
|
EXPORT_SYMBOL(Chip_Get_Revision);
|
|
EXPORT_SYMBOL(Chip_Get_Platform_Name);
|
|
EXPORT_SYMBOL(Chip_Boot_Get_Dev_Type);
|
|
EXPORT_SYMBOL(Chip_Get_Storage_Type);
|
|
EXPORT_SYMBOL(Chip_Get_Package_Type);
|
|
|
|
EXPORT_SYMBOL(Chip_Get_US_Ticks);
|
|
|
|
EXPORT_SYMBOL(Chip_Get_RIU_Phys);
|
|
EXPORT_SYMBOL(Chip_Get_RIU_Size);
|
|
EXPORT_SYMBOL(Chip_Function_Set);
|
|
|
|
|
|
|
|
|
|
|