388 lines
11 KiB
C
Vendored
388 lines
11 KiB
C
Vendored
/*
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* platform.h- Sigmastar
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*
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* Copyright (C) 2018 Sigmastar Technology Corp.
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*
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* Author: jiang.ann <jiang.ann@sigmastar.com.tw>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __PLATFORM_H__
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#define __PLATFORM_H__
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#define USBHOST_LIB_VER "2018.01.12"
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#include "MsTypes_usb.h"
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/* Select a OS Platform */
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//#define SERET_ENV
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#define MSTAR_UBOOT_ENV
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/* General Setting for Mstar Platform USB Portting */
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//#ifdef SERET_ENV
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//#define CONFIG_USB_STORAGE 1
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//#define USB_BAD_DEVICE_RETRY_PATCH 1
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/* normal 1 + additional N */
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//#define USB_BAD_DEV_MAX_RETRY 2
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//#endif
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#define USB_WAIT_LOOP_COUNT 0 // for super speed device
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/* USB Test Mode */
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// #define USB_TEST
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#define USB_LEGEND_DATA_TOGGLE_METHOD
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/****** Chip variable setting ******/
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#if 1 /* Every Mstar chip should appley it */
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#define _USB_FLUSH_BUFFER 1
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#else
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#define _USB_FLUSH_BUFFER 0
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#endif
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//------ Hardware ECO enable switch ----------------------------------
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//---- 1. cross point
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#if 0 // every chip must enable it manually
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#else
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#define ENABLE_LS_CROSS_POINT_ECO
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#define LS_CROSS_POINT_ECO_OFFSET (0x04*2)
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#define LS_CROSS_POINT_ECO_BITSET MS_BIT6
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#endif
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//---- 2. power noise
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#if 0 // every chip must enable it manually
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#else
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#define ENABLE_PWR_NOISE_ECO
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#endif
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//---- 3. tx/rx reset clock gating cause XIU timeout
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#if 0 // every chip must enable it manually
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#else
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#define ENABLE_TX_RX_RESET_CLK_GATING_ECO
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#define TX_RX_RESET_CLK_GATING_ECO_OFFSET (0x04*2)
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#define TX_RX_RESET_CLK_GATING_ECO_BITSET MS_BIT5
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#endif
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//---- 4. short packet lose interrupt without IOC
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#if 0
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#define ENABLE_LOSS_SHORT_PACKET_INTR_ECO
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#define LOSS_SHORT_PACKET_INTR_ECO_OPOR
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#define LOSS_SHORT_PACKET_INTR_ECO_OFFSET (0x04*2)
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#define LOSS_SHORT_PACKET_INTR_ECO_BITSET BIT7
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#endif
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//---- 5. babble avoidance
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#if 0
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#define ENABLE_BABBLE_ECO
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#endif
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//---- 6. lose packet in MDATA condition
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#if 0
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#define MDATA_ECO_OFFSET (0x0F*2-1)
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#define MDATA_ECO_BITSET BIT4
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#endif
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//---- 7. change override to hs_txser_en condition (DM always keep high issue)
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#if 0
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#define ENABLE_HS_DM_KEEP_HIGH_ECO
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#endif
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//---- 8. fix pv2mi bridge mis-behavior
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#if 1 /* Every Mstar chip should appley it */
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#define ENABLE_PV2MI_BRIDGE_ECO
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#endif
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//---- 9. change to 55 interface
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#if 1 /* Every Mstar chip should appley it */
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#define ENABLE_UTMI_55_INTERFACE
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#endif
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//---- 10. 240's phase as 120's clock
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#if 1 /* Every Mstar chip should appley it */
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/* bit<3> for 240's phase as 120's clock set 1, bit<4> for 240Mhz in mac 0 for faraday 1 for etron */
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#define ENABLE_UTMI_240_AS_120_PHASE_ECO
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//#define UTMI_240_AS_120_PHASE_ECO_INV
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#endif
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//---- 11. double date rate (480MHz)
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//#define ENABLE_DOUBLE_DATARATE_SETTING
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//---- 12. UPLL setting, normally it should be done in sboot
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//#define ENABLE_UPLL_SETTING
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//---- 13. chip top performance tuning
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//#define ENABLE_CHIPTOP_PERFORMANCE_SETTING
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//---- 14. HS connection fail problem (Gate into VFALL state)
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#define ENABLE_HS_CONNECTION_FAIL_INTO_VFALL_ECO
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//---- 15. Enable UHC Preamble ECO function
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#define ENABLE_UHC_PREAMBLE_ECO
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//---- 16. Don't close RUN bit when device disconnect
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#define ENABLE_UHC_RUN_BIT_ALWAYS_ON_ECO
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//---- 18. Extra HS SOF after bus reset
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#define ENABLE_UHC_EXTRA_HS_SOF_ECO
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//---- 19. Not yet support MIU lower bound address subtraction ECO (for chips which use ENABLE_USB_NEW_MIU_SLE)
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//#define DISABLE_MIU_LOW_BOUND_ADDR_SUBTRACT_ECO
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//---- 20. UHC speed type report should be reset by device disconnection
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#define ENABLE_DISCONNECT_SPEED_REPORT_RESET_ECO
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//---- 21. Port Change Detect (PCD) is triggered by babble. Pulse trigger will not hang this condition.
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/* 1'b0: level trigger
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* 1'b1: one-pulse trigger
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*/
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#define ENABLE_BABBLE_PCD_ONE_PULSE_TRIGGER_ECO
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//---- 22. generation of hhc_reset_u
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/* 1'b0: hhc_reset is_u double sync of hhc_reset
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* 1'b1: hhc_reset_u is one-pulse of hhc_reset
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*/
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#define ENABLE_HC_RESET_FAIL_ECO
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//---- 23. EHCI keeps running when device is disconnected
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//#define ENABLE_DISCONNECT_HC_KEEP_RUNNING_ECO
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//---- 24. Chirp patch use software overwrite value
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/* reg_sw_chirp_override_bit set to 0 */
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#define DISABLE_NEW_HW_CHRIP_ECO
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//--------------------------------------------------------------------
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//------ Software patch enable switch --------------------------------
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//---- 1. flush MIU pipe
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#if 0 // every chip must apply it
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#define _USB_T3_WBTIMEOUT_PATCH 0
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#else
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#define _USB_T3_WBTIMEOUT_PATCH 1
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#endif
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//---- 2. data structure (qtd ,...) must be 128-byte aligment
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#if 0 // every chip must apply it
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#define _USB_128_ALIGMENT 0
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#else
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#define _USB_128_ALIGMENT 1
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#endif
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//---- 3. tx/rx reset clock gating cause XIU timeout
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#if 0
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#define _USB_XIU_TIMEOUT_PATCH 1
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#else
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#define _USB_XIU_TIMEOUT_PATCH 0
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#endif
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//---- 4. short packet lose interrupt without IOC
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#if 0
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#define _USB_SHORT_PACKET_LOSE_INT_PATCH 1
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#else
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#define _USB_SHORT_PACKET_LOSE_INT_PATCH 0
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#endif
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//---- 5. QH blocking in MDATA condition, split zero-size data
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#if 0 // every chip must apply it
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#define _USB_SPLIT_MDATA_BLOCKING_PATCH 0
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#else
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#define _USB_SPLIT_MDATA_BLOCKING_PATCH 1
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#endif
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//---- 6. DM always keep high issue
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#if 1 // if without ECO solution, use SW patch.
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#if 0
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#define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 1
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#else
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#define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 0
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#endif
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#else
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#define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 0
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#endif
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//---- 7. clear port eanble when device disconnect while bus reset
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#if 0 // every chip must apply it, so far
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#define _USB_CLEAR_PORT_ENABLE_AFTER_FAIL_RESET_PATCH 0
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#else
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#define _USB_CLEAR_PORT_ENABLE_AFTER_FAIL_RESET_PATCH 1
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#endif
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//---- 8. mstar host only supports "Throttle Mode" in split translation
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#if 0 // every chip must apply it, so far
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#define _USB_TURN_ON_TT_THROTTLE_MODE_PATCH 0
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#else
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#define _USB_TURN_ON_TT_THROTTLE_MODE_PATCH 1
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#endif
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//---- 9. lower squelch level to cover weak cable link
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#if 0
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#define _USB_ANALOG_RX_SQUELCH_PATCH 1
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#else
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#define _USB_ANALOG_RX_SQUELCH_PATCH 0
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#endif
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//---- 10. high speed reset chirp patch
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#define _USB_HS_CHIRP_PATCH 1
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//---- 11. friendly customer patch
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#define _USB_FRIENDLY_CUSTOMER_PATCH 1
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//---- 12. enabe PVCI i_miwcplt wait for mi2uh_last_done_z
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#if 1 /* Every Mstar New chip should appley it */
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#define _USB_MIU_WRITE_WAIT_LAST_DONE_Z_PATCH 1
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#endif
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//------ UTMI disconnect level parameters ---------------------------------
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// 0x00: 550mv, 0x20: 575, 0x40: 600, 0x60: 625
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#define UTMI_DISCON_LEVEL_2A (0x62)
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//------ UTMI eye diagram parameters ---------------------------------
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#if 0
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// for 40nm
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#define UTMI_EYE_SETTING_2C (0x98)
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#define UTMI_EYE_SETTING_2D (0x02)
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#define UTMI_EYE_SETTING_2E (0x10)
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#define UTMI_EYE_SETTING_2F (0x01)
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#define UTMI_ALL_EYE_SETTING (0x01100298)
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#elif 0
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// for 40nm after Agate, use 55nm setting7
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#define UTMI_EYE_SETTING_2C (0x90)
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#define UTMI_EYE_SETTING_2D (0x03)
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#define UTMI_EYE_SETTING_2E (0x30)
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#define UTMI_EYE_SETTING_2F (0x81)
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#define UTMI_ALL_EYE_SETTING (0x81300390)
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#elif 0
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// for 40nm after Agate, use 55nm setting6
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#define UTMI_EYE_SETTING_2C (0x10)
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#define UTMI_EYE_SETTING_2D (0x03)
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#define UTMI_EYE_SETTING_2E (0x30)
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#define UTMI_EYE_SETTING_2F (0x81)
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#define UTMI_ALL_EYE_SETTING (0x81300310)
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#elif 0
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// for 40nm after Agate, use 55nm setting5
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#define UTMI_EYE_SETTING_2C (0x90)
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#define UTMI_EYE_SETTING_2D (0x02)
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#define UTMI_EYE_SETTING_2E (0x30)
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#define UTMI_EYE_SETTING_2F (0x81)
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#define UTMI_ALL_EYE_SETTING (0x81300290)
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#elif 0
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// for 40nm after Agate, use 55nm setting4
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#define UTMI_EYE_SETTING_2C (0x90)
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#define UTMI_EYE_SETTING_2D (0x03)
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#define UTMI_EYE_SETTING_2E (0x00)
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#define UTMI_EYE_SETTING_2F (0x81)
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#define UTMI_ALL_EYE_SETTING (0x81000390)
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#elif 0
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// for 40nm after Agate, use 55nm setting3
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#define UTMI_EYE_SETTING_2C (0x10)
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#define UTMI_EYE_SETTING_2D (0x03)
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#define UTMI_EYE_SETTING_2E (0x00)
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#define UTMI_EYE_SETTING_2F (0x81)
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#define UTMI_ALL_EYE_SETTING (0x81000310)
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#elif 0
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// for 40nm after Agate, use 55nm setting2
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#define UTMI_EYE_SETTING_2C (0x90)
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#define UTMI_EYE_SETTING_2D (0x02)
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#define UTMI_EYE_SETTING_2E (0x00)
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#define UTMI_EYE_SETTING_2F (0x81)
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#define UTMI_ALL_EYE_SETTING (0x81000290)
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#else
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// for 40nm after Agate, use 55nm setting1, the default
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#define UTMI_EYE_SETTING_2C (0x10)
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#define UTMI_EYE_SETTING_2D (0x02)
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#define UTMI_EYE_SETTING_2E (0x00)
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#define UTMI_EYE_SETTING_2F (0x81)
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#define UTMI_ALL_EYE_SETTING (0x81000210)
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#endif
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#define CONFIG_MIU0_BUSADDR 0x20000000
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#define CONFIG_MIU1_BUSADDR 0xC0000000
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/****** Porting environment setting ******/
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#if defined(SERET_ENV)
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/* Delay Function */
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#include <timer.h>
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#define udelay(us) udelay(us)
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/* buncing buffer enable for non cache flush API in cache enable system */
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// #define USB_BOUNCING_BUF 1
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#define readb(addr) *((unsigned char volatile *)(addr))
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#define writeb(val, addr) (*((unsigned char volatile *)(addr)) = (unsigned char)val)
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#define mdelay(ms) { MS_U32 i; \
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for(i=0;i<ms;i++) \
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udelay(1000); \
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}
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#define USB_DELAY(ms) mdelay(ms)
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#define wait_ms(ms) mdelay(ms)
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#endif
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#if defined(MSTAR_UBOOT_ENV)
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extern MS_U32 MsOS_USB_VA2PA(MS_U32 addr);
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extern MS_U32 MsOS_USB_PA2KSEG0(MS_U32 addr);
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extern MS_U32 MsOS_USB_PA2KSEG1(MS_U32 addr);
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extern void Chip_Read_Memory(void);
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extern void Chip_Flush_Memory(void);
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extern void flush_cache (unsigned long, unsigned long);
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/* Delay Function */
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void udelay (unsigned long);
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#define readb(addr) *((unsigned char volatile *)(addr))
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#define writeb(val, addr) (*((unsigned char volatile *)(addr)) = (unsigned char)val)
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#define readw(addr) *((volatile MS_UINT16 *)(addr))
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#define writew(val, addr) (*((volatile MS_UINT16 *)(addr)) = (MS_UINT16)val)
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#define readl(addr) *((volatile MS_UINT32 *)(addr))
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#define writel(val, addr) (*((volatile MS_UINT32 *)(addr)) = (MS_UINT32)val)
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/*
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#define mdelay(ms) { MS_U32 i; \
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for(i=0;i<ms;i++) \
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udelay(1000); \
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}
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*/
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#define USB_DELAY(ms) mdelay(ms)
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#if defined(__ARM__)
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#define KSEG02KSEG1(addr) MsOS_USB_PA2KSEG1(MsOS_USB_VA2PA((MS_U32)addr))
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#define KSEG12KSEG0(addr) MsOS_USB_PA2KSEG0(MsOS_USB_VA2PA((MS_U32)addr))
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#else
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#define KSEG02KSEG1(addr) ((void *)((MS_U32)(addr)|0x20000000)) //cached -> unchched
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#define KSEG12KSEG0(addr) ((void *)((MS_U32)(addr)&~0x20000000)) //unchched -> cached
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#endif
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/* virtual address to physical address translation */
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#if defined(__ARM__)
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#define ENABLE_USB_NEW_MIU_SEL 1 /* Unit: 4GB / 16 = 256MB */
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#define USB_MIU_SEL0 0x70 /* MIU0: 2GB */
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#define USB_MIU_SEL1 0xF8 /* MIU1: 2GB */
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#define USB_MIU_SEL2 0xEF
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#define USB_MIU_SEL3 0xEF
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#define MIU0_BUS_BASE_ADDR CONFIG_MIU0_BUSADDR
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#define MIU0_PHY_BASE_ADDR 0x00000000UL
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#define MIU1_BUS_BASE_ADDR CONFIG_MIU1_BUSADDR
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#define MIU1_PHY_BASE_ADDR 0x80000000UL
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/* transmit between BUS and USB PHY Addr */
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extern unsigned int VA2PA(unsigned int u32_DMAAddr);
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extern unsigned int PA2VA(unsigned int u32_DMAAddr);
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#elif defined(__MIPS__)
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#define VA2PA(a) (a)
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#define PA2VA(a) (a)
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#else // ??? which CPU
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#define VA2PA(a) ((a) & 0x1FFFFFFF)
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#define PA2VA(a) ((a) | 0xA0000000) //// mapping to uncache address
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#endif
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#endif
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#endif /* __PLATFORM_H__*/
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