130 lines
4.8 KiB
C
Executable File
130 lines
4.8 KiB
C
Executable File
/*
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* drvSPINAND_dev.c- Sigmastar
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*
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* Copyright (C) 2018 Sigmastar Technology Corp.
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*
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* Author: edie.chen <edie.chen@sigmastar.com.tw>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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* Collect Device Dependent functions
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*/
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#include <linux/string.h>
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#include <common.h>
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// Common Definition
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#include "MsCommon.h"
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#include "MsIRQ.h"
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#include "MsTypes.h"
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#include "halSPINAND_common.h"
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//#include "MsOS.h"
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//#include "drvMMIO.h"
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#include "../../inc/common/drvSPINAND.h"
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//#ifndef _DRV_SPICMD_H_
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//#include "../../inc/common/drvSPICMD.h"
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//#endif
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#include "../../inc/common/spinand.h"
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//-------------------------------------------------------------------------------------------------
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// Macro definition
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//-------------------------------------------------------------------------------------------------
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#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); }
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#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2))
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#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val))
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#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2))
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#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val))
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#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val))
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#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2))
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#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask))
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#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val))
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#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2))
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#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2))
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#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val))
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#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask))
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#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2))
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#define CLKGEN_READ(addr) READ_WORD(_hal_fsp.u32ClkGenBaseAddr + (addr<<2))
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#define CLKGEN_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32ClkGenBaseAddr + (addr<<2),(val))
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#define CLKGEN_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32ClkGenBaseAddr + ((addr)<<2), (val), (mask))
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//-------------------------------------------------------------------------------------------------
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// Local Structures
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Local Variables
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//-------------------------------------------------------------------------------------------------
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U32 GD_SPINAND_SetDriving(U16 u16Driving)
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{
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U8 status = 0;
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U32 u32Ret;
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U8 val, u8NewV;
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BOOL bSet = FALSE;
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u32Ret = MDrv_SPINAND_ReadStatusRegister((U8*)&status, SPI_NAND_REG_FUT);
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//S1/S0: BIT5-BiT6
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// 0 0 : 50
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// 0 1 :25
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// 1 0 :75
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// 1 1 : 100
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if(u32Ret == ERR_SPINAND_SUCCESS)
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{
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val = status & (BIT(5) | BIT(6));
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u8NewV = status & (~(BIT(5) | BIT(6)));
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printf("Set driving :%d Reg.Value from %X\n", u16Driving, status);
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if(u16Driving == 0 || u16Driving == 50)
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{
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if(val != 0)
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{
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bSet = TRUE;
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}
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}
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else if(u16Driving == 1 || u16Driving == 25)
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{
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if(val != BIT(5))
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{
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u8NewV |= BIT(5);
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bSet = TRUE;
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}
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}
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else if(u16Driving == 2 || u16Driving == 75)
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{
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if(val != BIT(6))
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{
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u8NewV |= BIT(6);
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bSet = TRUE;
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}
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}
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else if(u16Driving == 3 || u16Driving == 100)
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{
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if(val != (BIT(5) | BIT(6)))
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{
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u8NewV |= BIT(5) | BIT(6);
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bSet = TRUE;
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}
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}
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else {
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printk("Invalid value 0x%X", u16Driving);
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return ERR_SPINAND_INVALID;
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}
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if(bSet)
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{
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printf("to %X\n", u8NewV);
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u32Ret = MDrv_SPINAND_WriteStatusRegister((U8*)&u8NewV, SPI_NAND_REG_FUT);
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}
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}
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return u32Ret;
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}
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