97 lines
3.4 KiB
C
Vendored
97 lines
3.4 KiB
C
Vendored
/*
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* isp_hal.h- Sigmastar
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*
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* Copyright (C) 2018 Sigmastar Technology Corp.
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*
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* Author: eroy.yang <eroy.yang@sigmastar.com.tw>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef ISP_HAL_H
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#include <asm/types.h>
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#define MS_BASE_REG_RIU_PA (0x1F000000)
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#define BANK_TO_ADDR32(b) (b<<9)
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#define BANK_BASE_ADDR(bank) (MS_BASE_REG_RIU_PA+BANK_TO_ADDR32(bank))
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typedef enum
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{
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RIUBASE_ISP_0 = 0x1302,
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RIUBASE_ISP_1 = 0x1303,
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RIUBASE_ISP_2 = 0x1304,
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RIUBASE_ISP_3 = 0x1305,
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RIUBASE_ISP_4 = 0x1306,
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RIUBASE_ISP_5 = 0x1307,
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RIUBASE_ISP_6 = 0x1308,
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RIUBASE_ISP_7 = 0x1309,
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RIUBASE_ISP_8 = 0x130A,
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RIUBASE_ISP_9 = 0x130B,
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RIUBASE_CHIPTOP = 0x101E,
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RIUBASE_CLKGEN = 0x1038,
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RIUBASE_PADTOP = 0x103C,
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RIUBASE_CSI_MAC = 0x1204,
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RIUBASE_DPHY_CSI_ANA = 0x1202,
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RIUBASE_DPHY_CSI_DIG = 0x1203
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} REG_BANKS;
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//clock gen
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#define OFFSET_CLKGEN_TO_CLK_SENSOR (0x62<<2)
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typedef enum { //for reg_ckg_sr_mclk_select_clock_source
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SEN_MAIN_CLK_27M = 0 ,
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SEN_MAIN_CLK_21P6M = 1 ,
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SEN_MAIN_CLK_12M = 2 ,
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SEN_MAIN_CLK_5P4M = 3 ,
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SEN_MAIN_CLK_36M = 4 ,
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SEN_MAIN_CLK_54M = 5 ,
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SEN_MAIN_CLK_43P2M = 6 ,
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SEN_MAIN_CLK_61P7M = 7 ,
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}SENSOR_MAIN_CLK;
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/*! @brief Sensor master clock select */
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typedef enum {
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CUS_CMU_CLK_5P4M = 0 , /**< Sensor MCLK 5.4MHz */
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CUS_CMU_CLK_12M = 1 , /**< Sensor MCLK 12MHz */
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CUS_CMU_CLK_21P6M = 2 , /**< Sensor MCLK 21.6MHz */
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CUS_CMU_CLK_27M = 3 , /**< Sensor MCLK 27MHz */
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CUS_CMU_CLK_36M = 4 , /**< Sensor MCLK 36MHz */
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CUS_CMU_CLK_43P2M = 5 , /**< Sensor MCLK 43.2MHz */
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CUS_CMU_CLK_54M = 6 , /**< Sensor MCLK 54MHz */
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CUS_CMU_CLK_61P7M = 7 , /**< Sensor MCLK 61.7MHz */
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CUS_CMU_CLK_ISP_MAX = 128, /**< Reserved , Do not use */
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CUS_CMU_SCL_CLK_36M = 129, /**< Sensor MCLK 36MHz from SCL */
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CUS_CMU_SCL_CLK_27M = 130, /**< Sensor MCLK 36MHz from SCL */
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CUS_CMU_SCL_CLK_37P125M = 131, /**< Sensor MCLK 36MHz from SCL */
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CUS_CMU_SCL_CLK_33M = 132, /**< Sensor MCLK 33MHz from SCL */
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CUS_CMU_SCL_CLK_34M = 133, /**< Sensor MCLK 34MHz from SCL */
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CUS_CMU_SCL_CLK_36P125M = 134, /**< Sensor MCLK 36.125MHz from SCL */
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CUS_CMU_SCL_CLK_21P6M = 135, /**< Sensor MCLK 36.125MHz from SCL */
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} CUS_MCLK_FREQ;
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typedef struct {
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u32 reg_ckg_sr_disable_clock :1; //pixel clock
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u32 reg_ckg_sr_invert_clock :1; //pixel clock
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u32 reg_ckg_sr_select_clock_source :2; //enum SENSOR_PCLK
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u32 :4;
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u32 reg_ckg_sr_mclk_disable_clock :1; //mclk
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u32 reg_ckg_sr_mclk_invert_clock :1; //mclk
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u32 reg_ckg_sr_mclk_select_clock_source :3;//enum SENSOR_MAIN_CLK
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u32 :19;
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} clk_sensor;
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#define OFFSET_CHIPTOP_TO_SENSOR_MODE (0x06<<2)
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typedef struct {
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u32 reg_sr_mode :3;
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u32 :1;
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u32 reg_sr_i2c_mode :2;
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u32 :26;
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} chiptop_sensor_mode;
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#endif
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