327 lines
14 KiB
C
Executable File
Vendored
327 lines
14 KiB
C
Executable File
Vendored
/*
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* mhal_emac.h- Sigmastar
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*
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* Copyright (C) 2018 Sigmastar Technology Corp.
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*
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* Author: richard.guo <richard.guo@sigmastar.com.tw>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRV_EMAC__
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#define __DRV_EMAC__
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#include <common.h>
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#include <command.h>
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//#include <configs/uboot_board_config.h>
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//-------------------------------------------------------------------------------------------------
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// Define Enable or Compiler Switches
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//-------------------------------------------------------------------------------------------------
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//#define RX_SOFTWARE_DESCRIPTOR
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#define SOFTWARE_DESCRIPTOR
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//#define CONFIG_ETHERNET_ALBANY
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//#define RX_CHECKSUM
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//#define INT_DELAY
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//#define CHECKSUM_TEST
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// Compiler Switches
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#define REG_BIT_MAP
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#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */
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//#define CHIP_FLUSH_READ
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//--------------------------------------------------------------------------------------------------
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// Constant definition
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//--------------------------------------------------------------------------------------------------
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#define TRUE 1
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#define FALSE 0
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#define BIT(x) (1<<x)
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#define PHY_REG_BASIC (0)
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#define PHY_REG_STATUS (1)
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#define PHY_REG_LINK_PARTNER (5)
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#define EMAC_ALLFF 0xFFFFFFFF
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// Base address here:
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#ifdef CONFIG_MS_EMAC1
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#define REG_ADDR_BASE (0x1F000000 | (REG_BANK_EMAC0 << 9))
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#else
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#define REG_ADDR_BASE 0x1F2A2000 // The register address base. Depends on system define.
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#endif
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#define BUS_MIU0_BASE_CACHE 0x20000000//CONFIG_SYS_MIU0_CACHE //Beginning cachable bus address of MIU0
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#define BUS_MIU0_BASE_NONCACHE 0x20000000//CONFIG_SYS_MIU0_NON_CACHE //Beginning non-cachable bus address of MIU0
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#define REG_BANK_EFUSE 0x0020
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#define REG_BANK_CLKGEN0 0x1038
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#define REG_BANK_SCGPCTRL 0x1133
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#define REG_BANK_CHIPTOP 0x101E
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//#define REG_BANK_ANA_MISC 0x110C
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#ifdef CONFIG_MS_EMAC1
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#define REG_BANK_EMAC0 0x1514
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#define REG_BANK_EMAC1 0x1515
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#define REG_BACK_EMAC2 0x1516
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#define REG_BANK_EMAC3 0x1517
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#else
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#define REG_BANK_EMAC0 0x1510 //0x1020
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#define REG_BANK_EMAC1 0x1511 //0x1021
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#define REG_BACK_EMAC2 0x1512 //0x1022
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#define REG_BANK_EMAC3 0x1513 //0x1023
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#endif
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#ifdef CONFIG_ETHERNET_ALBANY
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#define REG_BANK_ALBANY0 0x0031
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#define REG_BANK_ALBANY1 0x0032
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#define REG_BANK_ALBANY2 0x0033
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#endif
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#define REG_BANK_PMSLEEP 0x000E
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#define MAX_INT_COUNTER 100
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#define barrier() __asm__ __volatile__("": : :"memory")
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#define _DLine() {printf("%s line:%u\n",__FILE__, __LINE__);}
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/* The forced speed, 10Mb, 100Mb. */
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#define SPEED_10 10
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#define SPEED_100 100
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/* Duplex, half or full. */
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#define DUPLEX_HALF 0x00
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#define DUPLEX_FULL 0x01
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#define PHY_CODE_SHIFT (16)
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#define PHY_REG_SHIFT (18)
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#define PHY_ADDR_SHIFT (23)
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#define PHY_RW_SHIFT (28)
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#define PHY_LOW_HIGH_SHIFT (30)
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#define PHY_CODE (0x02)
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#define PHY_LOW_HIGH (0x01)
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#define PHY_WRITE_OP (0x01)
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#define PHY_READ_OP (0x02)
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#define PHY_AN_DONE (0x1 << 5)
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#define PHY_LINK_UP (0x1 << 2)
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//0x100
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#define EMAC_MIU_WP_EN BIT(6)
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#define EMAC_MIU_WP_INT_EN BIT(7)
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//0x102
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#define EMAC_MIU_WP_INT_STATUS BIT(4)
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//0x11E
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#define MIU_MIU_WP_UB (0x11E)
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//0x122
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#define MIU_MIU_WP_LB (0x122)
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#define MIU_ADDR_UNIT (8)
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#define EMAC_RIU_REG_BASE (0x1F000000)
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//-------------------------------------------------------------------------------------------------
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// Bit Define
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//-------------------------------------------------------------------------------------------------
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#define EMAC_MIU_RW (0x3 << 10) //EMAC power on clk
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// -------- EMAC_CTL : (EMAC Offset: 0x0) --------
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#define EMAC_LB ( 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
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#define EMAC_LBL ( 0x1 << 1) // (EMAC) Loopback local.
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#define EMAC_RE ( 0x1 << 2) // (EMAC) Receive enable.
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#define EMAC_TE ( 0x1 << 3) // (EMAC) Transmit enable.
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#define EMAC_MPE ( 0x1 << 4) // (EMAC) Management port enable.
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#define EMAC_CSR ( 0x1 << 5) // (EMAC) Clear statistics registers.
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#define EMAC_ISR ( 0x1 << 6) // (EMAC) Increment statistics registers.
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#define EMAC_WES ( 0x1 << 7) // (EMAC) Write enable for statistics registers.
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#define EMAC_BP ( 0x1 << 8) // (EMAC) Back pressure.
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// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------
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#define EMAC_SPD ( 0x1 << 0) // (EMAC) Speed.
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#define EMAC_FD ( 0x1 << 1) // (EMAC) Full duplex.
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#define EMAC_BR ( 0x1 << 2) // (EMAC) Bit rate.
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#define EMAC_CAF ( 0x1 << 4) // (EMAC) Copy all frames.
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#define EMAC_NBC ( 0x1 << 5) // (EMAC) No broadcast.
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#define EMAC_MTI ( 0x1 << 6) // (EMAC) Multicast hash enable
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#define EMAC_UNI ( 0x1 << 7) // (EMAC) Unicast hash enable.
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#define EMAC_RLF ( 0x1 << 8) // (EMAC) Receive Long Frame.
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#define EMAC_EAE ( 0x1 << 9) // (EMAC) External address match enable.
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#define EMAC_CLK ( 0x3 << 10) // (EMAC)
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#define EMAC_CLK_HCLK_8 ( 0x0 << 10) // (EMAC) HCLK divided by 8
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#define EMAC_CLK_HCLK_16 ( 0x1 << 10) // (EMAC) HCLK divided by 16
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#define EMAC_CLK_HCLK_32 ( 0x2 << 10) // (EMAC) HCLK divided by 32
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#define EMAC_CLK_HCLK_64 ( 0x3 << 10) // (EMAC) HCLK divided by 64
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#define EMAC_RT ( 0x1 << 12) // (EMAC) Retry test
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#define EMAC_CAMMEG ( 0x1 << 13) // (EMAC)
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// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------
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#define EMAC_MDIO ( 0x1 << 1) // (EMAC)
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#define EMAC_IDLE ( 0x1 << 2) // (EMAC)
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// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register --------
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#define EMAC_LEN ( 0x7FF << 0) // (EMAC)
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#define EMAC_NCRC ( 0x1 << 15) // (EMAC)
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// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register --------
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#define EMAC_OVR ( 0x1 << 0) // (EMAC)
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#define EMAC_COL ( 0x1 << 1) // (EMAC)
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#define EMAC_RLE ( 0x1 << 2) // (EMAC)
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//#define EMAC_TXIDLE ( 0x1 << 3) // (EMAC)
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#define EMAC_IDLETSR ( 0x1 << 3) // (EMAC)
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#define EMAC_BNQ ( 0x1 << 4) // (EMAC)
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#define EMAC_COMP ( 0x1 << 5) // (EMAC)
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#define EMAC_UND ( 0x1 << 6) // (EMAC)
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// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
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#define EMAC_DNA ( 0x1 << 0) // (EMAC)
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#define EMAC_REC ( 0x1 << 1) // (EMAC)
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#define EMAC_RSROVR ( 0x1 << 2) // (EMAC)
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#define EMAC_BNA ( 0x1 << 3) // (EMAC)
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// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
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#define EMAC_INT_DONE ( 0x1 << 0) // (EMAC)
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#define EMAC_INT_RCOM ( 0x1 << 1) // (EMAC)
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#define EMAC_INT_RBNA ( 0x1 << 2) // (EMAC)
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#define EMAC_INT_TOVR ( 0x1 << 3) // (EMAC)
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#define EMAC_INT_TUND ( 0x1 << 4) // (EMAC)
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#define EMAC_INT_RTRY ( 0x1 << 5) // (EMAC)
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#define EMAC_INT_TBRE ( 0x1 << 6) // (EMAC)
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#define EMAC_INT_TCOM ( 0x1 << 7) // (EMAC)
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#define EMAC_INT_TIDLE ( 0x1 << 8) // (EMAC)
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#define EMAC_INT_LINK ( 0x1 << 9) // (EMAC)
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#define EMAC_INT_ROVR ( 0x1 << 10) // (EMAC)
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#define EMAC_INT_HRESP ( 0x1 << 11) // (EMAC)
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// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
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// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
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// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
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// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
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#define EMAC_DATA ( 0xFFFF << 0) // (EMAC)
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#define EMAC_CODE ( 0x3 << 16) // (EMAC)
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#define EMAC_CODE_802_3 ( 0x2 << 16) // (EMAC) Write Operation
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#define EMAC_REGA ( 0x1F << 18) // (EMAC)
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#define EMAC_PHYA ( 0x1F << 23) // (EMAC)
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#define EMAC_RW ( 0x3 << 28) // (EMAC)
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#define EMAC_RW_R ( 0x2 << 28) // (EMAC) Read Operation
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#define EMAC_RW_W ( 0x1 << 28) // (EMAC) Write Operation
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#define EMAC_HIGH ( 0x1 << 30) // (EMAC)
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#define EMAC_LOW ( 0x1 << 31) // (EMAC)
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// -------- EMAC_RBRP: (EMAC Offset: 0x38) Receive Buffer First full pointer--------
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#define EMAC_WRAP_R ( 0x1 << 14) // Wrap bit
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// -------- EMAC_RBWP: (EMAC Offset: 0x3C) Receive Buffer Current pointer--------
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#define EMAC_WRAP_W ( 0x1 << 14) // Wrap bit
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// ........................................................................ //
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//URANUS PHY //
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#define MII_URANUS_ID 0x01111//Test value
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//URANUS specific registers //
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#define MII_USCR_REG 16
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#define MII_USCSR_REG 17
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#define MII_USINTR_REG 21
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/* ........................................................................ */
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#define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */
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#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
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#define EMAC_BROADCAST 0x80000000 /* broadcast address */
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#define EMAC_MULTICAST 0x40000000 /* multicast address */
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#define EMAC_UNICAST 0x20000000 /* unicast address */
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/* eWaveTest */
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#define EWAVE_TEST_NUM 5
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typedef void (*eWaveTestCb)(void);
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void MHal_EMAC_WritReg32( u32 xoffset, u32 xval );
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u32 MHal_EMAC_ReadReg32( u32 xoffset );
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s32 MHal_EMAC_NegotiationPHY(void);
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s32 MHal_EMAC_CableConnection(void);
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u32 MHal_EMAC_get_SA1H_addr(void);
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u32 MHal_EMAC_get_SA1L_addr(void);
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u32 MHal_EMAC_get_SA2H_addr(void);
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u32 MHal_EMAC_get_SA2L_addr(void);
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u32 MHal_EMAC_Read_CTL(void);
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u32 MHal_EMAC_Read_CFG(void);
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u32 MHal_EMAC_Read_RBQP(void);
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u32 MHal_EMAC_Read_ISR(void);
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u32 MHal_EMAC_Read_IDR(void);
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u32 MHal_EMAC_Read_IER(void);
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u32 MHal_EMAC_Read_IMR(void);
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u32 MHal_EMAC_Read_RDPTR(void);
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u32 MHal_EMAC_Read_BUFF(void);
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u32 MHal_EMAC_Read_FRA(void);
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u32 MHal_EMAC_Read_SCOL(void);
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u32 MHal_EMAC_Read_MCOL(void);
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u32 MHal_EMAC_Read_OK(void);
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u32 MHal_EMAC_Read_SEQE(void);
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u32 MHal_EMAC_Read_ALE(void);
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u32 MHal_EMAC_Read_LCOL(void);
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u32 MHal_EMAC_Read_ECOL(void);
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u32 MHal_EMAC_Read_TUE(void);
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u32 MHal_EMAC_Read_TSR(void);
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u32 MHal_EMAC_Read_RSR(void);
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u32 MHal_EMAC_Read_CSE(void);
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u32 MHal_EMAC_Read_RE(void);
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u32 MHal_EMAC_Read_ROVR(void);
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u32 MHal_EMAC_Read_MAN(void);
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u32 MHal_EMAC_Read_SE(void);
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u32 MHal_EMAC_Read_ELR(void);
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u32 MHal_EMAC_Read_RJB(void);
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u32 MHal_EMAC_Read_USF(void);
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u32 MHal_EMAC_Read_SQEE(void);
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u32 MHal_EMAC_Read_JULIAN_0100(void);
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u32 MHal_EMAC_Read_JULIAN_0104(void);
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u32 MHal_EMAC_Read_JULIAN_0108(void);
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void MHal_EMAC_update_HSH(u8 mc0, u8 mc1);
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void MHal_EMAC_Write_CTL(u32 xval);
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void MHal_EMAC_Write_CFG(u32 xval);
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void MHal_EMAC_Write_RBQP(u32 u32des);
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void MHal_EMAC_Write_BUFF(u32 xval);
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void MHal_EMAC_Write_MAN(u32 xval);
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void MHal_EMAC_Write_TAR(u32 xval);
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void MHal_EMAC_Write_TCR(u32 xval);
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void MHal_EMAC_Write_RDPTR(u32 xval);
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void MHal_EMAC_Write_WRPTR(u32 xval);
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void MHal_EMAC_Write_IER(u32 xval);
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void MHal_EMAC_Write_IDR(u32 xval);
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void MHal_EMAC_Write_IMR(u32 xval);
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void MHal_EMAC_Write_SA1H(u32 xval);
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void MHal_EMAC_Write_SA1L(u32 xval);
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void MHal_EMAC_Write_SA2H(u32 xval);
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void MHal_EMAC_Write_SA2L(u32 xval);
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void MHal_EMAC_Write_JULIAN_0100(u32 xval);
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void MHal_EMAC_Write_JULIAN_0104(u32 xval);
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void MHal_EMAC_Write_JULIAN_0108(u32 xval);
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void MHal_EMAC_Power_On_Clk(void);
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void MHal_EMAC_Power_Off_Clk(void);
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void MHal_EMAC_HW_init(void);
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void MHal_EMAC_timer_callback(unsigned long value);
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void MHal_EMAC_WritRam32(u32 uRamAddr, u32 xoffset,u32 xval);
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void MHal_EMAC_enable_mdi(void);
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void MHal_EMAC_disable_mdi(void);
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void MHal_EMAC_write_phy (unsigned char phy_addr, unsigned char address, u32 value);
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void MHal_EMAC_read_phy(unsigned char phy_addr, unsigned char address,u32 *value);
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void MHal_EMAC_enable_phyirq (void);
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void MHal_EMAC_disable_phyirq (void);
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void MHal_EMAC_update_speed_duplex(u32 uspeed, u32 uduplex);
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void MHal_EMAC_Write_SA1_MAC_Address(u8 m0,u8 m1,u8 m2,u8 m3,u8 m4,u8 m5);
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void MHal_EMAC_Write_SA2_MAC_Address(u8 m0,u8 m1,u8 m2,u8 m3,u8 m4,u8 m5);
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void MHal_EMAC_Write_SA3_MAC_Address(u8 m0,u8 m1,u8 m2,u8 m3,u8 m4,u8 m5);
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void MHal_EMAC_Write_SA4_MAC_Address(u8 m0,u8 m1,u8 m2,u8 m3,u8 m4,u8 m5);
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void MHal_EMAC_WritCAM_Address(u32 addr,u8 m0,u8 m1,u8 m2,u8 m3,u8 m4,u8 m5);
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void MHal_EMAC_ReadCAM_Address(u32 addr,u32 *w0,u32 *w1);
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void MHal_EMAC_WriteProtect(u8 bEnable, u32 u32AddrUB, u32 u32AddrLB);
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void MHal_EMAC_CheckTSR(void);
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void MHal_EMAC_Ewavetest_100M(void);
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void MHal_EMAC_Ewavetest_10M_LTP(void);
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void MHal_EMAC_Ewavetest_10M_ALLONE(void);
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void MHal_EMAC_Ewavetest_10M_TPIDLE(void);
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void MHal_EMAC_eWave_Table_Init(void);
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#if (SUPPORT_ALBANY)
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void MHal_EMAC_Albany_I2C(u8 enable);
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#endif
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#endif
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// -----------------------------------------------------------------------------
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// Linux EMAC.c End
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// -----------------------------------------------------------------------------
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