diff --git a/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qpf b/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qpf new file mode 100644 index 000000000..b5fcca407 --- /dev/null +++ b/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:29:32 June 24, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "16:29:32 September 10, 2021" + +# Revisions + +PROJECT_REVISION = "tzpuFusionX_PCW8256" diff --git a/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qsf b/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qsf new file mode 100644 index 000000000..6b3ebd9b5 --- /dev/null +++ b/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qsf @@ -0,0 +1,243 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:29:32 June 24, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# tzpuFusionX.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY MAX7000AE +set_global_assignment -name DEVICE "EPM7512AETC144-10" +set_global_assignment -name TOP_LEVEL_ENTITY tzpuFusionX_PCW8256 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL + +# Z80 Data Bus +# ============ +set_location_assignment PIN_81 -to Z80_DATA[0] +set_location_assignment PIN_78 -to Z80_DATA[1] +set_location_assignment PIN_87 -to Z80_DATA[2] +set_location_assignment PIN_100 -to Z80_DATA[3] +set_location_assignment PIN_102 -to Z80_DATA[4] +set_location_assignment PIN_93 -to Z80_DATA[5] +set_location_assignment PIN_94 -to Z80_DATA[6] +set_location_assignment PIN_84 -to Z80_DATA[7] + +# Z80 Control signals. +# ==================== +set_location_assignment PIN_69 -to Z80_INTn +set_location_assignment PIN_70 -to Z80_NMIn +set_location_assignment PIN_71 -to Z80_HALTn +set_location_assignment PIN_68 -to Z80_MREQn +set_location_assignment PIN_65 -to Z80_IORQn +set_location_assignment PIN_67 -to Z80_RDn +set_location_assignment PIN_66 -to Z80_WRn +set_location_assignment PIN_63 -to Z80_BUSAKn +set_location_assignment PIN_62 -to Z80_WAITn +set_location_assignment PIN_61 -to Z80_BUSRQn +set_location_assignment PIN_79 -to Z80_RFSHn +set_location_assignment PIN_60 -to Z80_M1n +set_location_assignment PIN_56 -to Z80_RESETn +set_location_assignment PIN_101 -to Z80_CLK + +# Z80 Address Bus +# =============== +set_location_assignment PIN_80 -to Z80_ADDR[0] +set_location_assignment PIN_90 -to Z80_ADDR[1] +set_location_assignment PIN_83 -to Z80_ADDR[2] +set_location_assignment PIN_86 -to Z80_ADDR[3] +set_location_assignment PIN_88 -to Z80_ADDR[4] +set_location_assignment PIN_91 -to Z80_ADDR[5] +set_location_assignment PIN_92 -to Z80_ADDR[6] +set_location_assignment PIN_96 -to Z80_ADDR[7] +set_location_assignment PIN_97 -to Z80_ADDR[8] +set_location_assignment PIN_98 -to Z80_ADDR[9] +set_location_assignment PIN_99 -to Z80_ADDR[10] +set_location_assignment PIN_110 -to Z80_ADDR[11] +set_location_assignment PIN_108 -to Z80_ADDR[12] +set_location_assignment PIN_107 -to Z80_ADDR[13] +set_location_assignment PIN_106 -to Z80_ADDR[14] +set_location_assignment PIN_103 -to Z80_ADDR[15] + +# SOM SPI +# ======= +set_location_assignment PIN_32 -to VSOM_SPI_CSn +set_location_assignment PIN_31 -to VSOM_SPI_CLK +set_location_assignment PIN_30 -to VSOM_SPI_MOSI +set_location_assignment PIN_29 -to VSOM_SPI_MISO + +# SOM Parallel Bus +# ================ +set_location_assignment PIN_41 -to VSOM_DATA_OUT[0] +set_location_assignment PIN_40 -to VSOM_DATA_OUT[1] +set_location_assignment PIN_39 -to VSOM_DATA_OUT[2] +set_location_assignment PIN_38 -to VSOM_DATA_OUT[3] +set_location_assignment PIN_37 -to VSOM_DATA_OUT[4] +set_location_assignment PIN_36 -to VSOM_DATA_OUT[5] +set_location_assignment PIN_35 -to VSOM_DATA_OUT[6] +set_location_assignment PIN_34 -to VSOM_DATA_OUT[7] +set_location_assignment PIN_132 -to VSOM_HBYTE + +# SOM Reserved signals. +# ===================== +set_location_assignment PIN_21 -to VSOM_RSV[1] + +# SOM Control Signals +# =================== +set_location_assignment PIN_28 -to VSOM_READY +set_location_assignment PIN_19 -to VSOM_LTSTATE +set_location_assignment PIN_27 -to VSOM_BUSRQ +set_location_assignment PIN_26 -to VSOM_BUSACK +set_location_assignment PIN_18 -to VSOM_INT +set_location_assignment PIN_22 -to VSOM_NMI +set_location_assignment PIN_25 -to VSOM_WAIT +set_location_assignment PIN_23 -to VSOM_RESET +set_location_assignment PIN_16 -to PM_RESET + +# VGA_Palette Control +# =================== +set_location_assignment PIN_133 -to VGA_R[7] +set_location_assignment PIN_137 -to VGA_R[8] +set_location_assignment PIN_140 -to VGA_R[9] +set_location_assignment PIN_134 -to VGA_G[7] +set_location_assignment PIN_138 -to VGA_G[8] +set_location_assignment PIN_141 -to VGA_G[9] +set_location_assignment PIN_136 -to VGA_B[8] +set_location_assignment PIN_139 -to VGA_B[9] + + +# VGA Control Signals +# =================== +set_location_assignment PIN_142 -to VGA_PXL_CLK +set_location_assignment PIN_14 -to VGA_DISPEN +set_location_assignment PIN_12 -to VGA_VSYNCn +set_location_assignment PIN_11 -to VGA_HSYNCn +set_location_assignment PIN_82 -to VGA_COLR +set_location_assignment PIN_109 -to VGA_CSYNCn +set_location_assignment PIN_143 -to VGA_BLANKn + +# CRT Control Signals +# =================== +set_location_assignment PIN_15 -to MONO_PXL_CLK +set_location_assignment PIN_114 -to MONO_BLANKn +set_location_assignment PIN_113 -to MONO_CSYNCn +set_location_assignment PIN_116 -to MONO_RSV + +# CRT Lower Chrominance Control +# ============================= +set_location_assignment PIN_1 -to MONO_R[0] +set_location_assignment PIN_6 -to MONO_R[1] +set_location_assignment PIN_10 -to MONO_R[2] +set_location_assignment PIN_2 -to MONO_G[0] +set_location_assignment PIN_7 -to MONO_G[1] +set_location_assignment PIN_9 -to MONO_G[2] +set_location_assignment PIN_5 -to MONO_B[1] +set_location_assignment PIN_8 -to MONO_B[2] + +# MUX Control Signals +# =================== +set_location_assignment PIN_72 -to VIDEO_SRC +set_location_assignment PIN_74 -to MONO_VIDEO_SRC +set_location_assignment PIN_77 -to AUDIO_SRC_L +set_location_assignment PIN_75 -to AUDIO_SRC_R + +# Mainboard Reset Signals +# ======================= +#set_location_assignment PIN_127 -to CPU_RESETn +set_location_assignment PIN_122 -to MB_RESETn +set_location_assignment PIN_111 -to MB_IPLn + +# USB Power Control +# ================= +set_location_assignment PIN_55 -to VBUS_EN + +# Clocks +# ====== +#set_location_assignment PIN_125 -to CPU_CLK +set_location_assignment PIN_128 -to CLK_50M + +# Unused ports +# ============ +#set_location_assignment PIN_42 -to +#set_location_assignment PIN_43 -to +#set_location_assignment PIN_44 -to +#set_location_assignment PIN_45 -to +#set_location_assignment PIN_112 -to +#set_location_assignment PIN_131 -to +#set_location_assignment PIN_117 -to +#set_location_assignment PIN_118 -to +#set_location_assignment PIN_119 -to +#set_location_assignment PIN_120 -to +#set_location_assignment PIN_121 -to +#set_location_assignment PIN_25 -to +#set_location_assignment PIN_53 -to +#set_location_assignment PIN_128 -to +#set_location_assignment PIN_47 -to +#set_location_assignment PIN_54 -to +#set_location_assignment PIN_127 -to +#set_location_assignment PIN_125 -to +#set_location_assignment PIN_48 -to +#set_location_assignment PIN_46 -to +#set_location_assignment PIN_49 -to + + +set_global_assignment -name VHDL_FILE ../tzpuFusionX_Toplevel.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX_pkg.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX.vhd +set_global_assignment -name SDC_FILE tzpuFusionX_PCW8256_constraints.sdc + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name AUTO_RESOURCE_SHARING OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF + +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF +set_global_assignment -name AUTO_LCELL_INSERTION ON + +set_global_assignment -name CDF_FILE output_files/tzpuFusionX_PCW8256.cdf diff --git a/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256_constraints.sdc b/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256_constraints.sdc new file mode 100644 index 000000000..6f2e57520 --- /dev/null +++ b/CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256_constraints.sdc @@ -0,0 +1,324 @@ +## Generated SDC file "tzpuFusionX.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jun 26 22:10:05 2020" + +## +## DEVICE "EPM7160STC100-10" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +# Standard mainboard clock. If using tzpuFusionX on a different host then set to the host frequency. +create_clock -name {Z80_CLK} -period 250.000 -waveform { 0.000 125.000 } [get_ports { Z80_CLK }] + +# For 50MHz crystal. +create_clock -name {CLK_50M} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CLK_50M }] + +# For SPI CSn +#create_clock -name {VSOM_SPI_CSn} -period 200.000 -waveform { 160.000 40.000 } [ get_ports { VSOM_SPI_CSn }] + +# For SPI CLK +create_clock -name {VSOM_SPI_CLK} -period 14.000 -waveform { 0.000 7.000 } [ get_ports { VSOM_SPI_CLK }] + +# For basic board with oscillator. +#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }] +#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ] +##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSEL}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HI_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {R_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {G_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {B_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {COLR_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CSYNC_IN}] +##set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {HSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CS2n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A18_INTn_V_R}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSRQn_V_G}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A16_WAITn_V_B}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A17_NMIn_V_COLR}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RFSHn}] + +# For K64F +#set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}] + +# For basic board with oscillator. +#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}] + +#************************************************************** +# Set Max Delay +#************************************************************** +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 30.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 50.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 60.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 60.000 + +#************************************************************** +# Set Min Delay +#************************************************************** +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +# For K64F +#set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For basic board with oscillator. +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For both configurations. +#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} + +#************************************************************** +# Set Multicycle Path +#************************************************************** +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/software/FusionX/modules/ttymzdrv.ko b/software/FusionX/modules/ttymzdrv.ko index 3ebeb0180..33a4a1d07 100644 Binary files a/software/FusionX/modules/ttymzdrv.ko and b/software/FusionX/modules/ttymzdrv.ko differ diff --git a/software/FusionX/src/spitools/mspi_main b/software/FusionX/src/spitools/mspi_main index 1f4ef7049..8f5a3dae0 100755 Binary files a/software/FusionX/src/spitools/mspi_main and b/software/FusionX/src/spitools/mspi_main differ diff --git a/software/FusionX/src/ttymz/Makefile b/software/FusionX/src/ttymz/Makefile index 507105be0..219cf1880 100644 --- a/software/FusionX/src/ttymz/Makefile +++ b/software/FusionX/src/ttymz/Makefile @@ -10,7 +10,7 @@ FUSIONX := $(PWD)/../.. CROSS := arm-linux-gnueabihf- CTRLINC = -IZeta/API -IZ80/API -DTARGET_HOST_$(MODEL)=1 -ccflags-y = -O2 -I${KERNEL}/drivers/sstar/include -I${KERNEL}/drivers/sstar/include/infinity2m -I${KERNEL}/drivers/sstar/gpio/infinity2m -D__KERNEL_DRIVER__ -DTARGET_HOST_$(MODEL)=1 +ccflags-y = -O2 -I${KERNEL}/drivers/sstar/include -I${KERNEL}/drivers/sstar/include/infinity2m -I${KERNEL}/drivers/sstar/gpio/infinity2m -D__KERNEL_DRIVER__ -DTARGET_HOST_$(MODEL)=1 -Wno-error ifeq ($(DEBUG),y) ccflags-y += -DTTYMZ_DEBUG endif diff --git a/software/FusionX/src/ttymz/sharpmz.c b/software/FusionX/src/ttymz/sharpmz.c index 4f307df8e..dc0b04de6 100644 --- a/software/FusionX/src/ttymz/sharpmz.c +++ b/software/FusionX/src/ttymz/sharpmz.c @@ -2455,17 +2455,34 @@ static t_ansiKeyMap ansiKeySeq[] = { #endif // Set the module control structures to default values according to build target. - static t_displayBuffer display = displayDefault; - static t_keyboard keyboard = keyboardDefault; - static t_audio audio = audioDefault; - static t_AnsiTerm ansiterm = ansitermDefault; - static t_control ctrl = ctrlDefault; + // NB: Cannot use const locals as initializers for static variables in C (not compile-time constants). + // Defaults are applied at runtime in sharpmz_init_defaults(). + static t_displayBuffer display; + static t_keyboard keyboard; + static t_audio audio; + static t_AnsiTerm ansiterm; + static t_control ctrl; + static int defaultsInitialised = 0; // -------------------------------------------------------------------------------------------------------------- // Methods // -------------------------------------------------------------------------------------------------------------- +// Initialise the static control structures with default values. +// Called once from the module init path before any hardware access. +void sharpmz_init_defaults(void) +{ + if (!defaultsInitialised) { + display = displayDefault; + keyboard = keyboardDefault; + audio = audioDefault; + ansiterm = ansitermDefault; + ctrl = ctrlDefault; + defaultsInitialised = 1; + } +} + // Method to configure the motherboard hardware after a reset. // uint8_t mzInitMBHardware(void) diff --git a/software/FusionX/src/ttymz/sharpmz.h b/software/FusionX/src/ttymz/sharpmz.h index 5ab902de5..d12b045d8 100755 --- a/software/FusionX/src/ttymz/sharpmz.h +++ b/software/FusionX/src/ttymz/sharpmz.h @@ -556,6 +556,7 @@ typedef struct { // Prototypes. // +void sharpmz_init_defaults(void); uint8_t mzInitMBHardware(void); uint8_t mzInit(void); void mzBeep(uint32_t, uint32_t); diff --git a/software/FusionX/src/ttymz/ttymz.c b/software/FusionX/src/ttymz/ttymz.c index 344caaf7f..c666a2cf7 100644 --- a/software/FusionX/src/ttymz/ttymz.c +++ b/software/FusionX/src/ttymz/ttymz.c @@ -823,6 +823,9 @@ static int __init ttymz_init(void) int i; char buf[80]; + // Initialise the sharpmz module control structures with default values. + sharpmz_init_defaults(); + // Allocate the tty driver handles, one per potential device. ttymzCtrl.ttymzDriver = alloc_tty_driver(SHARPMZ_TTY_MINORS); if(!ttymzCtrl.ttymzDriver) diff --git a/software/linux/Build_FusionX.sh b/software/linux/Build_FusionX.sh index 7dbf14027..c790ed1f9 100755 --- a/software/linux/Build_FusionX.sh +++ b/software/linux/Build_FusionX.sh @@ -190,7 +190,7 @@ else fi cd ${RELEASEDIR}/project -make clean;make image-nocheck +make clean;make image-nocheck || echo "WARNING: make image-nocheck had errors (non-fatal, SD rootfs build continues)" # Save the rootfs before copying latest release. if [ -f ${RELEASEDIR}/project/image/rootfs/rootfs ]; then @@ -326,9 +326,9 @@ tar -cf ${RELEASEDIR}/project/image/output/images/sdrootfs.tar.gz * echo "Building Upgrade image in project/image/output/images/ - " cd ${RELEASEDIR}/project/ echo -n "SigmastarUpgradeSD.bin " -yes | ./make_sd_upgrade_sigmastar.sh +yes | ./make_sd_upgrade_sigmastar.sh || echo "(incomplete - flash images not fully generated)" echo -n "SigmastarUpgrade.bin " -yes | ./make_usb_upgrade_sigmastar.sh +yes | ./make_usb_upgrade_sigmastar.sh || echo "(incomplete - flash images not fully generated)" echo "" echo "Copy image to SD card or USB drive, install and reboot FusionX to upgrade." diff --git a/software/linux/project/configs/current.configs b/software/linux/project/configs/current.configs index 4dfea7fa3..1844266e0 100644 --- a/software/linux/project/configs/current.configs +++ b/software/linux/project/configs/current.configs @@ -1,14 +1,14 @@ -PROJ_ROOT = /srv/dvlp/Projects/tzpu/FusionX/software/linux/project +PROJ_ROOT = /dvlp/Projects/tzpu/FusionX/software/linux/project CONFIG_NAME = config_module_list.mk SOURCE_MK = ../sdk/sdk.mk -KERNEL_MEMADR = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM phyaddr) -KERNEL_MEMLEN = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM size) -KERNEL_MEMADR2 = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM2 phyaddr) -KERNEL_MEMLEN2 = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM2 size) -KERNEL_MEMADR3 = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM3 phyaddr) -KERNEL_MEMLEN3 = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM3 size) -LOGO_ADDR = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) $(BOOTLOGO_ADDR) miuaddr) -BOOTLOGO_BUFSIZE = $(shell /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) $(BOOTLOGO_ADDR) size) +KERNEL_MEMADR = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM phyaddr) +KERNEL_MEMLEN = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM size) +KERNEL_MEMADR2 = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM2 phyaddr) +KERNEL_MEMLEN2 = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM2 size) +KERNEL_MEMADR3 = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM3 phyaddr) +KERNEL_MEMLEN3 = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) E_LX_MEM3 size) +LOGO_ADDR = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) $(BOOTLOGO_ADDR) miuaddr) +BOOTLOGO_BUFSIZE = $(shell /dvlp/Projects/tzpu/FusionX/software/linux/project/image/makefiletools/bin/mmapparser /dvlp/Projects/tzpu/FusionX/software/linux/project/board/$(CHIP)/mmap/$(MMAP) $(CHIP) $(BOOTLOGO_ADDR) size) CHIP = i2m BOARD = 011A BOARD_NAME = SSC011A-S01A