commit 372b4debad662afc5fd7cdf5615bc6915185658c Author: Philip Smart Date: Thu Dec 1 09:35:39 2022 +0000 Initial repo build diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..c84b70c21 --- /dev/null +++ b/.gitignore @@ -0,0 +1,816 @@ +*.bin +build/ADV7123_TEST.qpf +build/ADV7123_TEST.qsf +build/ADV7123.vhd +build/A-Hdrive +build/audio_shifter.v +build/audio_top.v +build/Clock_50to100.BAK.vhd +build/constraints.sdc +build/db/ +build/ddr2_sodimm.qpf +build/ddr2_sodimm.qpf.v1 +build/ddr2_sodimm.qsf +build/ddr2_sodimm.qsf.v1 +build/incremental_db/ +build/KEY_TEST.qpf +build/KEY_TEST.qsf +build/KEY_TEST.v +build/ledwater.qpf +build/ledwater.qsf +build/ledwater.v +build/Makefile.1306 +build/mypll.cmp +build/mypll.qip +build/mypll.vhd +build/output_files/ +build/.qsys_edit/ +build/serial.qpf +build/serial.qsf +build/serial.v +build/serv_req_info.txt +build/simulation/ +build/template.qsf +build/unsaved/ +build/unsaved.qsys +build/unsaved.sopcinfo +c5_pin_model_dump.txt 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+software/FusionX/src/driver/test +software/FusionX/src/driver/x.mzf +software/FusionX/src/driver/z80ctrl +software/FusionX/src/spitools/Makefile.drv +software/FusionX/src/spitools/hold/ +software/FusionX/src/spitools/mspi_main_0.08 +software/FusionX/src/spitools/spi +software/FusionX/src/spitools/spi_0.08 +software/old/ +software/READ.ME +software/asm/ +software/build.sh +software/config/ +software/dis/ +software/exploringBB/ +software/hdr/ +software/linux-kernel-module/ +software/linux/ +software/mif/ +software/roms/ +software/rt-tests/ +software/src/ +software/tools/ +CPLD/v1.0/MZ2000/rrrr +_config.yml +software/WebServer/WebServer +software/WebServer/WebServer.cpp.sk +software/WebServer/WebServer.h.sk +software/WebServer/webfs/ + diff --git a/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000.qpf b/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000.qpf new file mode 100644 index 000000000..5fe4c88c6 --- /dev/null +++ b/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:29:32 June 24, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "16:29:32 September 10, 2021" + +# Revisions + +PROJECT_REVISION = "tzpuFusionX_MZ2000" diff --git a/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000.qsf b/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000.qsf new file mode 100644 index 000000000..bc46a3d6b --- /dev/null +++ b/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000.qsf @@ -0,0 +1,243 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:29:32 June 24, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# tzpuFusionX.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY MAX7000AE +set_global_assignment -name DEVICE "EPM7512AETC144-10" +set_global_assignment -name TOP_LEVEL_ENTITY tzpuFusionX_MZ2000 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL + +# Z80 Data Bus +# ============ +set_location_assignment PIN_81 -to Z80_DATA[0] +set_location_assignment PIN_78 -to Z80_DATA[1] +set_location_assignment PIN_87 -to Z80_DATA[2] +set_location_assignment PIN_100 -to Z80_DATA[3] +set_location_assignment PIN_102 -to Z80_DATA[4] +set_location_assignment PIN_93 -to Z80_DATA[5] +set_location_assignment PIN_94 -to Z80_DATA[6] +set_location_assignment PIN_84 -to Z80_DATA[7] + +# Z80 Control signals. +# ==================== +set_location_assignment PIN_69 -to Z80_INTn +set_location_assignment PIN_70 -to Z80_NMIn +set_location_assignment PIN_71 -to Z80_HALTn +set_location_assignment PIN_68 -to Z80_MREQn +set_location_assignment PIN_65 -to Z80_IORQn +set_location_assignment PIN_67 -to Z80_RDn +set_location_assignment PIN_66 -to Z80_WRn +set_location_assignment PIN_63 -to Z80_BUSAKn +set_location_assignment PIN_62 -to Z80_WAITn +set_location_assignment PIN_61 -to Z80_BUSRQn +set_location_assignment PIN_79 -to Z80_RFSHn +set_location_assignment PIN_60 -to Z80_M1n +set_location_assignment PIN_56 -to Z80_RESETn +set_location_assignment PIN_101 -to Z80_CLK + +# Z80 Address Bus +# =============== +set_location_assignment PIN_80 -to Z80_ADDR[0] +set_location_assignment PIN_90 -to Z80_ADDR[1] +set_location_assignment PIN_83 -to Z80_ADDR[2] +set_location_assignment PIN_86 -to Z80_ADDR[3] +set_location_assignment PIN_88 -to Z80_ADDR[4] +set_location_assignment PIN_91 -to Z80_ADDR[5] +set_location_assignment PIN_92 -to Z80_ADDR[6] +set_location_assignment PIN_96 -to Z80_ADDR[7] +set_location_assignment PIN_97 -to Z80_ADDR[8] +set_location_assignment PIN_98 -to Z80_ADDR[9] +set_location_assignment PIN_99 -to Z80_ADDR[10] +set_location_assignment PIN_110 -to Z80_ADDR[11] +set_location_assignment PIN_108 -to Z80_ADDR[12] +set_location_assignment PIN_107 -to Z80_ADDR[13] +set_location_assignment PIN_106 -to Z80_ADDR[14] +set_location_assignment PIN_103 -to Z80_ADDR[15] + +# SOM SPI +# ======= +set_location_assignment PIN_32 -to VSOM_SPI_CSn +set_location_assignment PIN_31 -to VSOM_SPI_CLK +set_location_assignment PIN_30 -to VSOM_SPI_MOSI +set_location_assignment PIN_29 -to VSOM_SPI_MISO + +# SOM Parallel Bus +# ================ +set_location_assignment PIN_41 -to VSOM_DATA_OUT[0] +set_location_assignment PIN_40 -to VSOM_DATA_OUT[1] +set_location_assignment PIN_39 -to VSOM_DATA_OUT[2] +set_location_assignment PIN_38 -to VSOM_DATA_OUT[3] +set_location_assignment PIN_37 -to VSOM_DATA_OUT[4] +set_location_assignment PIN_36 -to VSOM_DATA_OUT[5] +set_location_assignment PIN_35 -to VSOM_DATA_OUT[6] +set_location_assignment PIN_34 -to VSOM_DATA_OUT[7] +set_location_assignment PIN_132 -to VSOM_HBYTE + +# SOM Reserved signals. +# ===================== +set_location_assignment PIN_21 -to VSOM_RSV[1] + +# SOM Control Signals +# =================== +set_location_assignment PIN_28 -to VSOM_READY +set_location_assignment PIN_18 -to VSOM_LTSTATE +set_location_assignment PIN_27 -to VSOM_BUSRQ +set_location_assignment PIN_26 -to VSOM_BUSACK +set_location_assignment PIN_19 -to VSOM_INT +set_location_assignment PIN_22 -to VSOM_NMI +set_location_assignment PIN_25 -to VSOM_WAIT +set_location_assignment PIN_23 -to VSOM_RESET +set_location_assignment PIN_16 -to PM_RESET + +# VGA_Palette Control +# =================== +set_location_assignment PIN_133 -to VGA_R[7] +set_location_assignment PIN_137 -to VGA_R[8] +set_location_assignment PIN_140 -to VGA_R[9] +set_location_assignment PIN_134 -to VGA_G[7] +set_location_assignment PIN_138 -to VGA_G[8] +set_location_assignment PIN_141 -to VGA_G[9] +set_location_assignment PIN_136 -to VGA_B[8] +set_location_assignment PIN_139 -to VGA_B[9] + + +# VGA Control Signals +# =================== +set_location_assignment PIN_142 -to VGA_PXL_CLK +set_location_assignment PIN_14 -to VGA_DISPEN +set_location_assignment PIN_12 -to VGA_VSYNCn +set_location_assignment PIN_11 -to VGA_HSYNCn +set_location_assignment PIN_82 -to VGA_COLR +set_location_assignment PIN_109 -to VGA_CSYNCn +set_location_assignment PIN_143 -to VGA_BLANKn + +# CRT Control Signals +# =================== +set_location_assignment PIN_15 -to MONO_PXL_CLK +set_location_assignment PIN_114 -to MONO_BLANKn +set_location_assignment PIN_113 -to MONO_CSYNCn +set_location_assignment PIN_116 -to MONO_RSV + +# CRT Lower Chrominance Control +# ============================= +set_location_assignment PIN_1 -to MONO_R[0] +set_location_assignment PIN_6 -to MONO_R[1] +set_location_assignment PIN_10 -to MONO_R[2] +set_location_assignment PIN_2 -to MONO_G[0] +set_location_assignment PIN_7 -to MONO_G[1] +set_location_assignment PIN_9 -to MONO_G[2] +set_location_assignment PIN_5 -to MONO_B[1] +set_location_assignment PIN_8 -to MONO_B[2] + +# MUX Control Signals +# =================== +set_location_assignment PIN_72 -to VIDEO_SRC +set_location_assignment PIN_74 -to MONO_VIDEO_SRC +set_location_assignment PIN_77 -to AUDIO_SRC_L +set_location_assignment PIN_75 -to AUDIO_SRC_R + +# Mainboard Reset Signals +# ======================= +#set_location_assignment PIN_127 -to CPU_RESETn +set_location_assignment PIN_122 -to MB_RESETn +set_location_assignment PIN_111 -to MB_IPLn + +# USB Power Control +# ================= +set_location_assignment PIN_55 -to VBUS_EN + +# Clocks +# ====== +#set_location_assignment PIN_125 -to CPU_CLK +set_location_assignment PIN_128 -to CLK_50M + +# Unused ports +# ============ +#set_location_assignment PIN_42 -to +#set_location_assignment PIN_43 -to +#set_location_assignment PIN_44 -to +#set_location_assignment PIN_45 -to +#set_location_assignment PIN_112 -to +#set_location_assignment PIN_131 -to +#set_location_assignment PIN_117 -to +#set_location_assignment PIN_118 -to +#set_location_assignment PIN_119 -to +#set_location_assignment PIN_120 -to +#set_location_assignment PIN_121 -to +#set_location_assignment PIN_25 -to +#set_location_assignment PIN_53 -to +#set_location_assignment PIN_128 -to +#set_location_assignment PIN_47 -to +#set_location_assignment PIN_54 -to +#set_location_assignment PIN_127 -to +#set_location_assignment PIN_125 -to +#set_location_assignment PIN_48 -to +#set_location_assignment PIN_46 -to +#set_location_assignment PIN_49 -to + + +set_global_assignment -name VHDL_FILE ../tzpuFusionX_Toplevel.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX_pkg.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX.vhd +set_global_assignment -name SDC_FILE tzpuFusionX_MZ2000_constraints.sdc + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name AUTO_RESOURCE_SHARING OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF + +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF +set_global_assignment -name AUTO_LCELL_INSERTION ON + +set_global_assignment -name CDF_FILE output_files/tzpuFusionX_MZ2000.cdf diff --git a/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000_constraints.sdc b/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000_constraints.sdc new file mode 100644 index 000000000..6f2e57520 --- /dev/null +++ b/CPLD/v1.0/MZ2000/build/tzpuFusionX_MZ2000_constraints.sdc @@ -0,0 +1,324 @@ +## Generated SDC file "tzpuFusionX.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jun 26 22:10:05 2020" + +## +## DEVICE "EPM7160STC100-10" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +# Standard mainboard clock. If using tzpuFusionX on a different host then set to the host frequency. +create_clock -name {Z80_CLK} -period 250.000 -waveform { 0.000 125.000 } [get_ports { Z80_CLK }] + +# For 50MHz crystal. +create_clock -name {CLK_50M} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CLK_50M }] + +# For SPI CSn +#create_clock -name {VSOM_SPI_CSn} -period 200.000 -waveform { 160.000 40.000 } [ get_ports { VSOM_SPI_CSn }] + +# For SPI CLK +create_clock -name {VSOM_SPI_CLK} -period 14.000 -waveform { 0.000 7.000 } [ get_ports { VSOM_SPI_CLK }] + +# For basic board with oscillator. +#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }] +#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ] +##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSEL}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HI_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {R_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {G_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {B_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {COLR_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CSYNC_IN}] +##set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {HSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CS2n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A18_INTn_V_R}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSRQn_V_G}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A16_WAITn_V_B}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A17_NMIn_V_COLR}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RFSHn}] + +# For K64F +#set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}] + +# For basic board with oscillator. +#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}] + +#************************************************************** +# Set Max Delay +#************************************************************** +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 30.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 50.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 60.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 60.000 + +#************************************************************** +# Set Min Delay +#************************************************************** +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +# For K64F +#set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For basic board with oscillator. +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For both configurations. +#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} + +#************************************************************** +# Set Multicycle Path +#************************************************************** +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/CPLD/v1.0/MZ2000/tzpuFusionX.vhd b/CPLD/v1.0/MZ2000/tzpuFusionX.vhd new file mode 100644 index 000000000..75b688022 --- /dev/null +++ b/CPLD/v1.0/MZ2000/tzpuFusionX.vhd @@ -0,0 +1,985 @@ +------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX.vhd +-- Version: MZ-2000 +-- Created: June 2020 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD logic definition file. +-- This module contains the definition of the tzpuFusionX project plus enhancements +-- for the MZ-2000. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: Oct 2022 - Initial write for the MZ-2000. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use work.tzpuFusionX_pkg.all; + +entity cpld512 is + generic ( + SPI_CLK_POLARITY : std_logic := '0' + ); + port ( + -- Z80 Address Bus + Z80_ADDR : inout std_logic_vector(15 downto 0); + + -- Z80 Data Bus + Z80_DATA : inout std_logic_vector(7 downto 0); + + -- Z80 Control signals. + Z80_BUSRQn : in std_logic; + Z80_BUSAKn : out std_logic; + Z80_INTn : in std_logic; + Z80_IORQn : inout std_logic; + Z80_MREQn : inout std_logic; + Z80_NMIn : in std_logic; + Z80_RDn : inout std_logic; + Z80_WRn : inout std_logic; + Z80_RESETn : in std_logic; -- Host CPU Reset signal, also CPLD reset. + Z80_HALTn : out std_logic; + Z80_WAITn : in std_logic; + Z80_M1n : inout std_logic; + Z80_RFSHn : inout std_logic; + + -- SOM Control Signals + VSOM_SPI_CLK : in std_logic; -- SOM SPI Channel 0 Clock. + VSOM_SPI_MOSI : in std_logic; -- MOSI Input. + VSOM_SPI_MISO : out std_logic; -- MISO Output. + VSOM_SPI_CSn : in std_logic; -- Enable. + + -- SOM Parallel Bus. + VSOM_DATA_OUT : out std_logic_vector(7 downto 0); -- Address/Data bus for CPLD control registers. + VSOM_HBYTE : in std_logic; -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY : out std_logic; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE : out std_logic; -- Last T-State in current cycle, 1 = active. + VSOM_BUSRQ : out std_logic; -- Host device requesting Z80 Bus. + VSOM_BUSACK : out std_logic; -- Host device granted Z80 Bus + VSOM_INT : out std_logic; -- Z80 INT signal + VSOM_NMI : out std_logic; -- Z80 NMI signal + VSOM_WAIT : out std_logic; -- Z80 WAIT signal + VSOM_RESET : out std_logic; -- Z80 RESET signal + VSOM_RSV : out std_logic_vector(1 downto 1); -- Reserved pins. + + -- SOM Control Signals + PM_RESET : out std_logic; -- Reset SOM + + -- VGA_Palette Control + VGA_R : in std_logic_vector(9 downto 7); -- Signals used for detecting blank or no video output. + VGA_G : in std_logic_vector(9 downto 7); + VGA_B : in std_logic_vector(9 downto 8); + + -- VGA Control Signals + VGA_PXL_CLK : in std_logic; -- VGA Pixel clock for DAC conversion. + VGA_DISPEN : in std_logic; -- Displayed Enabled (SOM video output). + VGA_VSYNCn : in std_logic; -- SOM VSync. + VGA_HSYNCn : in std_logic; -- SOM HSync. + VGA_COLR : out std_logic; -- COLR colour carrier frequency. + VGA_CSYNCn : out std_logic; -- VGA Composite Sync. + VGA_BLANKn : out std_logic; -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK : out std_logic; -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn : out std_logic; -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn : out std_logic; -- Mono CRT composite sync. + MONO_RSV : out std_logic; + + -- CRT Lower Chrominance Control + MONO_R : out std_logic_vector(2 downto 0); -- Signals to fine tune Red level of monochrome chrominance. + MONO_G : out std_logic_vector(2 downto 0); -- Signals to fine tune Green level of monochrome chrominance. + MONO_B : out std_logic_vector(2 downto 1); -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC : out std_logic; -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC : out std_logic; -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L : out std_logic; -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R : out std_logic; -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals + MB_RESETn : in std_logic; -- Motherboard Reset pressed. + MB_IPLn : in std_logic; -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN : out std_logic; -- USB Enable Power Output + + -- Clocks. + Z80_CLK : in std_logic; -- Host CPU Clock + CLK_50M : in std_logic -- 50MHz oscillator. + ); +end entity; + +architecture rtl of cpld512 is + + -- Finite State Machine states. + type SOMFSMState is + ( + IdleCycle, + FetchCycle, + FetchCycle_11, + FetchCycle_20, + FetchCycle_21, + FetchCycle_30, + RefreshCycle, + RefreshCycle_11, + RefreshCycle_20, + RefreshCycle_21, + RefreshCycle_3, + WriteCycle, + WriteCycle_11, + WriteCycle_20, + WriteCycle_21, + WriteCycle_30, + WriteCycle_31, + ReadCycle, + ReadCycle_11, + ReadCycle_20, + ReadCycle_21, + ReadCycle_30, + ReadCycle_31, + WriteIOCycle, + WriteIOCycle_11, + WriteIOCycle_20, + WriteIOCycle_21, + WriteIOCycle_30, + WriteIOCycle_31, + WriteIOCycle_40, + WriteIOCycle_41, + ReadIOCycle, + ReadIOCycle_11, + ReadIOCycle_20, + ReadIOCycle_21, + ReadIOCycle_30, + ReadIOCycle_31, + ReadIOCycle_40, + ReadIOCycle_41, + HaltCycle, + BusReqCycle + ); + + -- CPU Interface internal signals. + signal Z80_BUSRQni : std_logic; + signal Z80_INTni : std_logic; + signal Z80_IORQni : std_logic; + signal Z80_MREQni : std_logic; + signal Z80_NMIni : std_logic; + signal Z80_RDni : std_logic; + signal Z80_WRni : std_logic; + signal Z80_HALTni : std_logic; + signal Z80_M1ni : std_logic; + signal Z80_RFSHni : std_logic; + signal Z80_DATAi : std_logic_vector(7 downto 0); + signal Z80_BUSRQ_ACKni : std_logic; + + -- Internal CPU state control. + signal CPU_ADDR : std_logic_vector(15 downto 0) := (others => '0'); + signal CPU_DATA_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal CPU_DATA_OUT : std_logic_vector(7 downto 0) := (others => '0'); + signal CPU_DATA_EN : std_logic; + + -- Clocks. + signal CLK_25Mi : std_logic := '0'; + + -- Reset control + signal PM_RESETi : std_logic := '1'; + signal VSOM_RESETni : std_logic := '1'; + + -- Refresh control. + signal FSM_STATE : SOMFSMState := IdleCycle; + signal NEW_SPI_CMD : std_logic := '0'; + signal VCPU_CS_EDGE : std_logic_vector(1 downto 0) := "11"; + signal AUTOREFRESH_CNT : integer range 0 to 7; + signal FSM_STATUS : std_logic := '0'; + signal FSM_CHECK_WAIT : std_logic := '0'; + signal FSM_WAIT_ACTIVE : std_logic := '0'; + signal RFSH_STATUS : std_logic := '0'; + signal REFRESH_ADDR : std_logic_vector(7 downto 0); + signal IPAR : std_logic_vector(7 downto 0); + signal AUTOREFRESH : std_logic; + + -- Clock edge detection and flagging. + signal Z80_CLKi : std_logic; + signal Z80_CLK_LAST : std_logic_vector(1 downto 0); + signal Z80_CLK_RE : std_logic; + signal Z80_CLK_FE : std_logic; + signal Z80_CLK_TGL : std_logic; + signal CPU_T_STATE_SET : integer range 0 to 5; + signal CPU_LAST_T_STATE : std_logic := '0'; + + -- SPI Slave interface. + signal SPI_SHIFT_EN : std_logic; + signal SPI_TX_SREG : std_logic_vector(6 downto 0); -- TX Shift Register + signal SPI_RX_SREG : std_logic_vector(7 downto 0); -- RX Shift Register + signal SPI_TX_DATA : std_logic_vector(31 downto 0); -- Data to transmit. + signal SPI_RX_DATA : std_logic_vector(31 downto 0); -- Data received. + signal SPI_BIT_CNT : integer range 0 to 16; -- Count of bits tx/rx'd. + signal SPI_FRAME_CNT : integer range 0 to 4; -- Number of frames received (8bit chunks). + + -- SPI Command interface. + signal SOM_CMD : std_logic_vector(7 downto 0) := (others => '0'); + signal SPI_NEW_DATA : std_logic; + signal SPI_PROCESSING : std_logic; + signal SPI_CPU_ADDR : std_logic_vector(15 downto 0) := (others => '0'); + signal SPI_CPU_DATA : std_logic_vector(7 downto 0) := (others => '0'); + + -- Test modes. + signal SPI_LOOPBACK_TEST : std_logic := '0'; + + -- Video/Audio control + signal VIDEO_SRCi : std_logic := '0'; + signal MONO_VIDEO_SRCi : std_logic := '0'; + signal AUDIO_SRC_Li : std_logic := '0'; + signal AUDIO_SRC_Ri : std_logic := '0'; + signal VBUS_ENi : std_logic := '1'; + + + function to_std_logic(L: boolean) return std_logic is + begin + if L then + return('1'); + else + return('0'); + end if; + end function to_std_logic; +begin + + + -- System RESET. + -- + -- Multiple reset sources, Z80_RESETn, MB_IPLn, MB_RESETn. On the MZ-2000, MB_IPLn is a full reset where all the gate array + -- registers are reset and the memory map resets to the power on state for initial program loading. MB_RESETn is a warm + -- restart for loaded programs, ie. keeps the programmed memory state but resets the Z80 which automatically executes the + -- loaded program. Like the MZ-700, we trigger on Z80_RESETn after having sampled the MB_IPLn and MB_RESETn states to decide + -- on any extra actions needed within the CPLD and the signals are forwarded onto the SOM so it too can take the correct + -- reset path. + -- + -- If the external reset switch is pressed, a Z80_RESETn is invoked sending the signal low for approx 30ms. + -- On the first edge the VSOM_RESETn signal is set which allows the SOM to see it and the Z80 application to enter a reset state. + -- On the second edge, if occurring within 1 second of the first, the PM_RESET signal to the SOM is triggered, held low for 1 second, + -- forcing the SOM to reboot. + SYSRESET: process( Z80_CLKi, Z80_RESETn ) + variable timer1 : integer range 0 to 354000 := 0; + variable timer100 : integer range 0 to 10 := 0; + variable timerPMReset : integer range 0 to 10 := 0; + variable resetCount : integer range 0 to 3 := 0; + variable cpuResetEdge : std_logic := '1'; + begin + -- Synchronous on the HOST Clock. + if(rising_edge(Z80_CLKi)) then + + -- If the PM Reset timer is active, count down and on expiry release the SOM PM_RESET line. + if(timerPMReset = 0 and PM_RESETi = '1') then + PM_RESETi <= '0'; + end if; + + -- If the VSOM_RESETni is active after reset timer expiry, cancel the RESET state. + if(timerPMReset = 0 and VSOM_RESETni = '0') then + VSOM_RESETni <= '1'; + end if; + + -- Each time the reset button is pressed, count the edges. + if(Z80_RESETn = '0' and cpuResetEdge = '1' and (resetCount = 0 or timer100 > 5)) then + resetCount := resetCount + 1; + VSOM_RESETni <= '0'; + timerPMReset := 5; + timer100 := 0; + + -- If there are 2 or more reset signals in a given period it means a SOM reset is required. + if(resetCount >= 2) then + PM_RESETi <= '1'; + timerPMReset := 10; + resetCount := 0; + end if; + + end if; + + -- 100ms interval. + if(timer1 = 354000) then + timer100 := timer100 + 1; + + if(timer100 >= 10) then + timer100 := 0; + resetCount := 0; + end if; + + if(timerPMReset > 0) then + timerPMReset := timerPMReset - 1; + end if; + end if; + + timer1 := timer1 - 1; + cpuResetEdge := Z80_RESETn; + end if; + end process; + + -- Create Mono DAC Clock based on primary clock. + MONOCLK: process( CLK_50M ) + begin + if(rising_edge(CLK_50M)) then + CLK_25Mi <= not CLK_25Mi; + end if; + end process; + + -- SPI Slave input. Receive command and data from the SOM. + SPI_INPUT : process(VSOM_SPI_CLK) + begin + -- SPI_CLK_POLARITY='0' => falling edge; SPI_CLK_POLARITY='1' => rising edge + if(VSOM_SPI_CLK'event and VSOM_SPI_CLK = SPI_CLK_POLARITY) then + if(VSOM_SPI_CSn = '0') then + SPI_RX_SREG <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + -- End of frame then store the data prior to next bit arrival. + -- Convert to Little Endian, same as SOM. + if(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 1 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(7 downto 0) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 2 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(15 downto 8) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 3 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(23 downto 16) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 4 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(31 downto 24) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + end if; + end if; + end if; + end process; + + -- SPI Slave output. Return the current data set as selected by the input signals XACT. + SPI_OUTPUT : process(VSOM_SPI_CLK,VSOM_SPI_CSn,SPI_TX_DATA) + begin + if(VSOM_SPI_CSn = '1') then + SPI_SHIFT_EN <= '0'; + SPI_BIT_CNT <= 15; + + -- SPI_CLK_POLARITY='0' => falling edge; SPI_CLK_POLARITY='1' => risinge edge + elsif(VSOM_SPI_CLK'event and VSOM_SPI_CLK = not SPI_CLK_POLARITY) then + SPI_SHIFT_EN <= '1'; + + if(SPI_BIT_CNT > 0) then + SPI_BIT_CNT <= SPI_BIT_CNT - 1; + end if; + + VSOM_SPI_MISO <= SPI_TX_SREG(6); + SPI_TX_SREG <= SPI_TX_SREG(5 downto 0) & '0'; + + -- First clock after CS goes active, load up the data to be sent to the SOM. + if(SPI_SHIFT_EN = '0' or SPI_BIT_CNT = 0) then + + if(SPI_LOOPBACK_TEST = '1') then + VSOM_SPI_MISO<= SPI_RX_SREG(7); + SPI_TX_SREG <= SPI_RX_SREG(6 downto 0); + + elsif(SPI_SHIFT_EN = '0') then + SPI_FRAME_CNT<= 1; + VSOM_SPI_MISO<= SPI_TX_DATA(7); + SPI_TX_SREG <= SPI_TX_DATA(6 downto 0); + elsif(SPI_FRAME_CNT = 1) then + SPI_FRAME_CNT<= 2; + VSOM_SPI_MISO<= SPI_TX_DATA(15); + SPI_TX_SREG <= SPI_TX_DATA(14 downto 8); + elsif(SPI_FRAME_CNT = 2) then + SPI_FRAME_CNT<= 3; + VSOM_SPI_MISO<= SPI_TX_DATA(23); + SPI_TX_SREG <= SPI_TX_DATA(22 downto 16); + else + -- Increment frame count for each word received. We handle 8bit (1 frame), 16bit (2 frames) or 32bit (4 frames) reception. + SPI_FRAME_CNT<= 4; + VSOM_SPI_MISO<= SPI_TX_DATA(31); + SPI_TX_SREG <= SPI_TX_DATA(30 downto 24); + end if; + + SPI_BIT_CNT <= 7; + end if; + end if; + end process; + + SPI_REGISTER : process(Z80_RESETn, VSOM_SPI_CSn, SPI_FRAME_CNT) + begin + if(Z80_RESETn = '0') then + VIDEO_SRCi <= '0'; + VGA_BLANKn <= '1'; + VBUS_ENi <= '1'; + MONO_VIDEO_SRCi <= '1'; + AUDIO_SRC_Li <= '0'; + AUDIO_SRC_Ri <= '0'; + AUTOREFRESH <= '0'; + SPI_LOOPBACK_TEST <= '0'; + SOM_CMD <= (others => '0'); + SPI_CPU_ADDR <= (others => '0'); + SPI_NEW_DATA <= '0'; + + -- On rising edge of SPI CSn a new data packet from the SOM has arrived and in the shift register SPI_RX_SREG. + -- The variable SPI_FRAME_CNT indicates which byte (frame) in a 32bit word has been transmitted. This allows + -- for 8bit, 16bit and 32bit transmissions. + -- The packet is formatted as follows: + -- + -- < SPI_FRAME_CNT=4 >< SPI_FRAME=3 > < SPI_FRAME_CNT=2 >< SPI_FRAME_CNT=1> + -- < 16bit Z80 Address > < Z80 Data > + -- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + -- < > < Data > + -- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + elsif(VSOM_SPI_CSn'event and VSOM_SPI_CSn = '1') then + + -- Command is always located in the upper byte of frame 1. + SOM_CMD <= SPI_RX_DATA(7 downto 0); + + -- Toggle flag to indicate new data arrived. + SPI_NEW_DATA <= not SPI_NEW_DATA; + + -- Process the command. Some commands require the FSM, others can be serviced immediately. + case SPI_RX_DATA(7 downto 0) is + + -- Z80XACT(0..15): Setup data and address as provided then execute FSM. + when X"10" | X"11" | X"12" | X"13" | X"14" | X"15" | X"16" | X"17" | -- Fetch + X"18" | X"19" | X"1A" | X"1B" | X"1C" | X"1D" | X"1E" | X"1F" | -- Write + X"20" | X"21" | X"22" | X"23" | X"24" | X"25" | X"26" | X"27" | -- Read + X"28" | X"29" | X"2A" | X"2B" | X"2C" | X"2D" | X"2E" | X"2F" | -- WriteIO + X"30" | X"31" | X"32" | X"33" | X"34" | X"35" | X"36" | X"37" | -- ReadIO + X"38" | X"39" | X"3A" | X"3B" | X"3C" | X"3D" | X"3E" | X"3F" | -- + X"40" | X"41" | X"42" | X"43" | X"44" | X"45" | X"46" | X"47" | -- + X"48" | X"49" | X"4A" | X"4B" | X"4C" | X"4D" | X"4E" | X"4F" => + + -- Direct address set. + if(SPI_FRAME_CNT = 4) then + SPI_CPU_ADDR <= SPI_RX_DATA(31 downto 16); + else + -- if(SPI_CPU_ADDR >= X"D010" and SPI_CPU_ADDR < X"D020") then + -- SPI_CPU_ADDR <= std_logic_vector(X"D020" + unsigned(SPI_RX_DATA(2 downto 0))); + -- else + SPI_CPU_ADDR <= std_logic_vector(unsigned(SPI_CPU_ADDR) + unsigned(SPI_RX_DATA(2 downto 0))); + -- end if; + end if; + + if(SPI_FRAME_CNT > 1) then + SPI_CPU_DATA <= SPI_RX_DATA(15 downto 8); + end if; + + -- SETSIGSET1: Set control lines directly. + when X"F0" => + VIDEO_SRCi <= SPI_RX_DATA(8); + MONO_VIDEO_SRCi <= SPI_RX_DATA(9); + AUDIO_SRC_Li <= SPI_RX_DATA(10); + AUDIO_SRC_Ri <= SPI_RX_DATA(11); + VBUS_ENi <= SPI_RX_DATA(12); + VGA_BLANKn <= not SPI_RX_DATA(13); + + -- Enable auto refresh DRAM cycle. + when X"F1" => + AUTOREFRESH <= '1'; + + -- Disable auto refresh DRAM cycle. + when X"F2" => + AUTOREFRESH <= '0'; + + -- SETLOOPBACK: Enable loopback test mode. + when X"FE" => + SPI_LOOPBACK_TEST<= '1'; + + -- No action, called to retrieve status. + when X"00" | X"FF" => + + when others => + end case; + end if; + end process; + + -- Process to detect the Z80 Clock edges. Each edge is used to recreate the Z80 external signals. + -- + Z80CLK: process( CLK_50M, Z80_CLKi, Z80_RESETn ) + begin + if(Z80_RESETn = '0') then + Z80_CLK_RE <= '1'; + Z80_CLK_FE <= '1'; + Z80_CLK_TGL <= '1'; + + elsif(rising_edge(CLK_50M)) then + + -- Default is to clear the signals, only active for 1 clock period. + Z80_CLK_RE <= '0'; + Z80_CLK_FE <= '0'; + Z80_CLK_TGL <= '0'; + + -- Rising Edge. + if(Z80_CLKi = '1' and Z80_CLK_LAST = "00") then + Z80_CLK_RE <= '1'; + + -- Toggle on rising edge is delayed by one clock to allow time for command to be decoded. + elsif(Z80_CLKi = '1' and Z80_CLK_LAST = "01") then + Z80_CLK_TGL <= '1'; + + -- Falling Edge. + elsif(Z80_CLKi = '0' and Z80_CLK_LAST = "11") then + Z80_CLK_FE <= '1'; + Z80_CLK_TGL <= '1'; + end if; + Z80_CLK_LAST <= Z80_CLK_LAST(0) & Z80_CLKi; + end if; + end process; + + -- SOM Finite State Machine. + -- + -- A command processor, based on an FSM concept, to process requested commands, ie. Z80 Write, Z80 Read etc. + -- The external signal SOM_CMD_EN, when set, indicates a new command available in SOM_CMD. + -- + SOMFSM: process( CLK_50M, Z80_CLKi, Z80_RESETn ) + begin + if(Z80_RESETn = '0') then + Z80_IORQni <= '1'; + Z80_MREQni <= '1'; + Z80_RDni <= '1'; + Z80_WRni <= '1'; + Z80_HALTni <= '1'; + Z80_M1ni <= '1'; + Z80_RFSHni <= '1'; + Z80_BUSRQ_ACKni <= '1'; + FSM_CHECK_WAIT <= '0'; + FSM_WAIT_ACTIVE <= '0'; + FSM_STATUS <= '0'; + FSM_STATE <= IdleCycle; + RFSH_STATUS <= '0'; + CPU_DATA_EN <= '0'; + CPU_DATA_IN <= (others => '0'); + REFRESH_ADDR <= (others => '0'); + AUTOREFRESH_CNT <= 7; + IPAR <= (others => '0'); + NEW_SPI_CMD <= '0'; + VCPU_CS_EDGE <= "11"; + SPI_PROCESSING <= '0'; + + elsif(rising_edge(CLK_50M)) then + + -- Bus request mechanism. If an externel Bus Request comes in and the FSM is idle, run the Bus Request command which + -- suspends processing and tri-states the bus. + if(Z80_BUSRQn = '0' and Z80_BUSRQ_ACKni = '1' and FSM_STATE = IdleCycle) then + FSM_STATE <= BusReqCycle; + end if; + if(Z80_BUSRQn = '1' and Z80_BUSRQ_ACKni = '0' and FSM_STATE = IdleCycle) then + Z80_BUSRQ_ACKni <= '1'; + end if; + + -- New command, set flag as the signal is only 1 clock wide. + if(SPI_LOOPBACK_TEST = '0' and VSOM_SPI_CSn = '1' and VCPU_CS_EDGE = "01") then + NEW_SPI_CMD <= '1'; + end if; + + -- Whenever we return to Idle or just prior to Refresh from a Fetch cycle set all control signals to default. + if(FSM_STATE = IdleCycle or FSM_STATE = RefreshCycle) then + CPU_DATA_EN <= '0'; + Z80_MREQni <= '1'; + Z80_IORQni <= '1'; + Z80_RDni <= '1'; + Z80_WRni <= '1'; + Z80_M1ni <= '1'; + FSM_STATUS <= '0'; + Z80_RFSHni <= '1'; + + -- Auto DRAM refresh cycles. When enabled, every 7 host clock cycles, a 2 cycle refresh period commences. + -- This will be overriden if the SPI receives a new command. + -- + if AUTOREFRESH = '1' and FSM_STATE = IdleCycle then + AUTOREFRESH_CNT <= AUTOREFRESH_CNT - 1; + if(AUTOREFRESH_CNT = 0) then + FSM_STATE <= RefreshCycle_3; + end if; + end if; + end if; + + -- If new command has been given and the FSM enters idle state, load up new command for processing. + if(NEW_SPI_CMD = '1' and FSM_STATE = IdleCycle and Z80_CLK_RE = '1') then + NEW_SPI_CMD <= '0'; + + -- Store new address and data for this command. + CPU_ADDR <= SPI_CPU_ADDR; + if(SPI_CPU_DATA /= CPU_DATA_OUT) then + CPU_DATA_OUT <= SPI_CPU_DATA; + end if; + + -- Process the SOM command. The SPI_REGISTER executes non FSM commands and stores FSM + -- data prior to this execution block, which fires 1 cycle later on the same control clock. + -- If the command is not for the FSM then the READY mechanism is held for one + -- further cycle before going inactive. + case SOM_CMD is + when X"10" | X"11" | X"12" | X"13" | X"14" | X"15" | X"16" | X"17" => + -- Initiate a Fetch Cycle. + FSM_STATE <= FetchCycle; + + when X"18" | X"19" | X"1A" | X"1B" | X"1C" | X"1D" | X"1E" | X"1F" => + + -- Set the Z80 data bus value and initiate a Write Cycle. + FSM_STATE <= WriteCycle; + + when X"20" | X"21" | X"22" | X"23" | X"24" | X"25" | X"26" | X"27" => + -- Initiate a Read Cycle. + FSM_STATE <= ReadCycle; + + when X"28" | X"29" | X"2A" | X"2B" | X"2C" | X"2D" | X"2E" | X"2F" => + -- Set the Z80 data bus value and initiate an IO Write Cycle. + -- The SOM should set 15:8 to the B register value. + FSM_STATE <= WriteIOCycle; + + when X"30" | X"31" | X"32" | X"33" | X"34" | X"35" | X"36" | X"37" => + -- Initiate a Read IO Cycle. + FSM_STATE <= ReadIOCycle; + + when X"50" => + -- Register a Halt state. + FSM_STATE <= HaltCycle; + + when X"51" => + -- Initiate a refresh cycle. + FSM_STATE <= RefreshCycle_3; + + when X"E0" => + -- Initiate a Halt Cycle. + FSM_STATE <= HaltCycle; + + -- Set the Refresh Address register. + when X"E1" => + REFRESH_ADDR <= CPU_DATA_OUT; + + -- Set the Interrupt Page Address Register. + when X"E2" => + IPAR <= CPU_DATA_OUT; + + when others => + end case; + + -- Toggle the processing flag to negate the new data flag. Used to indicate device is busy. + if(SPI_NEW_DATA /= SPI_PROCESSING) then + SPI_PROCESSING <= not SPI_PROCESSING; + end if; + + -- FSM Status bit. When processing a command it is set, cleared when idle. Used by SOM to determine command completion. + FSM_STATUS <= '1'; + end if; + + -- Refresh status bit. Indicates a Refresh cycle is under way. + if FSM_STATE = RefreshCycle or FSM_STATE = RefreshCycle_11 or FSM_STATE = RefreshCycle_20 or FSM_STATE = RefreshCycle_21 or FSM_STATE = RefreshCycle_3 then + RFSH_STATUS <= '1'; + else + RFSH_STATUS <= '0'; + end if; + + -- If we are in a WAIT sampling 1/2 cycle and wait goes active, set the state so we repeat the full clock cycle by winding back 2 places. + if(FSM_CHECK_WAIT = '1' and Z80_WAITn = '0' and Z80_CLK_TGL = '0') then + FSM_WAIT_ACTIVE <= '1'; + end if; + + -- On each Z80 edge we advance the FSM to recreate the Z80 external signal transactions. + if(Z80_CLK_TGL = '1') then + + -- The FSM advances to the next stage on each Z80 edge unless in Idle state. + if(FSM_STATE /= IdleCycle) then + FSM_STATE <= SOMFSMState'val(SOMFSMState'POS(FSM_STATE)+1); + end if; + + -- Half cycle expired so we dont check the Z80 wait again. + FSM_CHECK_WAIT <= '0'; + FSM_WAIT_ACTIVE <= '0'; + + -- FSM to implement all the required Z80 cycles. + -- + case FSM_STATE is + + when IdleCycle => + CPU_LAST_T_STATE <= '1'; + -- FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 Fetch Cycle. + ----------------------------- + when FetchCycle => + Z80_M1ni <= '0'; + + when FetchCycle_11 => + Z80_M1ni <= '0'; + Z80_MREQni <= '0'; + Z80_RDni <= '0'; + + when FetchCycle_20 => + FSM_CHECK_WAIT <= '1'; + + when FetchCycle_21 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= FetchCycle_20; + end if; + + when FetchCycle_30 => + -- To meet the timing diagrams, just after Rising edge on T3 clear signals. Data wont be available until + -- a short period before the falling edge of T3 (could be an MZ-2000 design restriction or the Z80 timing diagrams are a bit out). + FSM_STATE <= RefreshCycle; + + ----------------------------- + -- Z80 Refresh Cycle. + ----------------------------- + when RefreshCycle => + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + Z80_RFSHni <= '0'; + + when RefreshCycle_11 => + -- Falling edge of T3 activates the MREQ line. + Z80_MREQni <= '0'; + + when RefreshCycle_20 => + + when RefreshCycle_21 => + Z80_MREQni <= '1'; + REFRESH_ADDR(6 downto 0) <= REFRESH_ADDR(6 downto 0) + 1; + FSM_STATE <= IdleCycle; + + when RefreshCycle_3 => + Z80_RFSHni <= '0'; + FSM_STATE <= RefreshCycle_11; + + ----------------------------- + -- Z80 Write Cycle. + ----------------------------- + when WriteCycle => + + when WriteCycle_11 => + Z80_MREQni <= '0'; + CPU_DATA_EN <= '1'; + + when WriteCycle_20 => + FSM_CHECK_WAIT <= '1'; + + when WriteCycle_21 => + Z80_WRni <= '0'; + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= WriteCycle_20; + end if; + + when WriteCycle_30 => + + when WriteCycle_31 => + FSM_STATUS <= '0'; + Z80_MREQni <= '1'; + Z80_WRni <= '1'; + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 Read Cycle. + ----------------------------- + when ReadCycle => + + when ReadCycle_11 => + Z80_MREQni <= '0'; + Z80_RDni <= '0'; + + when ReadCycle_20 => + FSM_CHECK_WAIT <= '1'; + + when ReadCycle_21 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= ReadCycle_20; + end if; + + when ReadCycle_30 => + + when ReadCycle_31 => + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + FSM_STATE <= IdleCycle; + + + ----------------------------- + -- Z80 IO Write Cycle. + ----------------------------- + when WriteIOCycle => + + when WriteIOCycle_11 => + CPU_DATA_EN <= '1'; + + when WriteIOCycle_20 => + Z80_IORQni <= '0'; + Z80_WRni <= '0'; + + when WriteIOCycle_21 => + + when WriteIOCycle_30 => + FSM_CHECK_WAIT <= '1'; + + when WriteIOCycle_31 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= WriteIOCycle_20; + end if; + + when WriteIOCycle_40 => + + when WriteIOCycle_41 => + FSM_STATUS <= '0'; + Z80_IORQni <= '1'; + Z80_WRni <= '1'; + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 IO Read Cycle. + ----------------------------- + when ReadIOCycle => + + when ReadIOCycle_11 => + + when ReadIOCycle_20 => + Z80_IORQni <= '0'; + Z80_RDni <= '0'; + + when ReadIOCycle_21 => + + when ReadIOCycle_30 => + FSM_CHECK_WAIT <= '1'; + + when ReadIOCycle_31 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= ReadIOCycle_20; + end if; + + when ReadIOCycle_40 => + + when ReadIOCycle_41 => + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + + -- IORQ/RD are deactivated at idle giving 1 clock to latch the data in. + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Halt Request. + ----------------------------- + when HaltCycle => + Z80_HALTni <= '0'; + FSM_STATUS <= '0'; + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 Bus Request. + ----------------------------- + when BusReqCycle => + Z80_BUSRQ_ACKni <= '0'; + FSM_STATE <= IdleCycle; + + when others => + FSM_STATE <= IdleCycle; + end case; + end if; + + VCPU_CS_EDGE <= VCPU_CS_EDGE(0) & VSOM_SPI_CSn; + end if; + end process; + + Z80_CLKi <= not Z80_CLK; + + -- CPU Interface tri-state control based on acknowledged bus request. + Z80_ADDR <= IPAR & REFRESH_ADDR when Z80_RFSHni = '0' + else + CPU_ADDR when Z80_BUSRQ_ACKni = '1' + else + (others => 'Z'); + Z80_DATA <= CPU_DATA_OUT when Z80_BUSRQ_ACKni = '1' and CPU_DATA_EN = '1' + else + (others => 'Z'); + -- Z80_DATAi <= Z80_DATA when Z80_RDn = '0' + -- else (others => '1'); + Z80_RDn <= Z80_RDni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_WRn <= Z80_WRni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_M1n <= Z80_M1ni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_RFSHn <= Z80_RFSHni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_MREQn <= Z80_MREQni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_IORQn <= Z80_IORQni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_BUSAKn <= Z80_BUSRQ_ACKni; + + -- CPU Interface single state output. + Z80_HALTn <= Z80_HALTni; + + -- CPU Interface single state input. + Z80_NMIni <= Z80_NMIn; + Z80_INTni <= Z80_INTn; + Z80_BUSRQni <= Z80_BUSRQn; + + -- SOM Reset. + PM_RESET <= PM_RESETi; + + -- SOM to CPLD Interface. + VSOM_DATA_OUT <= CPU_DATA_IN when VSOM_HBYTE = '1' + else + FSM_STATUS & RFSH_STATUS & Z80_BUSRQ_ACKni & Z80_BUSRQni & Z80_INTni & Z80_NMIni & Z80_WAITn & Z80_RESETn when VSOM_HBYTE = '0' + else + (others => '0'); + + -- Loopback test, echo what was received. + SPI_TX_DATA <= SPI_RX_DATA when SPI_LOOPBACK_TEST = '1' + else + --CPU_ADDR & SOM_CMD & FSM_STATUS & RFSH_STATUS & std_logic_vector(to_unsigned(SOMFSMState'POS(FSM_STATE), 6)); + CPU_ADDR & CPU_DATA_IN & FSM_STATUS & RFSH_STATUS & Z80_BUSRQ_ACKni & Z80_BUSRQni & Z80_INTni & Z80_NMIni & Z80_WAITn & Z80_RESETn; + + -- Signal mirrors. + VSOM_READY <= '0' when FSM_STATUS='1' or SPI_NEW_DATA /= SPI_PROCESSING + else '1'; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE <= '1' when CPU_LAST_T_STATE = '1' -- Last T-State in current cycle. + else '0'; + VSOM_BUSRQ <= not Z80_BUSRQn; -- Host device requesting Z80 Bus. + VSOM_BUSACK <= not Z80_BUSRQ_ACKni; -- Host device granted Z80 Bus + VSOM_INT <= not Z80_INTn; -- Z80 INT signal + VSOM_NMI <= not Z80_NMIn; -- Z80 NMI signal + VSOM_WAIT <= not Z80_WAITn; -- Z80 WAIT signal + VSOM_RESET <= not VSOM_RESETni; -- Z80 RESET signal + VSOM_RSV <= (others => '0'); -- Reserved pins. + + -- Video/Audio control signals. + VIDEO_SRC <= VIDEO_SRCi; + MONO_VIDEO_SRC <= MONO_VIDEO_SRCi; + AUDIO_SRC_L <= AUDIO_SRC_Li; + AUDIO_SRC_R <= AUDIO_SRC_Ri; + + -- USB Power Supply enable. + VBUS_EN <= VBUS_ENi; + + -- Monochrome output is based on the incoming VGA to give the best chrominance levels. + MONO_R <= VGA_R; + MONO_G <= VGA_G; + MONO_B <= VGA_B; + + -- Blanking is active when all colour signals are at 0. The DAC converts values in range 4v .. 5v to adjust chrominance + -- but true off can obly be achieved by bringing the signal value to 0v which is achieved by a Mux activated with this blanking signal. + MONO_BLANKn <= '0' when VGA_R = "000" and VGA_G = "000" and VGA_B = "000" + else '1'; + + -- Generate composite sync. + VGA_CSYNCn <= VGA_HSYNCn xor not VGA_VSYNCn; + MONO_CSYNCn <= not VGA_HSYNCn xor not VGA_VSYNCn; + + -- DAC clocks. + --VGA_PXL_CLK <= CLK_50M; + MONO_PXL_CLK <= VGA_PXL_CLK; + +end architecture; diff --git a/CPLD/v1.0/MZ2000/tzpuFusionX_Toplevel.vhd b/CPLD/v1.0/MZ2000/tzpuFusionX_Toplevel.vhd new file mode 100644 index 000000000..918c4c582 --- /dev/null +++ b/CPLD/v1.0/MZ2000/tzpuFusionX_Toplevel.vhd @@ -0,0 +1,222 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX_Toplevel.vhd +-- Version: MZ-2000 +-- Created: June 2020 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD Top Level module. +-- +-- This module contains the basic pin definition of the CPLD<->logic needed in the +-- project which targets the MZ-2000 host. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: June 2020 - Snapshot taken from the MZ80A version of the tranZPUter SW-700 source. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.tzpuFusionX_pkg.all; +library altera; +use altera.altera_syn_attributes.all; + +entity tzpuFusionX_MZ2000 is + port ( + -- Z80 Address Bus + Z80_ADDR : inout std_logic_vector(15 downto 0); + + -- Z80 Data Bus + Z80_DATA : inout std_logic_vector(7 downto 0); + + -- Z80 Control signals. + Z80_BUSRQn : in std_logic; + Z80_BUSAKn : out std_logic; + Z80_INTn : in std_logic; + Z80_IORQn : inout std_logic; + Z80_MREQn : inout std_logic; + Z80_NMIn : in std_logic; + Z80_RDn : inout std_logic; + Z80_WRn : inout std_logic; + Z80_RESETn : in std_logic; -- Host CPU Reset signal, also CPLD reset. + Z80_HALTn : out std_logic; + Z80_WAITn : in std_logic; + Z80_M1n : inout std_logic; + Z80_RFSHn : inout std_logic; + + -- SOM SPI + VSOM_SPI_CSn : in std_logic; -- SPI Slave Select + VSOM_SPI_CLK : in std_logic; -- SPI Clock + VSOM_SPI_MOSI : in std_logic; -- SPI Master Output Slave Input + VSOM_SPI_MISO : out std_logic; -- SPI Master Input Slave Output + + -- SOM Parallel Bus. + VSOM_DATA_OUT : out std_logic_vector(7 downto 0); -- Address/Data bus for CPLD control registers. + VSOM_HBYTE : in std_logic; -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY : out std_logic; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE : out std_logic; -- Last T-State in current cycle, 1 = active. + VSOM_BUSRQ : out std_logic; -- Host device requesting Z80 Bus. + VSOM_BUSACK : out std_logic; -- Host device granted Z80 Bus + VSOM_INT : out std_logic; -- Z80 INT signal + VSOM_NMI : out std_logic; -- Z80 NMI signal + VSOM_WAIT : out std_logic; -- Z80 WAIT signal + VSOM_RESET : out std_logic; -- Z80 RESET signal + VSOM_RSV : out std_logic_vector(1 downto 1); -- Reserved pins. + + -- SOM Control Signals + PM_RESET : out std_logic; -- Reset SOM + + -- VGA_Palette Control + VGA_R : in std_logic_vector(9 downto 7); -- Signals used for detecting blank or no video output. + VGA_G : in std_logic_vector(9 downto 7); + VGA_B : in std_logic_vector(9 downto 8); + + -- VGA Control Signals + VGA_PXL_CLK : in std_logic; -- VGA Pixel clock for DAC conversion. + VGA_DISPEN : in std_logic; -- Displayed Enabled (SOM video output). + VGA_VSYNCn : in std_logic; -- SOM VSync. + VGA_HSYNCn : in std_logic; -- SOM HSync. + VGA_COLR : out std_logic; -- COLR colour carrier frequency. + VGA_CSYNCn : out std_logic; -- VGA Composite Sync. + VGA_BLANKn : out std_logic; -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK : out std_logic; -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn : out std_logic; -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn : out std_logic; -- Mono CRT composite sync. + MONO_RSV : out std_logic; + + -- CRT Lower Chrominance Control + MONO_R : out std_logic_vector(2 downto 0); -- Signals to fine tune Red level of monochrome chrominance. + MONO_G : out std_logic_vector(2 downto 0); -- Signals to fine tune Green level of monochrome chrominance. + MONO_B : out std_logic_vector(2 downto 1); -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC : out std_logic; -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC : out std_logic; -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L : out std_logic; -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R : out std_logic; -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals + MB_RESETn : in std_logic; -- Motherboard Reset pressed. + MB_IPLn : in std_logic; -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN : out std_logic; -- USB Enable Power Output + + -- Clocks. + Z80_CLK : in std_logic; -- Host CPU Clock + CLK_50M : in std_logic -- 50MHz oscillator. + ); +END entity; + +architecture rtl of tzpuFusionX_MZ2000 is + +begin + + cpldl512Toplevel : entity work.cpld512 + generic map ( + SPI_CLK_POLARITY => '0' + ) + port map + ( + -- Z80 Address Bus + Z80_ADDR => Z80_ADDR, + + -- Z80 Data Bus + Z80_DATA => Z80_DATA, + + -- Z80 Control signals. + Z80_BUSRQn => Z80_BUSRQn, + Z80_BUSAKn => Z80_BUSAKn, + Z80_INTn => Z80_INTn, + Z80_IORQn => Z80_IORQn, + Z80_MREQn => Z80_MREQn, + Z80_NMIn => Z80_NMIn, + Z80_RDn => Z80_RDn, + Z80_WRn => Z80_WRn, + Z80_RESETn => Z80_RESETn, + Z80_HALTn => Z80_HALTn, + Z80_WAITn => Z80_WAITn, + Z80_M1n => Z80_M1n, + Z80_RFSHn => Z80_RFSHn, + + -- SOM SPI + VSOM_SPI_CSn => VSOM_SPI_CSn, -- SPI Slave Select + VSOM_SPI_CLK => VSOM_SPI_CLK, -- SPI Clock + VSOM_SPI_MOSI => VSOM_SPI_MOSI, -- SPI Master Output Slave Input + VSOM_SPI_MISO => VSOM_SPI_MISO, -- SPI Master Input Slave Output + + -- SOM Parallel Bus. + VSOM_DATA_OUT => VSOM_DATA_OUT, -- Address/Data bus for CPLD control registers. + VSOM_HBYTE => VSOM_HBYTE, -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY => VSOM_READY, -- FSM Ready (1), Busy (0) + VSOM_LTSTATE => VSOM_LTSTATE, -- Last T-State in current cycle. + VSOM_BUSRQ => VSOM_BUSRQ, -- Host device requesting Z80 Bus. + VSOM_BUSACK => VSOM_BUSACK, -- Host device granted Z80 Bus + VSOM_INT => VSOM_INT, -- Z80 INT signal + VSOM_NMI => VSOM_NMI, -- Z80 NMI signal + VSOM_WAIT => VSOM_WAIT, -- Z80 WAIT signal + VSOM_RESET => VSOM_RESET, -- Z80 RESET signal + VSOM_RSV => VSOM_RSV, -- Reserved pins. + + -- SOM Control Signals + PM_RESET => PM_RESET, -- Reset SOM + + -- VGA_Palette Control + VGA_R => VGA_R, -- Signals used for detecting blank or no video output. + VGA_G => VGA_G, + VGA_B => VGA_B, + + -- VGA Control Signals + VGA_PXL_CLK => VGA_PXL_CLK, -- VGA Pixel clock for DAC conversion. + VGA_DISPEN => VGA_DISPEN, -- Displayed Enabled (SOM video output). + VGA_VSYNCn => VGA_VSYNCn, -- SOM VSync. + VGA_HSYNCn => VGA_HSYNCn, -- SOM HSync. + VGA_COLR => VGA_COLR, -- COLR colour carrier frequency. + VGA_CSYNCn => VGA_CSYNCn, -- VGA Composite Sync. + VGA_BLANKn => VGA_BLANKn, -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK => MONO_PXL_CLK, -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn => MONO_BLANKn, -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn => MONO_CSYNCn, -- Mono CRT composite sync. + MONO_RSV => MONO_RSV, + + -- CRT Lower Chrominance Control + MONO_R => MONO_R, -- Signals to fine tune Red level of monochrome chrominance. + MONO_G => MONO_G, -- Signals to fine tune Green level of monochrome chrominance. + MONO_B => MONO_B, -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC => VIDEO_SRC, -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC => MONO_VIDEO_SRC, -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L => AUDIO_SRC_L, -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R => AUDIO_SRC_R, -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals=> MONO_R, + MB_RESETn => MB_RESETn, -- Motherboard Reset pressed. + MB_IPLn => MB_IPLn, -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN => VBUS_EN, -- USB Enable Power Output + + -- Clocks. + Z80_CLK => Z80_CLK, -- Host CPU Clock + CLK_50M => CLK_50M -- 50MHz oscillator. + ); + +end architecture; diff --git a/CPLD/v1.0/MZ2000/tzpuFusionX_pkg.vhd b/CPLD/v1.0/MZ2000/tzpuFusionX_pkg.vhd new file mode 100644 index 000000000..21a493c74 --- /dev/null +++ b/CPLD/v1.0/MZ2000/tzpuFusionX_pkg.vhd @@ -0,0 +1,221 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX_pkg.vhd +-- Created: June 2020 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD configuration file. +-- +-- This module contains parameters for the CPLD in the tzpuFusionX project +-- which targets the MZ-2000 host. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: June 2020 - Snapshot taken from the MZ2000 version of the tranZPUter SW-700 source. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +package tzpuFusionX_pkg is + + ------------------------------------------------------------ + -- Constants + ------------------------------------------------------------ + + -- Potential logic state constants. + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + constant HIZ : std_logic := 'Z'; + + -- CPLD Command instructions. + constant CPLD_CMD_RESET_HOST : integer := 1; + constant CPLD_CMD_HOLD_HOST_BUS : integer := 2; + constant CPLD_CMD_RELEASE_HOST_BUS: integer := 3; + + -- Target hardware modes. + constant MODE_MZ80K : integer := 0; + constant MODE_MZ80C : integer := 1; + constant MODE_MZ1200 : integer := 2; + constant MODE_MZ80A : integer := 3; + constant MODE_MZ700 : integer := 4; + constant MODE_MZ800 : integer := 5; + constant MODE_MZ80B : integer := 6; + constant MODE_MZ2000 : integer := 7; + + -- Memory management modes. + constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063). + constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted. + constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected. + constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1. + constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2. + constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3. + constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected. + -- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_COMPAT : integer := 08; -- Compatibility monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF. + constant TZMM_HOSTACCESS : integer := 09; -- Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory. + constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard. + constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ800 : integer := 15; -- MZ800 Mode - Running on MZ800 hardware, configuration set according to MZ700/MZ800 mode. + constant TZMM_MZ2000 : integer := 16; -- MZ2000 Mode - Running on MZ2000 hardware, configuration set according to runtime configuration registers. + constant TZMM_FPGA : integer := 21; -- Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked. + constant TZMM_TZPUM : integer := 22; -- Everything in on mainboard, no access to tranZPUter memory. + constant TZMM_TZPU : integer := 23; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected. + constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected. + constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected. + constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected. + constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected. + constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected. + constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected. + + + + ------------------------------------------------------------ + -- Configurable parameters. + ------------------------------------------------------------ + -- Target hardware. + constant CPLD_HOST_HW : integer := MODE_MZ700; + + -- Target video hardware. + constant CPLD_HAS_FPGA_VIDEO : std_logic := '1'; + + -- Version of hdl. + constant CPLD_VERSION : integer := 2; + + -- Clock source for the secondary clock. If a K64F is installed then enable it otherwise use the onboard oscillator. + -- + constant USE_K64F_CTL_CLOCK : integer := 1; + + ------------------------------------------------------------ + -- Function prototypes + ------------------------------------------------------------ + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer; + + -- Function to reverse the order of the bits in a standard logic vector. + -- ie. 1010 becomes 0101 + function reverse_vector(slv:std_logic_vector) return std_logic_vector; + + -- Function to convert an integer (0 or 1) into std_logic. + -- + function to_std_logic(i : in integer) return std_logic; + + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural; + + ------------------------------------------------------------ + -- Records + ------------------------------------------------------------ + + ------------------------------------------------------------ + -- Components + ------------------------------------------------------------ + +end tzpuFusionX_pkg; + +------------------------------------------------------------ +-- Function definitions. +------------------------------------------------------------ +package body tzpuFusionX_pkg is + + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer is + begin + if a > b then + return a; + else + return b; + end if; + return a; + end function IntMax; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural is + variable tmp : positive := 1; + variable log : natural := 0; + begin + if arg = 1 then + return 0; + end if; + + while arg > tmp loop + tmp := tmp * 2; + log := log + 1; + end loop; + return log; + end function; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer is + variable ticks : real; + variable fracTicks : real; + begin + ticks := (Real(period) * Real(clock)) / 1000000000.0; + fracTicks := ticks - CEIL(ticks); + if fracTicks > 0.0001 then + return Integer(CEIL(ticks + 1.0)); + else + return Integer(CEIL(ticks)); + end if; + end function; + + function reverse_vector(slv:std_logic_vector) return std_logic_vector is + variable target : std_logic_vector(slv'high downto slv'low); + begin + for idx in slv'high downto slv'low loop + target(idx) := slv(slv'low + (slv'high-idx)); + end loop; + return target; + end reverse_vector; + + function to_std_logic(i : in integer) return std_logic is + begin + if i = 0 then + return '0'; + end if; + return '1'; + end function; + + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural is + begin + if s = '1' then + return 1; + else + return 0; + end if; + end function; +end package body; diff --git a/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700.qpf b/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700.qpf new file mode 100644 index 000000000..95e89327b --- /dev/null +++ b/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 14:14:16 November 28, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "14:14:16 November 28, 2022" + +# Revisions + +PROJECT_REVISION = "tzpuFusionX_MZ700" diff --git a/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700.qsf b/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700.qsf new file mode 100644 index 000000000..934556f84 --- /dev/null +++ b/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700.qsf @@ -0,0 +1,243 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:29:32 June 24, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# tzpuFusionX_MZ700.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY MAX7000AE +set_global_assignment -name DEVICE "EPM7512AETC144-10" +set_global_assignment -name TOP_LEVEL_ENTITY tzpuFusionX_MZ700 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL + +# Z80 Data Bus +# ============ +set_location_assignment PIN_88 -to Z80_DATA[0] +set_location_assignment PIN_91 -to Z80_DATA[1] +set_location_assignment PIN_83 -to Z80_DATA[2] +set_location_assignment PIN_79 -to Z80_DATA[3] +set_location_assignment PIN_60 -to Z80_DATA[4] +set_location_assignment PIN_93 -to Z80_DATA[5] +set_location_assignment PIN_80 -to Z80_DATA[6] +set_location_assignment PIN_86 -to Z80_DATA[7] + +# Z80 Control signals. +# ==================== +set_location_assignment PIN_92 -to Z80_INTn +set_location_assignment PIN_96 -to Z80_NMIn +set_location_assignment PIN_97 -to Z80_HALTn +set_location_assignment PIN_98 -to Z80_MREQn +set_location_assignment PIN_99 -to Z80_IORQn +set_location_assignment PIN_110 -to Z80_RDn +set_location_assignment PIN_108 -to Z80_WRn +set_location_assignment PIN_107 -to Z80_BUSAKn +set_location_assignment PIN_106 -to Z80_WAITn +set_location_assignment PIN_103 -to Z80_BUSRQn +set_location_assignment PIN_100 -to Z80_RFSHn +set_location_assignment PIN_102 -to Z80_M1n +set_location_assignment PIN_56 -to Z80_RESETn +set_location_assignment PIN_101 -to Z80_CLK + +# Z80 Address Bus +# =============== +set_location_assignment PIN_94 -to Z80_ADDR[0] +set_location_assignment PIN_90 -to Z80_ADDR[1] +set_location_assignment PIN_87 -to Z80_ADDR[2] +set_location_assignment PIN_84 -to Z80_ADDR[3] +set_location_assignment PIN_81 -to Z80_ADDR[4] +set_location_assignment PIN_78 -to Z80_ADDR[5] +set_location_assignment PIN_69 -to Z80_ADDR[6] +set_location_assignment PIN_70 -to Z80_ADDR[7] +set_location_assignment PIN_71 -to Z80_ADDR[8] +set_location_assignment PIN_68 -to Z80_ADDR[9] +set_location_assignment PIN_65 -to Z80_ADDR[10] +set_location_assignment PIN_67 -to Z80_ADDR[11] +set_location_assignment PIN_66 -to Z80_ADDR[12] +set_location_assignment PIN_63 -to Z80_ADDR[13] +set_location_assignment PIN_62 -to Z80_ADDR[14] +set_location_assignment PIN_61 -to Z80_ADDR[15] + +# SOM SPI +# ======= +set_location_assignment PIN_32 -to VSOM_SPI_CSn +set_location_assignment PIN_31 -to VSOM_SPI_CLK +set_location_assignment PIN_30 -to VSOM_SPI_MOSI +set_location_assignment PIN_29 -to VSOM_SPI_MISO + +# SOM Parallel Bus +# ================ +set_location_assignment PIN_41 -to VSOM_DATA_OUT[0] +set_location_assignment PIN_40 -to VSOM_DATA_OUT[1] +set_location_assignment PIN_39 -to VSOM_DATA_OUT[2] +set_location_assignment PIN_38 -to VSOM_DATA_OUT[3] +set_location_assignment PIN_37 -to VSOM_DATA_OUT[4] +set_location_assignment PIN_36 -to VSOM_DATA_OUT[5] +set_location_assignment PIN_35 -to VSOM_DATA_OUT[6] +set_location_assignment PIN_34 -to VSOM_DATA_OUT[7] +set_location_assignment PIN_132 -to VSOM_HBYTE + +# SOM Reserved signals. +# ===================== +set_location_assignment PIN_21 -to VSOM_RSV[1] + +# SOM Control Signals +# =================== +set_location_assignment PIN_28 -to VSOM_READY +set_location_assignment PIN_18 -to VSOM_LTSTATE +set_location_assignment PIN_27 -to VSOM_BUSRQ +set_location_assignment PIN_26 -to VSOM_BUSACK +set_location_assignment PIN_19 -to VSOM_INT +set_location_assignment PIN_22 -to VSOM_NMI +set_location_assignment PIN_25 -to VSOM_WAIT +set_location_assignment PIN_23 -to VSOM_RESET +set_location_assignment PIN_16 -to PM_RESET + +# VGA_Palette Control +# =================== +set_location_assignment PIN_133 -to VGA_R[7] +set_location_assignment PIN_137 -to VGA_R[8] +set_location_assignment PIN_140 -to VGA_R[9] +set_location_assignment PIN_134 -to VGA_G[7] +set_location_assignment PIN_138 -to VGA_G[8] +set_location_assignment PIN_141 -to VGA_G[9] +set_location_assignment PIN_136 -to VGA_B[8] +set_location_assignment PIN_139 -to VGA_B[9] + + +# VGA Control Signals +# =================== +set_location_assignment PIN_142 -to VGA_PXL_CLK +set_location_assignment PIN_14 -to VGA_DISPEN +set_location_assignment PIN_12 -to VGA_VSYNCn +set_location_assignment PIN_11 -to VGA_HSYNCn +set_location_assignment PIN_82 -to VGA_COLR +set_location_assignment PIN_109 -to VGA_CSYNCn +set_location_assignment PIN_143 -to VGA_BLANKn + +# CRT Control Signals +# =================== +set_location_assignment PIN_15 -to MONO_PXL_CLK +set_location_assignment PIN_114 -to MONO_BLANKn +set_location_assignment PIN_113 -to MONO_CSYNCn +set_location_assignment PIN_116 -to MONO_RSV + +# CRT Lower Chrominance Control +# ============================= +set_location_assignment PIN_1 -to MONO_R[0] +set_location_assignment PIN_6 -to MONO_R[1] +set_location_assignment PIN_10 -to MONO_R[2] +set_location_assignment PIN_2 -to MONO_G[0] +set_location_assignment PIN_7 -to MONO_G[1] +set_location_assignment PIN_9 -to MONO_G[2] +set_location_assignment PIN_5 -to MONO_B[1] +set_location_assignment PIN_8 -to MONO_B[2] + +# MUX Control Signals +# =================== +set_location_assignment PIN_72 -to VIDEO_SRC +set_location_assignment PIN_74 -to MONO_VIDEO_SRC +set_location_assignment PIN_77 -to AUDIO_SRC_L +set_location_assignment PIN_75 -to AUDIO_SRC_R + +# Mainboard Reset Signals +# ======================= +#set_location_assignment PIN_127 -to CPU_RESETn +set_location_assignment PIN_122 -to MB_RESETn +set_location_assignment PIN_111 -to MB_IPLn + +# USB Power Control +# ================= +set_location_assignment PIN_55 -to VBUS_EN + +# Clocks +# ====== +#set_location_assignment PIN_125 -to CPU_CLK +set_location_assignment PIN_128 -to CLK_50M + +# Unused ports +# ============ +#set_location_assignment PIN_42 -to +#set_location_assignment PIN_43 -to +#set_location_assignment PIN_44 -to +#set_location_assignment PIN_45 -to +#set_location_assignment PIN_112 -to +#set_location_assignment PIN_131 -to +#set_location_assignment PIN_117 -to +#set_location_assignment PIN_118 -to +#set_location_assignment PIN_119 -to +#set_location_assignment PIN_120 -to +#set_location_assignment PIN_121 -to +#set_location_assignment PIN_25 -to +#set_location_assignment PIN_53 -to +#set_location_assignment PIN_128 -to +#set_location_assignment PIN_47 -to +#set_location_assignment PIN_54 -to +#set_location_assignment PIN_127 -to +#set_location_assignment PIN_125 -to +#set_location_assignment PIN_48 -to +#set_location_assignment PIN_46 -to +#set_location_assignment PIN_49 -to + + +set_global_assignment -name VHDL_FILE ../tzpuFusionX_Toplevel.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX_pkg.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX.vhd +set_global_assignment -name SDC_FILE tzpuFusionX_MZ700_constraints.sdc + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name AUTO_RESOURCE_SHARING OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF + +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF +set_global_assignment -name AUTO_LCELL_INSERTION ON + +set_global_assignment -name CDF_FILE output_files/tzpuFusionX_MZ700.cdf diff --git a/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700_constraints.sdc b/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700_constraints.sdc new file mode 100644 index 000000000..f024022a5 --- /dev/null +++ b/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700_constraints.sdc @@ -0,0 +1,324 @@ +## Generated SDC file "tzpuFusionX.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jun 26 22:10:05 2020" + +## +## DEVICE "EPM7160STC100-10" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +# Standard mainboard clock. If using tzpuFusionX on a different host then set to the host frequency. +create_clock -name {Z80_CLK} -period 282.486 -waveform { 0.000 141.243 } [get_ports { Z80_CLK }] + +# For 50MHz crystal. +create_clock -name {CLK_50M} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CLK_50M }] + +# For SPI CSn +#create_clock -name {VSOM_SPI_CSn} -period 200.000 -waveform { 160.000 40.000 } [ get_ports { VSOM_SPI_CSn }] + +# For SPI CLK +create_clock -name {VSOM_SPI_CLK} -period 14.000 -waveform { 0.000 7.000 } [ get_ports { VSOM_SPI_CLK }] + +# For basic board with oscillator. +#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }] +#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ] +##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSEL}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HI_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {R_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {G_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {B_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {COLR_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CSYNC_IN}] +##set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {HSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CS2n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A18_INTn_V_R}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSRQn_V_G}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A16_WAITn_V_B}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A17_NMIn_V_COLR}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RFSHn}] + +# For K64F +#set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}] + +# For basic board with oscillator. +#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}] + +#************************************************************** +# Set Max Delay +#************************************************************** +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 30.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 50.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 60.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 60.000 + +#************************************************************** +# Set Min Delay +#************************************************************** +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +# For K64F +#set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For basic board with oscillator. +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For both configurations. +#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} + +#************************************************************** +# Set Multicycle Path +#************************************************************** +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/CPLD/v1.0/MZ700/tzpuFusionX.vhd b/CPLD/v1.0/MZ700/tzpuFusionX.vhd new file mode 100644 index 000000000..e031e0519 --- /dev/null +++ b/CPLD/v1.0/MZ700/tzpuFusionX.vhd @@ -0,0 +1,999 @@ +------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX.vhd +-- Version: MZ-700 +-- Created: June 2020 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD logic definition file. +-- This module contains the definition of the tzpuFusionX project plus enhancements +-- for the MZ700. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: Oct 2022 - Initial write for the MZ-700. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use work.tzpuFusionX_pkg.all; + +entity cpld512 is + generic ( + SPI_CLK_POLARITY : std_logic := '0' + ); + port ( + -- Z80 Address Bus + Z80_ADDR : inout std_logic_vector(15 downto 0); + + -- Z80 Data Bus + Z80_DATA : inout std_logic_vector(7 downto 0); + + -- Z80 Control signals. + Z80_BUSRQn : in std_logic; + Z80_BUSAKn : out std_logic; + Z80_INTn : in std_logic; + Z80_IORQn : inout std_logic; + Z80_MREQn : inout std_logic; + Z80_NMIn : in std_logic; + Z80_RDn : inout std_logic; + Z80_WRn : inout std_logic; + Z80_RESETn : in std_logic; -- Host CPU Reset signal, also CPLD reset. + Z80_HALTn : out std_logic; + Z80_WAITn : in std_logic; + Z80_M1n : inout std_logic; + Z80_RFSHn : inout std_logic; + + -- SOM Control Signals + VSOM_SPI_CLK : in std_logic; -- SOM SPI Channel 0 Clock. + VSOM_SPI_MOSI : in std_logic; -- MOSI Input. + VSOM_SPI_MISO : out std_logic; -- MISO Output. + VSOM_SPI_CSn : in std_logic; -- Enable. + + -- SOM Parallel Bus. + VSOM_DATA_OUT : out std_logic_vector(7 downto 0); -- Address/Data bus for CPLD control registers. + VSOM_HBYTE : in std_logic; -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY : out std_logic; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE : out std_logic; -- Last T-State in current cycle, 1 = active. + VSOM_BUSRQ : out std_logic; -- Host device requesting Z80 Bus. + VSOM_BUSACK : out std_logic; -- Host device granted Z80 Bus + VSOM_INT : out std_logic; -- Z80 INT signal + VSOM_NMI : out std_logic; -- Z80 NMI signal + VSOM_WAIT : out std_logic; -- Z80 WAIT signal + VSOM_RESET : out std_logic; -- Z80 RESET signal + VSOM_RSV : out std_logic_vector(1 downto 1); -- Reserved pins. + + -- SOM Control Signals + PM_RESET : out std_logic; -- Reset SOM + + -- VGA_Palette Control + VGA_R : in std_logic_vector(9 downto 7); -- Signals used for detecting blank or no video output. + VGA_G : in std_logic_vector(9 downto 7); + VGA_B : in std_logic_vector(9 downto 8); + + -- VGA Control Signals + VGA_PXL_CLK : in std_logic; -- VGA Pixel clock for DAC conversion. + VGA_DISPEN : in std_logic; -- Displayed Enabled (SOM video output). + VGA_VSYNCn : in std_logic; -- SOM VSync. + VGA_HSYNCn : in std_logic; -- SOM HSync. + VGA_COLR : out std_logic; -- COLR colour carrier frequency. + VGA_CSYNCn : out std_logic; -- VGA Composite Sync. + VGA_BLANKn : out std_logic; -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK : out std_logic; -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn : out std_logic; -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn : out std_logic; -- Mono CRT composite sync. + MONO_RSV : out std_logic; + + -- CRT Lower Chrominance Control + MONO_R : out std_logic_vector(2 downto 0); -- Signals to fine tune Red level of monochrome chrominance. + MONO_G : out std_logic_vector(2 downto 0); -- Signals to fine tune Green level of monochrome chrominance. + MONO_B : out std_logic_vector(2 downto 1); -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC : out std_logic; -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC : out std_logic; -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L : out std_logic; -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R : out std_logic; -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals + MB_RESETn : in std_logic; -- Motherboard Reset pressed. + MB_IPLn : in std_logic; -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN : out std_logic; -- USB Enable Power Output + + -- Clocks. + Z80_CLK : in std_logic; -- Host CPU Clock + CLK_50M : in std_logic -- 50MHz oscillator. + ); +end entity; + +architecture rtl of cpld512 is + + -- Finite State Machine states. + type SOMFSMState is + ( + IdleCycle, + FetchCycle, + FetchCycle_2, + FetchCycle_3, + FetchCycle_4, + RefreshCycle, + RefreshCycle_1, + RefreshCycle_2, + RefreshCycle_3, + WriteCycle, + WriteCycle_2, + WriteCycle_3, + WriteCycle_4, + ReadCycle, + ReadCycle_2, + ReadCycle_3, + ReadCycle_4, + WriteIOCycle, + WriteIOCycle_2, + WriteIOCycle_3, + WriteIOCycle_4, + WriteIOCycle_5, + ReadIOCycle, + ReadIOCycle_2, + ReadIOCycle_3, + ReadIOCycle_4, + HaltCycle, + BusReqCycle + ); + + -- CPU Interface internal signals. + signal Z80_BUSRQni : std_logic; + signal Z80_BUSAKni : std_logic; + signal Z80_INTni : std_logic; + signal Z80_IORQni : std_logic; + signal Z80_MREQni : std_logic; + signal Z80_NMIni : std_logic; + signal Z80_RDni : std_logic; + signal Z80_WRni : std_logic; + signal Z80_HALTni : std_logic; + signal Z80_WAITni : std_logic; + signal Z80_M1ni : std_logic; + signal Z80_RFSHni : std_logic; + signal Z80_DATAi : std_logic_vector(7 downto 0); + signal Z80_BUSRQ_ACKni : std_logic; + + -- Internal CPU state control. + signal CPU_ADDR : std_logic_vector(15 downto 0) := (others => '0'); + signal CPU_DATA_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal CPU_DATA_OUT : std_logic_vector(7 downto 0) := (others => '0'); + signal CPU_DATA_EN : std_logic; + + -- Clocks. + signal CLK_25Mi : std_logic := '0'; + + -- Reset control + signal PM_RESETi : std_logic := '1'; + signal VSOM_RESETni : std_logic := '1'; + + -- Refresh control. + signal FSM_STATE : SOMFSMState := IdleCycle; + signal NEW_SPI_CMD : std_logic := '0'; + signal VCPU_CS_EDGE : std_logic_vector(1 downto 0) := "11"; + signal AUTOREFRESH_CNT : integer range 0 to 7; + signal FSM_STATUS : std_logic := '0'; + signal RFSH_STATUS : std_logic := '0'; + signal REFRESH_ADDR : std_logic_vector(7 downto 0); + signal IPAR : std_logic_vector(7 downto 0); + signal AUTOREFRESH : std_logic; + + -- Clock edge detection and flagging. + signal Z80_CLK_RE : std_logic := '0'; + signal Z80_CLK_FE : std_logic := '0'; + signal Z80_CLK_LEVEL : std_logic := '0'; + signal Z80_CLK_LAST : std_logic := '0'; + signal CPU_T_STATE : integer range 0 to 5; + signal CPU_T_STATES : integer range 0 to 5; + signal CPU_T_STATE_SET : integer range 0 to 5; + signal CPU_LAST_T_STATE : std_logic := '0'; + + -- SPI Slave interface. + signal SPI_SHIFT_EN : std_logic; + signal SPI_TX_SREG : std_logic_vector(6 downto 0); -- TX Shift Register + signal SPI_RX_SREG : std_logic_vector(7 downto 0); -- RX Shift Register + signal SPI_TX_DATA : std_logic_vector(31 downto 0); -- Data to transmit. + signal SPI_RX_DATA : std_logic_vector(31 downto 0); -- Data received. + signal SPI_BIT_CNT : integer range 0 to 16; -- Count of bits tx/rx'd. + signal SPI_FRAME_CNT : integer range 0 to 4; -- Number of frames received (8bit chunks). + + -- SPI Command interface. + signal SOM_CMD : std_logic_vector(7 downto 0) := (others => '0'); + signal SPI_NEW_DATA : std_logic; + signal SPI_PROCESSING : std_logic; + signal SPI_CPU_ADDR : std_logic_vector(15 downto 0) := (others => '0'); + signal SPI_CPU_DATA : std_logic_vector(7 downto 0) := (others => '0'); + + -- Test modes. + signal SPI_LOOPBACK_TEST : std_logic := '0'; + + -- Video/Audio control + signal VIDEO_SRCi : std_logic := '0'; + signal MONO_VIDEO_SRCi : std_logic := '0'; + signal AUDIO_SRC_Li : std_logic := '0'; + signal AUDIO_SRC_Ri : std_logic := '0'; + signal VBUS_ENi : std_logic := '1'; + + + function to_std_logic(L: boolean) return std_logic is + begin + if L then + return('1'); + else + return('0'); + end if; + end function to_std_logic; +begin + + + -- System RESET. + -- + -- Multiple reset sources, Z80_RESETn, MB_IPLn, MB_RESETn. On the MZ-700 we are only concerned with the Z80_RESETn. + -- If the external reset switch is pressed, a Z80_RESETn is invoked sending the signal low for approx 30ms. + -- On the first edge the VSOM_RESETn signal is set which allows the SOM to see it and the Z80 application to enter a reset state. + -- On the second edge, if occurring within 1 second of the first, the PM_RESET signal to the SOM is triggered, held low for 1 second, + -- forcing the SOM to reboot. + SYSRESET: process( Z80_CLK, Z80_RESETn ) + variable timer1 : integer range 0 to 354000 := 0; + variable timer100 : integer range 0 to 10 := 0; + variable timerPMReset : integer range 0 to 10 := 0; + variable resetCount : integer range 0 to 3 := 0; + variable cpuResetEdge : std_logic := '1'; + begin + -- Synchronous on the HOST Clock. + if(rising_edge(Z80_CLK)) then + + -- If the PM Reset timer is active, count down and on expiry release the SOM PM_RESET line. + if(timerPMReset = 0 and PM_RESETi = '1') then + PM_RESETi <= '0'; + end if; + + -- If the VSOM_RESETni is active after reset timer expiry, cancel the RESET state. + if(timerPMReset = 0 and VSOM_RESETni = '0') then + VSOM_RESETni <= '1'; + end if; + + -- Each time the reset button is pressed, count the edges. + if(Z80_RESETn = '0' and cpuResetEdge = '1' and (resetCount = 0 or timer100 > 5)) then + resetCount := resetCount + 1; + VSOM_RESETni <= '0'; + timerPMReset := 5; + timer100 := 0; + + -- If there are 2 or more reset signals in a given period it means a SOM reset is required. + if(resetCount >= 2) then + PM_RESETi <= '1'; + timerPMReset := 10; + resetCount := 0; + end if; + + end if; + + -- 100ms interval. + if(timer1 = 354000) then + timer100 := timer100 + 1; + + if(timer100 >= 10) then + timer100 := 0; + resetCount := 0; + end if; + + if(timerPMReset > 0) then + timerPMReset := timerPMReset - 1; + end if; + end if; + + timer1 := timer1 - 1; + cpuResetEdge := Z80_RESETn; + end if; + end process; + + -- Create Mono DAC Clock based on primary clock. + MONOCLK: process( CLK_50M ) + begin + if(rising_edge(CLK_50M)) then + CLK_25Mi <= not CLK_25Mi; + end if; + end process; + + -- SPI Slave input. Receive command and data from the SOM. + SPI_INPUT : process(VSOM_SPI_CLK) + begin + -- SPI_CLK_POLARITY='0' => falling edge; SPI_CLK_POLARITY='1' => rising edge + if(VSOM_SPI_CLK'event and VSOM_SPI_CLK = SPI_CLK_POLARITY) then + if(VSOM_SPI_CSn = '0') then + SPI_RX_SREG <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + -- End of frame then store the data prior to next bit arrival. + -- Convert to Little Endian, same as SOM. + if(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 1 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(7 downto 0) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 2 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(15 downto 8) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 3 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(23 downto 16) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 4 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(31 downto 24) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + end if; + end if; + end if; + end process; + + -- SPI Slave output. Return the current data set as selected by the input signals XACT. + SPI_OUTPUT : process(VSOM_SPI_CLK,VSOM_SPI_CSn,SPI_TX_DATA) + begin + if(VSOM_SPI_CSn = '1') then + SPI_SHIFT_EN <= '0'; + SPI_BIT_CNT <= 15; + + -- SPI_CLK_POLARITY='0' => falling edge; SPI_CLK_POLARITY='1' => risinge edge + elsif(VSOM_SPI_CLK'event and VSOM_SPI_CLK = not SPI_CLK_POLARITY) then + SPI_SHIFT_EN <= '1'; + + if(SPI_BIT_CNT > 0) then + SPI_BIT_CNT <= SPI_BIT_CNT - 1; + end if; + + VSOM_SPI_MISO <= SPI_TX_SREG(6); + SPI_TX_SREG <= SPI_TX_SREG(5 downto 0) & '0'; + + -- First clock after CS goes active, load up the data to be sent to the SOM. + if(SPI_SHIFT_EN = '0' or SPI_BIT_CNT = 0) then + + if(SPI_LOOPBACK_TEST = '1') then + VSOM_SPI_MISO<= SPI_RX_SREG(7); + SPI_TX_SREG <= SPI_RX_SREG(6 downto 0); + + elsif(SPI_SHIFT_EN = '0') then + SPI_FRAME_CNT<= 1; + VSOM_SPI_MISO<= SPI_TX_DATA(7); + SPI_TX_SREG <= SPI_TX_DATA(6 downto 0); + elsif(SPI_FRAME_CNT = 1) then + SPI_FRAME_CNT<= 2; + VSOM_SPI_MISO<= SPI_TX_DATA(15); + SPI_TX_SREG <= SPI_TX_DATA(14 downto 8); + elsif(SPI_FRAME_CNT = 2) then + SPI_FRAME_CNT<= 3; + VSOM_SPI_MISO<= SPI_TX_DATA(23); + SPI_TX_SREG <= SPI_TX_DATA(22 downto 16); + else + -- Increment frame count for each word received. We handle 8bit (1 frame), 16bit (2 frames) or 32bit (4 frames) reception. + SPI_FRAME_CNT<= 4; + VSOM_SPI_MISO<= SPI_TX_DATA(31); + SPI_TX_SREG <= SPI_TX_DATA(30 downto 24); + end if; + + SPI_BIT_CNT <= 7; + end if; + end if; + end process; + + SPI_REGISTER : process(Z80_RESETn, VSOM_SPI_CSn, SPI_FRAME_CNT) + begin + if(Z80_RESETn = '0') then + VIDEO_SRCi <= '0'; + VGA_BLANKn <= '1'; + VBUS_ENi <= '1'; + MONO_VIDEO_SRCi <= '1'; + AUDIO_SRC_Li <= '0'; + AUDIO_SRC_Ri <= '0'; + AUTOREFRESH <= '1'; + SPI_LOOPBACK_TEST <= '0'; + SOM_CMD <= (others => '0'); + SPI_CPU_ADDR <= (others => '0'); + SPI_NEW_DATA <= '0'; + + -- On rising edge of SPI CSn a new data packet from the SOM has arrived and in the shift register SPI_RX_SREG. + -- The variable SPI_FRAME_CNT indicates which byte (frame) in a 32bit word has been transmitted. This allows + -- for 8bit, 16bit and 32bit transmissions. + -- The packet is formatted as follows: + -- + -- < SPI_FRAME_CNT=4 >< SPI_FRAME=3 > < SPI_FRAME_CNT=2 >< SPI_FRAME_CNT=1> + -- < 16bit Z80 Address > < Z80 Data >< Command = 00.. 80 > + -- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2 0 + -- + -- < > < Data >< Command = F0.. FF > + -- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2 0 + -- + elsif(VSOM_SPI_CSn'event and VSOM_SPI_CSn = '1') then + + -- Command is always located in the upper byte of frame 1. + SOM_CMD <= SPI_RX_DATA(7 downto 0); + + -- Toggle flag to indicate new data arrived. + SPI_NEW_DATA <= not SPI_NEW_DATA; + + -- Process the command. Some commands require the FSM, others can be serviced immediately. + case SPI_RX_DATA(7 downto 0) is + + -- Z80XACT(0..15): Setup data and address as provided then execute FSM. + when X"10" | X"11" | X"12" | X"13" | X"14" | X"15" | X"16" | X"17" | -- Fetch + X"18" | X"19" | X"1A" | X"1B" | X"1C" | X"1D" | X"1E" | X"1F" | -- Write + X"20" | X"21" | X"22" | X"23" | X"24" | X"25" | X"26" | X"27" | -- Read + X"28" | X"29" | X"2A" | X"2B" | X"2C" | X"2D" | X"2E" | X"2F" | -- WriteIO + X"30" | X"31" | X"32" | X"33" | X"34" | X"35" | X"36" | X"37" | -- ReadIO + X"38" | X"39" | X"3A" | X"3B" | X"3C" | X"3D" | X"3E" | X"3F" | -- + X"40" | X"41" | X"42" | X"43" | X"44" | X"45" | X"46" | X"47" | -- + X"48" | X"49" | X"4A" | X"4B" | X"4C" | X"4D" | X"4E" | X"4F" => + + -- Direct address set. + if(SPI_FRAME_CNT = 4) then + SPI_CPU_ADDR <= SPI_RX_DATA(31 downto 16); + else + SPI_CPU_ADDR <= std_logic_vector(unsigned(CPU_ADDR) + unsigned(SPI_RX_DATA(2 downto 0))); + end if; + + if(SPI_FRAME_CNT > 1) then + SPI_CPU_DATA <= SPI_RX_DATA(15 downto 8); + end if; + + -- SETSIGSET1: Set control lines directly. + when X"F0" => + VIDEO_SRCi <= SPI_RX_DATA(8); + MONO_VIDEO_SRCi <= SPI_RX_DATA(9); + AUDIO_SRC_Li <= SPI_RX_DATA(10); + AUDIO_SRC_Ri <= SPI_RX_DATA(11); + VBUS_ENi <= SPI_RX_DATA(12); + VGA_BLANKn <= not SPI_RX_DATA(13); + + -- Enable auto refresh DRAM cycle. + when X"F1" => + AUTOREFRESH <= '1'; + + -- Disable auto refresh DRAM cycle. + when X"F2" => + AUTOREFRESH <= '0'; + + -- SETLOOPBACK: Enable loopback test mode. + when X"FE" => + SPI_LOOPBACK_TEST <= '1'; + + -- No action, called to retrieve status. + when X"00" | X"FF" => + + when others => + end case; + end if; + end process; + + -- Z80 Clock edge detection. Each falling and rising edge sets a flag for 1 cycle along with the current clock level flag. + -- On expiry of the defined T-States, a flag is raised to indicate end of cycle. + CLKEDGE: process( CLK_50M, Z80_RESETn, Z80_CLK, CPU_T_STATE_SET ) + begin + if(Z80_RESETn = '0') then + Z80_CLK_RE <= '0'; + Z80_CLK_FE <= '0'; + Z80_CLK_LEVEL <= '0'; + CPU_T_STATE <= 1; + CPU_LAST_T_STATE <= '0'; + + elsif(rising_edge(CLK_50M)) then + -- Host clock edge detection. For Z80 operations the clock edge is required to meet host and original timings. + if(Z80_CLK = '1' and Z80_CLK_LAST = '0') then + Z80_CLK_RE <= '1'; + Z80_CLK_LEVEL <= '1'; + + -- T state increments on each rising edge unless WAIT asserted. + if(Z80_WAITni = '1') then + + -- Wrap around to next T-State if limit for last transaction type reached. + if(CPU_T_STATE = CPU_T_STATES) then + CPU_T_STATE <= 1; + CPU_LAST_T_STATE <= '0'; + else + CPU_T_STATE <= CPU_T_STATE + 1; + end if; + + end if; + + elsif(Z80_CLK = '0' and Z80_CLK_LAST = '1') then + Z80_CLK_FE <= '1'; + Z80_CLK_LEVEL <= '0'; + + -- Falling edge of the last T-State sets the Last T-State flag. This gives the SOM sufficient time to detect it + -- and execute necessary code before next T-State commences. + if(CPU_T_STATE = CPU_T_STATES) then + CPU_LAST_T_STATE <= '1'; + end if; + else + Z80_CLK_RE <= '0'; + Z80_CLK_FE <= '0'; + end if; + + -- Mechanism to set the T-State. + if(CPU_T_STATE_SET /= 0) then + CPU_T_STATE <= CPU_T_STATE_SET; + CPU_LAST_T_STATE <= '0'; + end if; + + Z80_CLK_LAST <= Z80_CLK; + end if; + end process; + + -- SOM Finite State Machine. + -- + -- A command processor, based on an FSM concept, to process requested commands, ie. Z80 Write, Z80 Read etc. + -- The external signal SOM_CMD_EN, when set, indicates a new command available in SOM_CMD. + -- + SOMFSM: process( CLK_50M, Z80_RESETn ) + begin + if(Z80_RESETn = '0') then + Z80_BUSAKni <= '1'; + Z80_IORQni <= '1'; + Z80_MREQni <= '1'; + Z80_RDni <= '1'; + Z80_WRni <= '1'; + Z80_HALTni <= '1'; + Z80_M1ni <= '1'; + Z80_RFSHni <= '1'; + Z80_BUSRQ_ACKni <= '1'; + FSM_STATUS <= '0'; + RFSH_STATUS <= '0'; + CPU_DATA_EN <= '0'; + CPU_DATA_IN <= (others => '0'); + REFRESH_ADDR <= (others => '0'); + AUTOREFRESH_CNT <= 7; + IPAR <= (others => '0'); + FSM_STATE <= IdleCycle; + NEW_SPI_CMD <= '0'; + VCPU_CS_EDGE <= "11"; + CPU_T_STATES <= 3; + CPU_T_STATE_SET <= 0; + SPI_PROCESSING <= '0'; + + elsif(rising_edge(CLK_50M)) then + + -- Setup of T State is one cycle wide. + CPU_T_STATE_SET <= 0; + + -- Bus request mechanism. If an externel Bus Request comes in and the FSM is idle, run the Bus Request command which + -- suspends processing and tri-states the bus. + if(Z80_BUSRQn = '0' and Z80_BUSRQ_ACKni = '1' and FSM_STATE = IdleCycle) then + FSM_STATE <= BusReqCycle; + end if; + if(Z80_BUSRQn = '1' and Z80_BUSRQ_ACKni = '0' and FSM_STATE = IdleCycle) then + Z80_BUSRQ_ACKni <= '1'; + end if; + + -- New command, set flag as the signal is only 1 clock wide. + if(SPI_LOOPBACK_TEST = '0' and VSOM_SPI_CSn = '1' and VCPU_CS_EDGE = "01") then + NEW_SPI_CMD <= '1'; + end if; + + -- Whenever we return to Idle or just prior to Refresh from a Fetch cycle set all control signals to default. + if(FSM_STATE = IdleCycle or FSM_STATE = RefreshCycle) then + CPU_DATA_EN <= '0'; + Z80_MREQni <= '1'; + Z80_IORQni <= '1'; + Z80_RDni <= '1'; + Z80_WRni <= '1'; + Z80_M1ni <= '1'; + FSM_STATUS <= '0'; + Z80_RFSHni <= '1'; + + -- Auto DRAM refresh cycles. When enabled, every 7 host clock cycles, a 2 cycle refresh period commences. + -- This will be overriden if the SPI receives a new command. + -- + if AUTOREFRESH = '1' and FSM_STATE = IdleCycle then + AUTOREFRESH_CNT <= AUTOREFRESH_CNT - 1; + if(AUTOREFRESH_CNT = 0) then + FSM_STATE <= RefreshCycle_3; + end if; + end if; + end if; + + -- If new command has been given and the FSM enters idle state, load up new command for processing. + if(NEW_SPI_CMD = '1' and FSM_STATE = IdleCycle) then + NEW_SPI_CMD <= '0'; + + -- Store new address and data for this command. + CPU_ADDR <= SPI_CPU_ADDR; + if(SPI_CPU_DATA /= CPU_DATA_OUT) then + CPU_DATA_OUT <= SPI_CPU_DATA; + end if; + + -- Process the SOM command. The SPI_REGISTER executes non FSM commands and stores FSM + -- data prior to this execution block, which fires 1 cycle later on the same control clock. + -- If the command is not for the FSM then the READY mechanism is held for one + -- further cycle before going inactive. + case SOM_CMD is + when X"10" | X"11" | X"12" | X"13" | X"14" | X"15" | X"16" | X"17" => + -- Initiate a Fetch Cycle. + FSM_STATE <= FetchCycle; + + when X"18" | X"19" | X"1A" | X"1B" | X"1C" | X"1D" | X"1E" | X"1F" => + + -- Set the Z80 data bus value and initiate a Write Cycle. + FSM_STATE <= WriteCycle; + + when X"20" | X"21" | X"22" | X"23" | X"24" | X"25" | X"26" | X"27" => + -- Initiate a Read Cycle. + FSM_STATE <= ReadCycle; + + when X"28" | X"29" | X"2A" | X"2B" | X"2C" | X"2D" | X"2E" | X"2F" => + -- Set the Z80 data bus value and initiate an IO Write Cycle. + -- The SOM should set 15:8 to the B register value. + FSM_STATE <= WriteIOCycle; + + when X"30" | X"31" | X"32" | X"33" | X"34" | X"35" | X"36" | X"37" => + -- Initiate a Read IO Cycle. + FSM_STATE <= ReadIOCycle; + + when X"50" => + -- Register a Halt state. + FSM_STATE <= HaltCycle; + + when X"51" => + -- Initiate a refresh cycle. + FSM_STATE <= RefreshCycle_3; + + when X"E0" => + -- Initiate a Halt Cycle. + FSM_STATE <= HaltCycle; + + -- Set the Refresh Address register. + when X"E1" => + REFRESH_ADDR <= CPU_DATA_OUT; + + -- Set the Interrupt Page Address Register. + when X"E2" => + IPAR <= CPU_DATA_OUT; + + when others => + end case; + + -- Toggle the processing flag to negate the new data flag. Used to indicate device is busy. + if(SPI_NEW_DATA /= SPI_PROCESSING) then + SPI_PROCESSING <= not SPI_PROCESSING; + end if; + + -- FSM Status bit. When processing a command it is set, cleared when idle. Used by SOM to determine command completion. + FSM_STATUS <= '1'; + end if; + + -- Refresh status bit. Indicates a Refresh cycle is under way. + if FSM_STATE = RefreshCycle or FSM_STATE = RefreshCycle_1 or FSM_STATE = RefreshCycle_2 or FSM_STATE = RefreshCycle_3 then + RFSH_STATUS <= '1'; + else + RFSH_STATUS <= '0'; + end if; + + -- FSM to implement all the required Z80 cycles. + -- + case FSM_STATE is + when IdleCycle => + + ----------------------------- + -- Z80 Fetch Cycle. + ----------------------------- + when FetchCycle => + if(Z80_CLK_RE = '1' or Z80_CLK_LEVEL = '1') then + CPU_T_STATE_SET<= 1; + CPU_T_STATES <= 4; + Z80_M1ni <= '0'; + FSM_STATE <= FetchCycle_2; + end if; + + when FetchCycle_2 => + if(Z80_CLK_FE = '1' and CPU_T_STATE = 1) then + Z80_MREQni <= '0'; + Z80_RDni <= '0'; + FSM_STATE <= FetchCycle_3; + end if; + + when FetchCycle_3 => + if(CPU_T_STATE = 2 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + FSM_STATE <= FetchCycle_4; + end if; + + when FetchCycle_4 => + -- To meet the timing diagrams, just after Rising edge on T3 clear signals. Data wont be available until + -- a short period before the falling edge of T3 (could be an MZ-700 design restriction or the Z80 timing diagrams are a bit out). + if(CPU_T_STATE = 3 and Z80_CLK_RE = '1' and Z80_WAITni = '1') then + FSM_STATE <= RefreshCycle; + end if; + + ----------------------------- + -- Z80 Refresh Cycle. + ----------------------------- + when RefreshCycle => + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + Z80_RFSHni <= '0'; + FSM_STATE <= RefreshCycle_1; + + when RefreshCycle_1 => + -- Falling edge of T3 activates the MREQ line. + if(Z80_CLK_FE = '1' and CPU_T_STATE = 3) then + Z80_MREQni <= '0'; + FSM_STATE <= RefreshCycle_2; + end if; + + when RefreshCycle_2 => + if(Z80_CLK_FE = '1' and CPU_T_STATE = 4) then + Z80_MREQni <= '1'; + end if; + if(Z80_MREQni = '1' and CPU_T_STATE = 4) then + REFRESH_ADDR(6 downto 0) <= REFRESH_ADDR(6 downto 0) + 1; + FSM_STATE <= IdleCycle; + end if; + + when RefreshCycle_3 => + CPU_T_STATE_SET <= 3; + CPU_T_STATES <= 4; + Z80_RFSHni <= '0'; + FSM_STATE <= RefreshCycle_1; + + ----------------------------- + -- Z80 Write Cycle. + ----------------------------- + when WriteCycle => + FSM_STATUS <= '0'; + if(Z80_CLK_RE = '1' or Z80_CLK_LEVEL = '1') then + CPU_T_STATE_SET<= 1; + CPU_T_STATES <= 3; + FSM_STATE <= WriteCycle_2; + end if; + + when WriteCycle_2 => + if(Z80_CLK_FE = '1' and CPU_T_STATE = 1) then + Z80_MREQni <= '0'; + CPU_DATA_EN <= '1'; + FSM_STATE <= WriteCycle_3; + end if; + + when WriteCycle_3 => + if(CPU_T_STATE = 2 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + Z80_WRni <= '0'; + FSM_STATE <= WriteCycle_4; + end if; + + when WriteCycle_4 => + if(CPU_T_STATE = 3 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + Z80_MREQni <= '1'; + Z80_WRni <= '1'; + FSM_STATE <= IdleCycle; + end if; + + + ----------------------------- + -- Z80 Read Cycle. + ----------------------------- + when ReadCycle => + if(Z80_CLK_RE = '1' or Z80_CLK_LEVEL = '1') then + CPU_T_STATE_SET<= 1; + CPU_T_STATES <= 3; + FSM_STATE <= ReadCycle_2; + end if; + + when ReadCycle_2 => + if(Z80_CLK_FE = '1' and CPU_T_STATE = 1) then + Z80_MREQni <= '0'; + Z80_RDni <= '0'; + FSM_STATE <= ReadCycle_3; + end if; + + when ReadCycle_3 => + if(CPU_T_STATE = 2 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + FSM_STATE <= ReadCycle_4; + end if; + + when ReadCycle_4 => + if(CPU_T_STATE = 3 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + + -- MREQ/RD are deactivated at idle giving 1 clock to latch the data in. + FSM_STATE <= IdleCycle; + end if; + + + ----------------------------- + -- Z80 IO Write Cycle. + ----------------------------- + when WriteIOCycle => + FSM_STATUS <= '0'; + if(Z80_CLK_RE = '1' or Z80_CLK_LEVEL = '1') then + CPU_T_STATE_SET<= 1; + CPU_T_STATES <= 4; + FSM_STATE <= WriteIOCycle_2; + end if; + + when WriteIOCycle_2 => + if(Z80_CLK_FE = '1') then + CPU_DATA_EN <= '1'; + FSM_STATE <= WriteIOCycle_3; + end if; + + when WriteIOCycle_3 => + if(Z80_CLK_FE = '1' and CPU_T_STATE = 2) then + Z80_IORQni <= '0'; + Z80_WRni <= '0'; + FSM_STATE <= WriteIOCycle_4; + end if; + + when WriteIOCycle_4 => + -- Add automatic Wait State (called T3 here but actually TW). + if(CPU_T_STATE = 3 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + FSM_STATE <= WriteIOCycle_5; + end if; + + when WriteIOCycle_5 => + if(CPU_T_STATE = 4 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + Z80_IORQni <= '1'; + Z80_WRni <= '1'; + FSM_STATE <= IdleCycle; + end if; + + ----------------------------- + -- Z80 IO Read Cycle. + ----------------------------- + when ReadIOCycle => + if(Z80_CLK_RE = '1' or Z80_CLK_LEVEL = '1') then + CPU_T_STATE_SET<= 1; + CPU_T_STATES <= 4; + FSM_STATE <= ReadIOCycle_2; + end if; + + when ReadIOCycle_2 => + if(Z80_CLK_FE = '1' and CPU_T_STATE = 2) then + Z80_IORQni <= '0'; + Z80_RDni <= '0'; + FSM_STATE <= ReadIOCycle_3; + end if; + + when ReadIOCycle_3 => + -- Add automatic Wait State. + if(CPU_T_STATE = 3 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + CPU_T_STATE_SET<= 2; + FSM_STATE <= ReadIOCycle_4; + end if; + + when ReadIOCycle_4 => + if(CPU_T_STATE = 4 and Z80_CLK_FE = '1' and Z80_WAITni = '1') then + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + + -- IORA/RD are deactivated at idle giving 1 clock to latch the data in. + FSM_STATE <= IdleCycle; + end if; + + ----------------------------- + -- Halt Request. + ----------------------------- + when HaltCycle => + Z80_HALTni <= '0'; + FSM_STATUS <= '0'; + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 Bus Request. + ----------------------------- + when BusReqCycle => + Z80_BUSRQ_ACKni <= '0'; + FSM_STATE <= IdleCycle; + end case; + + VCPU_CS_EDGE <= VCPU_CS_EDGE(0) & VSOM_SPI_CSn; + end if; + end process; + + -- CPU Interface tri-state control based on acknowledged bus request. + Z80_ADDR <= IPAR & REFRESH_ADDR when Z80_RFSHni = '0' + else + CPU_ADDR when Z80_BUSRQ_ACKni = '1' + else + (others => 'Z'); + Z80_DATA <= CPU_DATA_OUT when Z80_BUSRQ_ACKni = '1' and CPU_DATA_EN = '1' + else + (others => 'Z'); + -- Z80_DATAi <= Z80_DATA when Z80_RDn = '0' + -- else (others => '1'); + Z80_RDn <= Z80_RDni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_WRn <= Z80_WRni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_M1n <= Z80_M1ni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_RFSHn <= Z80_RFSHni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_MREQn <= Z80_MREQni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_IORQn <= Z80_IORQni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_BUSAKn <= Z80_BUSRQ_ACKni; + + -- CPU Interface single state output. + Z80_HALTn <= Z80_HALTni; + + -- CPU Interface single state input. + Z80_NMIni <= Z80_NMIn; + Z80_INTni <= Z80_INTn; + Z80_WAITni <= Z80_WAITn; + Z80_BUSRQni <= Z80_BUSRQn; + + -- SOM Reset. + PM_RESET <= PM_RESETi; + + -- SOM to CPLD Interface. + VSOM_DATA_OUT <= CPU_DATA_IN when VSOM_HBYTE = '1' + else + FSM_STATUS & RFSH_STATUS & Z80_BUSRQ_ACKni & Z80_BUSRQn & Z80_INTn & Z80_NMIn & Z80_WAITn & Z80_RESETn when VSOM_HBYTE = '0' + else + (others => '0'); + + -- Loopback test, echo what was received. + SPI_TX_DATA <= SPI_RX_DATA when SPI_LOOPBACK_TEST = '1' + else + CPU_ADDR & CPU_DATA_IN & FSM_STATUS & RFSH_STATUS & Z80_BUSRQ_ACKni & Z80_BUSRQn & Z80_INTn & Z80_NMIn & Z80_WAITn & Z80_RESETn; + + -- Signal mirrors. + VSOM_READY <= '0' when FSM_STATUS='1' or SPI_NEW_DATA /= SPI_PROCESSING + else '1'; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE <= '1' when CPU_LAST_T_STATE = '1' -- Last T-State in current cycle. + else '0'; + VSOM_BUSRQ <= not Z80_BUSRQn; -- Host device requesting Z80 Bus. + VSOM_BUSACK <= not Z80_BUSRQ_ACKni; -- Host device granted Z80 Bus + VSOM_INT <= not Z80_INTn; -- Z80 INT signal + VSOM_NMI <= not Z80_NMIn; -- Z80 NMI signal + VSOM_WAIT <= not Z80_WAITn; -- Z80 WAIT signal + VSOM_RESET <= not VSOM_RESETni; -- Z80 RESET signal + VSOM_RSV <= (others => '0'); -- Reserved pins. + + -- Video/Audio control signals. + VIDEO_SRC <= VIDEO_SRCi; + MONO_VIDEO_SRC <= MONO_VIDEO_SRCi; + AUDIO_SRC_L <= AUDIO_SRC_Li; + AUDIO_SRC_R <= AUDIO_SRC_Ri; + + -- USB Power Supply enable. + VBUS_EN <= VBUS_ENi; + + -- Monochrome output is based on the incoming VGA to give the best chrominance levels. + MONO_R <= VGA_R; + MONO_G <= VGA_G; + MONO_B <= VGA_B; + + -- Blanking is active when all colour signals are at 0. The DAC converts values in range 4v .. 5v to adjust chrominance + -- but true off can obly be achieved by bringing the signal value to 0v which is achieved by a Mux activated with this blanking signal. + MONO_BLANKn <= '0' when VGA_R = "000" and VGA_G = "000" and VGA_B = "000" + else '1'; + + -- Generate composite sync. + VGA_CSYNCn <= VGA_HSYNCn xor not VGA_VSYNCn; + MONO_CSYNCn <= VGA_HSYNCn xor not VGA_VSYNCn; + + -- DAC clocks. + --VGA_PXL_CLK <= CLK_50M; + MONO_PXL_CLK <= VGA_PXL_CLK; + +end architecture; diff --git a/CPLD/v1.0/MZ700/tzpuFusionX_Toplevel.vhd b/CPLD/v1.0/MZ700/tzpuFusionX_Toplevel.vhd new file mode 100644 index 000000000..484aa3e1a --- /dev/null +++ b/CPLD/v1.0/MZ700/tzpuFusionX_Toplevel.vhd @@ -0,0 +1,222 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX_Toplevel.vhd +-- Version: MZ-700 +-- Created: June 2020 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD Top Level module. +-- +-- This module contains the basic pin definition of the CPLD<->logic needed in the +-- project which targets the MZ-700 host. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: June 2020 - Snapshot taken from the MZ80A version of the tranZPUter SW-700 source. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.tzpuFusionX_pkg.all; +library altera; +use altera.altera_syn_attributes.all; + +entity tzpuFusionX_MZ700 is + port ( + -- Z80 Address Bus + Z80_ADDR : inout std_logic_vector(15 downto 0); + + -- Z80 Data Bus + Z80_DATA : inout std_logic_vector(7 downto 0); + + -- Z80 Control signals. + Z80_BUSRQn : in std_logic; + Z80_BUSAKn : out std_logic; + Z80_INTn : in std_logic; + Z80_IORQn : inout std_logic; + Z80_MREQn : inout std_logic; + Z80_NMIn : in std_logic; + Z80_RDn : inout std_logic; + Z80_WRn : inout std_logic; + Z80_RESETn : in std_logic; -- Host CPU Reset signal, also CPLD reset. + Z80_HALTn : out std_logic; + Z80_WAITn : in std_logic; + Z80_M1n : inout std_logic; + Z80_RFSHn : inout std_logic; + + -- SOM SPI + VSOM_SPI_CSn : in std_logic; -- SPI Slave Select + VSOM_SPI_CLK : in std_logic; -- SPI Clock + VSOM_SPI_MOSI : in std_logic; -- SPI Master Output Slave Input + VSOM_SPI_MISO : out std_logic; -- SPI Master Input Slave Output + + -- SOM Parallel Bus. + VSOM_DATA_OUT : out std_logic_vector(7 downto 0); -- Address/Data bus for CPLD control registers. + VSOM_HBYTE : in std_logic; -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY : out std_logic; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE : out std_logic; -- Last T-State in current cycle, 1 = active. + VSOM_BUSRQ : out std_logic; -- Host device requesting Z80 Bus. + VSOM_BUSACK : out std_logic; -- Host device granted Z80 Bus + VSOM_INT : out std_logic; -- Z80 INT signal + VSOM_NMI : out std_logic; -- Z80 NMI signal + VSOM_WAIT : out std_logic; -- Z80 WAIT signal + VSOM_RESET : out std_logic; -- Z80 RESET signal + VSOM_RSV : out std_logic_vector(1 downto 1); -- Reserved pins. + + -- SOM Control Signals + PM_RESET : out std_logic; -- Reset SOM + + -- VGA_Palette Control + VGA_R : in std_logic_vector(9 downto 7); -- Signals used for detecting blank or no video output. + VGA_G : in std_logic_vector(9 downto 7); + VGA_B : in std_logic_vector(9 downto 8); + + -- VGA Control Signals + VGA_PXL_CLK : in std_logic; -- VGA Pixel clock for DAC conversion. + VGA_DISPEN : in std_logic; -- Displayed Enabled (SOM video output). + VGA_VSYNCn : in std_logic; -- SOM VSync. + VGA_HSYNCn : in std_logic; -- SOM HSync. + VGA_COLR : out std_logic; -- COLR colour carrier frequency. + VGA_CSYNCn : out std_logic; -- VGA Composite Sync. + VGA_BLANKn : out std_logic; -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK : out std_logic; -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn : out std_logic; -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn : out std_logic; -- Mono CRT composite sync. + MONO_RSV : out std_logic; + + -- CRT Lower Chrominance Control + MONO_R : out std_logic_vector(2 downto 0); -- Signals to fine tune Red level of monochrome chrominance. + MONO_G : out std_logic_vector(2 downto 0); -- Signals to fine tune Green level of monochrome chrominance. + MONO_B : out std_logic_vector(2 downto 1); -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC : out std_logic; -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC : out std_logic; -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L : out std_logic; -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R : out std_logic; -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals + MB_RESETn : in std_logic; -- Motherboard Reset pressed. + MB_IPLn : in std_logic; -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN : out std_logic; -- USB Enable Power Output + + -- Clocks. + Z80_CLK : in std_logic; -- Host CPU Clock + CLK_50M : in std_logic -- 50MHz oscillator. + ); +END entity; + +architecture rtl of tzpuFusionX_MZ700 is + +begin + + cpldl512Toplevel : entity work.cpld512 + generic map ( + SPI_CLK_POLARITY => '0' + ) + port map + ( + -- Z80 Address Bus + Z80_ADDR => Z80_ADDR, + + -- Z80 Data Bus + Z80_DATA => Z80_DATA, + + -- Z80 Control signals. + Z80_BUSRQn => Z80_BUSRQn, + Z80_BUSAKn => Z80_BUSAKn, + Z80_INTn => Z80_INTn, + Z80_IORQn => Z80_IORQn, + Z80_MREQn => Z80_MREQn, + Z80_NMIn => Z80_NMIn, + Z80_RDn => Z80_RDn, + Z80_WRn => Z80_WRn, + Z80_RESETn => Z80_RESETn, + Z80_HALTn => Z80_HALTn, + Z80_WAITn => Z80_WAITn, + Z80_M1n => Z80_M1n, + Z80_RFSHn => Z80_RFSHn, + + -- SOM SPI + VSOM_SPI_CSn => VSOM_SPI_CSn, -- SPI Slave Select + VSOM_SPI_CLK => VSOM_SPI_CLK, -- SPI Clock + VSOM_SPI_MOSI => VSOM_SPI_MOSI, -- SPI Master Output Slave Input + VSOM_SPI_MISO => VSOM_SPI_MISO, -- SPI Master Input Slave Output + + -- SOM Parallel Bus. + VSOM_DATA_OUT => VSOM_DATA_OUT, -- Address/Data bus for CPLD control registers. + VSOM_HBYTE => VSOM_HBYTE, -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY => VSOM_READY, -- FSM Ready (1), Busy (0) + VSOM_LTSTATE => VSOM_LTSTATE, -- Last T-State in current cycle. + VSOM_BUSRQ => VSOM_BUSRQ, -- Host device requesting Z80 Bus. + VSOM_BUSACK => VSOM_BUSACK, -- Host device granted Z80 Bus + VSOM_INT => VSOM_INT, -- Z80 INT signal + VSOM_NMI => VSOM_NMI, -- Z80 NMI signal + VSOM_WAIT => VSOM_WAIT, -- Z80 WAIT signal + VSOM_RESET => VSOM_RESET, -- Z80 RESET signal + VSOM_RSV => VSOM_RSV, -- Reserved pins. + + -- SOM Control Signals + PM_RESET => PM_RESET, -- Reset SOM + + -- VGA_Palette Control + VGA_R => VGA_R, -- Signals used for detecting blank or no video output. + VGA_G => VGA_G, + VGA_B => VGA_B, + + -- VGA Control Signals + VGA_PXL_CLK => VGA_PXL_CLK, -- VGA Pixel clock for DAC conversion. + VGA_DISPEN => VGA_DISPEN, -- Displayed Enabled (SOM video output). + VGA_VSYNCn => VGA_VSYNCn, -- SOM VSync. + VGA_HSYNCn => VGA_HSYNCn, -- SOM HSync. + VGA_COLR => VGA_COLR, -- COLR colour carrier frequency. + VGA_CSYNCn => VGA_CSYNCn, -- VGA Composite Sync. + VGA_BLANKn => VGA_BLANKn, -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK => MONO_PXL_CLK, -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn => MONO_BLANKn, -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn => MONO_CSYNCn, -- Mono CRT composite sync. + MONO_RSV => MONO_RSV, + + -- CRT Lower Chrominance Control + MONO_R => MONO_R, -- Signals to fine tune Red level of monochrome chrominance. + MONO_G => MONO_G, -- Signals to fine tune Green level of monochrome chrominance. + MONO_B => MONO_B, -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC => VIDEO_SRC, -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC => MONO_VIDEO_SRC, -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L => AUDIO_SRC_L, -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R => AUDIO_SRC_R, -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals=> MONO_R, + MB_RESETn => MB_RESETn, -- Motherboard Reset pressed. + MB_IPLn => MB_IPLn, -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN => VBUS_EN, -- USB Enable Power Output + + -- Clocks. + Z80_CLK => Z80_CLK, -- Host CPU Clock + CLK_50M => CLK_50M -- 50MHz oscillator. + ); + +end architecture; diff --git a/CPLD/v1.0/MZ700/tzpuFusionX_pkg.vhd b/CPLD/v1.0/MZ700/tzpuFusionX_pkg.vhd new file mode 100644 index 000000000..189389673 --- /dev/null +++ b/CPLD/v1.0/MZ700/tzpuFusionX_pkg.vhd @@ -0,0 +1,221 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX_pkg.vhd +-- Created: June 2020 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD configuration file. +-- +-- This module contains parameters for the CPLD in the tzpuFusionX project +-- which targets the MZ-700 host. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: June 2020 - Snapshot taken from the MZ700 version of the tranZPUter SW-700 source. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +package tzpuFusionX_pkg is + + ------------------------------------------------------------ + -- Constants + ------------------------------------------------------------ + + -- Potential logic state constants. + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + constant HIZ : std_logic := 'Z'; + + -- CPLD Command instructions. + constant CPLD_CMD_RESET_HOST : integer := 1; + constant CPLD_CMD_HOLD_HOST_BUS : integer := 2; + constant CPLD_CMD_RELEASE_HOST_BUS: integer := 3; + + -- Target hardware modes. + constant MODE_MZ80K : integer := 0; + constant MODE_MZ80C : integer := 1; + constant MODE_MZ1200 : integer := 2; + constant MODE_MZ80A : integer := 3; + constant MODE_MZ700 : integer := 4; + constant MODE_MZ800 : integer := 5; + constant MODE_MZ80B : integer := 6; + constant MODE_MZ2000 : integer := 7; + + -- Memory management modes. + constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063). + constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted. + constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected. + constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1. + constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2. + constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3. + constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected. + -- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_COMPAT : integer := 08; -- Compatibility monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF. + constant TZMM_HOSTACCESS : integer := 09; -- Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory. + constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard. + constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ800 : integer := 15; -- MZ800 Mode - Running on MZ800 hardware, configuration set according to MZ700/MZ800 mode. + constant TZMM_MZ2000 : integer := 16; -- MZ2000 Mode - Running on MZ2000 hardware, configuration set according to runtime configuration registers. + constant TZMM_FPGA : integer := 21; -- Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked. + constant TZMM_TZPUM : integer := 22; -- Everything in on mainboard, no access to tranZPUter memory. + constant TZMM_TZPU : integer := 23; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected. + constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected. + constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected. + constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected. + constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected. + constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected. + constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected. + + + + ------------------------------------------------------------ + -- Configurable parameters. + ------------------------------------------------------------ + -- Target hardware. + constant CPLD_HOST_HW : integer := MODE_MZ700; + + -- Target video hardware. + constant CPLD_HAS_FPGA_VIDEO : std_logic := '1'; + + -- Version of hdl. + constant CPLD_VERSION : integer := 2; + + -- Clock source for the secondary clock. If a K64F is installed then enable it otherwise use the onboard oscillator. + -- + constant USE_K64F_CTL_CLOCK : integer := 1; + + ------------------------------------------------------------ + -- Function prototypes + ------------------------------------------------------------ + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer; + + -- Function to reverse the order of the bits in a standard logic vector. + -- ie. 1010 becomes 0101 + function reverse_vector(slv:std_logic_vector) return std_logic_vector; + + -- Function to convert an integer (0 or 1) into std_logic. + -- + function to_std_logic(i : in integer) return std_logic; + + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural; + + ------------------------------------------------------------ + -- Records + ------------------------------------------------------------ + + ------------------------------------------------------------ + -- Components + ------------------------------------------------------------ + +end tzpuFusionX_pkg; + +------------------------------------------------------------ +-- Function definitions. +------------------------------------------------------------ +package body tzpuFusionX_pkg is + + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer is + begin + if a > b then + return a; + else + return b; + end if; + return a; + end function IntMax; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural is + variable tmp : positive := 1; + variable log : natural := 0; + begin + if arg = 1 then + return 0; + end if; + + while arg > tmp loop + tmp := tmp * 2; + log := log + 1; + end loop; + return log; + end function; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer is + variable ticks : real; + variable fracTicks : real; + begin + ticks := (Real(period) * Real(clock)) / 1000000000.0; + fracTicks := ticks - CEIL(ticks); + if fracTicks > 0.0001 then + return Integer(CEIL(ticks + 1.0)); + else + return Integer(CEIL(ticks)); + end if; + end function; + + function reverse_vector(slv:std_logic_vector) return std_logic_vector is + variable target : std_logic_vector(slv'high downto slv'low); + begin + for idx in slv'high downto slv'low loop + target(idx) := slv(slv'low + (slv'high-idx)); + end loop; + return target; + end reverse_vector; + + function to_std_logic(i : in integer) return std_logic is + begin + if i = 0 then + return '0'; + end if; + return '1'; + end function; + + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural is + begin + if s = '1' then + return 1; + else + return 0; + end if; + end function; +end package body; diff --git a/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qpf b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qpf new file mode 100644 index 000000000..a802e0b1f --- /dev/null +++ b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:29:32 June 24, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "16:29:32 September 10, 2021" + +# Revisions + +PROJECT_REVISION = "tzpuFusionX_MZ80A" diff --git a/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf new file mode 100644 index 000000000..39de4a6f9 --- /dev/null +++ b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf @@ -0,0 +1,243 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:29:32 June 24, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# tzpuFusionX.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY MAX7000AE +set_global_assignment -name DEVICE "EPM7512AETC144-10" +set_global_assignment -name TOP_LEVEL_ENTITY tzpuFusionX_MZ80A +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL + +# Z80 Data Bus +# ============ +set_location_assignment PIN_81 -to Z80_DATA[0] +set_location_assignment PIN_78 -to Z80_DATA[1] +set_location_assignment PIN_87 -to Z80_DATA[2] +set_location_assignment PIN_100 -to Z80_DATA[3] +set_location_assignment PIN_102 -to Z80_DATA[4] +set_location_assignment PIN_93 -to Z80_DATA[5] +set_location_assignment PIN_94 -to Z80_DATA[6] +set_location_assignment PIN_84 -to Z80_DATA[7] + +# Z80 Control signals. +# ==================== +set_location_assignment PIN_69 -to Z80_INTn +set_location_assignment PIN_70 -to Z80_NMIn +set_location_assignment PIN_71 -to Z80_HALTn +set_location_assignment PIN_68 -to Z80_MREQn +set_location_assignment PIN_65 -to Z80_IORQn +set_location_assignment PIN_67 -to Z80_RDn +set_location_assignment PIN_66 -to Z80_WRn +set_location_assignment PIN_63 -to Z80_BUSAKn +set_location_assignment PIN_62 -to Z80_WAITn +set_location_assignment PIN_61 -to Z80_BUSRQn +set_location_assignment PIN_79 -to Z80_RFSHn +set_location_assignment PIN_60 -to Z80_M1n +set_location_assignment PIN_56 -to Z80_RESETn +set_location_assignment PIN_101 -to Z80_CLK + +# Z80 Address Bus +# =============== +set_location_assignment PIN_80 -to Z80_ADDR[0] +set_location_assignment PIN_90 -to Z80_ADDR[1] +set_location_assignment PIN_83 -to Z80_ADDR[2] +set_location_assignment PIN_86 -to Z80_ADDR[3] +set_location_assignment PIN_88 -to Z80_ADDR[4] +set_location_assignment PIN_91 -to Z80_ADDR[5] +set_location_assignment PIN_92 -to Z80_ADDR[6] +set_location_assignment PIN_96 -to Z80_ADDR[7] +set_location_assignment PIN_97 -to Z80_ADDR[8] +set_location_assignment PIN_98 -to Z80_ADDR[9] +set_location_assignment PIN_99 -to Z80_ADDR[10] +set_location_assignment PIN_110 -to Z80_ADDR[11] +set_location_assignment PIN_108 -to Z80_ADDR[12] +set_location_assignment PIN_107 -to Z80_ADDR[13] +set_location_assignment PIN_106 -to Z80_ADDR[14] +set_location_assignment PIN_103 -to Z80_ADDR[15] + +# SOM SPI +# ======= +set_location_assignment PIN_32 -to VSOM_SPI_CSn +set_location_assignment PIN_31 -to VSOM_SPI_CLK +set_location_assignment PIN_30 -to VSOM_SPI_MOSI +set_location_assignment PIN_29 -to VSOM_SPI_MISO + +# SOM Parallel Bus +# ================ +set_location_assignment PIN_41 -to VSOM_DATA_OUT[0] +set_location_assignment PIN_40 -to VSOM_DATA_OUT[1] +set_location_assignment PIN_39 -to VSOM_DATA_OUT[2] +set_location_assignment PIN_38 -to VSOM_DATA_OUT[3] +set_location_assignment PIN_37 -to VSOM_DATA_OUT[4] +set_location_assignment PIN_36 -to VSOM_DATA_OUT[5] +set_location_assignment PIN_35 -to VSOM_DATA_OUT[6] +set_location_assignment PIN_34 -to VSOM_DATA_OUT[7] +set_location_assignment PIN_132 -to VSOM_HBYTE + +# SOM Reserved signals. +# ===================== +set_location_assignment PIN_21 -to VSOM_RSV[1] + +# SOM Control Signals +# =================== +set_location_assignment PIN_28 -to VSOM_READY +set_location_assignment PIN_18 -to VSOM_LTSTATE +set_location_assignment PIN_27 -to VSOM_BUSRQ +set_location_assignment PIN_26 -to VSOM_BUSACK +set_location_assignment PIN_19 -to VSOM_INT +set_location_assignment PIN_22 -to VSOM_NMI +set_location_assignment PIN_25 -to VSOM_WAIT +set_location_assignment PIN_23 -to VSOM_RESET +set_location_assignment PIN_16 -to PM_RESET + +# VGA_Palette Control +# =================== +set_location_assignment PIN_133 -to VGA_R[7] +set_location_assignment PIN_137 -to VGA_R[8] +set_location_assignment PIN_140 -to VGA_R[9] +set_location_assignment PIN_134 -to VGA_G[7] +set_location_assignment PIN_138 -to VGA_G[8] +set_location_assignment PIN_141 -to VGA_G[9] +set_location_assignment PIN_136 -to VGA_B[8] +set_location_assignment PIN_139 -to VGA_B[9] + + +# VGA Control Signals +# =================== +set_location_assignment PIN_142 -to VGA_PXL_CLK +set_location_assignment PIN_14 -to VGA_DISPEN +set_location_assignment PIN_12 -to VGA_VSYNCn +set_location_assignment PIN_11 -to VGA_HSYNCn +set_location_assignment PIN_82 -to VGA_COLR +set_location_assignment PIN_109 -to VGA_CSYNCn +set_location_assignment PIN_143 -to VGA_BLANKn + +# CRT Control Signals +# =================== +set_location_assignment PIN_15 -to MONO_PXL_CLK +set_location_assignment PIN_114 -to MONO_BLANKn +set_location_assignment PIN_113 -to MONO_CSYNCn +set_location_assignment PIN_116 -to MONO_RSV + +# CRT Lower Chrominance Control +# ============================= +set_location_assignment PIN_1 -to MONO_R[0] +set_location_assignment PIN_6 -to MONO_R[1] +set_location_assignment PIN_10 -to MONO_R[2] +set_location_assignment PIN_2 -to MONO_G[0] +set_location_assignment PIN_7 -to MONO_G[1] +set_location_assignment PIN_9 -to MONO_G[2] +set_location_assignment PIN_5 -to MONO_B[1] +set_location_assignment PIN_8 -to MONO_B[2] + +# MUX Control Signals +# =================== +set_location_assignment PIN_72 -to VIDEO_SRC +set_location_assignment PIN_74 -to MONO_VIDEO_SRC +set_location_assignment PIN_77 -to AUDIO_SRC_L +set_location_assignment PIN_75 -to AUDIO_SRC_R + +# Mainboard Reset Signals +# ======================= +#set_location_assignment PIN_127 -to CPU_RESETn +set_location_assignment PIN_122 -to MB_RESETn +set_location_assignment PIN_111 -to MB_IPLn + +# USB Power Control +# ================= +set_location_assignment PIN_55 -to VBUS_EN + +# Clocks +# ====== +#set_location_assignment PIN_125 -to CPU_CLK +set_location_assignment PIN_128 -to CLK_50M + +# Unused ports +# ============ +#set_location_assignment PIN_42 -to +#set_location_assignment PIN_43 -to +#set_location_assignment PIN_44 -to +#set_location_assignment PIN_45 -to +#set_location_assignment PIN_112 -to +#set_location_assignment PIN_131 -to +#set_location_assignment PIN_117 -to +#set_location_assignment PIN_118 -to +#set_location_assignment PIN_119 -to +#set_location_assignment PIN_120 -to +#set_location_assignment PIN_121 -to +#set_location_assignment PIN_25 -to +#set_location_assignment PIN_53 -to +#set_location_assignment PIN_128 -to +#set_location_assignment PIN_47 -to +#set_location_assignment PIN_54 -to +#set_location_assignment PIN_127 -to +#set_location_assignment PIN_125 -to +#set_location_assignment PIN_48 -to +#set_location_assignment PIN_46 -to +#set_location_assignment PIN_49 -to + + +set_global_assignment -name VHDL_FILE ../tzpuFusionX_Toplevel.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX_pkg.vhd +set_global_assignment -name VHDL_FILE ../tzpuFusionX.vhd +set_global_assignment -name SDC_FILE tzpuFusionX_MZ80A_constraints.sdc + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name AUTO_RESOURCE_SHARING OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF + +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF +set_global_assignment -name AUTO_LCELL_INSERTION ON + +set_global_assignment -name CDF_FILE output_files/tzpuFusionX_MZ80A.cdf diff --git a/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A_constraints.sdc b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A_constraints.sdc new file mode 100644 index 000000000..2748108c7 --- /dev/null +++ b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A_constraints.sdc @@ -0,0 +1,324 @@ +## Generated SDC file "tzpuFusionX.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jun 26 22:10:05 2020" + +## +## DEVICE "EPM7160STC100-10" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +# Standard mainboard clock. If using tzpuFusionX on a different host then set to the host frequency. +create_clock -name {Z80_CLK} -period 500.000 -waveform { 0.000 250.000 } [get_ports { Z80_CLK }] + +# For 50MHz crystal. +create_clock -name {CLK_50M} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CLK_50M }] + +# For SPI CSn +#create_clock -name {VSOM_SPI_CSn} -period 200.000 -waveform { 160.000 40.000 } [ get_ports { VSOM_SPI_CSn }] + +# For SPI CLK +create_clock -name {VSOM_SPI_CLK} -period 14.000 -waveform { 0.000 7.000 } [ get_ports { VSOM_SPI_CLK }] + +# For basic board with oscillator. +#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }] +#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ] +##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSEL}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HI_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_ADDR[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {R_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {G_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {B_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {COLR_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CSYNC_IN}] +##set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {HSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VSYNC_IN}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_DATA[*]}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSACKn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CS2n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_ADDR[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_DATA[*]}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_CLK}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_RDn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_WRn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A18_INTn_V_R}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSRQn_V_G}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A16_WAITn_V_B}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A17_NMIn_V_COLR}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HALTn}] +#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RFSHn}] + +# For K64F +#set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}] + +# For basic board with oscillator. +#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}] + +#************************************************************** +# Set Max Delay +#************************************************************** +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 40.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 30.000 +#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 30.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 30.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 50.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 60.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 45.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000 +#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 60.000 + +#************************************************************** +# Set Min Delay +#************************************************************** +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 1.000 +#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000 +#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000 + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +# For K64F +#set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For basic board with oscillator. +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For both configurations. +#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +#set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} + +#************************************************************** +# Set Multicycle Path +#************************************************************** +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2 +#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/CPLD/v1.0/MZ80A/tzpuFusionX.vhd b/CPLD/v1.0/MZ80A/tzpuFusionX.vhd new file mode 100644 index 000000000..0b9d5c013 --- /dev/null +++ b/CPLD/v1.0/MZ80A/tzpuFusionX.vhd @@ -0,0 +1,982 @@ +------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX.vhd +-- Version: MZ-80A +-- Created: Nov 2022 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD logic definition file. +-- This module contains the definition of the tzpuFusionX project plus enhancements +-- for the MZ-80A. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: Nov 2022 - Initial write for the MZ-2000, adaption to MZ-80A underway. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use work.tzpuFusionX_pkg.all; + +entity cpld512 is + generic ( + SPI_CLK_POLARITY : std_logic := '0' + ); + port ( + -- Z80 Address Bus + Z80_ADDR : inout std_logic_vector(15 downto 0); + + -- Z80 Data Bus + Z80_DATA : inout std_logic_vector(7 downto 0); + + -- Z80 Control signals. + Z80_BUSRQn : in std_logic; + Z80_BUSAKn : out std_logic; + Z80_INTn : in std_logic; + Z80_IORQn : inout std_logic; + Z80_MREQn : inout std_logic; + Z80_NMIn : in std_logic; + Z80_RDn : inout std_logic; + Z80_WRn : inout std_logic; + Z80_RESETn : in std_logic; -- Host CPU Reset signal, also CPLD reset. + Z80_HALTn : out std_logic; + Z80_WAITn : in std_logic; + Z80_M1n : inout std_logic; + Z80_RFSHn : inout std_logic; + + -- SOM Control Signals + VSOM_SPI_CLK : in std_logic; -- SOM SPI Channel 0 Clock. + VSOM_SPI_MOSI : in std_logic; -- MOSI Input. + VSOM_SPI_MISO : out std_logic; -- MISO Output. + VSOM_SPI_CSn : in std_logic; -- Enable. + + -- SOM Parallel Bus. + VSOM_DATA_OUT : out std_logic_vector(7 downto 0); -- Address/Data bus for CPLD control registers. + VSOM_HBYTE : in std_logic; -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY : out std_logic; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE : out std_logic; -- Last T-State in current cycle, 1 = active. + VSOM_BUSRQ : out std_logic; -- Host device requesting Z80 Bus. + VSOM_BUSACK : out std_logic; -- Host device granted Z80 Bus + VSOM_INT : out std_logic; -- Z80 INT signal + VSOM_NMI : out std_logic; -- Z80 NMI signal + VSOM_WAIT : out std_logic; -- Z80 WAIT signal + VSOM_RESET : out std_logic; -- Z80 RESET signal + VSOM_RSV : out std_logic_vector(1 downto 1); -- Reserved pins. + + -- SOM Control Signals + PM_RESET : out std_logic; -- Reset SOM + + -- VGA_Palette Control + VGA_R : in std_logic_vector(9 downto 7); -- Signals used for detecting blank or no video output. + VGA_G : in std_logic_vector(9 downto 7); + VGA_B : in std_logic_vector(9 downto 8); + + -- VGA Control Signals + VGA_PXL_CLK : in std_logic; -- VGA Pixel clock for DAC conversion. + VGA_DISPEN : in std_logic; -- Displayed Enabled (SOM video output). + VGA_VSYNCn : in std_logic; -- SOM VSync. + VGA_HSYNCn : in std_logic; -- SOM HSync. + VGA_COLR : out std_logic; -- COLR colour carrier frequency. + VGA_CSYNCn : out std_logic; -- VGA Composite Sync. + VGA_BLANKn : out std_logic; -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK : out std_logic; -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn : out std_logic; -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn : out std_logic; -- Mono CRT composite sync. + MONO_RSV : out std_logic; + + -- CRT Lower Chrominance Control + MONO_R : out std_logic_vector(2 downto 0); -- Signals to fine tune Red level of monochrome chrominance. + MONO_G : out std_logic_vector(2 downto 0); -- Signals to fine tune Green level of monochrome chrominance. + MONO_B : out std_logic_vector(2 downto 1); -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC : out std_logic; -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC : out std_logic; -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L : out std_logic; -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R : out std_logic; -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals + MB_RESETn : in std_logic; -- Motherboard Reset pressed. + MB_IPLn : in std_logic; -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN : out std_logic; -- USB Enable Power Output + + -- Clocks. + Z80_CLK : in std_logic; -- Host CPU Clock + CLK_50M : in std_logic -- 50MHz oscillator. + ); +end entity; + +architecture rtl of cpld512 is + + -- Finite State Machine states. + type SOMFSMState is + ( + IdleCycle, + FetchCycle, + FetchCycle_11, + FetchCycle_20, + FetchCycle_21, + FetchCycle_30, + RefreshCycle, + RefreshCycle_11, + RefreshCycle_20, + RefreshCycle_21, + RefreshCycle_3, + WriteCycle, + WriteCycle_11, + WriteCycle_20, + WriteCycle_21, + WriteCycle_30, + WriteCycle_31, + ReadCycle, + ReadCycle_11, + ReadCycle_20, + ReadCycle_21, + ReadCycle_30, + ReadCycle_31, + WriteIOCycle, + WriteIOCycle_11, + WriteIOCycle_20, + WriteIOCycle_21, + WriteIOCycle_30, + WriteIOCycle_31, + WriteIOCycle_40, + WriteIOCycle_41, + ReadIOCycle, + ReadIOCycle_11, + ReadIOCycle_20, + ReadIOCycle_21, + ReadIOCycle_30, + ReadIOCycle_31, + ReadIOCycle_40, + ReadIOCycle_41, + HaltCycle, + BusReqCycle + ); + + -- CPU Interface internal signals. + signal Z80_BUSRQni : std_logic; + signal Z80_INTni : std_logic; + signal Z80_IORQni : std_logic; + signal Z80_MREQni : std_logic; + signal Z80_NMIni : std_logic; + signal Z80_RDni : std_logic; + signal Z80_WRni : std_logic; + signal Z80_HALTni : std_logic; + signal Z80_M1ni : std_logic; + signal Z80_RFSHni : std_logic; + signal Z80_DATAi : std_logic_vector(7 downto 0); + signal Z80_BUSRQ_ACKni : std_logic; + + -- Internal CPU state control. + signal CPU_ADDR : std_logic_vector(15 downto 0) := (others => '0'); + signal CPU_DATA_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal CPU_DATA_OUT : std_logic_vector(7 downto 0) := (others => '0'); + signal CPU_DATA_EN : std_logic; + + -- Clocks. + signal CLK_25Mi : std_logic := '0'; + + -- Reset control + signal PM_RESETi : std_logic := '1'; + signal VSOM_RESETni : std_logic := '1'; + + -- Refresh control. + signal FSM_STATE : SOMFSMState := IdleCycle; + signal NEW_SPI_CMD : std_logic := '0'; + signal VCPU_CS_EDGE : std_logic_vector(1 downto 0) := "11"; + signal AUTOREFRESH_CNT : integer range 0 to 7; + signal FSM_STATUS : std_logic := '0'; + signal FSM_CHECK_WAIT : std_logic := '0'; + signal FSM_WAIT_ACTIVE : std_logic := '0'; + signal RFSH_STATUS : std_logic := '0'; + signal REFRESH_ADDR : std_logic_vector(7 downto 0); + signal IPAR : std_logic_vector(7 downto 0); + signal AUTOREFRESH : std_logic; + + -- Clock edge detection and flagging. + signal Z80_CLKi : std_logic; + signal Z80_CLK_LAST : std_logic_vector(1 downto 0); + signal Z80_CLK_RE : std_logic; + signal Z80_CLK_FE : std_logic; + signal Z80_CLK_TGL : std_logic; + signal CPU_T_STATE_SET : integer range 0 to 5; + signal CPU_LAST_T_STATE : std_logic := '0'; + + -- SPI Slave interface. + signal SPI_SHIFT_EN : std_logic; + signal SPI_TX_SREG : std_logic_vector(6 downto 0); -- TX Shift Register + signal SPI_RX_SREG : std_logic_vector(7 downto 0); -- RX Shift Register + signal SPI_TX_DATA : std_logic_vector(31 downto 0); -- Data to transmit. + signal SPI_RX_DATA : std_logic_vector(31 downto 0); -- Data received. + signal SPI_BIT_CNT : integer range 0 to 16; -- Count of bits tx/rx'd. + signal SPI_FRAME_CNT : integer range 0 to 4; -- Number of frames received (8bit chunks). + + -- SPI Command interface. + signal SOM_CMD : std_logic_vector(7 downto 0) := (others => '0'); + signal SPI_NEW_DATA : std_logic; + signal SPI_PROCESSING : std_logic; + signal SPI_CPU_ADDR : std_logic_vector(15 downto 0) := (others => '0'); + signal SPI_CPU_DATA : std_logic_vector(7 downto 0) := (others => '0'); + + -- Test modes. + signal SPI_LOOPBACK_TEST : std_logic := '0'; + + -- Video/Audio control + signal VIDEO_SRCi : std_logic := '0'; + signal MONO_VIDEO_SRCi : std_logic := '0'; + signal AUDIO_SRC_Li : std_logic := '0'; + signal AUDIO_SRC_Ri : std_logic := '0'; + signal VBUS_ENi : std_logic := '1'; + + + function to_std_logic(L: boolean) return std_logic is + begin + if L then + return('1'); + else + return('0'); + end if; + end function to_std_logic; +begin + + + -- System RESET. + -- + -- Multiple reset sources, Z80_RESETn, MB_IPLn, MB_RESETn. On the MZ-80A, MB_RESETn is a full reset to the power on state. + -- Like the MZ-700, we trigger on Z80_RESETn after having sampled the MB_RESETn state to decide on any extra actions needed within + -- the CPLD and the signals are forwarded onto the SOM so it too can take the correct reset path. + -- + -- If the external reset switch is pressed, a Z80_RESETn is invoked sending the signal low for approx 30ms. + -- On the first edge the VSOM_RESETn signal is set which allows the SOM to see it and the Z80 application to enter a reset state. + -- On the second edge, if occurring within 1 second of the first, the PM_RESET signal to the SOM is triggered, held low for 1 second, + -- forcing the SOM to reboot. + SYSRESET: process( Z80_CLKi, Z80_RESETn ) + variable timer1 : integer range 0 to 354000 := 0; + variable timer100 : integer range 0 to 10 := 0; + variable timerPMReset : integer range 0 to 10 := 0; + variable resetCount : integer range 0 to 3 := 0; + variable cpuResetEdge : std_logic := '1'; + begin + -- Synchronous on the HOST Clock. + if(rising_edge(Z80_CLKi)) then + + -- If the PM Reset timer is active, count down and on expiry release the SOM PM_RESET line. + if(timerPMReset = 0 and PM_RESETi = '1') then + PM_RESETi <= '0'; + end if; + + -- If the VSOM_RESETni is active after reset timer expiry, cancel the RESET state. + if(timerPMReset = 0 and VSOM_RESETni = '0') then + VSOM_RESETni <= '1'; + end if; + + -- Each time the reset button is pressed, count the edges. + if(Z80_RESETn = '0' and cpuResetEdge = '1' and (resetCount = 0 or timer100 > 5)) then + resetCount := resetCount + 1; + VSOM_RESETni <= '0'; + timerPMReset := 5; + timer100 := 0; + + -- If there are 2 or more reset signals in a given period it means a SOM reset is required. + if(resetCount >= 2) then + PM_RESETi <= '1'; + timerPMReset := 10; + resetCount := 0; + end if; + + end if; + + -- 100ms interval. + if(timer1 = 354000) then + timer100 := timer100 + 1; + + if(timer100 >= 10) then + timer100 := 0; + resetCount := 0; + end if; + + if(timerPMReset > 0) then + timerPMReset := timerPMReset - 1; + end if; + end if; + + timer1 := timer1 - 1; + cpuResetEdge := Z80_RESETn; + end if; + end process; + + -- Create Mono DAC Clock based on primary clock. + MONOCLK: process( CLK_50M ) + begin + if(rising_edge(CLK_50M)) then + CLK_25Mi <= not CLK_25Mi; + end if; + end process; + + -- SPI Slave input. Receive command and data from the SOM. + SPI_INPUT : process(VSOM_SPI_CLK) + begin + -- SPI_CLK_POLARITY='0' => falling edge; SPI_CLK_POLARITY='1' => rising edge + if(VSOM_SPI_CLK'event and VSOM_SPI_CLK = SPI_CLK_POLARITY) then + if(VSOM_SPI_CSn = '0') then + SPI_RX_SREG <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + -- End of frame then store the data prior to next bit arrival. + -- Convert to Little Endian, same as SOM. + if(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 1 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(7 downto 0) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 2 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(15 downto 8) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 3 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(23 downto 16) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + + elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 4 and SPI_BIT_CNT = 0) then + SPI_RX_DATA(31 downto 24) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; + end if; + end if; + end if; + end process; + + -- SPI Slave output. Return the current data set as selected by the input signals XACT. + SPI_OUTPUT : process(VSOM_SPI_CLK,VSOM_SPI_CSn,SPI_TX_DATA) + begin + if(VSOM_SPI_CSn = '1') then + SPI_SHIFT_EN <= '0'; + SPI_BIT_CNT <= 15; + + -- SPI_CLK_POLARITY='0' => falling edge; SPI_CLK_POLARITY='1' => risinge edge + elsif(VSOM_SPI_CLK'event and VSOM_SPI_CLK = not SPI_CLK_POLARITY) then + SPI_SHIFT_EN <= '1'; + + if(SPI_BIT_CNT > 0) then + SPI_BIT_CNT <= SPI_BIT_CNT - 1; + end if; + + VSOM_SPI_MISO <= SPI_TX_SREG(6); + SPI_TX_SREG <= SPI_TX_SREG(5 downto 0) & '0'; + + -- First clock after CS goes active, load up the data to be sent to the SOM. + if(SPI_SHIFT_EN = '0' or SPI_BIT_CNT = 0) then + + if(SPI_LOOPBACK_TEST = '1') then + VSOM_SPI_MISO<= SPI_RX_SREG(7); + SPI_TX_SREG <= SPI_RX_SREG(6 downto 0); + + elsif(SPI_SHIFT_EN = '0') then + SPI_FRAME_CNT<= 1; + VSOM_SPI_MISO<= SPI_TX_DATA(7); + SPI_TX_SREG <= SPI_TX_DATA(6 downto 0); + elsif(SPI_FRAME_CNT = 1) then + SPI_FRAME_CNT<= 2; + VSOM_SPI_MISO<= SPI_TX_DATA(15); + SPI_TX_SREG <= SPI_TX_DATA(14 downto 8); + elsif(SPI_FRAME_CNT = 2) then + SPI_FRAME_CNT<= 3; + VSOM_SPI_MISO<= SPI_TX_DATA(23); + SPI_TX_SREG <= SPI_TX_DATA(22 downto 16); + else + -- Increment frame count for each word received. We handle 8bit (1 frame), 16bit (2 frames) or 32bit (4 frames) reception. + SPI_FRAME_CNT<= 4; + VSOM_SPI_MISO<= SPI_TX_DATA(31); + SPI_TX_SREG <= SPI_TX_DATA(30 downto 24); + end if; + + SPI_BIT_CNT <= 7; + end if; + end if; + end process; + + SPI_REGISTER : process(Z80_RESETn, VSOM_SPI_CSn, SPI_FRAME_CNT) + begin + if(Z80_RESETn = '0') then + VIDEO_SRCi <= '0'; + VGA_BLANKn <= '1'; + VBUS_ENi <= '1'; + MONO_VIDEO_SRCi <= '1'; + AUDIO_SRC_Li <= '0'; + AUDIO_SRC_Ri <= '0'; + AUTOREFRESH <= '0'; + SPI_LOOPBACK_TEST <= '0'; + SOM_CMD <= (others => '0'); + SPI_CPU_ADDR <= (others => '0'); + SPI_NEW_DATA <= '0'; + + -- On rising edge of SPI CSn a new data packet from the SOM has arrived and in the shift register SPI_RX_SREG. + -- The variable SPI_FRAME_CNT indicates which byte (frame) in a 32bit word has been transmitted. This allows + -- for 8bit, 16bit and 32bit transmissions. + -- The packet is formatted as follows: + -- + -- < SPI_FRAME_CNT=4 >< SPI_FRAME=3 > < SPI_FRAME_CNT=2 >< SPI_FRAME_CNT=1> + -- < 16bit Z80 Address > < Z80 Data > + -- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + -- < > < Data > + -- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + elsif(VSOM_SPI_CSn'event and VSOM_SPI_CSn = '1') then + + -- Command is always located in the upper byte of frame 1. + SOM_CMD <= SPI_RX_DATA(7 downto 0); + + -- Toggle flag to indicate new data arrived. + SPI_NEW_DATA <= not SPI_NEW_DATA; + + -- Process the command. Some commands require the FSM, others can be serviced immediately. + case SPI_RX_DATA(7 downto 0) is + + -- Z80XACT(0..15): Setup data and address as provided then execute FSM. + when X"10" | X"11" | X"12" | X"13" | X"14" | X"15" | X"16" | X"17" | -- Fetch + X"18" | X"19" | X"1A" | X"1B" | X"1C" | X"1D" | X"1E" | X"1F" | -- Write + X"20" | X"21" | X"22" | X"23" | X"24" | X"25" | X"26" | X"27" | -- Read + X"28" | X"29" | X"2A" | X"2B" | X"2C" | X"2D" | X"2E" | X"2F" | -- WriteIO + X"30" | X"31" | X"32" | X"33" | X"34" | X"35" | X"36" | X"37" | -- ReadIO + X"38" | X"39" | X"3A" | X"3B" | X"3C" | X"3D" | X"3E" | X"3F" | -- + X"40" | X"41" | X"42" | X"43" | X"44" | X"45" | X"46" | X"47" | -- + X"48" | X"49" | X"4A" | X"4B" | X"4C" | X"4D" | X"4E" | X"4F" => + + -- Direct address set. + if(SPI_FRAME_CNT = 4) then + SPI_CPU_ADDR <= SPI_RX_DATA(31 downto 16); + else + -- if(SPI_CPU_ADDR >= X"D010" and SPI_CPU_ADDR < X"D020") then + -- SPI_CPU_ADDR <= std_logic_vector(X"D020" + unsigned(SPI_RX_DATA(2 downto 0))); + -- else + SPI_CPU_ADDR <= std_logic_vector(unsigned(SPI_CPU_ADDR) + unsigned(SPI_RX_DATA(2 downto 0))); + -- end if; + end if; + + if(SPI_FRAME_CNT > 1) then + SPI_CPU_DATA <= SPI_RX_DATA(15 downto 8); + end if; + + -- SETSIGSET1: Set control lines directly. + when X"F0" => + VIDEO_SRCi <= SPI_RX_DATA(8); + MONO_VIDEO_SRCi <= SPI_RX_DATA(9); + AUDIO_SRC_Li <= SPI_RX_DATA(10); + AUDIO_SRC_Ri <= SPI_RX_DATA(11); + VBUS_ENi <= SPI_RX_DATA(12); + VGA_BLANKn <= not SPI_RX_DATA(13); + + -- Enable auto refresh DRAM cycle. + when X"F1" => + AUTOREFRESH <= '1'; + + -- Disable auto refresh DRAM cycle. + when X"F2" => + AUTOREFRESH <= '0'; + + -- SETLOOPBACK: Enable loopback test mode. + when X"FE" => + SPI_LOOPBACK_TEST<= '1'; + + -- No action, called to retrieve status. + when X"00" | X"FF" => + + when others => + end case; + end if; + end process; + + -- Process to detect the Z80 Clock edges. Each edge is used to recreate the Z80 external signals. + -- + Z80CLK: process( CLK_50M, Z80_CLKi, Z80_RESETn ) + begin + if(Z80_RESETn = '0') then + Z80_CLK_RE <= '1'; + Z80_CLK_FE <= '1'; + Z80_CLK_TGL <= '1'; + + elsif(rising_edge(CLK_50M)) then + + -- Default is to clear the signals, only active for 1 clock period. + Z80_CLK_RE <= '0'; + Z80_CLK_FE <= '0'; + Z80_CLK_TGL <= '0'; + + -- Rising Edge. + if(Z80_CLKi = '1' and Z80_CLK_LAST = "00") then + Z80_CLK_RE <= '1'; + + -- Toggle on rising edge is delayed by one clock to allow time for command to be decoded. + elsif(Z80_CLKi = '1' and Z80_CLK_LAST = "01") then + Z80_CLK_TGL <= '1'; + + -- Falling Edge. + elsif(Z80_CLKi = '0' and Z80_CLK_LAST = "11") then + Z80_CLK_FE <= '1'; + Z80_CLK_TGL <= '1'; + end if; + Z80_CLK_LAST <= Z80_CLK_LAST(0) & Z80_CLKi; + end if; + end process; + + -- SOM Finite State Machine. + -- + -- A command processor, based on an FSM concept, to process requested commands, ie. Z80 Write, Z80 Read etc. + -- The external signal SOM_CMD_EN, when set, indicates a new command available in SOM_CMD. + -- + SOMFSM: process( CLK_50M, Z80_CLKi, Z80_RESETn ) + begin + if(Z80_RESETn = '0') then + Z80_IORQni <= '1'; + Z80_MREQni <= '1'; + Z80_RDni <= '1'; + Z80_WRni <= '1'; + Z80_HALTni <= '1'; + Z80_M1ni <= '1'; + Z80_RFSHni <= '1'; + Z80_BUSRQ_ACKni <= '1'; + FSM_CHECK_WAIT <= '0'; + FSM_WAIT_ACTIVE <= '0'; + FSM_STATUS <= '0'; + FSM_STATE <= IdleCycle; + RFSH_STATUS <= '0'; + CPU_DATA_EN <= '0'; + CPU_DATA_IN <= (others => '0'); + REFRESH_ADDR <= (others => '0'); + AUTOREFRESH_CNT <= 7; + IPAR <= (others => '0'); + NEW_SPI_CMD <= '0'; + VCPU_CS_EDGE <= "11"; + SPI_PROCESSING <= '0'; + + elsif(rising_edge(CLK_50M)) then + + -- Bus request mechanism. If an externel Bus Request comes in and the FSM is idle, run the Bus Request command which + -- suspends processing and tri-states the bus. + if(Z80_BUSRQn = '0' and Z80_BUSRQ_ACKni = '1' and FSM_STATE = IdleCycle) then + FSM_STATE <= BusReqCycle; + end if; + if(Z80_BUSRQn = '1' and Z80_BUSRQ_ACKni = '0' and FSM_STATE = IdleCycle) then + Z80_BUSRQ_ACKni <= '1'; + end if; + + -- New command, set flag as the signal is only 1 clock wide. + if(SPI_LOOPBACK_TEST = '0' and VSOM_SPI_CSn = '1' and VCPU_CS_EDGE = "01") then + NEW_SPI_CMD <= '1'; + end if; + + -- Whenever we return to Idle or just prior to Refresh from a Fetch cycle set all control signals to default. + if(FSM_STATE = IdleCycle or FSM_STATE = RefreshCycle) then + CPU_DATA_EN <= '0'; + Z80_MREQni <= '1'; + Z80_IORQni <= '1'; + Z80_RDni <= '1'; + Z80_WRni <= '1'; + Z80_M1ni <= '1'; + FSM_STATUS <= '0'; + Z80_RFSHni <= '1'; + + -- Auto DRAM refresh cycles. When enabled, every 7 host clock cycles, a 2 cycle refresh period commences. + -- This will be overriden if the SPI receives a new command. + -- + if AUTOREFRESH = '1' and FSM_STATE = IdleCycle then + AUTOREFRESH_CNT <= AUTOREFRESH_CNT - 1; + if(AUTOREFRESH_CNT = 0) then + FSM_STATE <= RefreshCycle_3; + end if; + end if; + end if; + + -- If new command has been given and the FSM enters idle state, load up new command for processing. + if(NEW_SPI_CMD = '1' and FSM_STATE = IdleCycle and Z80_CLK_RE = '1') then + NEW_SPI_CMD <= '0'; + + -- Store new address and data for this command. + CPU_ADDR <= SPI_CPU_ADDR; + if(SPI_CPU_DATA /= CPU_DATA_OUT) then + CPU_DATA_OUT <= SPI_CPU_DATA; + end if; + + -- Process the SOM command. The SPI_REGISTER executes non FSM commands and stores FSM + -- data prior to this execution block, which fires 1 cycle later on the same control clock. + -- If the command is not for the FSM then the READY mechanism is held for one + -- further cycle before going inactive. + case SOM_CMD is + when X"10" | X"11" | X"12" | X"13" | X"14" | X"15" | X"16" | X"17" => + -- Initiate a Fetch Cycle. + FSM_STATE <= FetchCycle; + + when X"18" | X"19" | X"1A" | X"1B" | X"1C" | X"1D" | X"1E" | X"1F" => + + -- Set the Z80 data bus value and initiate a Write Cycle. + FSM_STATE <= WriteCycle; + + when X"20" | X"21" | X"22" | X"23" | X"24" | X"25" | X"26" | X"27" => + -- Initiate a Read Cycle. + FSM_STATE <= ReadCycle; + + when X"28" | X"29" | X"2A" | X"2B" | X"2C" | X"2D" | X"2E" | X"2F" => + -- Set the Z80 data bus value and initiate an IO Write Cycle. + -- The SOM should set 15:8 to the B register value. + FSM_STATE <= WriteIOCycle; + + when X"30" | X"31" | X"32" | X"33" | X"34" | X"35" | X"36" | X"37" => + -- Initiate a Read IO Cycle. + FSM_STATE <= ReadIOCycle; + + when X"50" => + -- Register a Halt state. + FSM_STATE <= HaltCycle; + + when X"51" => + -- Initiate a refresh cycle. + FSM_STATE <= RefreshCycle_3; + + when X"E0" => + -- Initiate a Halt Cycle. + FSM_STATE <= HaltCycle; + + -- Set the Refresh Address register. + when X"E1" => + REFRESH_ADDR <= CPU_DATA_OUT; + + -- Set the Interrupt Page Address Register. + when X"E2" => + IPAR <= CPU_DATA_OUT; + + when others => + end case; + + -- Toggle the processing flag to negate the new data flag. Used to indicate device is busy. + if(SPI_NEW_DATA /= SPI_PROCESSING) then + SPI_PROCESSING <= not SPI_PROCESSING; + end if; + + -- FSM Status bit. When processing a command it is set, cleared when idle. Used by SOM to determine command completion. + FSM_STATUS <= '1'; + end if; + + -- Refresh status bit. Indicates a Refresh cycle is under way. + if FSM_STATE = RefreshCycle or FSM_STATE = RefreshCycle_11 or FSM_STATE = RefreshCycle_20 or FSM_STATE = RefreshCycle_21 or FSM_STATE = RefreshCycle_3 then + RFSH_STATUS <= '1'; + else + RFSH_STATUS <= '0'; + end if; + + -- If we are in a WAIT sampling 1/2 cycle and wait goes active, set the state so we repeat the full clock cycle by winding back 2 places. + if(FSM_CHECK_WAIT = '1' and Z80_WAITn = '0' and Z80_CLK_TGL = '0') then + FSM_WAIT_ACTIVE <= '1'; + end if; + + -- On each Z80 edge we advance the FSM to recreate the Z80 external signal transactions. + if(Z80_CLK_TGL = '1') then + + -- The FSM advances to the next stage on each Z80 edge unless in Idle state. + if(FSM_STATE /= IdleCycle) then + FSM_STATE <= SOMFSMState'val(SOMFSMState'POS(FSM_STATE)+1); + end if; + + -- Half cycle expired so we dont check the Z80 wait again. + FSM_CHECK_WAIT <= '0'; + FSM_WAIT_ACTIVE <= '0'; + + -- FSM to implement all the required Z80 cycles. + -- + case FSM_STATE is + + when IdleCycle => + CPU_LAST_T_STATE <= '1'; + -- FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 Fetch Cycle. + ----------------------------- + when FetchCycle => + Z80_M1ni <= '0'; + + when FetchCycle_11 => + Z80_M1ni <= '0'; + Z80_MREQni <= '0'; + Z80_RDni <= '0'; + + when FetchCycle_20 => + FSM_CHECK_WAIT <= '1'; + + when FetchCycle_21 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= FetchCycle_20; + end if; + + when FetchCycle_30 => + -- To meet the timing diagrams, just after Rising edge on T3 clear signals. Data wont be available until + -- a short period before the falling edge of T3 (could be an MZ-80A design restriction or the Z80 timing diagrams are a bit out). + FSM_STATE <= RefreshCycle; + + ----------------------------- + -- Z80 Refresh Cycle. + ----------------------------- + when RefreshCycle => + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + Z80_RFSHni <= '0'; + + when RefreshCycle_11 => + -- Falling edge of T3 activates the MREQ line. + Z80_MREQni <= '0'; + + when RefreshCycle_20 => + + when RefreshCycle_21 => + Z80_MREQni <= '1'; + REFRESH_ADDR(6 downto 0) <= REFRESH_ADDR(6 downto 0) + 1; + FSM_STATE <= IdleCycle; + + when RefreshCycle_3 => + Z80_RFSHni <= '0'; + FSM_STATE <= RefreshCycle_11; + + ----------------------------- + -- Z80 Write Cycle. + ----------------------------- + when WriteCycle => + + when WriteCycle_11 => + Z80_MREQni <= '0'; + CPU_DATA_EN <= '1'; + + when WriteCycle_20 => + FSM_CHECK_WAIT <= '1'; + + when WriteCycle_21 => + Z80_WRni <= '0'; + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= WriteCycle_20; + end if; + + when WriteCycle_30 => + + when WriteCycle_31 => + FSM_STATUS <= '0'; + Z80_MREQni <= '1'; + Z80_WRni <= '1'; + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 Read Cycle. + ----------------------------- + when ReadCycle => + + when ReadCycle_11 => + Z80_MREQni <= '0'; + Z80_RDni <= '0'; + + when ReadCycle_20 => + FSM_CHECK_WAIT <= '1'; + + when ReadCycle_21 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= ReadCycle_20; + end if; + + when ReadCycle_30 => + + when ReadCycle_31 => + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + FSM_STATE <= IdleCycle; + + + ----------------------------- + -- Z80 IO Write Cycle. + ----------------------------- + when WriteIOCycle => + + when WriteIOCycle_11 => + CPU_DATA_EN <= '1'; + + when WriteIOCycle_20 => + Z80_IORQni <= '0'; + Z80_WRni <= '0'; + + when WriteIOCycle_21 => + + when WriteIOCycle_30 => + FSM_CHECK_WAIT <= '1'; + + when WriteIOCycle_31 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= WriteIOCycle_20; + end if; + + when WriteIOCycle_40 => + + when WriteIOCycle_41 => + FSM_STATUS <= '0'; + Z80_IORQni <= '1'; + Z80_WRni <= '1'; + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 IO Read Cycle. + ----------------------------- + when ReadIOCycle => + + when ReadIOCycle_11 => + + when ReadIOCycle_20 => + Z80_IORQni <= '0'; + Z80_RDni <= '0'; + + when ReadIOCycle_21 => + + when ReadIOCycle_30 => + FSM_CHECK_WAIT <= '1'; + + when ReadIOCycle_31 => + if(Z80_WAITn = '0' or FSM_WAIT_ACTIVE = '1') then + FSM_STATE <= ReadIOCycle_20; + end if; + + when ReadIOCycle_40 => + + when ReadIOCycle_41 => + -- Latch data from mainboard. + CPU_DATA_IN <= Z80_DATA; + FSM_STATUS <= '0'; + + -- IORQ/RD are deactivated at idle giving 1 clock to latch the data in. + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Halt Request. + ----------------------------- + when HaltCycle => + Z80_HALTni <= '0'; + FSM_STATUS <= '0'; + FSM_STATE <= IdleCycle; + + ----------------------------- + -- Z80 Bus Request. + ----------------------------- + when BusReqCycle => + Z80_BUSRQ_ACKni <= '0'; + FSM_STATE <= IdleCycle; + + when others => + FSM_STATE <= IdleCycle; + end case; + end if; + + VCPU_CS_EDGE <= VCPU_CS_EDGE(0) & VSOM_SPI_CSn; + end if; + end process; + + Z80_CLKi <= not Z80_CLK; + + -- CPU Interface tri-state control based on acknowledged bus request. + Z80_ADDR <= IPAR & REFRESH_ADDR when Z80_RFSHni = '0' + else + CPU_ADDR when Z80_BUSRQ_ACKni = '1' + else + (others => 'Z'); + Z80_DATA <= CPU_DATA_OUT when Z80_BUSRQ_ACKni = '1' and CPU_DATA_EN = '1' + else + (others => 'Z'); + -- Z80_DATAi <= Z80_DATA when Z80_RDn = '0' + -- else (others => '1'); + Z80_RDn <= Z80_RDni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_WRn <= Z80_WRni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_M1n <= Z80_M1ni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_RFSHn <= Z80_RFSHni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_MREQn <= Z80_MREQni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_IORQn <= Z80_IORQni when Z80_BUSRQ_ACKni = '1' + else 'Z'; + Z80_BUSAKn <= Z80_BUSRQ_ACKni; + + -- CPU Interface single state output. + Z80_HALTn <= Z80_HALTni; + + -- CPU Interface single state input. + Z80_NMIni <= Z80_NMIn; + Z80_INTni <= Z80_INTn; + Z80_BUSRQni <= Z80_BUSRQn; + + -- SOM Reset. + PM_RESET <= PM_RESETi; + + -- SOM to CPLD Interface. + VSOM_DATA_OUT <= CPU_DATA_IN when VSOM_HBYTE = '1' + else + FSM_STATUS & RFSH_STATUS & Z80_BUSRQ_ACKni & Z80_BUSRQni & Z80_INTni & Z80_NMIni & Z80_WAITn & Z80_RESETn when VSOM_HBYTE = '0' + else + (others => '0'); + + -- Loopback test, echo what was received. + SPI_TX_DATA <= SPI_RX_DATA when SPI_LOOPBACK_TEST = '1' + else + --CPU_ADDR & SOM_CMD & FSM_STATUS & RFSH_STATUS & std_logic_vector(to_unsigned(SOMFSMState'POS(FSM_STATE), 6)); + CPU_ADDR & CPU_DATA_IN & FSM_STATUS & RFSH_STATUS & Z80_BUSRQ_ACKni & Z80_BUSRQni & Z80_INTni & Z80_NMIni & Z80_WAITn & Z80_RESETn; + + -- Signal mirrors. + VSOM_READY <= '0' when FSM_STATUS='1' or SPI_NEW_DATA /= SPI_PROCESSING + else '1'; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE <= '1' when CPU_LAST_T_STATE = '1' -- Last T-State in current cycle. + else '0'; + VSOM_BUSRQ <= not Z80_BUSRQn; -- Host device requesting Z80 Bus. + VSOM_BUSACK <= not Z80_BUSRQ_ACKni; -- Host device granted Z80 Bus + VSOM_INT <= not Z80_INTn; -- Z80 INT signal + VSOM_NMI <= not Z80_NMIn; -- Z80 NMI signal + VSOM_WAIT <= not Z80_WAITn; -- Z80 WAIT signal + VSOM_RESET <= not VSOM_RESETni; -- Z80 RESET signal + VSOM_RSV <= (others => '0'); -- Reserved pins. + + -- Video/Audio control signals. + VIDEO_SRC <= VIDEO_SRCi; + MONO_VIDEO_SRC <= MONO_VIDEO_SRCi; + AUDIO_SRC_L <= AUDIO_SRC_Li; + AUDIO_SRC_R <= AUDIO_SRC_Ri; + + -- USB Power Supply enable. + VBUS_EN <= VBUS_ENi; + + -- Monochrome output is based on the incoming VGA to give the best chrominance levels. + MONO_R <= VGA_R; + MONO_G <= VGA_G; + MONO_B <= VGA_B; + + -- Blanking is active when all colour signals are at 0. The DAC converts values in range 4v .. 5v to adjust chrominance + -- but true off can obly be achieved by bringing the signal value to 0v which is achieved by a Mux activated with this blanking signal. + MONO_BLANKn <= '0' when VGA_R = "000" and VGA_G = "000" and VGA_B = "000" + else '1'; + + -- Generate composite sync. + VGA_CSYNCn <= VGA_HSYNCn xor not VGA_VSYNCn; + MONO_CSYNCn <= not VGA_HSYNCn xor not VGA_VSYNCn; + + -- DAC clocks. + --VGA_PXL_CLK <= CLK_50M; + MONO_PXL_CLK <= VGA_PXL_CLK; + +end architecture; diff --git a/CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd b/CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd new file mode 100644 index 000000000..5598e2619 --- /dev/null +++ b/CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd @@ -0,0 +1,222 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX_Toplevel.vhd +-- Version: MZ-80A +-- Created: Nov 2022 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD Top Level module. +-- +-- This module contains the basic pin definition of the CPLD<->logic needed in the +-- project which targets the MZ-80A host. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: Nov 2022 - Snapshot taken from the MZ-2000 version of the tzpuFusionX source. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.tzpuFusionX_pkg.all; +library altera; +use altera.altera_syn_attributes.all; + +entity tzpuFusionX_MZ80A is + port ( + -- Z80 Address Bus + Z80_ADDR : inout std_logic_vector(15 downto 0); + + -- Z80 Data Bus + Z80_DATA : inout std_logic_vector(7 downto 0); + + -- Z80 Control signals. + Z80_BUSRQn : in std_logic; + Z80_BUSAKn : out std_logic; + Z80_INTn : in std_logic; + Z80_IORQn : inout std_logic; + Z80_MREQn : inout std_logic; + Z80_NMIn : in std_logic; + Z80_RDn : inout std_logic; + Z80_WRn : inout std_logic; + Z80_RESETn : in std_logic; -- Host CPU Reset signal, also CPLD reset. + Z80_HALTn : out std_logic; + Z80_WAITn : in std_logic; + Z80_M1n : inout std_logic; + Z80_RFSHn : inout std_logic; + + -- SOM SPI + VSOM_SPI_CSn : in std_logic; -- SPI Slave Select + VSOM_SPI_CLK : in std_logic; -- SPI Clock + VSOM_SPI_MOSI : in std_logic; -- SPI Master Output Slave Input + VSOM_SPI_MISO : out std_logic; -- SPI Master Input Slave Output + + -- SOM Parallel Bus. + VSOM_DATA_OUT : out std_logic_vector(7 downto 0); -- Address/Data bus for CPLD control registers. + VSOM_HBYTE : in std_logic; -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY : out std_logic; -- FSM Ready (1), Busy (0) + VSOM_LTSTATE : out std_logic; -- Last T-State in current cycle, 1 = active. + VSOM_BUSRQ : out std_logic; -- Host device requesting Z80 Bus. + VSOM_BUSACK : out std_logic; -- Host device granted Z80 Bus + VSOM_INT : out std_logic; -- Z80 INT signal + VSOM_NMI : out std_logic; -- Z80 NMI signal + VSOM_WAIT : out std_logic; -- Z80 WAIT signal + VSOM_RESET : out std_logic; -- Z80 RESET signal + VSOM_RSV : out std_logic_vector(1 downto 1); -- Reserved pins. + + -- SOM Control Signals + PM_RESET : out std_logic; -- Reset SOM + + -- VGA_Palette Control + VGA_R : in std_logic_vector(9 downto 7); -- Signals used for detecting blank or no video output. + VGA_G : in std_logic_vector(9 downto 7); + VGA_B : in std_logic_vector(9 downto 8); + + -- VGA Control Signals + VGA_PXL_CLK : in std_logic; -- VGA Pixel clock for DAC conversion. + VGA_DISPEN : in std_logic; -- Displayed Enabled (SOM video output). + VGA_VSYNCn : in std_logic; -- SOM VSync. + VGA_HSYNCn : in std_logic; -- SOM HSync. + VGA_COLR : out std_logic; -- COLR colour carrier frequency. + VGA_CSYNCn : out std_logic; -- VGA Composite Sync. + VGA_BLANKn : out std_logic; -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK : out std_logic; -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn : out std_logic; -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn : out std_logic; -- Mono CRT composite sync. + MONO_RSV : out std_logic; + + -- CRT Lower Chrominance Control + MONO_R : out std_logic_vector(2 downto 0); -- Signals to fine tune Red level of monochrome chrominance. + MONO_G : out std_logic_vector(2 downto 0); -- Signals to fine tune Green level of monochrome chrominance. + MONO_B : out std_logic_vector(2 downto 1); -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC : out std_logic; -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC : out std_logic; -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L : out std_logic; -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R : out std_logic; -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals + MB_RESETn : in std_logic; -- Motherboard Reset pressed. + MB_IPLn : in std_logic; -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN : out std_logic; -- USB Enable Power Output + + -- Clocks. + Z80_CLK : in std_logic; -- Host CPU Clock + CLK_50M : in std_logic -- 50MHz oscillator. + ); +END entity; + +architecture rtl of tzpuFusionX_MZ80A is + +begin + + cpldl512Toplevel : entity work.cpld512 + generic map ( + SPI_CLK_POLARITY => '0' + ) + port map + ( + -- Z80 Address Bus + Z80_ADDR => Z80_ADDR, + + -- Z80 Data Bus + Z80_DATA => Z80_DATA, + + -- Z80 Control signals. + Z80_BUSRQn => Z80_BUSRQn, + Z80_BUSAKn => Z80_BUSAKn, + Z80_INTn => Z80_INTn, + Z80_IORQn => Z80_IORQn, + Z80_MREQn => Z80_MREQn, + Z80_NMIn => Z80_NMIn, + Z80_RDn => Z80_RDn, + Z80_WRn => Z80_WRn, + Z80_RESETn => Z80_RESETn, + Z80_HALTn => Z80_HALTn, + Z80_WAITn => Z80_WAITn, + Z80_M1n => Z80_M1n, + Z80_RFSHn => Z80_RFSHn, + + -- SOM SPI + VSOM_SPI_CSn => VSOM_SPI_CSn, -- SPI Slave Select + VSOM_SPI_CLK => VSOM_SPI_CLK, -- SPI Clock + VSOM_SPI_MOSI => VSOM_SPI_MOSI, -- SPI Master Output Slave Input + VSOM_SPI_MISO => VSOM_SPI_MISO, -- SPI Master Input Slave Output + + -- SOM Parallel Bus. + VSOM_DATA_OUT => VSOM_DATA_OUT, -- Address/Data bus for CPLD control registers. + VSOM_HBYTE => VSOM_HBYTE, -- Parallel Bus High (1)/Low (0) byte. + VSOM_READY => VSOM_READY, -- FSM Ready (1), Busy (0) + VSOM_LTSTATE => VSOM_LTSTATE, -- Last T-State in current cycle. + VSOM_BUSRQ => VSOM_BUSRQ, -- Host device requesting Z80 Bus. + VSOM_BUSACK => VSOM_BUSACK, -- Host device granted Z80 Bus + VSOM_INT => VSOM_INT, -- Z80 INT signal + VSOM_NMI => VSOM_NMI, -- Z80 NMI signal + VSOM_WAIT => VSOM_WAIT, -- Z80 WAIT signal + VSOM_RESET => VSOM_RESET, -- Z80 RESET signal + VSOM_RSV => VSOM_RSV, -- Reserved pins. + + -- SOM Control Signals + PM_RESET => PM_RESET, -- Reset SOM + + -- VGA_Palette Control + VGA_R => VGA_R, -- Signals used for detecting blank or no video output. + VGA_G => VGA_G, + VGA_B => VGA_B, + + -- VGA Control Signals + VGA_PXL_CLK => VGA_PXL_CLK, -- VGA Pixel clock for DAC conversion. + VGA_DISPEN => VGA_DISPEN, -- Displayed Enabled (SOM video output). + VGA_VSYNCn => VGA_VSYNCn, -- SOM VSync. + VGA_HSYNCn => VGA_HSYNCn, -- SOM HSync. + VGA_COLR => VGA_COLR, -- COLR colour carrier frequency. + VGA_CSYNCn => VGA_CSYNCn, -- VGA Composite Sync. + VGA_BLANKn => VGA_BLANKn, -- VGA Blank detected. + + -- CRT Control Signals + MONO_PXL_CLK => MONO_PXL_CLK, -- Mono CRT pixel clock for DAC conversion. + MONO_BLANKn => MONO_BLANKn, -- Mono CRT Blank (no active pixel) detection. + MONO_CSYNCn => MONO_CSYNCn, -- Mono CRT composite sync. + MONO_RSV => MONO_RSV, + + -- CRT Lower Chrominance Control + MONO_R => MONO_R, -- Signals to fine tune Red level of monochrome chrominance. + MONO_G => MONO_G, -- Signals to fine tune Green level of monochrome chrominance. + MONO_B => MONO_B, -- Signals to fine tune Blue level of monochrome chrominance. + + -- MUX Control Signals + VIDEO_SRC => VIDEO_SRC, -- Select video source, Mainboard or SOM. + MONO_VIDEO_SRC => MONO_VIDEO_SRC, -- Select crt video source, Mainboard or SOM. + AUDIO_SRC_L => AUDIO_SRC_L, -- Select Audio Source Left Channel, Mainboard or SOM. + AUDIO_SRC_R => AUDIO_SRC_R, -- Select Audio Source Right Channel, Mainboard or SOM. + + -- Mainboard Reset Signals=> MONO_R, + MB_RESETn => MB_RESETn, -- Motherboard Reset pressed. + MB_IPLn => MB_IPLn, -- Motherboard IPL pressed. + + -- USB Power Control + VBUS_EN => VBUS_EN, -- USB Enable Power Output + + -- Clocks. + Z80_CLK => Z80_CLK, -- Host CPU Clock + CLK_50M => CLK_50M -- 50MHz oscillator. + ); + +end architecture; diff --git a/CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd b/CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd new file mode 100644 index 000000000..e0b7c7f78 --- /dev/null +++ b/CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd @@ -0,0 +1,221 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: tzpuFusionX_pkg.vhd +-- Created: Nov 2022 +-- Author(s): Philip Smart +-- Description: tzpuFusionX CPLD configuration file. +-- +-- This module contains parameters for the CPLD in the tzpuFusionX project +-- which targets the MZ-80A host. +-- +-- Credits: +-- Copyright: (c) 2018-22 Philip Smart +-- +-- History: Nov 2022 - Snapshot taken from the MZ-2000 version of the tzpuFusionX source. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +package tzpuFusionX_pkg is + + ------------------------------------------------------------ + -- Constants + ------------------------------------------------------------ + + -- Potential logic state constants. + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + constant HIZ : std_logic := 'Z'; + + -- CPLD Command instructions. + constant CPLD_CMD_RESET_HOST : integer := 1; + constant CPLD_CMD_HOLD_HOST_BUS : integer := 2; + constant CPLD_CMD_RELEASE_HOST_BUS: integer := 3; + + -- Target hardware modes. + constant MODE_MZ80K : integer := 0; + constant MODE_MZ80C : integer := 1; + constant MODE_MZ1200 : integer := 2; + constant MODE_MZ80A : integer := 3; + constant MODE_MZ700 : integer := 4; + constant MODE_MZ800 : integer := 5; + constant MODE_MZ80B : integer := 6; + constant MODE_MZ2000 : integer := 7; + + -- Memory management modes. + constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063). + constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted. + constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected. + constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1. + constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2. + constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3. + constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected. + -- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_COMPAT : integer := 08; -- Compatibility monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF. + constant TZMM_HOSTACCESS : integer := 09; -- Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory. + constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard. + constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ800 : integer := 15; -- MZ800 Mode - Running on MZ800 hardware, configuration set according to MZ700/MZ800 mode. + constant TZMM_MZ2000 : integer := 16; -- MZ2000 Mode - Running on MZ2000 hardware, configuration set according to runtime configuration registers. + constant TZMM_FPGA : integer := 21; -- Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked. + constant TZMM_TZPUM : integer := 22; -- Everything in on mainboard, no access to tranZPUter memory. + constant TZMM_TZPU : integer := 23; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected. + constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected. + constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected. + constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected. + constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected. + constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected. + constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected. + + + + ------------------------------------------------------------ + -- Configurable parameters. + ------------------------------------------------------------ + -- Target hardware. + constant CPLD_HOST_HW : integer := MODE_MZ700; + + -- Target video hardware. + constant CPLD_HAS_FPGA_VIDEO : std_logic := '1'; + + -- Version of hdl. + constant CPLD_VERSION : integer := 2; + + -- Clock source for the secondary clock. If a K64F is installed then enable it otherwise use the onboard oscillator. + -- + constant USE_K64F_CTL_CLOCK : integer := 1; + + ------------------------------------------------------------ + -- Function prototypes + ------------------------------------------------------------ + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer; + + -- Function to reverse the order of the bits in a standard logic vector. + -- ie. 1010 becomes 0101 + function reverse_vector(slv:std_logic_vector) return std_logic_vector; + + -- Function to convert an integer (0 or 1) into std_logic. + -- + function to_std_logic(i : in integer) return std_logic; + + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural; + + ------------------------------------------------------------ + -- Records + ------------------------------------------------------------ + + ------------------------------------------------------------ + -- Components + ------------------------------------------------------------ + +end tzpuFusionX_pkg; + +------------------------------------------------------------ +-- Function definitions. +------------------------------------------------------------ +package body tzpuFusionX_pkg is + + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer is + begin + if a > b then + return a; + else + return b; + end if; + return a; + end function IntMax; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural is + variable tmp : positive := 1; + variable log : natural := 0; + begin + if arg = 1 then + return 0; + end if; + + while arg > tmp loop + tmp := tmp * 2; + log := log + 1; + end loop; + return log; + end function; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer is + variable ticks : real; + variable fracTicks : real; + begin + ticks := (Real(period) * Real(clock)) / 1000000000.0; + fracTicks := ticks - CEIL(ticks); + if fracTicks > 0.0001 then + return Integer(CEIL(ticks + 1.0)); + else + return Integer(CEIL(ticks)); + end if; + end function; + + function reverse_vector(slv:std_logic_vector) return std_logic_vector is + variable target : std_logic_vector(slv'high downto slv'low); + begin + for idx in slv'high downto slv'low loop + target(idx) := slv(slv'low + (slv'high-idx)); + end loop; + return target; + end reverse_vector; + + function to_std_logic(i : in integer) return std_logic is + begin + if i = 0 then + return '0'; + end if; + return '1'; + end function; + + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural is + begin + if s = '1' then + return 1; + else + return 0; + end if; + end function; +end package body; diff --git a/README.md b/README.md new file mode 100644 index 000000000..b3464d80a --- /dev/null +++ b/README.md @@ -0,0 +1,147 @@ + + +## Foreword + +
+The tranZPUterFusionX is a spinoff concept from the tranZPUter series. It shares the same purpose, to replace the Z80 in a Sharp or similar system and provide it with features such as faster CPU, more memory, better graphics, quicker application loading etc. +
+ +It shares similarities with the tranZPUterFusion but instead of realising it in hardware via an FPGA it realises +it in software as an application. This is made possible by a SOM (System On a Module), not much bigger than an FPGA device yet provides an abundance of features, ie. dual-core 1.2GHz Cortex-A7 ARM CPU, 128MB RAM, Wifi, HD Video, SD Card, USB port and runs the Linux operating system. +
+ +Using the same base design as the tranZPUterFusion it incorporates a CPLD to interface the Z80 host to the SOM and provide cycle accurate Z80 timing. The SOM interfaces to the CPLD via a 16bit bus to query signal status and initiate Z80 transactions. +
+ +A Linux Kernel driver instantiates a Z80 emulation which realises a Z80 CPU in software and in turn can command and control the host system. The kernel driver along with a controlling application +can provide a wealth of features to the host through this mechanism. The SOM is also connected to an SD Drive and USB 2.0 port so there is no limit to features which can be proivded. +
+ +Like the tranZPUterFusion, the tranZPUterFusionX can provide enhanced video and sound to the host. The SOM incorporates dual DAC audio and a 2D GPU with configurable resolutions. +
+ +To most retro users, the above wont have meaning or interest as it is primarily for software research and development. What the board can offer the end user is: +
    +
  • Original host specifications
    - there might be slight differences in the Z80 functionality as it is implemented in software but the Z80 hardware timing is accurate.
    • +
  • Accelerator
    - the Z80 can run at much higher speeds due to the abundance of memory and 1.2GHz dual-core processor, which would typically see performance equivalent to a 500MHz Z80.
    • +
  • Emulation
    - it is possible to emulate all the Sharp MZ series machines in software, experiencing it through the host system keyboard, monitor and I/O.
    • +
  • Graphics
    - all original Sharp MZ graphics modes, regardless of host, are available through GPU configuration and these can be selected and programmed via Basic etc.
    • +
  • Sound
    - the host will have access to the dual DAC channels, which can emulate the SN76489 or basic bit/timer sound of the Sharp series.
    • +
  • Processors
    - there are many software CPU implementations which can be ported to run on this platform, for example the BBC PiCoPro which uses the same Linux and ARM CPU platform. This in turn allows the potential for other machines, such as the BBC to run on this Sharp host.
    • +
  • Linux
    - using the host keyboard, speaker, monitor etc, a full blooded version of Linux can be utilised at the host console.
    • +
+ + +The tranZPUterFusionX is under development and this source and document repository will be updated as the project progresses. + +
+ +-------------------------------------------------------------------------------------------------------- + +## Daughter Boards + +
+The tranZPUter series was initially developed in the Sharp MZ-80A and was primarily a Z80 replacement. As the concept evolved and the tranZPUter SW-700 was developed for the MZ-700 it became more of an integral component of the machine, offering original and upgraded Video and Audio capabilites by intercepting and routing existing signals. +
+ +After significant developments on the tranZPUter SW-700 it became desirable to port it back to the MZ-80A and MZ-2000 but these machines had different CPU orientation and signal requirements, ie. driving internal and external monitor. This requirement led to the concept of daughter boards, where a specific board would be designed and developed for +the target host and would plug into the tranZPUter SW-700 card. Ideally I wanted to port the SW-700 to an MZ-800/MZ-1500 and X1 but the size of the card and orientation of the Z80 was a limitation. +
+ +During the design of the tranZPUterFusionX one of the main requirements was to make the board small and the Z80 orientation changeable and compatible with the tranZPUterFusion so that it could fit many machines and be interchangeable. As the SW-700 also interfaced to the Video and Audio of the machines and each was quite different, it became apparent that the tranZPUterFusionX needed +to include a concept to allow different video/audio interfaces according to the targetted host. This concept was realised via daughter boards. Two connectors would link the tranZPUterFusionX to a daughter board which would be specifically designed for the intended host. +
+ +The daughter boards would be responsible for switching and mixing video/audio signals and to drive internal monitors and provide the correct input and output connectors for ease of installation. +
+ +Currently three daughter boards have been developed, for the MZ-700, MZ-80A and MZ-2000 and more will follow as the design progresses. +
+ + +###### MZ-700 Daughter Board + +
+The MZ-700 daughter board is designed to be inserted into mainboard modulator output and the modulator in turn connected to the daughter board. +
+ +The MZ-700 requires switching of the original mainboard video and tranZPUterFusionX FPGA video to the existing output connectors. This is accomplished with analogue MUX switches. +
+ +The sound of the MZ-700 is sent directly to a speaker and in order to inject tranZPUterFusionX sound, the mainboard speaker output is routed to the daughter board, level converted and switched. The FPGA offers stereo sound so this is selectively switched/mixed with the original sound and fed to a Class D amplifier which then drives +the internal speaker. +
+ +This setup allows for emulated machines, whilst running in the host on the FPGA such as the MZ-800/MZ-1500, to output their sound to the internal speaker. An audio output connector is provided for connection to stereo speakers if desired. +
+ + +
+
+ +
+
+ +
+
+ +###### MZ-2000 Daughter Board + +
+The MZ-2000 daughter board is designed to be inserted simultaneously into the mainboard monitor and IPL connectors. The daughter board switches video source to the internal monitor, either the original mainboard video or FPGA video. The video source for the internal monitor is independent to the external moonitor source so different images can +be displayed on the internal monitor and external source at the same time. +
+ +The external video output can be fed from the original mainboard video or the FPGA video, the external video uses its own framebuffer so can be different to the internal monitor. +
+ +The audio is intercepted and switched/mixed prior to being sent to the internal audio amplifier. +
+ +The daughter board presents all the original connectors so it is easily installed. +
+ +
+ +
+
+ +
+
+ +
+
+ +###### MZ-80A Daughter Board + +
+The MZ-80A daughter board is designed to be inserted into the original Hirose monitor connector with the tape recorder plug being inserted through the gap in the daughter board. The system RESET is routed through the daughter board via 2pin connectors. +
+ +The daughter board switches video source to the internal monitor, either the original mainboard video or FPGA video. The video source for the internal monitor is independent to the external moonitor source so different images can +be displayed on the internal monitor and external source at the same time. +
+ +The external video output can be fed from the original mainboard video or the FPGA video, the external video uses its own framebuffer so can be different to the internal monitor. +
+ +The audio is intercepted and switched/mixed prior to being sent to the internal audio amplifier. +
+ +The daughter board presents all the original connectors so it is easily installed. +
+ +
+
+ +
+
+ +
+
+
+ + +
+ +-------------------------------------------------------------------------------------------------------- diff --git a/datasheets/ADV7123_Datasheet.pdf b/datasheets/ADV7123_Datasheet.pdf new file mode 100644 index 000000000..988e9839e Binary files /dev/null and b/datasheets/ADV7123_Datasheet.pdf differ diff --git a/datasheets/CH340E_Datasheet.pdf b/datasheets/CH340E_Datasheet.pdf new file mode 100644 index 000000000..6771654b1 Binary files /dev/null and b/datasheets/CH340E_Datasheet.pdf differ diff --git a/datasheets/EP4CE75F484I7_Datasheet.pdf b/datasheets/EP4CE75F484I7_Datasheet.pdf new file mode 100644 index 000000000..43fb6f580 Binary files /dev/null and b/datasheets/EP4CE75F484I7_Datasheet.pdf differ diff --git a/datasheets/EPCS7128_Datasheet.pdf b/datasheets/EPCS7128_Datasheet.pdf new file mode 100644 index 000000000..d6c14e02a Binary files /dev/null and b/datasheets/EPCS7128_Datasheet.pdf differ diff --git a/datasheets/EPM7512AEQFP144_Datasheet.pdf b/datasheets/EPM7512AEQFP144_Datasheet.pdf new file mode 100644 index 000000000..00b3a48d0 --- /dev/null +++ b/datasheets/EPM7512AEQFP144_Datasheet.pdf @@ -0,0 +1,28543 @@ +%PDF-1.3 +%âãÏÓ +1 0 obj +<> +endobj +2 0 obj +<>>> +endobj +3 0 obj +<> +stream + + + + + + 1998-10-08T17:00:10Z + 2003-09-17T09:51:34-07:00 + Acrobat Distiller 5.0.5 (Windows) + Altera Corporation + FrameMaker 7.0 + MAX 7000A Programmable Logic Device Data Sheet + MAX, MAX 7000, MAX 7000A, extended temperature + This data sheet provides information on MAX 7000A programmable logic devices. + + + + 1998-10-08T17:00:10Z + 2003-09-17T09:51:34-07:00 + Altera Corporation + 2003-09-17T09:51:34-07:00 + + + MAX 7000A Programmable Logic Device Data Sheet + + + + + This data sheet provides information on MAX 7000A programmable logic devices. + + + + + + Altera Corporation + MAX 7000A Programmable Logic Device Data Sheet + This data sheet provides information on MAX 7000A programmable logic devices. + + + + +endstream +endobj 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and b/docs/Nascom_Basic_Manual.pdf differ diff --git a/license.txt b/license.txt new file mode 100644 index 000000000..f288702d2 --- /dev/null +++ b/license.txt @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/pcb/FusionX/v1.0/tzpuFusionX_v1_0_109x55.zip b/pcb/FusionX/v1.0/tzpuFusionX_v1_0_109x55.zip new file mode 100644 index 000000000..59552f939 Binary files /dev/null and b/pcb/FusionX/v1.0/tzpuFusionX_v1_0_109x55.zip differ diff --git a/pcb/FusionX/v1.0/tzpuFusionX_v1_0_3D_Bottom.png b/pcb/FusionX/v1.0/tzpuFusionX_v1_0_3D_Bottom.png new file mode 100644 index 000000000..d1020b5dd Binary files /dev/null and b/pcb/FusionX/v1.0/tzpuFusionX_v1_0_3D_Bottom.png differ diff --git a/pcb/FusionX/v1.0/tzpuFusionX_v1_0_3D_Top.png b/pcb/FusionX/v1.0/tzpuFusionX_v1_0_3D_Top.png new file mode 100644 index 000000000..174896642 Binary files /dev/null and b/pcb/FusionX/v1.0/tzpuFusionX_v1_0_3D_Top.png differ diff --git a/pcb/VideoInterface/MZ2000/v1.0/VideoInterface_MZ2000_v1_0_3D_Bottom.png b/pcb/VideoInterface/MZ2000/v1.0/VideoInterface_MZ2000_v1_0_3D_Bottom.png new file mode 100644 index 000000000..febeaefb6 Binary files /dev/null and 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--git a/software/FusionX/bin/z80ctrl b/software/FusionX/bin/z80ctrl new file mode 100755 index 000000000..f617a39c3 Binary files /dev/null and b/software/FusionX/bin/z80ctrl differ diff --git a/software/FusionX/etc/cpuset.sh b/software/FusionX/etc/cpuset.sh new file mode 100755 index 000000000..a41091528 --- /dev/null +++ b/software/FusionX/etc/cpuset.sh @@ -0,0 +1,14 @@ +#!/bin/sh + +for f in `ps -eaf |grep -v kthread_z80 | awk '{print $1}'` +do + taskset -pc 0 $f >/dev/null 2>/dev/null +done + +for I in $(ls /proc/irq) +do + if [[ -d "/proc/irq/$I" ]] + then + echo 0 > /proc/irq/$I/smp_affinity_list 2>/dev/null + fi +done diff --git a/software/FusionX/etc/fb.sh b/software/FusionX/etc/fb.sh new file mode 100755 index 000000000..439f909ba --- /dev/null +++ b/software/FusionX/etc/fb.sh @@ -0,0 +1,14 @@ +#!/bin/sh -x + +fbdev=/dev/fb0 ; width=1280 ; bpp=4 +color="\x00\xFF\x00\x00" #red colored + +function pixel() +{ xx=$1 ; yy=$2 + printf "$color" | dd bs=$bpp seek=$(($yy * $width + $xx)) \ + of=$fbdev &>/dev/null +} +x=0 ; y=0 ; clear +for i in {1..10000}; do + pixel $((x++)) $((y++)) +done diff --git a/software/FusionX/etc/testgpio.sh b/software/FusionX/etc/testgpio.sh new file mode 100755 index 000000000..463c1aaae --- /dev/null +++ b/software/FusionX/etc/testgpio.sh @@ -0,0 +1,21 @@ +#!/bin/sh + +for f in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 47 48 85 86 90 73 59 +do + echo "PIN: ${f} ---------------------------------------------" + sleep 1 + echo "Export PIN" + echo $f > /sys/class/gpio/export + echo " Direction OUT" + echo out > /sys/class/gpio/gpio${f}/direction + echo " OUT 1" + echo 1 > /sys/class/gpio/gpio${f}/value + echo " OUT 0" + echo 0 > /sys/class/gpio/gpio${f}/value + echo " Direction IN" + echo in > /sys/class/gpio/gpio${f}/direction + echo " IN" + cat /sys/class/gpio/gpio${f}/value + echo "-------------------------------------------------------" + sleep 1 +done diff --git a/software/FusionX/etc/z80drv.sh b/software/FusionX/etc/z80drv.sh new file mode 100755 index 000000000..5712255d0 --- /dev/null +++ b/software/FusionX/etc/z80drv.sh @@ -0,0 +1,8 @@ +#!/bin/sh + +cd /customer +./cpuset.sh +rmmod z80drv 2>/dev/null +insmod z80drv.ko +#drvid=`ps -eaf | grep kthread_z80 | grep -v grep | awk '{print $1}'` +#taskset -pc 1 $drvid diff --git a/software/FusionX/modules/z80drv.ko b/software/FusionX/modules/z80drv.ko new file mode 100644 index 000000000..4462589b5 Binary files /dev/null and b/software/FusionX/modules/z80drv.ko differ diff --git a/software/FusionX/src/driver/CMakeLists.txt b/software/FusionX/src/driver/CMakeLists.txt new file mode 100644 index 000000000..879a76358 --- /dev/null +++ b/software/FusionX/src/driver/CMakeLists.txt @@ -0,0 +1,51 @@ +set(kerneldir "/srv/dvlp/Projects/tzpu/FusionX/software/linux/kernel" CACHE STRING "Path to the kernel build directory") +if("${kerneldir}" STREQUAL "") + execute_process(COMMAND uname -r OUTPUT_VARIABLE uname_r + OUTPUT_STRIP_TRAILING_WHITESPACE) + set(kerneldir "/lib/modules/${uname_r}/build") +endif() +include(GNUInstallDirs) +include_directories(${kerneldir}/include) +find_file(kernel_makefile NAMES Makefile + PATHS ${kerneldir} NO_DEFAULT_PATH) +if(NOT kernel_makefile) + message(FATAL_ERROR "There is no Makefile in kerneldir!") +endif() +add_library(mymodule-lib STATIC z80drv.c) +get_target_property(module_sources mymodule-lib SOURCES) +list(APPEND module_sources z80drv.c) + +#find_package(Z80 REQUIRED Shared) +add_subdirectory(Z80) +target_link_libraries(mymodule-lib Z80) + +# the name of the target operating system +set(CMAKE_SYSTEM_NAME Linux) + +# which compilers to use for C and C++ +set(CMAKE_C_COMPILER arm-linux-gnueabihf-gcc) +set(CMAKE_CXX_COMPILER arm-linux-gnueabihf-g++) + +# adjust the default behavior of the FIND_XXX() commands: +# search programs in the host environment +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) + +# search headers and libraries in the target environment +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +string(REPLACE ";" " " module_sources_string "${module_sources}") +configure_file(Kbuild.in Kbuild @ONLY) + +foreach(src ${module_sources}) + configure_file(${src} ${src} COPYONLY) +endforeach() + +set(module_cmd ${CMAKE_MAKE_PROGRAM} -C ${kerneldir} ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- M=${CMAKE_CURRENT_BINARY_DIR} modules) +add_custom_command(OUTPUT z80drv.ko + COMMAND ${module_cmd} modules + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + DEPENDS ${module_sources} ${CMAKE_CURRENT_BINARY_DIR}/Kbuild + VERBATIM) +add_custom_target(module DEPENDS z80drv.ko) +add_custom_target(module-clean COMMAND ${module_cmd} clean) diff --git a/software/FusionX/src/driver/MZ2000/optparse.h b/software/FusionX/src/driver/MZ2000/optparse.h new file mode 100644 index 000000000..f96184add --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/optparse.h @@ -0,0 +1,403 @@ +/* Optparse --- portable, reentrant, embeddable, getopt-like option parser + * + * This is free and unencumbered software released into the public domain. + * + * To get the implementation, define OPTPARSE_IMPLEMENTATION. + * Optionally define OPTPARSE_API to control the API's visibility + * and/or linkage (static, __attribute__, __declspec). + * + * The POSIX getopt() option parser has three fatal flaws. These flaws + * are solved by Optparse. + * + * 1) Parser state is stored entirely in global variables, some of + * which are static and inaccessible. This means only one thread can + * use getopt(). It also means it's not possible to recursively parse + * nested sub-arguments while in the middle of argument parsing. + * Optparse fixes this by storing all state on a local struct. + * + * 2) The POSIX standard provides no way to properly reset the parser. + * This means for portable code that getopt() is only good for one + * run, over one argv with one option string. It also means subcommand + * options cannot be processed with getopt(). Most implementations + * provide a method to reset the parser, but it's not portable. + * Optparse provides an optparse_arg() function for stepping over + * subcommands and continuing parsing of options with another option + * string. The Optparse struct itself can be passed around to + * subcommand handlers for additional subcommand option parsing. A + * full reset can be achieved by with an additional optparse_init(). + * + * 3) Error messages are printed to stderr. This can be disabled with + * opterr, but the messages themselves are still inaccessible. + * Optparse solves this by writing an error message in its errmsg + * field. The downside to Optparse is that this error message will + * always be in English rather than the current locale. + * + * Optparse should be familiar with anyone accustomed to getopt(), and + * it could be a nearly drop-in replacement. The option string is the + * same and the fields have the same names as the getopt() global + * variables (optarg, optind, optopt). + * + * Optparse also supports GNU-style long options with optparse_long(). + * The interface is slightly different and simpler than getopt_long(). + * + * By default, argv is permuted as it is parsed, moving non-option + * arguments to the end. This can be disabled by setting the `permute` + * field to 0 after initialization. + */ +#ifndef OPTPARSE_H +#define OPTPARSE_H + +#ifndef OPTPARSE_API +# define OPTPARSE_API +#endif + +struct optparse { + char **argv; + int permute; + int optind; + int optopt; + char *optarg; + char errmsg[64]; + int subopt; +}; + +enum optparse_argtype { + OPTPARSE_NONE, + OPTPARSE_REQUIRED, + OPTPARSE_OPTIONAL +}; + +struct optparse_long { + const char *longname; + int shortname; + enum optparse_argtype argtype; +}; + +/** + * Initializes the parser state. + */ +OPTPARSE_API +void optparse_init(struct optparse *options, char **argv); + +/** + * Read the next option in the argv array. + * @param optstring a getopt()-formatted option string. + * @return the next option character, -1 for done, or '?' for error + * + * Just like getopt(), a character followed by no colons means no + * argument. One colon means the option has a required argument. Two + * colons means the option takes an optional argument. + */ +OPTPARSE_API +int optparse(struct optparse *options, const char *optstring); + +/** + * Handles GNU-style long options in addition to getopt() options. + * This works a lot like GNU's getopt_long(). The last option in + * longopts must be all zeros, marking the end of the array. The + * longindex argument may be NULL. + */ +OPTPARSE_API +int optparse_long(struct optparse *options, + const struct optparse_long *longopts, + int *longindex); + +/** + * Used for stepping over non-option arguments. + * @return the next non-option argument, or NULL for no more arguments + * + * Argument parsing can continue with optparse() after using this + * function. That would be used to parse the options for the + * subcommand returned by optparse_arg(). This function allows you to + * ignore the value of optind. + */ +OPTPARSE_API +char *optparse_arg(struct optparse *options); + +/* Implementation */ +#ifdef OPTPARSE_IMPLEMENTATION + +#define OPTPARSE_MSG_INVALID "invalid option" +#define OPTPARSE_MSG_MISSING "option requires an argument" +#define OPTPARSE_MSG_TOOMANY "option takes no arguments" + +static int +optparse_error(struct optparse *options, const char *msg, const char *data) +{ + unsigned p = 0; + const char *sep = " -- '"; + while (*msg) + options->errmsg[p++] = *msg++; + while (*sep) + options->errmsg[p++] = *sep++; + while (p < sizeof(options->errmsg) - 2 && *data) + options->errmsg[p++] = *data++; + options->errmsg[p++] = '\''; + options->errmsg[p++] = '\0'; + return '?'; +} + +OPTPARSE_API +void +optparse_init(struct optparse *options, char **argv) +{ + options->argv = argv; + options->permute = 1; + options->optind = 1; + options->subopt = 0; + options->optarg = 0; + options->errmsg[0] = '\0'; +} + +static int +optparse_is_dashdash(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] == '-' && arg[2] == '\0'; +} + +static int +optparse_is_shortopt(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] != '-' && arg[1] != '\0'; +} + +static int +optparse_is_longopt(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] == '-' && arg[2] != '\0'; +} + +static void +optparse_permute(struct optparse *options, int index) +{ + char *nonoption = options->argv[index]; + int i; + for (i = index; i < options->optind - 1; i++) + options->argv[i] = options->argv[i + 1]; + options->argv[options->optind - 1] = nonoption; +} + +static int +optparse_argtype(const char *optstring, char c) +{ + int count = OPTPARSE_NONE; + if (c == ':') + return -1; + for (; *optstring && c != *optstring; optstring++); + if (!*optstring) + return -1; + if (optstring[1] == ':') + count += optstring[2] == ':' ? 2 : 1; + return count; +} + +OPTPARSE_API +int +optparse(struct optparse *options, const char *optstring) +{ + int type; + char *next; + char *option = options->argv[options->optind]; + options->errmsg[0] = '\0'; + options->optopt = 0; + options->optarg = 0; + if (option == 0) { + return -1; + } else if (optparse_is_dashdash(option)) { + options->optind++; /* consume "--" */ + return -1; + } else if (!optparse_is_shortopt(option)) { + if (options->permute) { + int index = options->optind++; + int r = optparse(options, optstring); + optparse_permute(options, index); + options->optind--; + return r; + } else { + return -1; + } + } + option += options->subopt + 1; + options->optopt = option[0]; + type = optparse_argtype(optstring, option[0]); + next = options->argv[options->optind + 1]; + switch (type) { + case -1: { + char str[2] = {0, 0}; + str[0] = option[0]; + options->optind++; + return optparse_error(options, OPTPARSE_MSG_INVALID, str); + } + case OPTPARSE_NONE: + if (option[1]) { + options->subopt++; + } else { + options->subopt = 0; + options->optind++; + } + return option[0]; + case OPTPARSE_REQUIRED: + options->subopt = 0; + options->optind++; + if (option[1]) { + options->optarg = option + 1; + } else if (next != 0) { + options->optarg = next; + options->optind++; + } else { + char str[2] = {0, 0}; + str[0] = option[0]; + options->optarg = 0; + return optparse_error(options, OPTPARSE_MSG_MISSING, str); + } + return option[0]; + case OPTPARSE_OPTIONAL: + options->subopt = 0; + options->optind++; + if (option[1]) + options->optarg = option + 1; + else + options->optarg = 0; + return option[0]; + } + return 0; +} + +OPTPARSE_API +char * +optparse_arg(struct optparse *options) +{ + char *option = options->argv[options->optind]; + options->subopt = 0; + if (option != 0) + options->optind++; + return option; +} + +static int +optparse_longopts_end(const struct optparse_long *longopts, int i) +{ + return !longopts[i].longname && !longopts[i].shortname; +} + +static void +optparse_from_long(const struct optparse_long *longopts, char *optstring) +{ + char *p = optstring; + int i; + for (i = 0; !optparse_longopts_end(longopts, i); i++) { + if (longopts[i].shortname && longopts[i].shortname < 127) { + int a; + *p++ = longopts[i].shortname; + for (a = 0; a < (int)longopts[i].argtype; a++) + *p++ = ':'; + } + } + *p = '\0'; +} + +/* Unlike strcmp(), handles options containing "=". */ +static int +optparse_longopts_match(const char *longname, const char *option) +{ + const char *a = option, *n = longname; + if (longname == 0) + return 0; + for (; *a && *n && *a != '='; a++, n++) + if (*a != *n) + return 0; + return *n == '\0' && (*a == '\0' || *a == '='); +} + +/* Return the part after "=", or NULL. */ +static char * +optparse_longopts_arg(char *option) +{ + for (; *option && *option != '='; option++); + if (*option == '=') + return option + 1; + else + return 0; +} + +static int +optparse_long_fallback(struct optparse *options, + const struct optparse_long *longopts, + int *longindex) +{ + int result; + char optstring[96 * 3 + 1]; /* 96 ASCII printable characters */ + optparse_from_long(longopts, optstring); + result = optparse(options, optstring); + if (longindex != 0) { + *longindex = -1; + if (result != -1) { + int i; + for (i = 0; !optparse_longopts_end(longopts, i); i++) + if (longopts[i].shortname == options->optopt) + *longindex = i; + } + } + return result; +} + +OPTPARSE_API +int +optparse_long(struct optparse *options, + const struct optparse_long *longopts, + int *longindex) +{ + int i; + char *option = options->argv[options->optind]; + if (option == 0) { + return -1; + } else if (optparse_is_dashdash(option)) { + options->optind++; /* consume "--" */ + return -1; + } else if (optparse_is_shortopt(option)) { + return optparse_long_fallback(options, longopts, longindex); + } else if (!optparse_is_longopt(option)) { + if (options->permute) { + int index = options->optind++; + int r = optparse_long(options, longopts, longindex); + optparse_permute(options, index); + options->optind--; + return r; + } else { + return -1; + } + } + + /* Parse as long option. */ + options->errmsg[0] = '\0'; + options->optopt = 0; + options->optarg = 0; + option += 2; /* skip "--" */ + options->optind++; + for (i = 0; !optparse_longopts_end(longopts, i); i++) { + const char *name = longopts[i].longname; + if (optparse_longopts_match(name, option)) { + char *arg; + if (longindex) + *longindex = i; + options->optopt = longopts[i].shortname; + arg = optparse_longopts_arg(option); + if (longopts[i].argtype == OPTPARSE_NONE && arg != 0) { + return optparse_error(options, OPTPARSE_MSG_TOOMANY, name); + } if (arg != 0) { + options->optarg = arg; + } else if (longopts[i].argtype == OPTPARSE_REQUIRED) { + options->optarg = options->argv[options->optind]; + if (options->optarg == 0) + return optparse_error(options, OPTPARSE_MSG_MISSING, name); + else + options->optind++; + } + return options->optopt; + } + } + return optparse_error(options, OPTPARSE_MSG_INVALID, option); +} + +#endif /* OPTPARSE_IMPLEMENTATION */ +#endif /* OPTPARSE_H */ diff --git a/software/FusionX/src/driver/MZ2000/z80ctrl.c b/software/FusionX/src/driver/MZ2000/z80ctrl.c new file mode 100644 index 000000000..6e7565c6a --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80ctrl.c @@ -0,0 +1,794 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80ctrl.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Control Interface +// This file contains a command line utility tool for controlling the z80drv device +// driver. The tool allows manipulation of the emulated Z80, inspection of its +// memory and data, transmission of adhoc commands to the underlying CPLD-Z80 +// gateway and loading/saving of programs and data to/from the Z80 virtual and +// host memory. +// +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of the Z80 device driver. +// Copyright: (c) 2019-2022 Philip Smart +// (c) 1999-2022 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80driver.h" + +#define VERSION "1.0" +#define AUTHOR "P.D.Smart" +#define COPYRIGHT "(c) 2018-22" + +// Getopt_long is buggy so we use optparse. +#define OPTPARSE_IMPLEMENTATION +#define OPTPARSE_API static +#include "optparse.h" + +// Device driver name. +#define DEVICE_FILENAME "/dev/z80drv" + +// Constants for the Sharp MZ80A MZF file format. +#define MZF_HEADER_SIZE 128 // Size of the MZF header. +#define MZF_ATTRIBUTE 0x00 // Code Type, 01 = Machine Code. +#define MZF_FILENAME 0x01 // Title/Name (17 bytes). +#define MZF_FILENAME_LEN 17 // Length of the filename, it is not NULL terminated, generally a CR can be taken as terminator but not guaranteed. +#define MZF_FILESIZE 0x12 // Size of program. +#define MZF_LOADADDR 0x14 // Load address of program. +#define MZF_EXECADDR 0x16 // Exec address of program. +#define MZF_COMMENT 0x18 // Comment, used for details of the file or startup code. +#define MZF_COMMENT_LEN 104 // Length of the comment field. +#define CMT_TYPE_OBJCD 0x001 // MZF contains a binary object. +#define CMT_TYPE_BTX1CD 0x002 // MZF contains a BASIC program. +#define CMT_TYPE_BTX2CD 0x005 // MZF contains a BASIC program. +#define CMT_TYPE_TZOBJCD0 0x0F8 // MZF contains a TZFS binary object for page 0. +#define CMT_TYPE_TZOBJCD1 0x0F9 +#define CMT_TYPE_TZOBJCD2 0x0FA +#define CMT_TYPE_TZOBJCD3 0x0FB +#define CMT_TYPE_TZOBJCD4 0x0FC +#define CMT_TYPE_TZOBJCD5 0x0FD +#define CMT_TYPE_TZOBJCD6 0x0FE +#define CMT_TYPE_TZOBJCD7 0x0FF // MZF contains a TZFS binary object for page 7. +#define MZ_CMT_ADDR 0x10F0 + +// Structure to define a Sharp MZ80A MZF directory structure. This header appears at the beginning of every Sharp MZ80A tape (and more recently archived/emulator) images. +// +typedef struct __attribute__((__packed__)) { + uint8_t attr; // MZF attribute describing the file. + uint8_t fileName[MZF_FILENAME_LEN]; // Each directory entry is the size of an MZF filename. + uint16_t fileSize; // Size of file. + uint16_t loadAddr; // Load address for the file. + uint16_t execAddr; // Execution address where the Z80 starts processing. + uint8_t comment[MZF_COMMENT_LEN]; // Text comment field but often contains a startup machine code program. +} t_svcDirEnt; + +// Possible commands to be issued to the Z80 driver. +enum CTRL_COMMANDS { + Z80_CMD_STOP = 0, + Z80_CMD_START = 1, + Z80_CMD_PAUSE = 2, + Z80_CMD_CONTINUE = 3, + Z80_CMD_RESET = 4, + Z80_CMD_SPEED = 5, + Z80_CMD_HOST_RAM = 6, + Z80_CMD_VIRTUAL_RAM = 7, + Z80_CMD_DUMP_MEMORY = 8, + Z80_CMD_MEMORY_TEST = 9, + CPLD_CMD_SEND_CMD = 10, + CPLD_CMD_SPI_TEST = 11, + CPLD_CMD_PRL_TEST = 12 +}; + + +// Shared memory between this process and the Z80 driver. +static t_Z80Ctrl *Z80Ctrl = NULL; + +// Method to obtain and return the output screen width. +// +uint8_t getScreenWidth(void) +{ + return(MAX_SCREEN_WIDTH); +} + +struct termios orig_termios; + +void reset_terminal_mode() +{ + tcsetattr(0, TCSANOW, &orig_termios); +} + +void set_conio_terminal_mode() +{ + struct termios new_termios; + + /* take two copies - one for now, one for later */ + tcgetattr(0, &orig_termios); + memcpy(&new_termios, &orig_termios, sizeof(new_termios)); + + /* register cleanup handler, and set the new terminal mode */ + atexit(reset_terminal_mode); + cfmakeraw(&new_termios); + tcsetattr(0, TCSANOW, &new_termios); +} + +int kbhit() +{ + struct timeval tv = { 0L, 0L }; + fd_set fds; + FD_ZERO(&fds); + FD_SET(0, &fds); + return select(1, &fds, NULL, NULL, &tv) > 0; +} + +int getch(uint8_t wait) +{ + int r; + unsigned char c; + + if(wait != 0 || (wait == 0 && kbhit())) + { + if ((r = read(0, &c, sizeof(c))) < 0) { + return r; + } else { + return c; + } + } + return 0; +} + +void delay(int number_of_seconds) +{ + // Converting time into milli_seconds + int milli_seconds = 1000 * number_of_seconds; + + // Storing start time + clock_t start_time = clock(); + + // looping till required time is not achieved + while (clock() < start_time + milli_seconds); +} + +// Function to dump out a given section of memory via the UART. +// +int memoryDump(uint32_t memaddr, uint32_t memsize, uint8_t memoryFlag, uint32_t memwidth, uint32_t dispaddr, uint8_t dispwidth) +{ + uint8_t displayWidth = dispwidth;; + uint32_t pnt = memaddr; + uint32_t endAddr = memaddr + memsize; + uint32_t addr = dispaddr; + uint32_t i = 0; + //uint32_t data; + int8_t keyIn; + int result = -1; + char c = 0; + + // Sanity check. memoryFlag == 0 required kernel driver to dump so we exit as it cannot be performed here. + if(memoryFlag == 0) + return(-1); + + // Reconfigure terminal to allow non-blocking key input. + // + set_conio_terminal_mode(); + + // If not set, calculate output line width according to connected display width. + // + if(displayWidth == 0) + { + switch(getScreenWidth()) + { + case 40: + displayWidth = 8; + break; + case 80: + displayWidth = 16; + break; + default: + displayWidth = 32; + break; + } + } + + while (1) + { + printf("%08lX", addr); // print address + printf(": "); + + // print hexadecimal data + for (i=0; i < displayWidth; ) + { + switch(memwidth) + { + case 16: + if(pnt+i < endAddr) + printf("%04X", memoryFlag == 1 ? (uint16_t)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (uint16_t)Z80Ctrl->page[pnt+i] : (uint16_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + + case 32: + if(pnt+i < endAddr) + printf("%08lX", memoryFlag == 1 ? (uint32_t)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (uint32_t)Z80Ctrl->page[pnt+i] : (uint32_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + + case 8: + default: + if(pnt+i < endAddr) + printf("%02X", memoryFlag == 1 ? (uint8_t)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (uint8_t)Z80Ctrl->page[pnt+i] : (uint8_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + } + fputc((char)' ', stdout); + } + + // print ascii data + printf(" |"); + + // print single ascii char + for (i=0; i < displayWidth; i++) + { + c = memoryFlag == 1 ? (char)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (char)Z80Ctrl->page[pnt+i] : (char)Z80Ctrl->iopage[pnt+i]; + if ((pnt+i < endAddr) && (c >= ' ') && (c <= '~')) + fputc((char)c, stdout); + else + fputc((char)' ', stdout); + } + + printf("|\r\n"); + fflush(stdout); + + // Move on one row. + pnt += displayWidth; + addr += displayWidth; + + // User abort (ESC), pause (Space) or all done? + // + keyIn = getch(0); + if(keyIn == ' ') + { + do { + keyIn = getch(0); + } while(keyIn != ' ' && keyIn != 0x1b); + } + // Escape key pressed, exit with 0 to indicate this to caller. + if (keyIn == 0x1b) + { + sleep(1); + result = 0; + goto memoryDumpExit; + } + + // End of buffer, exit the loop. + if(pnt >= (memaddr + memsize)) + { + break; + } + } + + // Normal exit, return -1 to show no key pressed. +memoryDumpExit: + reset_terminal_mode(); + return(result); +} + +// Method to load a program or data file into the Z80 memory. First load into Virtual memory and then trigger a sync to bring Host RAM in line. +// +int z80load(int fdZ80, char *fileName) +{ + // Locals. + struct ioctlCmd ioctlCmd; + int ret = 0; + t_svcDirEnt mzfHeader; + + // Pause the Z80. + // + ioctlCmd.cmd = IOCTL_CMD_Z80_PAUSE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + // Open the file and read directly into the Virtual memory via the share. + FILE *ptr; + ptr = fopen(fileName, "rb"); + if(ptr) + { + // First the header. + fread((uint8_t *)&mzfHeader, MZF_HEADER_SIZE, 1, ptr); + +#if(TARGET_HOST_MZ700 == 1) + if(mzfHeader.loadAddr > 0x1000) + { +#endif + // Copy in the header. + memcpy((uint8_t *)&Z80Ctrl->memory[MZ_CMT_ADDR], (uint8_t *)&mzfHeader, MZF_HEADER_SIZE); + + // Now read in the data. + fread(&Z80Ctrl->memory[mzfHeader.loadAddr], mzfHeader.fileSize, 1, ptr); + printf("Loaded %s, Size:%04x, Addr:%04x, Exec:%04x\n", fileName, mzfHeader.fileSize, mzfHeader.loadAddr, mzfHeader.execAddr); +#if(TARGET_HOST_MZ700 == 1) + } +#endif + + // Sync the loaded image from Virtual memory to hard memory. + ioctlCmd.cmd = IOCTL_CMD_SYNC_TO_HOST_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + +#if(TARGET_HOST_MZ2000 == 1) + // Set PC to 2 (NST) which switches to RUN mode and executes at 0000H + ioctlCmd.z80.pc = 2; +#endif +#if(TARGET_HOST_MZ700 == 1) + // MZ-700 just use the MZF header exec address. + ioctlCmd.z80.pc = mzfHeader.execAddr; +#endif + + // Set PC to required setting ready for run. + ioctlCmd.cmd = IOCTL_CMD_SETPC; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + // Resume Z80 processing. + // + ioctlCmd.cmd = IOCTL_CMD_Z80_CONTINUE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + else + printf("Couldnt open file\n"); + + return ret; +} + +// Method to request basic Z80 operations. +// +int ctrlCmd(int fdZ80, enum CTRL_COMMANDS cmd, long param1, long param2, long param3) +{ + // Locals. + struct ioctlCmd ioctlCmd; + uint32_t idx; + int ret = 0; + + switch(cmd) + { + case Z80_CMD_STOP: + // Use IOCTL to request Z80 to Stop (power off) processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_START: + // Use IOCTL to request Z80 to Start (power on) processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_START; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_PAUSE: + // Use IOCTL to request Z80 to pause processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_PAUSE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_CONTINUE: + // Use IOCTL to request Z80 continue processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_CONTINUE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_RESET: + // Use IOCTL to request Z80 reset. + ioctlCmd.cmd = IOCTL_CMD_Z80_RESET; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_SPEED: + // Check value is in range. + for(idx=1; idx < 256; idx+=idx) + { + if((uint32_t)param1 == idx) break; + } + if(idx == 256) + { + printf("Speed factor is illegal. It must be a multiple value of the original CPU clock, ie. 1x, 2x, 4x etc\n"); + ret = -1; + } else + { + // Use IOCTL to request Z80 cpu freq change. + ioctlCmd.speed.speedMultiplier = (uint32_t)param1; + ioctlCmd.cmd = IOCTL_CMD_Z80_CPU_FREQ; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case CPLD_CMD_SEND_CMD: + // Build up the IOCTL command to request the given data is sent to the CPLD. + ioctlCmd.cmd = IOCTL_CMD_CPLD_CMD; + ioctlCmd.cpld.cmd = (uint32_t)param1; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_DUMP_MEMORY: + // If virtual memory, we can dump it via the shared memory segment. + if((uint8_t)param1) + { + memoryDump((uint32_t)param2, (uint32_t)param3, (uint8_t)param1, (uint8_t)param1 == 2 || (uint8_t)param1 == 3 ? 32 : 8, (uint32_t)param2, 0); + } else + { + // Build an IOCTL command to get the driver to dump the memory. + ioctlCmd.cmd = IOCTL_CMD_DUMP_MEMORY; + ioctlCmd.addr.start = (uint32_t)param2; + ioctlCmd.addr.end = (uint32_t)param2+(uint32_t)param3; + ioctlCmd.addr.size = (uint32_t)param3; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case Z80_CMD_HOST_RAM: + // Use IOCTL to request change to host RAM. + ioctlCmd.cmd = IOCTL_CMD_USE_HOST_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_VIRTUAL_RAM: + // Use IOCTL to request change to host RAM. + ioctlCmd.cmd = IOCTL_CMD_USE_VIRTUAL_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_MEMORY_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_Z80_MEMTEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case CPLD_CMD_PRL_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_PRL_TEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case CPLD_CMD_SPI_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_SPI_TEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + + default: + printf("Command not supported!\n"); + ret = -1; + break; + } + + return ret; +} + +// Method to perform some simple tests on the Z80 emulator. +// +int z80test(int fdZ80) +{ + // Locals. + struct ioctlCmd ioctlCmd; + int ret = 0; + + // Stop the Z80. + // +printf("Send STOP\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + FILE *ptr; + ptr = fopen("/customer/mz700.rom", "rb"); + if(ptr) + { + fread(&Z80Ctrl->memory, 65536, 1, ptr); + } else printf("Couldnt open file\n"); + + // Configure the Z80. + // +printf("Send SETPC\n"); + ioctlCmd.z80.pc = 0; + ioctl(fdZ80, IOCTL_CMD_SETPC, &ioctlCmd); + + memoryDump(0 , 65536, 1, 8, 0, 0); + + // Start the Z80. + // +printf("Send START\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_START; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + delay(10); + +printf("Send STOP\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + memoryDump(0, 65536, 1, 8, 0, 0); +out: + return ret; +} + +// Output usage screen. So mamy commands you do need to be prompted!! +void showArgs(char *progName, struct optparse *options) +{ + printf("%s %s %s %s\n\n", progName, VERSION, COPYRIGHT, AUTHOR); + printf("Synopsis:\n"); + printf("%s --help # This help screen.\n", progName); + printf(" --cmd = RESET # Reset the Z80\n"); + printf(" = STOP # Stop and power off the Z80\n"); + printf(" = START # Power on and start the Z80\n"); + printf(" = PAUSE # Pause running Z80\n"); + printf(" = CONTINUE # Continue Z80 execution\n"); + printf(" = HOSTRAM # Use HOST DRAM\n"); + printf(" = VIRTRAM # Use Virtual RAM\n"); + printf(" = SPEED --speed <1, 2, 4, 8, 16, 32, 64, 128> # In Virtual RAM mode, set CPU speed to base clock x factor.\n"); + printf(" = LOADMZF --file # Load MZF file into memory.\n"); + printf(" = DUMP --addr <24bit addr> --end <24bit addr> [--size <24bit>]--virtual <0 - Host RAM, 1 = Virtual RAM, 2 = PageTable, 3 = IOPageTable>\n"); + printf(" = CPLDCMD --data <32bit command> # Send adhoc 32bit command to CPLD.\n"); + printf(" = Z80TEST # Perform various debugging tests\n"); + printf(" = SPITEST # Perform SPI testing\n"); + printf(" = PRLTEST # Perform Parallel Bus testing\n"); + printf(" = Z80MEMTEST # Perform HOST memory tests.\n"); + printf(" -- # Some commands can be abbreviated.\n"); + +} + +int main(int argc, char *argv[]) +{ + int fdZ80; + char buff[64]; + char cmd[64] = { 0 }; + char fileName[256] = { 0 }; + int opt; + uint32_t hexData = 0; + long speedMultiplier = 1; + long startAddr = 0x0000; + long endAddr = 0x1000; + int virtualMemory = 0; + int helpFlag = 0; + int verboseFlag = 0; + + // Define parameters to be processed. + struct optparse options; + static struct optparse_long long_options[] = + { + {"help", 'h', OPTPARSE_NONE}, + {"cmd", 'c', OPTPARSE_REQUIRED}, + {"file", 'f', OPTPARSE_REQUIRED}, + {"data", 'd', OPTPARSE_REQUIRED}, + {"speed", 'S', OPTPARSE_REQUIRED}, + {"virtual", 'V', OPTPARSE_REQUIRED}, + {"addr", 'a', OPTPARSE_REQUIRED}, + {"end", 'e', OPTPARSE_REQUIRED}, + {"size", 's', OPTPARSE_REQUIRED}, + {"verbose", 'v', OPTPARSE_NONE}, + {"dump", '1', OPTPARSE_NONE}, + {"loadmzf", '2', OPTPARSE_NONE}, + {"reset", '3', OPTPARSE_NONE}, + {"stop", '4', OPTPARSE_NONE}, + {"start", '5', OPTPARSE_NONE}, + {"pause", '6', OPTPARSE_NONE}, + {"continue", '7', OPTPARSE_NONE}, + {"speed", '8', OPTPARSE_NONE}, + {"cpldcmd", '9', OPTPARSE_NONE}, + {0} + }; + + // Parse the command line options. + // + optparse_init(&options, argv); + while((opt = optparse_long(&options, long_options, NULL)) != -1) + { + switch(opt) + { + // Hex data. + case 'd': + // hexData = (uint32_t)strtol(options.optarg, NULL, 0); + sscanf(options.optarg, "0x%08x", &hexData); + printf("Hex data:%08x\n", hexData); + break; + + // Start address for memory operations. + case 'a': + startAddr = strtol(options.optarg, NULL, 0); + //printf("Start Addr:%04x\n", startAddr); + break; + + // Speed multiplication factor for CPU governor when running in virtual memory. + case 'S': + speedMultiplier = strtol(options.optarg, NULL, 0); + //printf("Speed = base freq x %d\n", speedFactor); + break; + + // End address for memory operations. + case 'e': + endAddr = strtol(options.optarg, NULL, 0); + //printf("End Addr:%04x\n", endAddr); + break; + + // Size instead of end address for memory operations. + case 's': + endAddr = startAddr + strtol(options.optarg, NULL, 0); + //printf("End Addr:%04x\n", endAddr); + break; + + // Virtual memory flag, 0 = host, 1 = virtual memory, 2 = page table, 3 = iopage table. + case 'V': + virtualMemory = atoi(options.optarg); + break; + + // Filename. + case 'f': + strcpy(fileName, options.optarg); + break; + + // Command to execute. + case 'c': + strcpy(cmd, options.optarg); + break; + + // Quick command flags. + case '1': + strcpy(cmd, "DUMP"); + break; + case '2': + strcpy(cmd, "LOADMZF"); + break; + case '3': + strcpy(cmd, "RESET"); + break; + case '4': + strcpy(cmd, "STOP"); + break; + case '5': + strcpy(cmd, "START"); + break; + case '6': + strcpy(cmd, "PAUSE"); + break; + case '7': + strcpy(cmd, "CONTINUE"); + break; + case '8': + strcpy(cmd, "SPEED"); + break; + case '9': + strcpy(cmd, "CPLDCMD"); + break; + + // Verbose mode. + case 'v': + verboseFlag = 1; + break; + + // Command help needed. + case 'h': + helpFlag = 1; + showArgs(argv[0], &options); + break; + + // Unrecognised, show synopsis. + case '?': + showArgs(argv[0], &options); + printf("%s: %s\n", argv[0], options.errmsg); + return(1); + } + } + + // Open the z80drv driver and attach to its shared memory, basically the Z80 control structure which includes the virtual Z80 memory. + fdZ80 = open(DEVICE_FILENAME, O_RDWR|O_NDELAY); + if(fdZ80 >= 0) + { + Z80Ctrl = (t_Z80Ctrl *)mmap(0, sizeof(t_Z80Ctrl), PROT_READ | PROT_WRITE, MAP_SHARED, fdZ80, 0); + if(Z80Ctrl == (void *)-1) + { + printf("Failed to attach to the Z80 Control structure, cannot continue, exitting....\n"); + close(fdZ80); + exit(1); + } + } else + { + printf("Failed to open the Z80 Driver, exitting...\n"); + exit(1); + } + + // Basic string to method mapping. Started off with just 1 or two but has grown, may need a table! + if(strcasecmp(cmd, "LOADMZF") == 0) + { + z80load(fdZ80, fileName); + } else + if(strcasecmp(cmd, "RESET") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_RESET, 0, 0, 0); + } else + if(strcasecmp(cmd, "STOP") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_STOP, 0, 0, 0); + } else + if(strcasecmp(cmd, "START") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_START, 0, 0, 0); + } else + if(strcasecmp(cmd, "PAUSE") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_PAUSE, 0, 0, 0); + } else + if(strcasecmp(cmd, "CONTINUE") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_CONTINUE, 0, 0, 0); + } else + if(strcasecmp(cmd, "SPEED") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_SPEED, speedMultiplier, 0, 0); + } else + if(strcasecmp(cmd, "DUMP") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_DUMP_MEMORY, virtualMemory, startAddr, (endAddr - startAddr)); + } else + if(strcasecmp(cmd, "HOSTRAM") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_HOST_RAM, 0, 0, 0); + } else + if(strcasecmp(cmd, "VIRTRAM") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_VIRTUAL_RAM, 0, 0, 0); + } else + if(strcasecmp(cmd, "CPLDCMD") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_SEND_CMD, hexData, 0, 0); + } else + + // Test methods, if the code is built-in to the driver. + if(strcasecmp(cmd, "Z80TEST") == 0) + { + z80test(fdZ80); + } else + if(strcasecmp(cmd, "SPITEST") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_SPI_TEST, 0, 0, 0); + } else + if(strcasecmp(cmd, "PRLTEST") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_PRL_TEST, 0, 0, 0); + } else + if(strcasecmp(cmd, "Z80MEMTEST") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_MEMORY_TEST, 0, 0, 0); + } + else + { + showArgs(argv[0], &options); + printf("No command given, nothing done!\n"); + } + + // Unmap shared memory and close the device. + munmap(Z80Ctrl, sizeof(t_Z80Ctrl)); + close(fdZ80); + + return(0); +} diff --git a/software/FusionX/src/driver/MZ2000/z80driver.c b/software/FusionX/src/driver/MZ2000/z80driver.c new file mode 100644 index 000000000..019e605bc --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80driver.c @@ -0,0 +1,1616 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80driver.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Driver +// This file contains the methods used to create a linux device driver which provides +// the services of a Z80 CPU emulation and the control of an underlying Z80'less host +// system. In essence this driver is the host Z80 CPU. +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of this driver and in all ways, is compatible with +// the original Z80. +// Copyright: (c) 2019-2022 Philip Smart +// (c) 1999-2022 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" +#include "z80menu.h" +#include "z80driver.h" + +#include +#include +#include + +/* Meta Information */ +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Philip D Smart"); +MODULE_DESCRIPTION("Z80 CPU Emulator and Hardware Interface Driver"); + +/* Global variables for the threads */ +static struct task_struct *kthread_z80; +static int threadId_z80 = 1; + +// Device class and major numbers. +static struct class *class; +static struct device *device; +static int major; + +// CPU Instance. +static Z80 Z80CPU; + +// Z80 Control data. +static t_Z80Ctrl *Z80Ctrl = NULL; + +// Runtime control of the CPU. As the CPU runs in a detached thread on core 1, the cpu needs to be suspended before any external +// operations can take place. This is achieved with the runtime mutex. +enum Z80_RUN_STATES Z80RunMode; +static struct mutex Z80RunModeMutex; +static DEFINE_MUTEX(Z80DRV_MUTEX); + + +//------------------------------------------------------------------------------------------------------------------------------- +// +// Z80 CPU Kernel Logic. +// +// THe Z80 CPU is initialised and set running, processing instructions either from the underlying host hardware or internal +// memory. The configuration and flow is controlled via the Z80Ctrl structure which is User Space accessible. +// +//------------------------------------------------------------------------------------------------------------------------------- + +// Method to read a byte from physical hardware or internal virtual memory/devices. +// The page table indicates the source and the read is processed accordingly. +static zuint8 z80_read(void *context, zuint16 address) +{ + // Locals. + // + zuint8 data; +// uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + Z_UNUSED(context) + + // Only read if the address is in physical RAM. + if(isPhysical(address)) + { + // Commence cycle to retrieve the data from Real RAM. + // Optimise SPI according to last address sent to CPLD. +// if(addrDiff >=0 && addrDiff < 8) +// { +// SPI_SEND8((CPLD_CMD_READ_ADDR + addrDiff)); +// Z80Ctrl->z80PrevAddr += addrDiff; +// } else +// { + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = address; +// } + while(CPLD_READY() == 0); + data = READ_CPLD_DATA_IN(); + + // Pause until the Last T-State is detected. + // while(CPLD_LAST_TSTATE() == 0); + } + else if(isVirtualHW(address)) + { + // Virtual Hardware - call the handler. + switch(realAddress(address)) + { + default: + break; + } + } + else if(isVirtualMemory(address)) + { + // Retrieve data from virtual memory. + data = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); +// if(address >= 0xCF01 && address < 0xCF0A) +// pr_info("Read:0x%x, 0x%x, 0x%x", address, data, isVirtualROM(address) ? getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK) + Z80_VIRTUAL_RAM_SIZE : getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK)); + } + + // Keyport data? Store. + if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 8 && (data & 0x41) == 0) + { + Z80Ctrl->keyportShiftCtrl = 0x01; + } else + if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 0 && (data & 0x80) == 0) + { + Z80Ctrl->keyportHotKey = 0x01; + } + return(data); +} + +// Method to write a byte to physical hardware or internal virtual memory or devices. +// The page table indicates the target and the write is processed accordingly. +static void z80_write(void *context, zuint16 address, zuint8 data) +{ + // Locals. + // uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + Z_UNUSED(context) + + // To detect Hotkey presses, we need to store the keboard strobe data and on keydata read. + if(isHW(address) && address == 0xE000) + { + Z80Ctrl->keyportStrobe = data; + } + + // Write to physical host? + if(isPhysical(address)) + { + // Commence cycle to write the data to real RAM. + // Optimise SPI according to last address sent to CPLD. +// if(addrDiff >=0 && addrDiff < 8) +// { +//if(address >= 0xD010 && address < 0xD017) { data = 0x41; } +// SPI_SEND16((data << 8) | (CPLD_CMD_WRITE_ADDR + addrDiff)); +// Z80Ctrl->z80PrevAddr += addrDiff; +// } else +// { + SPI_SEND32((uint32_t)address << 16 | data << 8 | CPLD_CMD_WRITE_ADDR); + Z80Ctrl->z80PrevAddr = address; +// } + + // Write-thru to virtual memory if we update real memory. + // if(isPhysicalRAM(address)) + // writeVirtualRAM(address, data); + +// if(address >= 0xD000 && address < 0xD018) +// pr_info("Write:0x%x, 0x%x, 0x%x", address, data, isVirtualROM(address) ? getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK) + Z80_VIRTUAL_RAM_SIZE : getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK)); + + // Pause until the Last T-State is detected. + // while(CPLD_LAST_TSTATE() == 0); + } + else if(isVirtualHW(address)) + { + // Virtual Hardware - call the handler. + switch(realAddress(address)) + { + default: + break; + } + } + else if(isVirtualRAM(address)) + { + // Update virtual memory. + writeVirtualRAM(address, data); +//pr_info("Write:0x%x, 0x%x, 0x%x", address, data, isVirtualROM(address) ? getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK) + Z80_VIRTUAL_RAM_SIZE : getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK)); + } + // Cannot write to virtual ROM so no logic. +} + +// Primary Opcode fetch method. This method is called each time a single or multi-byte opcode is +// encountered. Opcode data is retrieved via the z80_fetch method. +// +// Depending on the address and the configured page map, the opcode is fetched from hardware +// or internal virtual memory. As this method is the primary timing method for Z80 instructions +// (read/write methods dont affect the timing so much as long as they operate in less than the read/write +// cycle of an original Z80). +// Initially the timing on the virtual memory is set by a governor delay but this will be updated to a more +// precise M/T-State cycle per instruction type delay. +static zuint8 z80_fetch_opcode(void *context, zuint16 address) +{ + // Locals. + zuint8 opcode = 0x00; +// uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + volatile uint32_t idx; // Leave as volatile otherwise optimiser will optimise out the delay code. + Z_UNUSED(context) + + // Normally only opcode fetches occur in RAM but allow any physical address as it could be a Z80 programming trick. + if(isPhysical(address)) + { + // Commence cycle to fetch the opcode from potentially Real RAM albeit it could be any physical hardware. + // Optimise SPI according to last address sent to CPLD. +// if(addrDiff >=0 && addrDiff < 8) +// { +// SPI_SEND8((CPLD_CMD_FETCH_ADDR + addrDiff)); +// Z80Ctrl->z80PrevAddr += addrDiff; +// } else +// { + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_FETCH_ADDR); + Z80Ctrl->z80PrevAddr = address; +// } + while(CPLD_READY() == 0); + opcode = READ_CPLD_DATA_IN(); + + // Pause until the Last T-State is detected. +// while(CPLD_LAST_TSTATE() == 0); + } else + // Virtual fetches only occur in memory as we are not emulating original hardware. + if(isVirtualMemory(address)) + { + // for(idx=0; idx < Z80Ctrl->cpuGovernorDelay; idx++); + // for(idx=0; idx < 238; idx++); + // 243 loaded + + // Retrieve data from virtual memory. + // opcode = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + + if(isVirtualROM(address)) + { + opcode = readVirtualROM(address); + for(idx=0; idx < Z80Ctrl->cpuGovernorDelayROM; idx++); + } else + { + opcode = readVirtualRAM(address); + for(idx=0; idx < Z80Ctrl->cpuGovernorDelayRAM; idx++); + } + } +//if(opcode == 0xED && address > 0x270) +// pr_info("Fetch:0x%x, 0x%x, 0x%x", address, opcode, isVirtualROM(address) ? getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK) + Z80_VIRTUAL_RAM_SIZE : getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK)); + return(opcode); +} + +// Method similar to z80_read, kept seperate to avoid additional what-if logic and doesnt require virtual hardware logic. +// +static zuint8 z80_fetch(void *context, zuint16 address) +{ + // Locals. + // + zuint8 data = 0x00; +// uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + Z_UNUSED(context) + + // Normally only opcode fetches occur in RAM but allow any physical address as it could be a Z80 programming trick. + if(isPhysical(address)) + { + // Commence cycle to retrieve the data from Real RAM. + // Optimise SPI according to last address sent to CPLD. +// if(addrDiff >=0 && addrDiff < 8) +// { +// SPI_SEND8((CPLD_CMD_READ_ADDR + addrDiff)); +// Z80Ctrl->z80PrevAddr += addrDiff; +// } else +// { + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = address; +// } + while(CPLD_READY() == 0); + data = READ_CPLD_DATA_IN(); + + // Pause until the Last T-State is detected. +// while(CPLD_LAST_TSTATE() == 0); + } else + if(isVirtualMemory(address)) + { + // Retrieve data from virtual memory. + data = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + } +//pr_info("(0x%x)", data); + + return(data); +} + +// Method to perform a Z80 input operation. This normally goes to hardware and the CPLD executes the required cycle. +// Some ports are dedicated virtual ports providing virtual services to the host computer/application. These are intercepted +// and processed in this driver. +static zuint8 z80_in(void *context, zuint16 port) +{ + // Locals. + zuint8 value; +// uint16_t portDiff = (uint16_t)port - Z80Ctrl->z80PrevPort; + Z_UNUSED(context) + + // Physical port go direct to hardware to retrieve value. + if(isPhysicalIO(port)) + { + // Commence cycle to retrieve the value from the I/O port. Port contains the 16bit BC value. + // Optimise SPI according to last port sent to CPLD. +// if(portDiff >=0 && portDiff < 8) +// { +// SPI_SEND8((CPLD_CMD_READIO_ADDR + portDiff)); +// Z80Ctrl->z80PrevPort += portDiff; +// } else +// { + SPI_SEND32((uint32_t)port << 16 | CPLD_CMD_READIO_ADDR); + Z80Ctrl->z80PrevPort = port; +// } + + // Whilst waiting for the CPLD, we now determine if this is a memory management port and update the memory page if required. + switch(port & 0x00FF) + { + // Port is not a memory management port. + default: + break; + } + + // Finally ensure the data from the port is ready and retrieve it. + while(CPLD_READY() == 0); + value = READ_CPLD_DATA_IN(); + } else + // Virtual I/O Port. + { + // Virtual I/O - call the handler. + switch(realPort(port)) + { + default: + value = 0x00; + break; + } + } +// if((port&0x00ff) == 0xE8) +// pr_info("z80_in:0x%x, 0x%x\n", port, value); + return(value); +} + +// Method to perform a Z80 output operation. This normally goes to hardware and the CPLD executes the required cycle. +// Some ports are dedicated virtual ports providing virtual services to the host computer/application. These are intercepted +// and processed in this driver. +// There are also ports which are both hardware and need mirroring in software. These ports, typically memory mapping ports. +// when activated in the hardware need to be mirrored in the page table so correct virtual memory is used when addressed. +static void z80_out(void *context, zuint16 port, zuint8 value) +{ + // Locals. + uint32_t idx; +// uint16_t portDiff = (uint16_t)port - Z80Ctrl->z80PrevPort; + Z_UNUSED(context) + +//if((port&0xff) == 0xe8) +//{ +// value |= 0xC0; +//} +//udelay(10); + // Physical port go direct to hardware to retrieve value. + if(isPhysicalIO(port)) + { + // Commence cycle to write the value to the I/O port. Port contains the 16bit BC value. + // Optimise SPI according to last port sent to CPLD. +// if(portDiff >=0 && portDiff < 8) +// { +// SPI_SEND16((value << 8) | (CPLD_CMD_WRITEIO_ADDR + portDiff)); +// Z80Ctrl->z80PrevPort += portDiff; +// if((port&0x00ff) == 0xE8) +//pr_info("OUT:0x%x(%x)=0x%x\n", port, portDiff, value); +// } else +// { + SPI_SEND32((uint32_t)port << 16 | value << 8 | CPLD_CMD_WRITEIO_ADDR); + Z80Ctrl->z80PrevPort = port; +// if((port&0x00ff) == 0xE8) +// { +// SPI_SEND32((uint32_t)port << 16 | value << 8 | CPLD_CMD_WRITEIO_ADDR); +// udelay(10); +// SPI_SEND32((uint32_t)port << 16 | value << 8 | CPLD_CMD_WRITEIO_ADDR); +// udelay(10); +// SPI_SEND32((uint32_t)port << 16 | value << 8 | CPLD_CMD_WRITEIO_ADDR); +// udelay(10); +// SPI_SEND32((uint32_t)port << 16 | value << 8 | CPLD_CMD_WRITEIO_ADDR); +// udelay(10); +//pr_info("OUT:0x%x=0x%x\n", port, value); +// } +// } + +//udelay(10); + // Determine if this is a memory management port and update the memory page if required. + switch(port & 0x00FF) + { +#if(TARGET_HOST_MZ2000 == 1) + case IO_ADDR_E0: + break; + + case IO_ADDR_E1: + break; + + case IO_ADDR_E2: + break; + + case IO_ADDR_E3: + // Program control register. + if(value & 0x80) + { + } else + { + switch((value >> 1) & 0x07) + { + // NST toggle. + case 1: + // NST pages in all RAM and resets cpu. + if(value & 0x01) + { + Z80Ctrl->lowMemorySwap = 0; + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(Z80Ctrl->defaultPageMode == USE_PHYSICAL_RAM) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + } + z80_instant_reset(&Z80CPU); + } + break; + + default: + break; + } + } + break; + + case IO_ADDR_E8: + // NEED FLAG TO SET THIS WHEN CALLED WITH NON MEMORY SWITCH BYTE + if(isPhysical(0xD000) && (value & 0x80) == 0) + { + for(idx=0xC000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(Z80Ctrl->defaultPageMode == USE_PHYSICAL_RAM) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (Z80Ctrl->lowMemorySwap ? idx - 0x8000 : idx)); + } + } + } else + if(value & 0x80) + { + if(value & 0x40) + { + setMemoryType(0xD000/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, 0xD000); + } else + { + for(idx=0xC000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + } + } + break; +#endif + +#if(TARGET_HOST_MZ700 == 1) + // Enable lower 4K block as DRAM + case IO_ADDR_E0: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + break; + + // Enable upper 12K block, including Video/Memory Mapped peripherals area, as DRAM. + case IO_ADDR_E1: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + // MZ-700 mode we only work in first 64K block. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + } + break; + + // Enable Monitor ROM in lower 4K block + case IO_ADDR_E2: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + break; + + // Enable Video RAM and Memory mapped peripherals in upper 12K block. + case IO_ADDR_E3: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Reset to power on condition memory map. + case IO_ADDR_E4: + // Lower 4K set to Monitor ROM. + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + if(!Z80Ctrl->inhibitMode) + { + // Upper 12K to hardware. + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Inhibit. Backup current page data in region 0xD000-0xFFFF and inhibit it. + case IO_ADDR_E5: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + backupMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_INHIBIT, idx); + } + Z80Ctrl->inhibitMode = 1; + break; + + // Restore D000-FFFF to its original state. + case IO_ADDR_E6: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + restoreMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + } + Z80Ctrl->inhibitMode = 0; + break; +#endif + + // Port is not a memory management port. + default: + break; + } + } else + if(isVirtualIO(port)) + { + // MZ700 memory mode switch. + // + // MZ-700 + // |0000:0FFF|1000:CFFF|D000:FFFF + // ------------------------------ + // OUT 0xE0 = |DRAM | | + // OUT 0xE1 = | | |DRAM + // OUT 0xE2 = |MONITOR | | + // OUT 0xE3 = | | |Memory Mapped I/O + // OUT 0xE4 = |MONITOR |DRAM |Memory Mapped I/O + // OUT 0xE5 = | | |Inhibit + // OUT 0xE6 = | | | + // + // = Return to the state prior to the complimentary command being invoked. + + // Determine if this is a memory management port and update the memory page if required. + switch(port & 0x00FF) + { +#if(TARGET_HOST_MZ700 == 1) + // Enable lower 4K block as DRAM + case IO_ADDR_E0: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + break; + + // Enable upper 12K block, including Video/Memory Mapped peripherals area, as DRAM. + case IO_ADDR_E1: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + // MZ-700 mode we only work in first 64K block. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + } + break; + + // Enable MOnitor ROM in lower 4K block + case IO_ADDR_E2: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + break; + + // Enable Video RAM and Memory mapped peripherals in upper 12K block. + case IO_ADDR_E3: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Reset to power on condition memory map. + case IO_ADDR_E4: + // Lower 4K set to Monitor ROM. + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + if(!Z80Ctrl->inhibitMode) + { + // Upper 12K to hardware. + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Inhibit. Backup current page data in region 0xD000-0xFFFF and inhibit it. + case IO_ADDR_E5: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + backupMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_INHIBIT, idx); + } + Z80Ctrl->inhibitMode = 1; + break; + + // Restore D000-FFFF to its original state. + case IO_ADDR_E6: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + restoreMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + } + Z80Ctrl->inhibitMode = 0; + break; +#endif + + // Port is not a memory management port. + default: + break; + } + } else + { + // Virtual I/O - call the handler. + switch(realPort(port)) + { + default: + break; + } + } +//pr_info("z80_out:0x%x, 0x%x\n", port, value); +} + +// NOP - No Operation method. This instruction is used for timing, padding out an application or during +// HALT cycles to ensure Refresh occurs. +// If the address is configured as hardware (via the page table) then a refresh cycle is requested otherwise +// nothing to be done. +static zuint8 z80_nop(void *context, zuint16 address) +{ + // Locals. + Z_UNUSED(context) + + if(isPhysical(address)) + { + // If autorefresh is not enabled, send a single refresh request. + if(Z80Ctrl->refreshDRAM == 0) + SPI_SEND8(CPLD_CMD_REFRESH); +pr_info("NOP"); + } + return 0x00; +} + +// HALT - CPU executes a HALT instruction which results in the HALT line going active low and then it enters +// a state executing NOP instructions to ensure DRAM refresh until a reset or INT event. +static void z80_halt(void *context, zboolean state) +{ + // Locals. + Z_UNUSED(context) Z_UNUSED(state) + + // Inform CPLD of halt state. + printk("z80_halt\n"); + SPI_SEND8(CPLD_CMD_HALT); + Z80CPU.cycles = Z80_MAXIMUM_CYCLES; +} + +// Methods below are not yet implemented, Work In Progress! +static zuint8 z80_context(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_context\n"); + return 0x00; +} +static zuint8 z80_nmia(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_nmia\n"); + return 0x00; +} +static zuint8 z80_inta(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_inta\n"); + return 0x00; +} +static zuint8 z80_intFetch(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_int_fetch\n"); + return 0x00; +} +static void z80_ldia(void *context) +{ + Z_UNUSED(context) + printk("z80_ldia\n"); +} +static void z80_ldra(void *context) +{ + Z_UNUSED(context) + printk("z80_ldra\n"); +} +static void z80_reti(void *context) +{ + Z_UNUSED(context) + printk("z80_reti\n"); +} +static void z80_retn(void *context) +{ + Z_UNUSED(context) + printk("z80_retn\n"); +} +static zuint8 z80_illegal(void *context, zuint8 opcode) +{ + Z_UNUSED(context) + printk("z80_illegal\n"); + return 0x00; +} + +// Z80 CPU Emulation Thread +// ------------------------ +// This is a kernel thread, bound to CPU 1 with IRQ's disabled. +// The Z80 is controlled by a mutex protected variable to define run, stop, pause and terminate modes. +int thread_z80(void * thread_nr) +{ + // Locals. + uint8_t canRun = 0; + int t_nr = *(int *) thread_nr; + //struct sched_param param = {.sched_priority = 99}; + spinlock_t spinLock; + unsigned long flags; + + // Initialise spinlock and disable IRQ's. We should be the only process running on core 1. + spin_lock_init(&spinLock); + spin_lock_irqsave(&spinLock, flags); + + // Assign this emulation to high priority realtime scheduling. Also the task will be assigned to an isolated CPU. + //sched_setscheduler(current, SCHED_RR, ¶m); + + // Run the CPU forever or until a stop occurs. + while(!kthread_should_stop()) + { + // Run the Z80 emulation if enabled. + if(canRun) z80_run(&Z80CPU, 100); + + // Reset pressed? + if(CPLD_RESET()) + { + z80_instant_reset(&Z80CPU); + setupMemory(Z80Ctrl->defaultPageMode); + + // Wait for release before restarting CPU. + while(CPLD_RESET()); + } else + { + // Update state to indicate request has been actioned. + mutex_lock(&Z80RunModeMutex); + if(Z80RunMode == Z80_STOP) Z80RunMode = Z80_STOPPED; + if(Z80RunMode == Z80_PAUSE) Z80RunMode = Z80_PAUSED; + if(Z80RunMode == Z80_CONTINUE) Z80RunMode = Z80_RUNNING; + if(Z80RunMode == Z80_RUNNING) canRun=1; else canRun=0; + mutex_unlock(&Z80RunModeMutex); + + // Hotkey pressed? Bring up user menu. + if(Z80Ctrl->keyportShiftCtrl && Z80Ctrl->keyportHotKey) + { + z80menu(); + Z80Ctrl->keyportShiftCtrl = 0; + Z80Ctrl->keyportHotKey = 0; + } + } + } + + // Release spinlock as we are unloading driver. + spin_unlock_irqrestore(&spinLock, flags); + printk("kthread - Z80 Thread %d finished execution!\n", t_nr); + return 0; +} + + +//------------------------------------------------------------------------------------------------------------------------------- +// +// User space driver access. +// +//------------------------------------------------------------------------------------------------------------------------------- + + +// Device close. +// When a user space application terminates or closes the z80drv device driver, this function is called +// to close any open connections, memory and variables required to handle the user space application +// requests. +static int z80drv_release(struct inode *inodep, struct file *filep) +{ + // Locals. + + mutex_unlock(&Z80DRV_MUTEX); + //pr_info("z80drv: Device successfully closed\n"); + + return(0); +} + +// Device open. +// When a user space application open's the z80drv device driver, this function is called +// to initialise and allocate any required memory or devices prior to servicing requests from the +// user space application. +static int z80drv_open(struct inode *inodep, struct file *filep) +{ + // Locals. + int ret = 0; + + if(!mutex_trylock(&Z80DRV_MUTEX)) + { + pr_alert("z80drv: device busy!\n"); + ret = -EBUSY; + goto out; + } + + //pr_info("z80drv: Device opened\n"); + +out: + return(ret); +} + +// Map shared memory. +// The z80drv allocates on the stack a chunk of memory and control variables which is used to control the Z80 Emulation state +// and provide it with internal 'virtual memory'. This virtual memory is either used as the core Z80 memory or as banked extensions +// to the host DRAM. +// The user space application is able to bind with the shared memory to perform tasks such as load/save of applications. +static int z80drv_mmap(struct file *filp, struct vm_area_struct *vma) +{ + // Locals. + int ret = 0; + struct page *page = NULL; + unsigned long size = (unsigned long)(vma->vm_end - vma->vm_start); + + // Make sure requested size is within range of the Z80 control structure. The kernel may page align it so the size may be bigger than + // the structure. + if(size < sizeof(t_Z80Ctrl) || size > sizeof(t_Z80Ctrl)*2) + { + ret = -EINVAL; + goto out; + } + + // Map the memory and exit. + page = virt_to_page((unsigned long)Z80Ctrl + (vma->vm_pgoff << PAGE_SHIFT)); + ret = remap_pfn_range(vma, vma->vm_start, page_to_pfn(page), size, vma->vm_page_prot); + if (ret != 0) + { + goto out; + } + +out: + return ret; +} + +// Device read. +// This method allows an application which opens the z80drv driver to read data in a stream. It is here for +// possible future use. +static ssize_t z80drv_read(struct file *filep, char *buffer, size_t len, loff_t *offset) +{ + // Locals. + int ret; + + if (len > Z80_VIRTUAL_RAM_SIZE) + { + pr_info("read overflow!\n"); + ret = -EFAULT; + goto out; + } + + if (copy_to_user(buffer, Z80Ctrl, len) == 0) + { + pr_info("z80drv: copy %u char to the user\n", len); + ret = len; + } else + { + ret = -EFAULT; + } + +out: + return ret; +} + +// Device write. +// This method allows an application which opens the z80drv driver to write stream data. It is here for +// possible future use. +static ssize_t z80drv_write(struct file *filep, const char *buffer, size_t len, loff_t *offset) +{ + // Locals. + int ret; + + if (copy_from_user(Z80Ctrl, buffer, len)) + { + pr_err("z80drv: write fault!\n"); + ret = -EFAULT; + goto out; + } + pr_info("z80drv: copy %d char from the user\n", len); + ret = len; + +out: + return ret; +} + +// Function to dump out a given section of the physical host memory. +// +int memoryDump(uint32_t memaddr, uint32_t memsize, uint32_t dispaddr, uint8_t dispwidth) +{ + uint8_t displayWidth = dispwidth; + uint32_t pnt = memaddr; + uint32_t endAddr = memaddr + memsize; + uint32_t addr = dispaddr; + uint8_t data; + uint32_t i = 0; + int result = -1; + char c = 0; + + // If not set, calculate output line width according to connected display width. + // + if(displayWidth == 0) + { + switch(MAX_SCREEN_WIDTH) + { + case 40: + displayWidth = 8; + break; + case 80: + displayWidth = 16; + break; + default: + displayWidth = 32; + break; + } + } + + while (1) + { + printk(KERN_INFO "%08X", addr); // print address + printk(KERN_CONT ": "); + + // print hexadecimal data + for (i=0; i < displayWidth; ) + { + if(pnt+i < endAddr) + { + SPI_SEND32((uint16_t)(pnt+i) << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = pnt+i; + while(CPLD_READY() == 0); + data = READ_CPLD_DATA_IN(); + printk(KERN_CONT "%02X", data); + } + else + printk(KERN_CONT " "); + i++; + + printk(KERN_CONT " "); + } + + // print ascii data + printk(KERN_CONT " |"); + + // print single ascii char + for (i=0; i < displayWidth; i++) + { + SPI_SEND32((uint16_t)(pnt+i) << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = pnt+i; + while(CPLD_READY() == 0); + c = (char)READ_CPLD_DATA_IN(); + if ((pnt+i < endAddr) && (c >= ' ') && (c <= '~')) + printk(KERN_CONT "%c", (char)c); + else + printk(KERN_CONT " "); + } + + printk(KERN_CONT "|\n"); + + // Move on one row. + pnt += displayWidth; + addr += displayWidth; + + // End of buffer, exit the loop. + if(pnt >= (memaddr + memsize)) + { + break; + } + } + + return(result); +} + +// Method to setup a default memory/IO profile. This profile will be changed by the host processing and also can be tweaked +// by the z80ctrl application. +// +void setupMemory(enum Z80_MEMORY_PROFILE mode) +{ + // Locals. + uint32_t idx; + + if(mode == USE_PHYSICAL_RAM) + { + // Initialise the page pointers and memory to use physical RAM. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x8000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + else //if(idx >= 0x8000 && idx < 0xD000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + + // Video RAM labelled as HW as we dont want to cache it. + //else if(idx >= 0xD000 && idx < 0xE000) + // { + // setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + //} else + // { + // setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + // } + } + for(idx=0x0000; idx < 0x10000; idx++) + { + Z80Ctrl->iopage[idx] = idx | IO_TYPE_PHYSICAL_HW; + } + // Cancel refresh as using physical RAM for program automatically refreshes DRAM. + Z80Ctrl->refreshDRAM = 0; + } + else if(mode == USE_VIRTUAL_RAM) + { +#if(TARGET_HOST_MZ2000 == 1) + // Initialise the page pointers and memory to use virtual RAM. + // MZ-2000 comes up in IPL mode where lower 32K is ROM and upper 32K is RAM remapped from 0x0000. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x8000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (Z80Ctrl->lowMemorySwap ? idx - 0x8000 : idx)); + } + } + for(idx=0x0000; idx < 0x10000; idx++) + { + Z80Ctrl->iopage[idx] = idx | IO_TYPE_PHYSICAL_HW; + } + // Enable refresh as using virtual RAM stops refresh of host DRAM. + Z80Ctrl->refreshDRAM = 1; + pr_info("Im here\n"); + } +#endif + + // Enable autorefresh if refreshDRAM is set. + SPI_SEND8(Z80Ctrl->refreshDRAM == 1 ? CPLD_CMD_SET_AUTO_REFRESH : CPLD_CMD_CLEAR_AUTO_REFRESH); + + // Inhibit mode disabled. + Z80Ctrl->inhibitMode = 0; + return; +} + +// IOCTL Method +// This method allows User Space application to control the Z80 CPU and internal functionality of the +// device driver. This is the preferred control method along with the shared memory segment for the driver. +static long int z80drv_ioctl(struct file *file, unsigned cmd, unsigned long arg) +{ + // Locals. + struct ioctlCmd ioctlCmd; + uint16_t idx; + uint32_t tmp[2]; + enum Z80_RUN_STATES currentRunMode; + enum Z80_RUN_STATES nextRunMode; + + // Get current running mode so any operations on the Z80 return it to original mode unless action overrides it. + mutex_lock(&Z80RunModeMutex); currentRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + + switch(cmd) + { + // Basic commands. + case IOCTL_CMD_SEND: + if(copy_from_user(&ioctlCmd, (int32_t *)arg, sizeof(ioctlCmd))) + printk("IOCTL - Couldnt retrieve command!\n"); + else + { + //printk("IOCTL - Command (%08x)\n", ioctlCmd.cmd); + switch(ioctlCmd.cmd) + { + // Command to stop the Z80 CPU and power off. + case IOCTL_CMD_Z80_STOP: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + z80_power(&Z80CPU, FALSE); + Z80_PC(Z80CPU) = 0; + printk("Z80 stopped.\n"); + break; + + // Command to power on and start the Z80 CPU. + case IOCTL_CMD_Z80_START: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_RUNNING; mutex_unlock(&Z80RunModeMutex); + + z80_power(&Z80CPU, TRUE); + printk("Z80 started.\n"); + break; + + // Command to pause the Z80. + case IOCTL_CMD_Z80_PAUSE: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_PAUSE; mutex_unlock(&Z80RunModeMutex); + printk("Z80 paused.\n"); + break; + + // Command to release a paused Z80. + case IOCTL_CMD_Z80_CONTINUE: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_CONTINUE; mutex_unlock(&Z80RunModeMutex); + printk("Z80 running.\n"); + break; + + // Command to perform a CPU reset. + case IOCTL_CMD_Z80_RESET: + // Stop the CPU prior to reset. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + z80_instant_reset(&Z80CPU); + setupMemory(Z80Ctrl->defaultPageMode); + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Reset.\n"); + break; + + // Command to setup the page table to use host memory and physical hardware. + case IOCTL_CMD_USE_HOST_RAM: + // Stop the CPU prior to memory reconfiguration. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80Ctrl->defaultPageMode = USE_PHYSICAL_RAM; + setupMemory(Z80Ctrl->defaultPageMode); + z80_instant_reset(&Z80CPU); + + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Set to use Host Memory.\n"); + break; + + // Command to setup the page table to use virtual memory, only physical hardware is accessed on the host. + case IOCTL_CMD_USE_VIRTUAL_RAM: + // Stop the CPU prior to memory reconfiguration. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80Ctrl->defaultPageMode = USE_VIRTUAL_RAM; + setupMemory(Z80Ctrl->defaultPageMode); + z80_instant_reset(&Z80CPU); + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Set to use Virtual Memory.\n"); + break; + + // Command to synchronise virtual memory to host DRAM. + case IOCTL_CMD_SYNC_TO_HOST_RAM: + // Stop the CPU prior to memory sync. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Copy virtual memory to host DRAM. + for(idx=0x1000; idx < 0xD000; idx++) + { + SPI_SEND32((uint32_t)idx << 16 | Z80Ctrl->memory[idx] << 8 | CPLD_CMD_WRITE_ADDR); + } + + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Host DRAM syncd with Virtual Memory.\n"); + break; + + // Command to dump out host memory. + case IOCTL_CMD_DUMP_MEMORY: + // Need to suspend the Z80 otherwise we will get memory clashes. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_PAUSE; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_PAUSE); + + // Dump out the physical memory address. + memoryDump(ioctlCmd.addr.start, ioctlCmd.addr.end - ioctlCmd.addr.start, ioctlCmd.addr.start, 0); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to set the governor delay to approximate real Z80 cpu frequencies when running in virtual memory. + case IOCTL_CMD_Z80_CPU_FREQ: + switch(ioctlCmd.speed.speedMultiplier) + { + case 2: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_7MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_7MHZ; + break; + + case 4: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_14MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_14MHZ; + break; + + case 8: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_28MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_28MHZ; + break; + + case 16: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_56MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_56MHZ; + break; + + case 32: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_112MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_112MHZ; + break; + + case 64: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_224MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_224MHZ; + break; + + case 128: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_448MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_448MHZ; + break; + + case 1: + default: + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_3_54MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_3_54MHZ; + break; + } + break; + + // Command to set the Z80 CPU Program Counter value. + case IOCTL_CMD_SETPC: + // Stop the CPU prior to PC change. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80_PC(Z80CPU) = ioctlCmd.z80.pc; + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Set PC to %04x\n", ioctlCmd.z80.pc); + break; + + // Method to send adhoc commands to the CPLD, ie for switching active display etc. + case IOCTL_CMD_CPLD_CMD: + // Stop the CPU prior to sending a direct command to the CPLD. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Send the command, small delay then send NOP to retrieve the response. + z80io_SPI_Send32(ioctlCmd.cpld.cmd, &tmp[0]); + udelay(50); + z80io_SPI_Send32(0x00000000, &tmp[0]); + z80io_SPI_Send32(0x00000000, &tmp[1]); + pr_info("CPLD TX:%08x, RX:%08x,%08x\n", ioctlCmd.cpld.cmd, tmp[0], tmp[1]); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of SOM to CPLD SPI tests. + case IOCTL_CMD_SPI_TEST: + // Stop the CPU prior to SPI testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform SPI Tests. + z80io_SPI_Test(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of SOM to CPLD Parallel Bus tests. + case IOCTL_CMD_PRL_TEST: + // Stop the CPU prior to SPI testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform Parallel Bus tests. + z80io_PRL_Test(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of Z80 host memory tests to assess the performance of the SOM->CPLD interface. + case IOCTL_CMD_Z80_MEMTEST: + // Stop the CPU prior to Host memory testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform host memory tests. + z80io_Z80_TestMemory(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + default: + break; + } + } + break; + + default: + printk("IOCTL - Unhandled Command (%08x)\n", ioctlCmd.cmd); + break; + + } + return 0; +} + +// Structure to declare public API methods. +// Standard Linux device driver structure to declare accessible methods within the driver. +static const struct file_operations z80drv_fops = { + .open = z80drv_open, + .read = z80drv_read, + .write = z80drv_write, + .release = z80drv_release, + .mmap = z80drv_mmap, + .unlocked_ioctl = z80drv_ioctl, + .owner = THIS_MODULE, +}; + +// Initialisation. +// This is the entry point into the device driver when loaded into the kernel. +// The method intialises any required hardware (ie. GPIO's, SPI etc), memory and the Z80 +// Emulation. It also allocates the Major and Minor device numbers and sets up the +// device in /dev. +static int __init ModuleInit(void) +{ + // Locals. + int idx; + int ret = 0; + + // Setup the Z80 handlers. + Z80CPU.context = z80_context; + Z80CPU.fetch = z80_fetch; + Z80CPU.fetch_opcode = z80_fetch_opcode; + Z80CPU.read = z80_read; + Z80CPU.write = z80_write; + Z80CPU.nop = z80_nop; + Z80CPU.in = z80_in; + Z80CPU.out = z80_out; + Z80CPU.halt = z80_halt; + Z80CPU.nmia = z80_nmia; + Z80CPU.inta = z80_inta; + Z80CPU.int_fetch = z80_intFetch; + Z80CPU.ld_i_a = z80_ldia; + Z80CPU.ld_r_a = z80_ldra; + Z80CPU.reti = z80_reti; + Z80CPU.retn = z80_retn; + Z80CPU.illegal = z80_illegal; + + mutex_init(&Z80DRV_MUTEX); + + // Get device Major number. + major = register_chrdev(0, DEVICE_NAME, &z80drv_fops); + if (major < 0) { + pr_info("z80drv: fail to register major number!"); + ret = major; + goto initExit; + } + + class = class_create(THIS_MODULE, CLASS_NAME); + if (IS_ERR(class)){ + unregister_chrdev(major, DEVICE_NAME); + pr_info("z80drv: failed to register device class"); + ret = PTR_ERR(class); + goto initExit; + } + + device = device_create(class, NULL, MKDEV(major, 0), NULL, DEVICE_NAME); + if (IS_ERR(device)) { + class_destroy(class); + unregister_chrdev(major, DEVICE_NAME); + ret = PTR_ERR(device); + goto initExit; + } + + // Allocate the Z80 memory to be shared between this kernel space driver and the controlling user space application. + Z80Ctrl = (t_Z80Ctrl *)kmalloc(sizeof(t_Z80Ctrl), GFP_KERNEL); + if (Z80Ctrl == NULL) + { + pr_info("z80drv: failed to allocate memory!"); + ret = -ENOMEM; + goto initExit; + } + + // Initialise the hardware to host interface. + z80io_init(); + + // Initialise the virtual RAM from the HOST DRAM. This is to maintain compatibility as some applications (in my experience) have + // bugs, which Im putting down to not initialising variables. The host DRAM is in a pattern of 0x00..0x00, 0xFF..0xFF repeating + // when first powered on. + for(idx=0; idx < Z80_VIRTUAL_RAM_SIZE; idx++) + { +#if(TARGET_HOST_MZ700 == 1) + if(idx >= 0x1000 && idx < 0xD000) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->memory[idx] = z80io_PRL_Read8(1); + } else + { + Z80Ctrl->memory[idx] = 0x00; + } +#endif +#if(TARGET_HOST_MZ2000 == 1) + if(idx >= 0x8000 && idx < 0x10000) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->memory[idx-0x8000] = z80io_PRL_Read8(1); + } else + { + if(idx >= 0x0000 && idx < 0x8000) + Z80Ctrl->memory[idx+0x8000] = 0x00; + else + Z80Ctrl->memory[idx] = 0x00; + } +#endif + } + +#if(TARGET_HOST_MZ700 == 1) + Z80Ctrl->memory[0x1200] = 0x01; + Z80Ctrl->memory[0x1201] = 0x86; + Z80Ctrl->memory[0x1202] = 0xf2; + Z80Ctrl->memory[0x1203] = 0x3e; + Z80Ctrl->memory[0x1204] = 0x15; + Z80Ctrl->memory[0x1205] = 0x3d; + Z80Ctrl->memory[0x1206] = 0x20; + Z80Ctrl->memory[0x1207] = 0xfd; + Z80Ctrl->memory[0x1208] = 0x0b; + Z80Ctrl->memory[0x1209] = 0x78; + Z80Ctrl->memory[0x120a] = 0xb1; + Z80Ctrl->memory[0x120b] = 0x20; + Z80Ctrl->memory[0x120c] = 0xf6; + Z80Ctrl->memory[0x120d] = 0xc3; + Z80Ctrl->memory[0x120e] = 0x00; + Z80Ctrl->memory[0x120f] = 0x00; +#endif + + // Copy the host BIOS into the Virtual ROM. + for(idx=0; idx < Z80_VIRTUAL_ROM_SIZE; idx++) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->memory[Z80_VIRTUAL_RAM_SIZE+idx] = z80io_PRL_Read8(1); + } + +#if(TARGET_HOST_MZ2000 == 1) + Z80Ctrl->lowMemorySwap = 1; +#endif + + // Setup Refresh so that an automatic refresh mode is performed by the CPLD whilst running in Virtual memory. This is necessary as opcode fetches from + // host memory, by the CPLD, normally performs the refresh and when running in virtual memory, these refresh cycles arent performed. + Z80Ctrl->refreshDRAM = 0; + + // Setup the governor delay, it is the delay per opcode fetch to restrict the Z80 CPU to a given speed. + Z80Ctrl->cpuGovernorDelayROM = INSTRUCTION_DELAY_ROM_3_54MHZ; + Z80Ctrl->cpuGovernorDelayRAM = INSTRUCTION_DELAY_RAM_3_54MHZ; + + // Setup the default Page Mode. This is needed if an event such as a reset occurs which needs to return the page and iotable back to default. + Z80Ctrl->defaultPageMode = USE_VIRTUAL_RAM; + + // Setup memory profile to use internal virtual RAM (SOM kernel RAM rather than HOST DRAM). + setupMemory(Z80Ctrl->defaultPageMode); + + // Initialse run control. + mutex_init(&Z80RunModeMutex); + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + + // Setup the address and port history for communicating addresses to the CPLD. Used to shorten the instruction length to increase latency. + Z80Ctrl->z80PrevAddr = 0xFFFF; + Z80Ctrl->z80PrevPort = 0xFFFF; + + // Initialse hotkey detection variables. + Z80Ctrl->keyportStrobe = 0x00; + Z80Ctrl->keyportShiftCtrl = 0x00; + Z80Ctrl->keyportHotKey = 0x00; + + // PC to start and power on the CPU + Z80_PC(Z80CPU) = 0; + z80_power(&Z80CPU, TRUE); + + // Create thread to run the Z80 cpu. + kthread_z80 = kthread_create(thread_z80, &threadId_z80, "kthread_z80"); + if(kthread_z80 != NULL) + { + printk("kthread - Thread Z80 was created, waking...!\n"); + kthread_bind(kthread_z80, 1); + wake_up_process(kthread_z80); + } + else { + printk("kthread - Thread Z80 could not be created!\n"); + ret = -1; + goto initExit; + } + +initExit: + return ret; +} + +// Exit +// This method is called when the device driver is removed from the kernel with the rmmod command. +// It is responsible for closing and freeing all allocated memory, terminating all threads and removing +// the device from the /dev directory. +static void __exit ModuleExit(void) +{ + // Stop the internal threads. + //printk("kthread - Stop Z80 thread\n"); + kthread_stop(kthread_z80); + + // Return the memory used for the Z80 'virtual memory' and control variables. + kfree(Z80Ctrl); + + // Nothing to be done for the hardware. + + // Cleanup and remove the device. + mutex_destroy(&Z80DRV_MUTEX); + device_destroy(class, MKDEV(major, 0)); + class_unregister(class); + class_destroy(class); + unregister_chrdev(major, DEVICE_NAME); + + //pr_info("z80drv: unregistered!\n"); +} + +module_init(ModuleInit); +module_exit(ModuleExit); diff --git a/software/FusionX/src/driver/MZ2000/z80driver.h b/software/FusionX/src/driver/MZ2000/z80driver.h new file mode 100644 index 000000000..bf622a6da --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80driver.h @@ -0,0 +1,326 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80driver.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Driver +// This file contains the declarations used in the z80drv device driver. +// +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of this driver and in all ways, is compatible with +// the original Z80. +// Copyright: (c) 2019-2022 Philip Smart +// (c) 1999-2022 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80DRIVER_H +#define Z80DRIVER_H + +// Constants. +#define TARGET_HOST_MZ700 0 +#define TARGET_HOST_MZ2000 1 +#define Z80_VIRTUAL_ROM_SIZE 16384 // Sized to maximum ROM which is the MZ-800 ROM. +#define Z80_VIRTUAL_RAM_SIZE (65536 * 8) // (PAGE_SIZE * 2) // max size mmaped to userspace +#define Z80_VIRTUAL_MEMORY_SIZE Z80_VIRTUAL_RAM_SIZE + Z80_VIRTUAL_ROM_SIZE +#define Z80_MEMORY_PAGE_SIZE 16 +#define MAX_SCREEN_WIDTH 132 +#define DEVICE_NAME "z80drv" +#define CLASS_NAME "mogu" + +// Memory and IO page types. Used to create a memory page which maps type of address space to real address space on host or virtual memory. +#define MEMORY_TYPE_VIRTUAL_MASK 0x00FFFFFF +#define MEMORY_TYPE_REAL_MASK 0x0000FFFF +#define IO_TYPE_MASK 0x0000FFFF +#define MEMORY_TYPE_INHIBIT 0x00000000 +#define MEMORY_TYPE_PHYSICAL_RAM 0x80000000 +#define MEMORY_TYPE_PHYSICAL_ROM 0x40000000 +#define MEMORY_TYPE_PHYSICAL_VRAM 0x20000000 +#define MEMORY_TYPE_PHYSICAL_HW 0x10000000 +#define MEMORY_TYPE_VIRTUAL_RAM 0x08000000 +#define MEMORY_TYPE_VIRTUAL_ROM 0x04000000 +#define MEMORY_TYPE_VIRTUAL_HW 0x02000000 +#define IO_TYPE_PHYSICAL_HW 0x80000000 +#define IO_TYPE_VIRTUAL_HW 0x40000000 + + +// Approximate governor delays to regulate emulated CPU speed. +// MZ-700 +#if(TARGET_HOST_MZ700 == 1) +#define INSTRUCTION_DELAY_ROM_3_54MHZ 253 +#define INSTRUCTION_DELAY_ROM_7MHZ 126 +#define INSTRUCTION_DELAY_ROM_14MHZ 63 +#define INSTRUCTION_DELAY_ROM_28MHZ 32 +#define INSTRUCTION_DELAY_ROM_56MHZ 16 +#define INSTRUCTION_DELAY_ROM_112MHZ 8 +#define INSTRUCTION_DELAY_ROM_224MHZ 4 +#define INSTRUCTION_DELAY_ROM_448MHZ 1 +#define INSTRUCTION_DELAY_RAM_3_54MHZ 253 +#define INSTRUCTION_DELAY_RAM_7MHZ 126 +#define INSTRUCTION_DELAY_RAM_14MHZ 63 +#define INSTRUCTION_DELAY_RAM_28MHZ 32 +#define INSTRUCTION_DELAY_RAM_56MHZ 16 +#define INSTRUCTION_DELAY_RAM_112MHZ 8 +#define INSTRUCTION_DELAY_RAM_224MHZ 4 +#define INSTRUCTION_DELAY_RAM_448MHZ 1 +#endif +// MZ-2000 +#if(TARGET_HOST_MZ2000 == 1) +#define INSTRUCTION_DELAY_ROM_3_54MHZ 243 +#define INSTRUCTION_DELAY_ROM_7MHZ 122 +#define INSTRUCTION_DELAY_ROM_14MHZ 61 +#define INSTRUCTION_DELAY_ROM_28MHZ 30 +#define INSTRUCTION_DELAY_ROM_56MHZ 15 +#define INSTRUCTION_DELAY_ROM_112MHZ 7 +#define INSTRUCTION_DELAY_ROM_224MHZ 3 +#define INSTRUCTION_DELAY_ROM_448MHZ 1 +#define INSTRUCTION_DELAY_RAM_3_54MHZ 218 +#define INSTRUCTION_DELAY_RAM_7MHZ 112 +#define INSTRUCTION_DELAY_RAM_14MHZ 56 +#define INSTRUCTION_DELAY_RAM_28MHZ 28 +#define INSTRUCTION_DELAY_RAM_56MHZ 14 +#define INSTRUCTION_DELAY_RAM_112MHZ 7 +#define INSTRUCTION_DELAY_RAM_224MHZ 3 +#define INSTRUCTION_DELAY_RAM_448MHZ 1 +#endif + +// IOCTL commands. Passed from user space using the IOCTL method to command the driver to perform an action. +#define IOCTL_CMD_Z80_STOP 's' +#define IOCTL_CMD_Z80_START 'S' +#define IOCTL_CMD_Z80_PAUSE 'P' +#define IOCTL_CMD_Z80_RESET 'R' +#define IOCTL_CMD_Z80_CONTINUE 'C' +#define IOCTL_CMD_USE_HOST_RAM 'x' +#define IOCTL_CMD_USE_VIRTUAL_RAM 'X' +#define IOCTL_CMD_DUMP_MEMORY 'M' +#define IOCTL_CMD_Z80_CPU_FREQ 'F' +#define IOCTL_CMD_CPLD_CMD 'z' +#define IOCTL_CMD_SEND _IOW('c', 'c', int32_t *) +#define IOCTL_CMD_SETPC _IOW('p', 'p', int32_t *) +#define IOCTL_CMD_SYNC_TO_HOST_RAM 'V' +#define IOCTL_CMD_SPI_TEST '1' +#define IOCTL_CMD_PRL_TEST '2' +#define IOCTL_CMD_Z80_MEMTEST '3' + + + +// Chip Select map MZ80K-MZ700. +// +// 0000 - 0FFF = CS_ROMni : R/W : MZ80K/A/700 = Monitor ROM or RAM (MZ80A rom swap) +// 1000 - CFFF = CS_RAMni : R/W : MZ80K/A/700 = RAM +// C000 - CFFF = CS_ROMni : R/W : MZ80A = Monitor ROM (MZ80A rom swap) +// D000 - D7FF = CS_VRAMni : R/W : MZ80K/A/700 = VRAM +// D800 - DFFF = CS_VRAMni : R/W : MZ700 = Colour VRAM (MZ700) +// E000 - E003 = CS_8255n : R/W : MZ80K/A/700 = 8255 +// E004 - E007 = CS_8254n : R/W : MZ80K/A/700 = 8254 +// E008 - E00B = CS_LS367n : R/W : MZ80K/A/700 = LS367 +// E00C - E00F = CS_ESWPn : R : MZ80A = Memory Swap (MZ80A) +// E010 - E013 = CS_ESWPn : R : MZ80A = Reset Memory Swap (MZ80A) +// E014 = CS_E5n : R/W : MZ80A/700 = Normal CRT display (in Video Controller) +// E015 = CS_E6n : R/W : MZ80A/700 = Reverse CRT display (in Video Controller) +// E200 - E2FF = : R/W : MZ80A/700 = VRAM roll up/roll down. +// E800 - EFFF = : R/W : MZ80K/A/700 = User ROM socket or DD Eprom (MZ700) +// F000 - F7FF = : R/W : MZ80K/A/700 = Floppy Disk interface. +// F800 - FFFF = : R/W : MZ80K/A/700 = Floppy Disk interface. +// +// Chip Select map MZ800 +// +// FC - FF = CS_PIOn : R/W : MZ800/MZ1500 = Z80 PIO Printer Interface +// F2 = CS_PSG0n : W : MZ800/MZ1500 = Programable Sound Generator, MZ-800 = Mono, MZ-1500 = Left Channel +// F3 = CS_PSG1n : W : MZ1500 = Programable Sound Generator, MZ-1500 = Right Channel +// E9 = CS_PSG(X)n: W : MZ1500 = Simultaneous write to both PSG's. +// F0 - F1 = CS_JOYSTK : R : MZ800 = Joystick 1 and 2 +// CC = CS_GWF : W : MZ800 = CRTC GWF Write format Register +// CD = CS_GRF : W : MZ800 = CRTC GRF Read format Register +// CE = CS_GDMD : W : MZ800 = CRTC GDMD Mode Register +// CF = CS_GCRTC : W : MZ800 = CRTC GCRTC Control Register +// D4 - D7 = CS +// D000 - DFFF + +// MZ700/MZ800 memory mode switch? +// +// MZ-700 MZ-800 +// |0000:0FFF|1000:1FFF|1000:CFFF|C000:CFFF|D000:FFFF |0000:7FFF|1000:1FFF|2000:7FFF|8000:BFFF|C000:CFFF|C000:DFFF|E000:FFFF +// -------------------------------------------------- ---------------------------------------------------------------------- +// OUT 0xE0 = |DRAM | | | | |DRAM | | | | | | +// OUT 0xE1 = | | | | |DRAM | | | | | | |DRAM +// OUT 0xE2 = |MONITOR | | | | |MONITOR | | | | | | +// OUT 0xE3 = | | | | |Memory Mapped I/O | | | | | | |Upper MONITOR ROM +// OUT 0xE4 = |MONITOR | |DRAM | |Memory Mapped I/O |MONITOR |CGROM |DRAM |VRAM | |DRAM |Upper MONITOR ROM +// OUT 0xE5 = | | | | |Inhibit | | | | | | |Inhibit +// OUT 0xE6 = | | | | | | | | | | | | +// IN 0xE0 = | |CGROM* | |VRAM* | | |CGROM | |VRAM | | | +// IN 0xE1 = | |DRAM | |DRAM | | | | |DRAM | | | +// +// = Return to the state prior to the complimentary command being invoked. +// * = MZ-800 host only. + +// Macros to lookup and test to see if a given memory block or IO byte is of a given type. Also macros to read/write to the memory block and IO byte. +#define MEMORY_BLOCK_GRANULARITY 0x800 +#define MEMORY_BLOCK_SLOTS (0x10000 / MEMORY_BLOCK_GRANULARITY) +#define MEMORY_BLOCK_MASK (0x10000 - MEMORY_BLOCK_GRANULARITY) +#define MEMORY_BLOCK_SHIFT 11 +#define getPageData(a) (Z80Ctrl->page[(a & 0xF800) >> MEMORY_BLOCK_SHIFT]) +#define getIOPageData(a) (Z80Ctrl->iopage[(a & 0xFFFF]) +#define getPageType(a, mask) (getPageData(a) & mask) +#define getPageAddr(a, mask) ((getPageData(a) & mask) + (a & (MEMORY_BLOCK_GRANULARITY-1))) +#define getIOPageType(a, mask) (getIOPageData(a) & mask) +#define getIOPageAddr(a, mask) (getIOPageData(a) & mask) +#define realAddress(a) (Z80Ctrl->page[getPageAddr(a, MEMORY_TYPE_REAL_MASK)]) +#define realPort(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_MASK) +#define isPhysicalRAM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_RAM)) +#define isPhysicalVRAM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_VRAM)) +#define isPhysicalROM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_ROM)) +#define isPhysicalMemory(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_ROM | MEMORY_TYPE_PHYSICAL_RAM | MEMORY_TYPE_PHYSICAL_VRAM))]) +#define isPhysicalHW(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_HW)) +#define isPhysical(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_HW | MEMORY_TYPE_PHYSICAL_ROM | MEMORY_TYPE_PHYSICAL_RAM | MEMORY_TYPE_PHYSICAL_VRAM))) +#define isPhysicalIO(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_PHYSICAL_HW) +#define isVirtualRAM(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_RAM)) +#define isVirtualROM(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_ROM)) +#define isVirtualMemory(a) (getPageType(a, (MEMORY_TYPE_VIRTUAL_ROM | MEMORY_TYPE_VIRTUAL_RAM))) +#define isVirtualHW(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_HW)) +#define isVirtualIO(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_VIRTUAL_HW) +#define isHW(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_HW | MEMORY_TYPE_VIRTUAL_HW))) +#define readVirtualRAM(a) (Z80Ctrl->memory[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) ]) +#define readVirtualROM(a) (Z80Ctrl->memory[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) + Z80_VIRTUAL_RAM_SIZE ]) +#define writeVirtualRAM(a, d) { Z80Ctrl->memory[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) ] = d; } +#define setMemoryType(_block_,_type_,_addr_) { Z80Ctrl->page[_block_] = _type_ | _addr_; } +#define backupMemoryType(_block_) { Z80Ctrl->shadowPage[_block_] = Z80Ctrl->page[_block_]; } +#define restoreMemoryType(_block_) { Z80Ctrl->page[_block_] = Z80Ctrl->shadowPage[_block_]; } + +#define IO_ADDR_E0 0xE0 +#define IO_ADDR_E1 0xE1 +#define IO_ADDR_E2 0xE2 +#define IO_ADDR_E3 0xE3 +#define IO_ADDR_E4 0xE4 +#define IO_ADDR_E5 0xE5 +#define IO_ADDR_E6 0xE6 +#define IO_ADDR_E7 0xE7 +#define IO_ADDR_E8 0xE8 +#define IO_ADDR_E9 0xE9 +#define IO_ADDR_EA 0xEA +#define IO_ADDR_EB 0xEB + + +enum Z80_RUN_STATES { + Z80_STOP = 0x00, + Z80_STOPPED = 0x01, + Z80_PAUSE = 0x02, + Z80_PAUSED = 0x03, + Z80_CONTINUE = 0x04, + Z80_RUNNING = 0x05, +}; +enum Z80_MEMORY_PROFILE { + USE_PHYSICAL_RAM = 0x00, + USE_VIRTUAL_RAM = 0x01 +}; + +typedef struct { + // Main memory, linear but indexed as though it were banks in 1K pages. + uint8_t memory[Z80_VIRTUAL_MEMORY_SIZE]; + + // Page pointer map. + // + // Each pointer points to a byte or block of bytes in the Z80 Memory frame, 64K Real + Banked. + // This is currently set at a block of size 0x800 per memory pointer for the MZ-700. + // The LSB of the pointer is a direct memory index to a byte or block of bytes, the upper byte of the pointer indicates type of memory space. + // 0x80 - physical host RAM + // 0x40 - physical host ROM + // 0x20 - physical host VRAM + // 0x10 - physical host hardware + // 0x08 - virtual host RAM + // 0x04 - virtual host ROM + // 0x02 - virtual host hardware + // 16bit Input Address -> map -> Pointer to 24bit memory address + type flag. + // -> Pointer+ to 24bit memory address + type flag. + uint32_t page[MEMORY_BLOCK_SLOTS]; + uint32_t shadowPage[MEMORY_BLOCK_SLOTS]; + + // I/O Page map. + // + // This is a map to indicate the use of the I/O page and allow any required remapping. + // <0x80>FF - physical host hardware + // <0x40>FF - virtual host hardware + // 16bit Input Address -> map -> Actual 16bit address to use + type flag. + uint32_t iopage[65536]; + + // Default page mode configured. This value reflects the default page and iotable map. + uint8_t defaultPageMode; + + // Refresh DRAM mode. 1 = Refresh, 0 = No refresh. Only applicable when running code in virtual Kernel RAM. + uint8_t refreshDRAM; + + // Inhibit mode is where certain memory ranges are inhibitted. The memory page is set to inhibit and this flag + // blocks actions which arent allowed during inhibit. + uint8_t inhibitMode; + + // Address caching. Used to minimise instruction length sent to CPLD. + uint16_t z80PrevAddr; + uint16_t z80PrevPort; + +#if(TARGET_HOST_MZ2000 == 1) + uint8_t lowMemorySwap; +#endif + + // Keyboard strobe and data. Required to detect hotkey press. + uint8_t keyportStrobe; + uint8_t keyportShiftCtrl; + uint8_t keyportHotKey; + + // Governor is the delay in a 32bit loop per Z80 opcode, used to govern execution speed when using virtual memory. + // This mechanism will eventually be tied into the M/T-state calculation for a more precise delay, but at the moment, + // with the Z80 assigned to an isolated CPU, it allows time sensitive tasks such as the tape recorder to work. + // The lower the value the faster the CPU speed. Two values are present as the optimiser, seeing ROM code not changing + // is quicker than RAM (both are in the same kernel memory) as a pointer calculation needs to be made. + uint32_t cpuGovernorDelayROM; + uint32_t cpuGovernorDelayRAM; +} t_Z80Ctrl; + +// IOCTL structure for passing data from user space to driver to perform commands. +// +struct z80_addr { + uint32_t start; + uint32_t end; + uint32_t size; +}; +struct z80_ctrl { + uint16_t pc; +}; +struct speed { + uint32_t speedMultiplier; +}; +struct cpld_ctrl { + uint32_t cmd; +}; +struct ioctlCmd { + int32_t cmd; + union { + struct z80_addr addr; + struct z80_ctrl z80; + struct speed speed; + struct cpld_ctrl cpld; + }; +}; + + +// Prototypes. +void setupMemory(enum Z80_MEMORY_PROFILE mode); + + +#endif diff --git a/software/FusionX/src/driver/MZ2000/z80io.c b/software/FusionX/src/driver/MZ2000/z80io.c new file mode 100644 index 000000000..08286199d --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80io.c @@ -0,0 +1,428 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface +// This file contains the methods used in interfacing the SOM to the Z80 socket +// and host hardware via a CPLD. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + +//#include +//#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" + +#include +#include +#include +#include + +//------------------------------------------------------------------------------------------------------------------------------- +// +// User space driver access. +// +//------------------------------------------------------------------------------------------------------------------------------- + + + +// Initialise the SOM hardware used to communicate with the z80 socket and host hardware. +// The SOM interfaces to a CPLD which provides voltage level translation and also encapsulates the Z80 timing cycles as recreating +// them within the SOM is much more tricky. +// +// As this is an embedded device and performance/latency are priorities, minimal structured code is used to keep call stack and +// generated code to a mimimum without relying on the optimiser. +int z80io_init(void) +{ + // Locals. + int ret = 0; + + // Initialise GPIO. We call the HAL api to minimise time but for actual bit set/reset and read we go directly to registers to save time, increase throughput and minimise latency. + // Initialise the HAL. + MHal_GPIO_Init(); + + // Set the pads as GPIO devices. The HAL takes care of allocating and deallocating the padmux resources. + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_0); // Word (16bit) bidirectional bus. Default is read with data set. + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_1); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_2); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_3); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_4); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_5); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_6); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_7); + MHal_GPIO_Pad_Set(PAD_Z80IO_HIGH_BYTE); + //MHal_GPIO_Pad_Set(PAD_GPIO8); // SPIO 4wire control lines setup by the spidev driver but controlled directly in this driver. + //MHal_GPIO_Pad_Set(PAD_GPIO9); + //MHal_GPIO_Pad_Set(PAD_GPIO10); + //MHal_GPIO_Pad_Set(PAD_GPIO11); + MHal_GPIO_Pad_Set(PAD_Z80IO_READY); + MHal_GPIO_Pad_Set(PAD_Z80IO_LTSTATE); + MHal_GPIO_Pad_Set(PAD_Z80IO_BUSRQ); + MHal_GPIO_Pad_Set(PAD_Z80IO_BUSACK); + MHal_GPIO_Pad_Set(PAD_Z80IO_INT); + MHal_GPIO_Pad_Set(PAD_Z80IO_NMI); + MHal_GPIO_Pad_Set(PAD_Z80IO_WAIT); + MHal_GPIO_Pad_Set(PAD_Z80IO_RESET); + MHal_GPIO_Pad_Set(PAD_Z80IO_RSV1); +#ifdef NOTNEEDED + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_0); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_1); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_2); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_3); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_4); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_5); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_6); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_7); + MHal_GPIO_Pad_Set(PAD_Z80IO_WRITE); +#endif + + // Set required input pads. + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_0); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_1); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_2); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_3); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_4); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_5); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_6); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_7); + MHal_GPIO_Pad_Odn(PAD_Z80IO_READY); + MHal_GPIO_Pad_Odn(PAD_Z80IO_LTSTATE); + MHal_GPIO_Pad_Odn(PAD_Z80IO_BUSRQ); + MHal_GPIO_Pad_Odn(PAD_Z80IO_BUSACK); + MHal_GPIO_Pad_Odn(PAD_Z80IO_INT); + MHal_GPIO_Pad_Odn(PAD_Z80IO_NMI); + MHal_GPIO_Pad_Odn(PAD_Z80IO_WAIT); + MHal_GPIO_Pad_Odn(PAD_Z80IO_RESET); + MHal_GPIO_Pad_Odn(PAD_Z80IO_RSV1); + + // Set required output pads. +#ifdef NOTNEEDED + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_0); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_1); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_2); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_3); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_4); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_5); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_6); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_7); + MHal_GPIO_Pad_Oen(PAD_Z80IO_WRITE); + MHal_GPIO_Pull_High(PAD_Z80IO_WRITE); +#endif + + // Control signals. + MHal_GPIO_Pad_Oen(PAD_Z80IO_HIGH_BYTE); + MHal_GPIO_Pull_High(PAD_Z80IO_HIGH_BYTE); + + // Setup the MSPI0 device. + // + // Setup control, interrupts are not used. + MSPI_WRITE(MSPI_CTRL_OFFSET, MSPI_CPU_CLOCK_1_2 | MSPI_CTRL_CPOL_LOW | MSPI_CTRL_CPHA_HIGH | MSPI_CTRL_RESET | MSPI_CTRL_ENABLE_SPI); + + // Setup LSB First mode. + MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, 0x0); + + // Setup clock. + CLK_WRITE(MSPI0_CLK_CFG, 0x1100) + + // Setup the frame size (all buffers to 8bits). + MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xfff); + MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+1, 0xfff); + MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xfff); + MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+1, 0xfff); + + // Setup Chip Selects to inactive. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Switch Video and Audio to host. + z80io_SPI_Send16(0x00f0, NULL); + + return ret; +} + + +//-------------------------------------------------------- +// Parallel bus Methods. +//-------------------------------------------------------- + +// Methods to read data from the parallel bus. +// The CPLD returns status and Z80 data on the 8bit bus as it is marginally quicker than retrieving it over the SPI bus. +// +inline uint8_t z80io_PRL_Read8(uint8_t dataFlag) +{ + // Locals. + uint8_t result = 0; + + // Byte according to flag. + if(dataFlag) + SET_CPLD_READ_DATA() + else + SET_CPLD_READ_STATUS() + + // Read the input registers and set value accordingly. + result = READ_CPLD_DATA_IN(); + + // Return 16bit value read from CPLD. + return(result); +} + +inline uint16_t z80io_PRL_Read16(void) +{ + // Locals. + uint16_t result = 0; + + // Low byte first. + CLEAR_CPLD_HIGH_BYTE(); + + // Read the input registers and set value accordingly. + result = (uint16_t)READ_CPLD_DATA_IN(); + + // High byte next. + SET_CPLD_HIGH_BYTE(); + + // Read the input registers and set value accordingly. + result |= (uint16_t)(READ_CPLD_DATA_IN() << 8); + + // Return 16bit value read from CPLD. + return(result); +} + + +// Parallel Bus methods were tried and tested but due to the GPIO bits being controlled by individual registers per bit, the setup time was longer +// than the transmission time of SPI. These methods are thus deprecated and a fusion of SPI and 8bit parallel is now used. +#ifdef NOTNEEDED +inline uint8_t z80io_PRL_Send8(uint8_t txData) +{ + // Locals. + // + + // Low byte only. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE].r_out) &= (~gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out); + + // Setup data. + if(txData & 0x0080) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x0040) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x0020) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x0010) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0008) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0004) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0002) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0001) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + return(0); +} + +inline uint8_t z80io_PRL_Send16(uint16_t txData) +{ + // Locals. + // + + // Low byte first. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE].r_out) &= (~gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out); + + // Setup data. + if(txData & 0x0080) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x0040) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x0020) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x0010) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0008) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0004) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0002) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0001) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + // High byte next. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + + // Setup high byte. + if(txData & 0x8000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x4000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x2000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x1000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0800) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0400) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0200) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0100) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + return(0); +} +#endif + + +//-------------------------------------------------------- +// SPI Methods. +//-------------------------------------------------------- + +// Methods to send 8,16 or 32 bits. Each method is seperate to minimise logic and execution time, 8bit being most sensitive. +// Macros have also been defined for inline inclusion which dont read back the response data. +// +uint8_t z80io_SPI_Send8(uint8_t txData, uint8_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)txData); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 1); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = (uint8_t)MSPI_READ(MSPI_FULL_DEPLUX_RD00); + + // Done. + return(timeout == 0); +} +uint8_t z80io_SPI_Send16(uint16_t txData, uint16_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, txData); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 2); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = MSPI_READ(MSPI_FULL_DEPLUX_RD00); + + // Done. + return(timeout == 0); +} +uint8_t z80io_SPI_Send32(uint32_t txData, uint32_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)txData); + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)(txData >> 16)); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = (uint32_t)(MSPI_READ(MSPI_FULL_DEPLUX_RD00) | (MSPI_READ(MSPI_FULL_DEPLUX_RD02) << 16)); + + // Done. + return(timeout == 0); +} + +//-------------------------------------------------------- +// Test Methods. +//-------------------------------------------------------- +#ifdef INCLUDE_TEST_METHODS +#include "z80io_test.c" +#else +uint8_t z80io_Z80_TestMemory(void) +{ + pr_info("Z80 Test Memory functionality not built-in.\n"); + return(0); +} +uint8_t z80io_SPI_Test(void) +{ + pr_info("SPI Test functionality not built-in.\n"); + return(0); +} +uint8_t z80io_PRL_Test(void) +{ + pr_info("Parallel Bus Test functionality not built-in.\n"); + return(0); +} +#endif diff --git a/software/FusionX/src/driver/MZ2000/z80io.h b/software/FusionX/src/driver/MZ2000/z80io.h new file mode 100755 index 000000000..9e5c1b0f2 --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80io.h @@ -0,0 +1,483 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface +// This file contains the declarations used in interfacing the SOM to the Z80 socket +// and host hardware via a CPLD. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80IO_H +#define Z80IO_H + +#ifdef __cplusplus + extern "C" { +#endif + +// Definitions to control compilation. +#define INCLUDE_TEST_METHODS 1 + +// CPLD Commands. +#define CPLD_CMD_FETCH_ADDR 0x10 +#define CPLD_CMD_FETCH_ADDR_P1 0x11 +#define CPLD_CMD_FETCH_ADDR_P2 0x12 +#define CPLD_CMD_FETCH_ADDR_P3 0x13 +#define CPLD_CMD_FETCH_ADDR_P4 0x14 +#define CPLD_CMD_FETCH_ADDR_P5 0x15 +#define CPLD_CMD_FETCH_ADDR_P6 0x16 +#define CPLD_CMD_FETCH_ADDR_P7 0x17 +#define CPLD_CMD_WRITE_ADDR 0x18 +#define CPLD_CMD_WRITE_ADDR_P1 0x19 +#define CPLD_CMD_WRITE_ADDR_P2 0x1A +#define CPLD_CMD_WRITE_ADDR_P3 0x1B +#define CPLD_CMD_WRITE_ADDR_P4 0x1C +#define CPLD_CMD_WRITE_ADDR_P5 0x1D +#define CPLD_CMD_WRITE_ADDR_P6 0x1E +#define CPLD_CMD_WRITE_ADDR_P7 0x1F +#define CPLD_CMD_READ_ADDR 0x20 +#define CPLD_CMD_READ_ADDR_P1 0x21 +#define CPLD_CMD_READ_ADDR_P2 0x22 +#define CPLD_CMD_READ_ADDR_P3 0x23 +#define CPLD_CMD_READ_ADDR_P4 0x24 +#define CPLD_CMD_READ_ADDR_P5 0x25 +#define CPLD_CMD_READ_ADDR_P6 0x26 +#define CPLD_CMD_READ_ADDR_P7 0x27 +#define CPLD_CMD_WRITEIO_ADDR 0x28 +#define CPLD_CMD_WRITEIO_ADDR_P1 0x29 +#define CPLD_CMD_WRITEIO_ADDR_P2 0x2A +#define CPLD_CMD_WRITEIO_ADDR_P3 0x2B +#define CPLD_CMD_WRITEIO_ADDR_P4 0x2C +#define CPLD_CMD_WRITEIO_ADDR_P5 0x2D +#define CPLD_CMD_WRITEIO_ADDR_P6 0x2E +#define CPLD_CMD_WRITEIO_ADDR_P7 0x2F +#define CPLD_CMD_READIO_ADDR 0x30 +#define CPLD_CMD_READIO_ADDR_P1 0x31 +#define CPLD_CMD_READIO_ADDR_P2 0x32 +#define CPLD_CMD_READIO_ADDR_P3 0x33 +#define CPLD_CMD_READIO_ADDR_P4 0x34 +#define CPLD_CMD_READIO_ADDR_P5 0x35 +#define CPLD_CMD_READIO_ADDR_P6 0x36 +#define CPLD_CMD_READIO_ADDR_P7 0x37 +#define CPLD_CMD_HALT 0x50 +#define CPLD_CMD_REFRESH 0x51 +#define CPLD_CMD_SET_SIGROUP1 0xF0 +#define CPLD_CMD_SET_AUTO_REFRESH 0xF1 +#define CPLD_CMD_CLEAR_AUTO_REFRESH 0xF2 +#define CPLD_CMD_SET_SPI_LOOPBACK 0xFE +#define CPLD_CMD_NOP1 0x00 +#define CPLD_CMD_NOP2 0xFF + + +// Pad numbers for using the MHal GPIO library. +#define PAD_Z80IO_IN_DATA_0 PAD_GPIO0 +#define PAD_Z80IO_IN_DATA_1 PAD_GPIO1 +#define PAD_Z80IO_IN_DATA_2 PAD_GPIO2 +#define PAD_Z80IO_IN_DATA_3 PAD_GPIO3 +#define PAD_Z80IO_IN_DATA_4 PAD_GPIO4 +#define PAD_Z80IO_IN_DATA_5 PAD_GPIO5 +#define PAD_Z80IO_IN_DATA_6 PAD_GPIO6 +#define PAD_Z80IO_IN_DATA_7 PAD_GPIO7 +#define PAD_SPIO_0 PAD_GPIO8 +#define PAD_SPIO_1 PAD_GPIO9 +#define PAD_SPIO_2 PAD_GPIO10 +#define PAD_SPIO_3 PAD_GPIO11 +#define PAD_Z80IO_HIGH_BYTE PAD_SAR_GPIO2 // Byte requiured, 0 = Low Byte, 1 = High Byte. +#define PAD_Z80IO_READY PAD_GPIO12 +#define PAD_Z80IO_LTSTATE PAD_PM_IRIN // IRIN +#define PAD_Z80IO_BUSRQ PAD_GPIO13 +#define PAD_Z80IO_BUSACK PAD_GPIO14 +#define PAD_Z80IO_INT PAD_UART0_RX // GPIO47 +#define PAD_Z80IO_NMI PAD_UART0_TX // GPIO48 +#define PAD_Z80IO_WAIT PAD_HSYNC_OUT // GPIO85 +#define PAD_Z80IO_RESET PAD_VSYNC_OUT // GPIO86 +#define PAD_Z80IO_RSV1 PAD_SATA_GPIO // GPIO90 + +// Physical register addresses. +#define PAD_Z80IO_IN_DATA_0_ADDR 0x103C00 +#define PAD_Z80IO_IN_DATA_1_ADDR 0x103C02 +#define PAD_Z80IO_IN_DATA_2_ADDR 0x103C04 +#define PAD_Z80IO_IN_DATA_3_ADDR 0x103C06 +#define PAD_Z80IO_IN_DATA_4_ADDR 0x103C08 +#define PAD_Z80IO_IN_DATA_5_ADDR 0x103C0A +#define PAD_Z80IO_IN_DATA_6_ADDR 0x103C0C +#define PAD_Z80IO_IN_DATA_7_ADDR 0x103C0E +#define PAD_SPIO_0_ADDR 0x103C10 +#define PAD_SPIO_1_ADDR 0x103C12 +#define PAD_SPIO_2_ADDR 0x103C14 +#define PAD_SPIO_3_ADDR 0x103C16 +#define PAD_Z80IO_HIGH_BYTE_ADDR 0x1425 +#define PAD_Z80IO_READY_ADDR 0x103C18 +#define PAD_Z80IO_LTSTATE_ADDR 0xF28 // IRIN +#define PAD_Z80IO_BUSRQ_ADDR 0x103C1A +#define PAD_Z80IO_BUSACK_ADDR 0x103C1C +#define PAD_Z80IO_INT_ADDR 0x103C30 // GPIO47 +#define PAD_Z80IO_NMI_ADDR 0x103C32 // GPIO48 +#define PAD_Z80IO_WAIT_ADDR 0x103C80 // GPIO85 +#define PAD_Z80IO_RESET_ADDR 0x103C82 // GPIO86 +#define PAD_Z80IO_RSV1_ADDR 0x103C8A // GPIO90 + +#ifdef NOTNEEDED +#define PAD_Z80IO_OUT_DATA_0 PAD_GPIO12 +#define PAD_Z80IO_OUT_DATA_1 PAD_GPIO13 +#define PAD_Z80IO_OUT_DATA_2 PAD_GPIO14 +#define PAD_Z80IO_OUT_DATA_3 PAD_UART0_RX // GPIO47 +#define PAD_Z80IO_OUT_DATA_4 PAD_UART0_TX // GPIO48 +#define PAD_Z80IO_OUT_DATA_5 PAD_HSYNC_OUT // GPIO85 +#define PAD_Z80IO_OUT_DATA_6 PAD_VSYNC_OUT // GPIO86 +#define PAD_Z80IO_OUT_DATA_7 PAD_SATA_GPIO // GPIO90 +#define PAD_Z80IO_WRITE PAD_PM_IRIN // Write data clock. +#endif + +//------------------------------------------------------------------------------------------------- +// The definitions below come from SigmaStar kernel drivers. No header file exists hence the +// duplication. +//------------------------------------------------------------------------------------------------- + +#define SUPPORT_SPI_1 0 +#define MAX_SUPPORT_BITS 16 + +#define BANK_TO_ADDR32(b) (b<<9) +#define BANK_SIZE 0x200 + +#define MS_BASE_REG_RIU_PA 0x1F000000 +#define gChipBaseAddr 0xFD203C00 +#define gPmSleepBaseAddr 0xFD001C00 +#define gSarBaseAddr 0xFD002800 +#define gRIUBaseAddr 0xFD000000 +#define gMOVDMAAddr 0xFD201600 +#define gClkBaseAddr 0xFD207000 +#define gMspBaseAddr 0xfd222000 + +#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) + + +#define MSPI0_BANK_ADDR 0x1110 +#define MSPI1_BANK_ADDR 0x1111 +#define CLK__BANK_ADDR 0x1038 +#define CHIPTOP_BANK_ADDR 0x101E +#define MOVDMA_BANK_ADDR 0x100B + +#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) +#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) +#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) +#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) + +//------------------------------------------------------------------------------------------------- +// Hardware Register Capability +//------------------------------------------------------------------------------------------------- +#define MSPI_WRITE_BUF_OFFSET 0x40 +#define MSPI_READ_BUF_OFFSET 0x44 +#define MSPI_WBF_SIZE_OFFSET 0x48 +#define MSPI_RBF_SIZE_OFFSET 0x48 + // read/ write buffer size +#define MSPI_RWSIZE_MASK 0xFF +#define MSPI_RSIZE_BIT_OFFSET 0x8 +#define MAX_READ_BUF_SIZE 0x8 +#define MAX_WRITE_BUF_SIZE 0x8 +// CLK config +#define MSPI_CTRL_OFFSET 0x49 +#define MSPI_CLK_CLOCK_OFFSET 0x49 +#define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 +#define MSPI_CLK_CLOCK_MASK 0xFF +#define MSPI_CLK_PHASE_MASK 0x40 +#define MSPI_CLK_PHASE_BIT_OFFSET 0x06 +#define MSPI_CLK_POLARITY_MASK 0x80 +#define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 +#define MSPI_CLK_PHASE_MAX 0x1 +#define MSPI_CLK_POLARITY_MAX 0x1 +#define MSPI_CLK_CLOCK_MAX 0x7 +#define MSPI_CTRL_CPOL_LOW 0x00 +#define MSPI_CTRL_CPOL_HIGH 0x80 +#define MSPI_CTRL_CPHA_LOW 0x00 +#define MSPI_CTRL_CPHA_HIGH 0x40 +#define MSPI_CTRL_3WIRE 0x10 +#define MSPI_CTRL_INTEN 0x04 +#define MSPI_CTRL_RESET 0x02 +#define MSPI_CTRL_ENABLE_SPI 0x01 +// DC config +#define MSPI_DC_MASK 0xFF +#define MSPI_DC_BIT_OFFSET 0x08 +#define MSPI_DC_TR_START_OFFSET 0x4A +#define MSPI_DC_TRSTART_MAX 0xFF +#define MSPI_DC_TR_END_OFFSET 0x4A +#define MSPI_DC_TREND_MAX 0xFF +#define MSPI_DC_TB_OFFSET 0x4B +#define MSPI_DC_TB_MAX 0xFF +#define MSPI_DC_TRW_OFFSET 0x4B +#define MSPI_DC_TRW_MAX 0xFF +// Frame Config +#define MSPI_FRAME_WBIT_OFFSET 0x4C +#define MSPI_FRAME_RBIT_OFFSET 0x4E +#define MSPI_FRAME_BIT_MAX 0x07 +#define MSPI_FRAME_BIT_MASK 0x07 +#define MSPI_FRAME_BIT_FIELD 0x03 +#define MSPI_LSB_FIRST_OFFSET 0x50 +#define MSPI_TRIGGER_OFFSET 0x5A +#define MSPI_DONE_OFFSET 0x5B +#define MSPI_DONE_CLEAR_OFFSET 0x5C +#define MSPI_CHIP_SELECT_OFFSET 0x5F +#define MSPI_CS1_DISABLE 0x01 +#define MSPI_CS1_ENABLE 0x00 +#define MSPI_CS2_DISABLE 0x02 +#define MSPI_CS2_ENABLE 0x00 +#define MSPI_CS3_DISABLE 0x04 +#define MSPI_CS3_ENABLE 0x00 +#define MSPI_CS4_DISABLE 0x08 +#define MSPI_CS4_ENABLE 0x00 +#define MSPI_CS5_DISABLE 0x10 +#define MSPI_CS5_ENABLE 0x00 +#define MSPI_CS6_DISABLE 0x20 +#define MSPI_CS6_ENABLE 0x00 +#define MSPI_CS7_DISABLE 0x40 +#define MSPI_CS7_ENABLE 0x00 +#define MSPI_CS8_DISABLE 0x80 +#define MSPI_CS8_ENABLE 0x00 + +#define MSPI_FULL_DEPLUX_RD_CNT (0x77) +#define MSPI_FULL_DEPLUX_RD00 (0x78) +#define MSPI_FULL_DEPLUX_RD01 (0x78) +#define MSPI_FULL_DEPLUX_RD02 (0x79) +#define MSPI_FULL_DEPLUX_RD03 (0x79) +#define MSPI_FULL_DEPLUX_RD04 (0x7a) +#define MSPI_FULL_DEPLUX_RD05 (0x7a) +#define MSPI_FULL_DEPLUX_RD06 (0x7b) +#define MSPI_FULL_DEPLUX_RD07 (0x7b) + +#define MSPI_FULL_DEPLUX_RD08 (0x7c) +#define MSPI_FULL_DEPLUX_RD09 (0x7c) +#define MSPI_FULL_DEPLUX_RD10 (0x7d) +#define MSPI_FULL_DEPLUX_RD11 (0x7d) +#define MSPI_FULL_DEPLUX_RD12 (0x7e) +#define MSPI_FULL_DEPLUX_RD13 (0x7e) +#define MSPI_FULL_DEPLUX_RD14 (0x7f) +#define MSPI_FULL_DEPLUX_RD15 (0x7f) + +//chip select bit map +#define MSPI_CHIP_SELECT_MAX 0x07 + +// control bit +#define MSPI_DONE_FLAG 0x01 +#define MSPI_TRIGGER 0x01 +#define MSPI_CLEAR_DONE 0x01 +#define MSPI_INT_ENABLE 0x04 +#define MSPI_RESET 0x02 +#define MSPI_ENABLE 0x01 + +// clk_mspi0 +#define MSPI0_CLK_CFG 0x33 //bit 2 ~bit 3 +#define MSPI0_CLK_108M 0x00 +#define MSPI0_CLK_54M 0x04 +#define MSPI0_CLK_12M 0x08 +#define MSPI0_CLK_MASK 0x0F + +// clk_mspi1 +#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 +#define MSPI1_CLK_108M 0x0000 +#define MSPI1_CLK_54M 0x0400 +#define MSPI1_CLK_12M 0x0800 +#define MSPI1_CLK_MASK 0x0F00 + +// clk_mspi +#define MSPI_CLK_CFG 0x33 +#define MSPI_SELECT_0 0x0000 +#define MSPI_SELECT_1 0x4000 +#define MSPI_CLK_MASK 0xF000 + +// Clock settings +#define MSPI_CPU_CLOCK_1_2 0x0000 +#define MSPI_CPU_CLOCK_1_4 0x0100 +#define MSPI_CPU_CLOCK_1_8 0x0200 +#define MSPI_CPU_CLOCK_1_16 0x0300 +#define MSPI_CPU_CLOCK_1_32 0x0400 +#define MSPI_CPU_CLOCK_1_64 0x0500 +#define MSPI_CPU_CLOCK_1_128 0x0600 +#define MSPI_CPU_CLOCK_1_256 0x0700 + +//CHITOP 101E mspi mode select +#define MSPI0_MODE 0x0C //bit0~bit1 +#define MSPI0_MODE_MASK 0x07 +#define MSPI1_MODE 0x0C //bit4~bit5 +#define MSPI1_MODE_MASK 0x70 +#define EJTAG_MODE 0xF +#define EJTAG_MODE_1 0x01 +#define EJTAG_MODE_2 0x02 +#define EJTAG_MODE_3 0x03 +#define EJTAG_MODE_MASK 0x03 + +//MOVDMA 100B +#define MOV_DMA_SRC_ADDR_L 0x03 +#define MOV_DMA_SRC_ADDR_H 0x04 +#define MOV_DMA_DST_ADDR_L 0x05 +#define MOV_DMA_DST_ADDR_H 0x06 +#define MOV_DMA_BYTE_CNT_L 0x07 +#define MOV_DMA_BYTE_CNT_H 0x08 +#define DMA_MOVE0_IRQ_CLR 0x28 +#define MOV_DMA_IRQ_FINAL_STATUS 0x2A +#define DMA_MOVE0_ENABLE 0x00 +#define DMA_RW 0x50 //0 for dma write to device, 1 for dma read from device +#define DMA_READ 0x01 +#define DMA_WRITE 0x00 +#define DMA_DEVICE_MODE 0x51 +#define DMA_DEVICE_SEL 0x52 + +//spi dma +#define MSPI_DMA_DATA_LENGTH_L 0x30 +#define MSPI_DMA_DATA_LENGTH_H 0x31 +#define MSPI_DMA_ENABLE 0x32 +#define MSPI_DMA_RW_MODE 0x33 +#define MSPI_DMA_WRITE 0x00 +#define MSPI_DMA_READ 0x01 + +#define MSTAR_SPI_TIMEOUT_MS 30000 +#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) + + +//------------------------------------------------------------------------------------------------- +// Macros +//------------------------------------------------------------------------------------------------- + + +#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) +#define READ_WORD(_reg) (*(volatile u16*)(_reg)) +#define READ_LONG(_reg) (*(volatile u32*)(_reg)) +#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } +#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } +#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } +#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } +#define READ_CPLD_DATA_IN() ((MHal_RIU_REG(PAD_Z80IO_IN_DATA_7_ADDR) & 0x1) << 7 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_6_ADDR) & 0x1) << 6 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_5_ADDR) & 0x1) << 5 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_4_ADDR) & 0x1) << 4 |\ + (MHal_RIU_REG(PAD_Z80IO_IN_DATA_3_ADDR) & 0x1) << 3 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_2_ADDR) & 0x1) << 2 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_1_ADDR) & 0x1) << 1 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_0_ADDR) & 0x1)) +#define SET_CPLD_READ_DATA() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;} +#define SET_CPLD_READ_STATUS() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;} +#define SET_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;} +#define CLEAR_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;} +#define CPLD_READY() (MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) +#define CPLD_RESET() (MHal_RIU_REG(PAD_Z80IO_RESET_ADDR) & 0x1) +#define CPLD_LAST_TSTATE() (MHal_RIU_REG(PAD_Z80IO_LTSTATE_ADDR) & 0x4) +#define SPI_SEND8(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 1); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE);\ + } +#define SPI_SEND16(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 2); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \ + } +#define SPI_SEND32(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)((_d_) >> 16)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \ + } + +// read 2 byte +#define MSPI_READ(_reg_) READ_WORD(gMspBaseAddr + ((_reg_)<<2)) +// write 2 byte +//#define MSPI_WRITE(_reg_, _val_) {pr_info("PDS: MSPI_WRITE(0x%x, 0x%x, 0x%x)\n", _reg_, _val_, gMspBaseAddr + ((_reg_)<<2)); WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_)); } +#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_)); +//write 2 byte mask +//#define MSPI_WRITE_MASK(_reg_, _val_, mask) {pr_info("PDS: WRITE_LONG(0x%x, 0x%x, mask=0x%x)\n", _reg_, _val_, mask); WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask)); } +#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask)); + +#define CLK_READ(_reg_) READ_WORD(gClkBaseAddr + ((_reg_)<<2)) +//#define CLK_WRITE(_reg_, _val_) {pr_info("PDS: CLK_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_)); } +#define CLK_WRITE(_reg_, _val_) WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_)); + +#define CHIPTOP_READ(_reg_) READ_WORD(gChipBaseAddr + ((_reg_)<<2)) +//#define CHIPTOP_WRITE(_reg_, _val_) {pr_info("PDS: CHIPTOP_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_)); } +#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_)); + +#define MOVDMA_READ(_reg_) READ_WORD(gMOVDMAAddr + ((_reg_)<<2)) +//#define MOVDMA_WRITE(_reg_, _val_) {pr_info("PDS: MOVDMA_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_)); } +#define MOVDMA_WRITE(_reg_, _val_) WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_)); + +#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) +#define MAX_CHECK_CNT 2000 + +#define MSPI_READ_INDEX 0x0 +#define MSPI_WRITE_INDEX 0x1 + +#define SPI_MIU0_BUS_BASE 0x20000000 +#define SPI_MIU1_BUS_BASE 0xFFFFFFFF + + +// Function definitions. +// +int z80io_init(void); +uint8_t z80io_SPI_Send8(uint8_t txData, uint8_t *rxData); +uint8_t z80io_SPI_Send16(uint16_t txData, uint16_t *rxData); +uint8_t z80io_SPI_Send32(uint32_t txData, uint32_t *rxData); +#ifdef NOTNEEDED +uint8_t z80io_PRL_Send8(uint8_t txData); +uint8_t z680io_PRL_Send16(uint16_t txData); +#endif +uint8_t z80io_PRL_Read8(uint8_t dataFlag); +uint16_t z80io_PRL_Read16(void); +uint8_t z80io_SPI_Test(void); +uint8_t z80io_PRL_Test(void); +uint8_t z80io_Z80_TestMemory(void); + +extern void MHal_GPIO_Init(void); +extern void MHal_GPIO_Pad_Set(uint8_t u8IndexGPIO); +extern int MHal_GPIO_PadGroupMode_Set(uint32_t u32PadMode); +extern int MHal_GPIO_PadVal_Set(uint8_t u8IndexGPIO, uint32_t u32PadMode); +extern void MHal_GPIO_Pad_Oen(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pad_Odn(uint8_t u8IndexGPIO); +extern uint8_t MHal_GPIO_Pad_Level(uint8_t u8IndexGPIO); +extern uint8_t MHal_GPIO_Pad_InOut(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pull_High(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pull_Low(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_High(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_Low(uint8_t u8IndexGPIO); +extern void MHal_Enable_GPIO_INT(uint8_t u8IndexGPIO); +extern int MHal_GPIO_To_Irq(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_POLARITY(uint8_t u8IndexGPIO, uint8_t reverse); +extern void MHal_GPIO_Set_Driving(uint8_t u8IndexGPIO, uint8_t setHigh); +extern void MHal_GPIO_PAD_32K_OUT(uint8_t u8Enable); + +#ifdef __cplusplus +} +#endif +#endif // Z80IO_H diff --git a/software/FusionX/src/driver/MZ2000/z80io_test.c b/software/FusionX/src/driver/MZ2000/z80io_test.c new file mode 100644 index 000000000..ac7346b57 --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80io_test.c @@ -0,0 +1,541 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io_test.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface Test Methods +// This file contains the methods used to test the SOM to CPLD interface and evaluate +// it's performance. Production builds wont include these methods. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include + +//-------------------------------------------------------- +// Test Methods. +//-------------------------------------------------------- +uint8_t z80io_Z80_TestMemory(void) +{ + // Locals. + // + uint32_t addr; + uint32_t fullCmd; + uint8_t cmd; + struct timeval start, stop; + uint32_t iterations = 100; + uint32_t errorCount; + uint32_t idx; + long totalTime; + long bytesMSec; + uint8_t result; + spinlock_t spinLock; + unsigned long flags; + + SPI_SEND8(CPLD_CMD_CLEAR_AUTO_REFRESH); + + SPI_SEND32(0x00E30000 | (0x07 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E80000 | (0x82 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E20000 | (0x58 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E00000 | (0xF7 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E90000 | (0x0F << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00EB0000 | (0xCF << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00EB0000 | (0xFF << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + pr_info("Z80 Host Test - IO.\n"); +// for(idx=0; idx < 1000000; idx++) +// { +// SPI_SEND32(0x00E80000 | (0xD3 << 8) | CPLD_CMD_WRITEIO_ADDR); +// SPI_SEND32(0xD0000000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0100000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0200000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0300000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0400000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0500000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// } + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing IO Write performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + for(addr=0x0000; addr < 0x10000; addr++) + { + fullCmd = 0x00000000| ((uint8_t)addr) << 8 | CPLD_CMD_WRITEIO_ADDR; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing IO Read performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible IO ports and write to it. + for(addr=0x0000; addr < 0x10000; addr++) + { + fullCmd = 0x00000000 | ((uint8_t)addr) << 8 | CPLD_CMD_READIO_ADDR; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing RAM Write performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x1000; addr < 0xD000; addr++) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write performance (opt).\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write/Fetch performance (opt).\n"); + errorCount = 0; + SET_CPLD_READ_DATA(); + //MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x8000; addr < 0xD000; addr++) + { + if(addr == 0x8000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + + // Read back the same byte. + cmd = 0x10; + SPI_SEND8(cmd); + while(CPLD_READY() == 0); + + result = READ_CPLD_DATA_IN(); + if(result != (uint8_t)addr) + { + if(errorCount < 50) pr_info("Read byte:0x%x, Written:0x%x\n", result, (uint8_t)addr); + errorCount++; + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, errorCount=%d, %ldBytes/sec\n", totalTime/1000, errorCount, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write/Read performance (opt).\n"); + errorCount = 0; + SET_CPLD_READ_DATA(); + //MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x8000; addr < 0xD000; addr++) + { + if(addr == 0x8000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + + // Read back the same byte. + cmd = 0x20; + SPI_SEND8(cmd); + while(CPLD_READY() == 0); + + result = READ_CPLD_DATA_IN(); + if(result != (uint8_t)addr) + { + if(errorCount < 50) pr_info("Read byte:0x%x, Written:0x%x\n", result, (uint8_t)addr); + errorCount++; + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, errorCount=%d, %ldBytes/sec\n", totalTime/1000, errorCount, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Fetch performance.\n"); + SET_CPLD_READ_DATA(); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and read from it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x10; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x11; + SPI_SEND8(cmd); + } + while(CPLD_READY() == 0); + result = READ_CPLD_DATA_IN(); + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Read performance (opt).\n"); + SET_CPLD_READ_DATA(); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and read from it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x20; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x21; + SPI_SEND8(cmd); + } + while(CPLD_READY() == 0); + result = READ_CPLD_DATA_IN(); + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + // Go through all the accessible attribute VRAM and initialise it. + pr_info("Z80 Host Test - Testing VRAM Write performance.\n"); + SPI_SEND32(0x00E80000 | (0xD3 << 8) | CPLD_CMD_WRITEIO_ADDR); + iterations = 256*10; + do_gettimeofday(&start); + for(addr=0xD800; addr < 0xE000; addr++) + { + //while(CPLD_READY() == 0); + if(addr == 0xD800) + { + fullCmd = (addr << 16) |(0x71 << 8) | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND8(cmd); + } + } + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible VRAM and write to it. + for(addr=0xD000; addr < 0xD800; addr++) + { + //while(CPLD_READY() == 0); + if(addr == 0xD000) + { + fullCmd = (addr << 16) | ((uint8_t)idx << 8) | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND8(cmd); + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)((1*iterations*0x800)+0x800)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + return(0); +} + + +// A simple test to verify the SOM to CPLD SPI connectivity and give an estimate of its performance. +// The performance is based on the SPI setup and transmit time along with the close and received data processing. +// In real use, the driver will just send a command and generally ignore received data so increased throughput can be achieved. +// +uint8_t z80io_SPI_Test(void) +{ + // Locals. + // + struct timeval start, stop; + uint32_t iterations = 10000000; + uint32_t idx; + uint8_t rxData8; + uint16_t rxData16; + uint16_t rxData16Last; + uint32_t rxData32; + uint32_t rxData32Last; + uint32_t errorCount; + long totalTime; + long bytesMSec; + + // Place the CPLD into echo test mode. + z80io_SPI_Send8(0xfe, &rxData8); + + // 1st. test, 8bit. + pr_info("SPI Test - Testing 8 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + z80io_SPI_Send8((uint8_t)idx, &rxData8); + if(idx > 1 && (uint8_t)(idx-1) != rxData8) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint8_t)(idx-1), rxData8 ); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 2nd. test, 16bit. + pr_info("SPI Test - Testing 16 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Byte re-ordering required as the CPLD echo's back the last 8bits received, it doesnt know if a transmission is 8/16/32bits. + z80io_SPI_Send16((uint16_t)idx, &rxData16); + if(idx > 0 && (uint16_t)(idx-1) != (uint16_t)(((rxData16&0x00ff) << 8) | ((rxData16Last & 0xff00) >> 8))) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint16_t)(idx-1), (uint16_t)(((rxData16&0x00ff) << 8) | ((rxData16Last & 0xff00) >> 8))); + errorCount++; + } + rxData16Last = rxData16; + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 3rd. test, 32bit. + pr_info("SPI Test - Testing 32 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + z80io_SPI_Send32((uint32_t)idx, &rxData32); + if(idx > 0 && (uint32_t)(idx-1) != (uint32_t)(((rxData32&0x00ff) << 8) | ((rxData32Last & 0xff000000) >> 8) | ((rxData32Last & 0xff0000) >> 8) | ((rxData32Last & 0xff00) >> 8))) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint32_t)(idx-1), (uint32_t)(((rxData32&0x00ff) << 8) | ((rxData32Last & 0xff000000) >> 8) | ((rxData32Last & 0xff0000) >> 8) | ((rxData32Last & 0xff00) >> 8))); + errorCount++; + } + rxData32Last = rxData32; + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(4*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + pr_info("Press host RESET button Once to reset the CPLD.\n"); + return(0); +} + +// Method to test the parallel bus, verifying integrity and assessing performance. +uint8_t z80io_PRL_Test(void) +{ + // Locals. + // + struct timeval start, stop; + uint32_t iterations = 10000000; + uint32_t idx; + uint8_t rxData8; + uint16_t rxData16; + long totalTime; + long bytesMSec; +#ifdef NOTNEEDED + uint32_t errorCount; +#endif + + // Place the CPLD into echo test mode. + + // 1st. test, 8bit RW. +#ifdef NOTNEEDED + pr_info("Parallel Test - Testing 8 bit r/w performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write byte and readback to compare. + z80io_PRL_Send8((uint8_t)idx); + rxData8 = z80io_PRL_Read8(); + if((uint8_t)idx != rxData8) + { + pr_info("0x%x: Written(0x%x) /= Read(0x%x)\n", idx, (uint8_t)(idx), rxData8); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 2nd. test, 8bit Write. + pr_info("Parallel Test - Testing 8 bit write performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write byte. + z80io_PRL_Send8((uint8_t)idx); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); +#endif + + // 3rd. test, 8bit Read. + pr_info("Parallel Test - Testing 8 bit read performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Read byte. + rxData8 = z80io_PRL_Read8(0); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + +#ifdef NOTNEEDED + // 4th test, 16bit. + pr_info("Parallel Test - Testing 16 bit r/w performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Byte re-ordering required as the CPLD echo's back the last 8bits received, it doesnt know if a transmission is 8/16/32bits. + z80io_PRL_Send16((uint16_t)idx); + rxData16 = z80io_PRL_Read16(); + if((uint16_t)idx != rxData16) + { + pr_info("0x%x: Written(0x%x) /= Read(0x%x)\n", idx, (uint16_t)(idx), rxData16); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 5th test, 16bit Write. + pr_info("Parallel Test - Testing 16 bit write performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write word. + z80io_PRL_Send16((uint16_t)idx); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); +#endif + + // 6th test, 16bit Read. + pr_info("Parallel Test - Testing 16 bit read performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Read word. + rxData16 = z80io_PRL_Read16(); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Press host RESET button Once to reset the CPLD.\n"); + return(0); +} diff --git a/software/FusionX/src/driver/MZ2000/z80menu.c b/software/FusionX/src/driver/MZ2000/z80menu.c new file mode 100644 index 000000000..bcc28a2ca --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80menu.c @@ -0,0 +1,57 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80menu.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 User Menu +// This file contains the methods used to present a menu of options to a user to aid +// in configuration and load/save of applications and data. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" +#include "z80menu.h" + +#include +#include +#include +#include + +void z80menu(void) +{ + // Locals. + +} diff --git a/software/FusionX/src/driver/MZ2000/z80menu.h b/software/FusionX/src/driver/MZ2000/z80menu.h new file mode 100755 index 000000000..107583682 --- /dev/null +++ b/software/FusionX/src/driver/MZ2000/z80menu.h @@ -0,0 +1,44 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80menu.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 User Interface Menu +// This file contains the declarations required to provide a menu system allowing a +// user to configure and load/save applications/data. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80MENU_H +#define Z80MENU_H + +#ifdef __cplusplus + extern "C" { +#endif + +// Function definitions. +// +void z80menu(void); + +#ifdef __cplusplus +} +#endif +#endif // Z80MENU_H diff --git a/software/FusionX/src/driver/MZ700/optparse.h b/software/FusionX/src/driver/MZ700/optparse.h new file mode 100644 index 000000000..f96184add --- /dev/null +++ b/software/FusionX/src/driver/MZ700/optparse.h @@ -0,0 +1,403 @@ +/* Optparse --- portable, reentrant, embeddable, getopt-like option parser + * + * This is free and unencumbered software released into the public domain. + * + * To get the implementation, define OPTPARSE_IMPLEMENTATION. + * Optionally define OPTPARSE_API to control the API's visibility + * and/or linkage (static, __attribute__, __declspec). + * + * The POSIX getopt() option parser has three fatal flaws. These flaws + * are solved by Optparse. + * + * 1) Parser state is stored entirely in global variables, some of + * which are static and inaccessible. This means only one thread can + * use getopt(). It also means it's not possible to recursively parse + * nested sub-arguments while in the middle of argument parsing. + * Optparse fixes this by storing all state on a local struct. + * + * 2) The POSIX standard provides no way to properly reset the parser. + * This means for portable code that getopt() is only good for one + * run, over one argv with one option string. It also means subcommand + * options cannot be processed with getopt(). Most implementations + * provide a method to reset the parser, but it's not portable. + * Optparse provides an optparse_arg() function for stepping over + * subcommands and continuing parsing of options with another option + * string. The Optparse struct itself can be passed around to + * subcommand handlers for additional subcommand option parsing. A + * full reset can be achieved by with an additional optparse_init(). + * + * 3) Error messages are printed to stderr. This can be disabled with + * opterr, but the messages themselves are still inaccessible. + * Optparse solves this by writing an error message in its errmsg + * field. The downside to Optparse is that this error message will + * always be in English rather than the current locale. + * + * Optparse should be familiar with anyone accustomed to getopt(), and + * it could be a nearly drop-in replacement. The option string is the + * same and the fields have the same names as the getopt() global + * variables (optarg, optind, optopt). + * + * Optparse also supports GNU-style long options with optparse_long(). + * The interface is slightly different and simpler than getopt_long(). + * + * By default, argv is permuted as it is parsed, moving non-option + * arguments to the end. This can be disabled by setting the `permute` + * field to 0 after initialization. + */ +#ifndef OPTPARSE_H +#define OPTPARSE_H + +#ifndef OPTPARSE_API +# define OPTPARSE_API +#endif + +struct optparse { + char **argv; + int permute; + int optind; + int optopt; + char *optarg; + char errmsg[64]; + int subopt; +}; + +enum optparse_argtype { + OPTPARSE_NONE, + OPTPARSE_REQUIRED, + OPTPARSE_OPTIONAL +}; + +struct optparse_long { + const char *longname; + int shortname; + enum optparse_argtype argtype; +}; + +/** + * Initializes the parser state. + */ +OPTPARSE_API +void optparse_init(struct optparse *options, char **argv); + +/** + * Read the next option in the argv array. + * @param optstring a getopt()-formatted option string. + * @return the next option character, -1 for done, or '?' for error + * + * Just like getopt(), a character followed by no colons means no + * argument. One colon means the option has a required argument. Two + * colons means the option takes an optional argument. + */ +OPTPARSE_API +int optparse(struct optparse *options, const char *optstring); + +/** + * Handles GNU-style long options in addition to getopt() options. + * This works a lot like GNU's getopt_long(). The last option in + * longopts must be all zeros, marking the end of the array. The + * longindex argument may be NULL. + */ +OPTPARSE_API +int optparse_long(struct optparse *options, + const struct optparse_long *longopts, + int *longindex); + +/** + * Used for stepping over non-option arguments. + * @return the next non-option argument, or NULL for no more arguments + * + * Argument parsing can continue with optparse() after using this + * function. That would be used to parse the options for the + * subcommand returned by optparse_arg(). This function allows you to + * ignore the value of optind. + */ +OPTPARSE_API +char *optparse_arg(struct optparse *options); + +/* Implementation */ +#ifdef OPTPARSE_IMPLEMENTATION + +#define OPTPARSE_MSG_INVALID "invalid option" +#define OPTPARSE_MSG_MISSING "option requires an argument" +#define OPTPARSE_MSG_TOOMANY "option takes no arguments" + +static int +optparse_error(struct optparse *options, const char *msg, const char *data) +{ + unsigned p = 0; + const char *sep = " -- '"; + while (*msg) + options->errmsg[p++] = *msg++; + while (*sep) + options->errmsg[p++] = *sep++; + while (p < sizeof(options->errmsg) - 2 && *data) + options->errmsg[p++] = *data++; + options->errmsg[p++] = '\''; + options->errmsg[p++] = '\0'; + return '?'; +} + +OPTPARSE_API +void +optparse_init(struct optparse *options, char **argv) +{ + options->argv = argv; + options->permute = 1; + options->optind = 1; + options->subopt = 0; + options->optarg = 0; + options->errmsg[0] = '\0'; +} + +static int +optparse_is_dashdash(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] == '-' && arg[2] == '\0'; +} + +static int +optparse_is_shortopt(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] != '-' && arg[1] != '\0'; +} + +static int +optparse_is_longopt(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] == '-' && arg[2] != '\0'; +} + +static void +optparse_permute(struct optparse *options, int index) +{ + char *nonoption = options->argv[index]; + int i; + for (i = index; i < options->optind - 1; i++) + options->argv[i] = options->argv[i + 1]; + options->argv[options->optind - 1] = nonoption; +} + +static int +optparse_argtype(const char *optstring, char c) +{ + int count = OPTPARSE_NONE; + if (c == ':') + return -1; + for (; *optstring && c != *optstring; optstring++); + if (!*optstring) + return -1; + if (optstring[1] == ':') + count += optstring[2] == ':' ? 2 : 1; + return count; +} + +OPTPARSE_API +int +optparse(struct optparse *options, const char *optstring) +{ + int type; + char *next; + char *option = options->argv[options->optind]; + options->errmsg[0] = '\0'; + options->optopt = 0; + options->optarg = 0; + if (option == 0) { + return -1; + } else if (optparse_is_dashdash(option)) { + options->optind++; /* consume "--" */ + return -1; + } else if (!optparse_is_shortopt(option)) { + if (options->permute) { + int index = options->optind++; + int r = optparse(options, optstring); + optparse_permute(options, index); + options->optind--; + return r; + } else { + return -1; + } + } + option += options->subopt + 1; + options->optopt = option[0]; + type = optparse_argtype(optstring, option[0]); + next = options->argv[options->optind + 1]; + switch (type) { + case -1: { + char str[2] = {0, 0}; + str[0] = option[0]; + options->optind++; + return optparse_error(options, OPTPARSE_MSG_INVALID, str); + } + case OPTPARSE_NONE: + if (option[1]) { + options->subopt++; + } else { + options->subopt = 0; + options->optind++; + } + return option[0]; + case OPTPARSE_REQUIRED: + options->subopt = 0; + options->optind++; + if (option[1]) { + options->optarg = option + 1; + } else if (next != 0) { + options->optarg = next; + options->optind++; + } else { + char str[2] = {0, 0}; + str[0] = option[0]; + options->optarg = 0; + return optparse_error(options, OPTPARSE_MSG_MISSING, str); + } + return option[0]; + case OPTPARSE_OPTIONAL: + options->subopt = 0; + options->optind++; + if (option[1]) + options->optarg = option + 1; + else + options->optarg = 0; + return option[0]; + } + return 0; +} + +OPTPARSE_API +char * +optparse_arg(struct optparse *options) +{ + char *option = options->argv[options->optind]; + options->subopt = 0; + if (option != 0) + options->optind++; + return option; +} + +static int +optparse_longopts_end(const struct optparse_long *longopts, int i) +{ + return !longopts[i].longname && !longopts[i].shortname; +} + +static void +optparse_from_long(const struct optparse_long *longopts, char *optstring) +{ + char *p = optstring; + int i; + for (i = 0; !optparse_longopts_end(longopts, i); i++) { + if (longopts[i].shortname && longopts[i].shortname < 127) { + int a; + *p++ = longopts[i].shortname; + for (a = 0; a < (int)longopts[i].argtype; a++) + *p++ = ':'; + } + } + *p = '\0'; +} + +/* Unlike strcmp(), handles options containing "=". */ +static int +optparse_longopts_match(const char *longname, const char *option) +{ + const char *a = option, *n = longname; + if (longname == 0) + return 0; + for (; *a && *n && *a != '='; a++, n++) + if (*a != *n) + return 0; + return *n == '\0' && (*a == '\0' || *a == '='); +} + +/* Return the part after "=", or NULL. */ +static char * +optparse_longopts_arg(char *option) +{ + for (; *option && *option != '='; option++); + if (*option == '=') + return option + 1; + else + return 0; +} + +static int +optparse_long_fallback(struct optparse *options, + const struct optparse_long *longopts, + int *longindex) +{ + int result; + char optstring[96 * 3 + 1]; /* 96 ASCII printable characters */ + optparse_from_long(longopts, optstring); + result = optparse(options, optstring); + if (longindex != 0) { + *longindex = -1; + if (result != -1) { + int i; + for (i = 0; !optparse_longopts_end(longopts, i); i++) + if (longopts[i].shortname == options->optopt) + *longindex = i; + } + } + return result; +} + +OPTPARSE_API +int +optparse_long(struct optparse *options, + const struct optparse_long *longopts, + int *longindex) +{ + int i; + char *option = options->argv[options->optind]; + if (option == 0) { + return -1; + } else if (optparse_is_dashdash(option)) { + options->optind++; /* consume "--" */ + return -1; + } else if (optparse_is_shortopt(option)) { + return optparse_long_fallback(options, longopts, longindex); + } else if (!optparse_is_longopt(option)) { + if (options->permute) { + int index = options->optind++; + int r = optparse_long(options, longopts, longindex); + optparse_permute(options, index); + options->optind--; + return r; + } else { + return -1; + } + } + + /* Parse as long option. */ + options->errmsg[0] = '\0'; + options->optopt = 0; + options->optarg = 0; + option += 2; /* skip "--" */ + options->optind++; + for (i = 0; !optparse_longopts_end(longopts, i); i++) { + const char *name = longopts[i].longname; + if (optparse_longopts_match(name, option)) { + char *arg; + if (longindex) + *longindex = i; + options->optopt = longopts[i].shortname; + arg = optparse_longopts_arg(option); + if (longopts[i].argtype == OPTPARSE_NONE && arg != 0) { + return optparse_error(options, OPTPARSE_MSG_TOOMANY, name); + } if (arg != 0) { + options->optarg = arg; + } else if (longopts[i].argtype == OPTPARSE_REQUIRED) { + options->optarg = options->argv[options->optind]; + if (options->optarg == 0) + return optparse_error(options, OPTPARSE_MSG_MISSING, name); + else + options->optind++; + } + return options->optopt; + } + } + return optparse_error(options, OPTPARSE_MSG_INVALID, option); +} + +#endif /* OPTPARSE_IMPLEMENTATION */ +#endif /* OPTPARSE_H */ diff --git a/software/FusionX/src/driver/MZ700/z80ctrl.c b/software/FusionX/src/driver/MZ700/z80ctrl.c new file mode 100644 index 000000000..70c69f2b5 --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80ctrl.c @@ -0,0 +1,734 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80ctrl.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Control Interface +// This file contains a command line utility tool for controlling the z80drv device +// driver. The tool allows manipulation of the emulated Z80, inspection of its +// memory and data, transmission of adhoc commands to the underlying CPLD-Z80 +// gateway and loading/saving of programs and data to/from the Z80 virtual and +// host memory. +// +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of the Z80 device driver. +// Copyright: (c) 2019-2022 Philip Smart +// (c) 1999-2022 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80driver.h" + +#define VERSION "1.0" +#define AUTHOR "P.D.Smart" +#define COPYRIGHT "(c) 2018-22" + +// Getopt_long is buggy so we use optparse. +#define OPTPARSE_IMPLEMENTATION +#define OPTPARSE_API static +#include "optparse.h" + +// Device driver name. +#define DEVICE_FILENAME "/dev/z80drv" + +// Constants for the Sharp MZ80A MZF file format. +#define MZF_HEADER_SIZE 128 // Size of the MZF header. +#define MZF_ATTRIBUTE 0x00 // Code Type, 01 = Machine Code. +#define MZF_FILENAME 0x01 // Title/Name (17 bytes). +#define MZF_FILENAME_LEN 17 // Length of the filename, it is not NULL terminated, generally a CR can be taken as terminator but not guaranteed. +#define MZF_FILESIZE 0x12 // Size of program. +#define MZF_LOADADDR 0x14 // Load address of program. +#define MZF_EXECADDR 0x16 // Exec address of program. +#define MZF_COMMENT 0x18 // Comment, used for details of the file or startup code. +#define MZF_COMMENT_LEN 104 // Length of the comment field. +#define CMT_TYPE_OBJCD 0x001 // MZF contains a binary object. +#define CMT_TYPE_BTX1CD 0x002 // MZF contains a BASIC program. +#define CMT_TYPE_BTX2CD 0x005 // MZF contains a BASIC program. +#define CMT_TYPE_TZOBJCD0 0x0F8 // MZF contains a TZFS binary object for page 0. +#define CMT_TYPE_TZOBJCD1 0x0F9 +#define CMT_TYPE_TZOBJCD2 0x0FA +#define CMT_TYPE_TZOBJCD3 0x0FB +#define CMT_TYPE_TZOBJCD4 0x0FC +#define CMT_TYPE_TZOBJCD5 0x0FD +#define CMT_TYPE_TZOBJCD6 0x0FE +#define CMT_TYPE_TZOBJCD7 0x0FF // MZF contains a TZFS binary object for page 7. +#define MZ_CMT_ADDR 0x10F0 + +// Structure to define a Sharp MZ80A MZF directory structure. This header appears at the beginning of every Sharp MZ80A tape (and more recently archived/emulator) images. +// +typedef struct __attribute__((__packed__)) { + uint8_t attr; // MZF attribute describing the file. + uint8_t fileName[MZF_FILENAME_LEN]; // Each directory entry is the size of an MZF filename. + uint16_t fileSize; // Size of file. + uint16_t loadAddr; // Load address for the file. + uint16_t execAddr; // Execution address where the Z80 starts processing. + uint8_t comment[MZF_COMMENT_LEN]; // Text comment field but often contains a startup machine code program. +} t_svcDirEnt; + +// Possible commands to be issued to the Z80 driver. +enum CTRL_COMMANDS { + Z80_CMD_STOP = 0, + Z80_CMD_START = 1, + Z80_CMD_PAUSE = 2, + Z80_CMD_CONTINUE = 3, + Z80_CMD_RESET = 4, + Z80_CMD_SPEED = 5, + Z80_CMD_HOST_RAM = 6, + Z80_CMD_VIRTUAL_RAM = 7, + Z80_CMD_DUMP_MEMORY = 8, + Z80_CMD_MEMORY_TEST = 9, + CPLD_CMD_SEND_CMD = 10, + CPLD_CMD_SPI_TEST = 11, + CPLD_CMD_PRL_TEST = 12 +}; + + +// Shared memory between this process and the Z80 driver. +static t_Z80Ctrl *Z80Ctrl = NULL; + +// Method to obtain and return the output screen width. +// +uint8_t getScreenWidth(void) +{ + return(MAX_SCREEN_WIDTH); +} + +struct termios orig_termios; + +void reset_terminal_mode() +{ + tcsetattr(0, TCSANOW, &orig_termios); +} + +void set_conio_terminal_mode() +{ + struct termios new_termios; + + /* take two copies - one for now, one for later */ + tcgetattr(0, &orig_termios); + memcpy(&new_termios, &orig_termios, sizeof(new_termios)); + + /* register cleanup handler, and set the new terminal mode */ + atexit(reset_terminal_mode); + cfmakeraw(&new_termios); + tcsetattr(0, TCSANOW, &new_termios); +} + +int kbhit() +{ + struct timeval tv = { 0L, 0L }; + fd_set fds; + FD_ZERO(&fds); + FD_SET(0, &fds); + return select(1, &fds, NULL, NULL, &tv) > 0; +} + +int getch(uint8_t wait) +{ + int r; + unsigned char c; + + if(wait != 0 || (wait == 0 && kbhit())) + { + if ((r = read(0, &c, sizeof(c))) < 0) { + return r; + } else { + return c; + } + } + return 0; +} + +void delay(int number_of_seconds) +{ + // Converting time into milli_seconds + int milli_seconds = 1000 * number_of_seconds; + + // Storing start time + clock_t start_time = clock(); + + // looping till required time is not achieved + while (clock() < start_time + milli_seconds); +} + +// Function to dump out a given section of memory via the UART. +// +int memoryDump(uint32_t memaddr, uint32_t memsize, uint8_t memoryFlag, uint32_t memwidth, uint32_t dispaddr, uint8_t dispwidth) +{ + uint8_t displayWidth = dispwidth;; + uint32_t pnt = memaddr; + uint32_t endAddr = memaddr + memsize; + uint32_t addr = dispaddr; + uint32_t i = 0; + //uint32_t data; + int8_t keyIn; + int result = -1; + char c = 0; + + // Sanity check. memoryFlag == 0 required kernel driver to dump so we exit as it cannot be performed here. + if(memoryFlag == 0) + return(-1); + + // Reconfigure terminal to allow non-blocking key input. + // + set_conio_terminal_mode(); + + // If not set, calculate output line width according to connected display width. + // + if(displayWidth == 0) + { + switch(getScreenWidth()) + { + case 40: + displayWidth = 8; + break; + case 80: + displayWidth = 16; + break; + default: + displayWidth = 32; + break; + } + } + + while (1) + { + printf("%08lX", addr); // print address + printf(": "); + + // print hexadecimal data + for (i=0; i < displayWidth; ) + { + switch(memwidth) + { + case 16: + if(pnt+i < endAddr) + printf("%04X", memoryFlag == 1 ? (uint16_t)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (uint16_t)Z80Ctrl->page[pnt+i] : (uint16_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + + case 32: + if(pnt+i < endAddr) + printf("%08lX", memoryFlag == 1 ? (uint32_t)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (uint32_t)Z80Ctrl->page[pnt+i] : (uint32_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + + case 8: + default: + if(pnt+i < endAddr) + printf("%02X", memoryFlag == 1 ? (uint8_t)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (uint8_t)Z80Ctrl->page[pnt+i] : (uint8_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + } + fputc((char)' ', stdout); + } + + // print ascii data + printf(" |"); + + // print single ascii char + for (i=0; i < displayWidth; i++) + { + c = memoryFlag == 1 ? (char)Z80Ctrl->memory[pnt+i] : memoryFlag == 2 ? (char)Z80Ctrl->page[pnt+i] : (char)Z80Ctrl->iopage[pnt+i]; + if ((pnt+i < endAddr) && (c >= ' ') && (c <= '~')) + fputc((char)c, stdout); + else + fputc((char)' ', stdout); + } + + printf("|\r\n"); + fflush(stdout); + + // Move on one row. + pnt += displayWidth; + addr += displayWidth; + + // User abort (ESC), pause (Space) or all done? + // + keyIn = getch(0); + if(keyIn == ' ') + { + do { + keyIn = getch(0); + } while(keyIn != ' ' && keyIn != 0x1b); + } + // Escape key pressed, exit with 0 to indicate this to caller. + if (keyIn == 0x1b) + { + sleep(1); + result = 0; + goto memoryDumpExit; + } + + // End of buffer, exit the loop. + if(pnt >= (memaddr + memsize)) + { + break; + } + } + + // Normal exit, return -1 to show no key pressed. +memoryDumpExit: + reset_terminal_mode(); + return(result); +} + +// Method to load a program or data file into the Z80 memory. First load into Virtual memory and then trigger a sync to bring Host RAM in line. +// +int z80load(int fdZ80, char *fileName) +{ + // Locals. + struct ioctlCmd ioctlCmd; + int ret = 0; + t_svcDirEnt mzfHeader; + + // Pause the Z80. + // + ioctlCmd.cmd = IOCTL_CMD_Z80_PAUSE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + // Open the file and read directly into the Virtual memory via the share. + FILE *ptr; + ptr = fopen(fileName, "rb"); + if(ptr) + { +printf("File:%s\n", fileName); + // First the header. + fread((uint8_t *)&mzfHeader, MZF_HEADER_SIZE, 1, ptr); +printf("Load:%x\n", mzfHeader.loadAddr); + if(mzfHeader.loadAddr > 0x1000) + { +printf("Memcpy:%x,%x\n", mzfHeader.loadAddr, mzfHeader.fileSize); + // Copy in the header. + memcpy((uint8_t *)&Z80Ctrl->memory[MZ_CMT_ADDR], (uint8_t *)&mzfHeader, MZF_HEADER_SIZE); + +printf("Memcpy:%x,%x\n", mzfHeader.loadAddr, mzfHeader.fileSize); + // Now read in the data. + fread(&Z80Ctrl->memory[mzfHeader.loadAddr], mzfHeader.fileSize, 1, ptr); +printf("Memcpy:%x,%x\n", mzfHeader.loadAddr, mzfHeader.fileSize); + printf("Loaded %s, Size:%04x, Addr:%04x, Exec:%04x\n", fileName, mzfHeader.fileSize, mzfHeader.loadAddr, mzfHeader.execAddr); + } + + // Sync the loaded image from Virtual memory to hard memory. + ioctlCmd.cmd = IOCTL_CMD_SYNC_TO_HOST_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + // Resume Z80 processing. + // + ioctlCmd.cmd = IOCTL_CMD_Z80_CONTINUE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + else + printf("Couldnt open file\n"); + + return ret; +} + +// Method to request basic Z80 operations. +// +int ctrlCmd(int fdZ80, enum CTRL_COMMANDS cmd, long param1, long param2, long param3) +{ + // Locals. + struct ioctlCmd ioctlCmd; + uint32_t idx; + int ret = 0; + + switch(cmd) + { + case Z80_CMD_STOP: + // Use IOCTL to request Z80 to Stop (power off) processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_START: + // Use IOCTL to request Z80 to Start (power on) processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_START; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_PAUSE: + // Use IOCTL to request Z80 to pause processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_PAUSE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_CONTINUE: + // Use IOCTL to request Z80 continue processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_CONTINUE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_RESET: + // Use IOCTL to request Z80 reset. + ioctlCmd.cmd = IOCTL_CMD_Z80_RESET; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_SPEED: + // Check value is in range. + for(idx=1; idx < 256; idx+=idx) + { + if((uint32_t)param1 == idx) break; + } + if(idx == 256) + { + printf("Speed factor is illegal. It must be a multiple value of the original CPU clock, ie. 1x, 2x, 4x etc\n"); + ret = -1; + } else + { + // Use IOCTL to request Z80 cpu freq change. + ioctlCmd.speed.speedMultiplier = (uint32_t)param1; + ioctlCmd.cmd = IOCTL_CMD_Z80_CPU_FREQ; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case CPLD_CMD_SEND_CMD: + // Build up the IOCTL command to request the given data is sent to the CPLD. + ioctlCmd.cmd = IOCTL_CMD_CPLD_CMD; + ioctlCmd.cpld.cmd = (uint32_t)param1; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_DUMP_MEMORY: + // If virtual memory, we can dump it via the shared memory segment. + if((uint8_t)param1) + { + memoryDump((uint32_t)param2, (uint32_t)param3, (uint8_t)param1, (uint8_t)param1 == 2 || (uint8_t)param1 == 3 ? 32 : 8, (uint32_t)param2, 0); + } else + { + // Build an IOCTL command to get the driver to dump the memory. + ioctlCmd.cmd = IOCTL_CMD_DUMP_MEMORY; + ioctlCmd.addr.start = (uint32_t)param2; + ioctlCmd.addr.end = (uint32_t)param2+(uint32_t)param3; + ioctlCmd.addr.size = (uint32_t)param3; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case Z80_CMD_HOST_RAM: + // Use IOCTL to request change to host RAM. + ioctlCmd.cmd = IOCTL_CMD_USE_HOST_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_VIRTUAL_RAM: + // Use IOCTL to request change to host RAM. + ioctlCmd.cmd = IOCTL_CMD_USE_VIRTUAL_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_MEMORY_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_Z80_MEMTEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case CPLD_CMD_PRL_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_PRL_TEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case CPLD_CMD_SPI_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_SPI_TEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + + default: + printf("Command not supported!\n"); + ret = -1; + break; + } + + return ret; +} + +// Method to perform some simple tests on the Z80 emulator. +// +int z80test(int fdZ80) +{ + // Locals. + struct ioctlCmd ioctlCmd; + int ret = 0; + + // Stop the Z80. + // +printf("Send STOP\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + FILE *ptr; + ptr = fopen("/customer/mz700.rom", "rb"); + if(ptr) + { + fread(&Z80Ctrl->memory, 65536, 1, ptr); + } else printf("Couldnt open file\n"); + + // Configure the Z80. + // +printf("Send SETPC\n"); + ioctlCmd.z80.pc = 0; + ioctl(fdZ80, IOCTL_CMD_SETPC, &ioctlCmd); + + memoryDump(0 , 65536, 1, 8, 0, 0); + + // Start the Z80. + // +printf("Send START\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_START; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + delay(10); + +printf("Send STOP\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + memoryDump(0, 65536, 1, 8, 0, 0); +out: + return ret; +} + +// Output usage screen. So mamy commands you do need to be prompted!! +void showArgs(char *progName, struct optparse *options) +{ + printf("%s %s %s %s\n\n", progName, VERSION, COPYRIGHT, AUTHOR); + printf("Synopsis:\n"); + printf("%s --help # This help screen.\n", progName); + printf(" --cmd = RESET # Reset the Z80\n"); + printf(" = STOP # Stop and power off the Z80\n"); + printf(" = START # Power on and start the Z80\n"); + printf(" = PAUSE # Pause running Z80\n"); + printf(" = CONTINUE # Continue Z80 execution\n"); + printf(" = HOSTRAM # Use HOST DRAM\n"); + printf(" = VIRTRAM # Use Virtual RAM\n"); + printf(" = SPEED --speed <1, 2, 4, 8, 16, 32, 64, 128> # In Virtual RAM mode, set CPU speed to base clock x factor.\n"); + printf(" = LOADMZF --file # Load MZF file into memory.\n"); + printf(" = DUMP --start <24bit addr> --end <24bit addr> --virtual <0 - Host RAM, 1 = Virtual RAM, 2 = PageTable, 3 = IOPageTable>\n"); + printf(" = CPLDCMD --data <32bit command> # Send adhoc 32bit command to CPLD.\n"); + printf(" = Z80TEST # Perform various debugging tests\n"); + printf(" = SPITEST # Perform SPI testing\n"); + printf(" = PRLTEST # Perform Parallel Bus testing\n"); + printf(" = Z80MEMTEST # Perform HOST memory tests.\n"); + +} + +int main(int argc, char *argv[]) +{ + int fdZ80; + char buff[64]; + char cmd[64] = { 0 }; + char fileName[256] = { 0 }; + int opt; + long hexData = 0; + long speedMultiplier = 1; + long startAddr = 0x0000; + long endAddr = 0x1000; + int virtualMemory = 0; + int helpFlag = 0; + int verboseFlag = 0; + + // Define parameters to be processed. + struct optparse options; + static struct optparse_long long_options[] = + { + {"help", 'h', OPTPARSE_NONE}, + {"cmd", 'c', OPTPARSE_REQUIRED}, + {"file", 'f', OPTPARSE_REQUIRED}, + {"data", 'd', OPTPARSE_REQUIRED}, + {"speed", 'S', OPTPARSE_REQUIRED}, + {"virtual", 'V', OPTPARSE_REQUIRED}, + {"start", 's', OPTPARSE_REQUIRED}, + {"end", 'e', OPTPARSE_REQUIRED}, + {"verbose", 'v', OPTPARSE_NONE}, + {0} + }; + + // Parse the command line options. + // + optparse_init(&options, argv); + while((opt = optparse_long(&options, long_options, NULL)) != -1) + { + switch(opt) + { + // Hex data. + case 'd': + hexData = strtol(options.optarg, NULL, 0); + //printf("Hex data:%08x\n", hexData); + break; + + // Start address for memory operations. + case 's': + startAddr = strtol(options.optarg, NULL, 0); + //printf("Start Addr:%04x\n", startAddr); + break; + + // Speed multiplication factor for CPU governor when running in virtual memory. + case 'S': + speedMultiplier = strtol(options.optarg, NULL, 0); + //printf("Speed = base freq x %d\n", speedFactor); + break; + + // End address for memory operations. + case 'e': + endAddr = strtol(options.optarg, NULL, 0); + //printf("End Addr:%04x\n", endAddr); + break; + + // Virtual memory flag, 0 = host, 1 = virtual memory, 2 = page table, 3 = iopage table. + case 'V': + virtualMemory = atoi(options.optarg); + break; + + // Filename. + case 'f': + strcpy(fileName, options.optarg); + break; + + // Command to execute. + case 'c': + strcpy(cmd, options.optarg); + break; + + // Verbose mode. + case 'v': + verboseFlag = 1; + break; + + // Command help needed. + case 'h': + helpFlag = 1; + showArgs(argv[0], &options); + break; + + // Unrecognised, show synopsis. + case '?': + showArgs(argv[0], &options); + printf("%s: %s\n", argv[0], options.errmsg); + return(1); + } + } + + // Open the z80drv driver and attach to its shared memory, basically the Z80 control structure which includes the virtual Z80 memory. + fdZ80 = open(DEVICE_FILENAME, O_RDWR|O_NDELAY); + if(fdZ80 >= 0) + { + Z80Ctrl = (t_Z80Ctrl *)mmap(0, sizeof(t_Z80Ctrl), PROT_READ | PROT_WRITE, MAP_SHARED, fdZ80, 0); + if(Z80Ctrl == (void *)-1) + { + printf("Failed to attach to the Z80 Control structure, cannot continue, exitting....\n"); + close(fdZ80); + exit(1); + } + } else + { + printf("Failed to open the Z80 Driver, exitting...\n"); + exit(1); + } + + // Basic string to method mapping. Started off with just 1 or two but has grown, may need a table! + if(strcasecmp(cmd, "LOADMZF") == 0) + { + z80load(fdZ80, fileName); + } else + if(strcasecmp(cmd, "RESET") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_RESET, 0, 0, 0); + } else + if(strcasecmp(cmd, "STOP") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_STOP, 0, 0, 0); + } else + if(strcasecmp(cmd, "START") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_START, 0, 0, 0); + } else + if(strcasecmp(cmd, "PAUSE") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_PAUSE, 0, 0, 0); + } else + if(strcasecmp(cmd, "CONTINUE") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_CONTINUE, 0, 0, 0); + } else + if(strcasecmp(cmd, "SPEED") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_SPEED, speedMultiplier, 0, 0); + } else + if(strcasecmp(cmd, "DUMP") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_DUMP_MEMORY, virtualMemory, startAddr, (endAddr - startAddr)); + } else + if(strcasecmp(cmd, "HOSTRAM") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_HOST_RAM, 0, 0, 0); + } else + if(strcasecmp(cmd, "VIRTRAM") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_VIRTUAL_RAM, 0, 0, 0); + } else + if(strcasecmp(cmd, "CPLDCMD") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_SEND_CMD, hexData, 0, 0); + } else + + // Test methods, if the code is built-in to the driver. + if(strcasecmp(cmd, "Z80TEST") == 0) + { + z80test(fdZ80); + } else + if(strcasecmp(cmd, "SPITEST") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_SPI_TEST, 0, 0, 0); + } else + if(strcasecmp(cmd, "PRLTEST") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_PRL_TEST, 0, 0, 0); + } else + if(strcasecmp(cmd, "Z80MEMTEST") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_MEMORY_TEST, 0, 0, 0); + } + else + { + showArgs(argv[0], &options); + printf("No command given, nothing done!\n"); + } + + // Unmap shared memory and close the device. + munmap(Z80Ctrl, sizeof(t_Z80Ctrl)); + close(fdZ80); + + return(0); +} diff --git a/software/FusionX/src/driver/MZ700/z80driver.c b/software/FusionX/src/driver/MZ700/z80driver.c new file mode 100644 index 000000000..6ed61f9e5 --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80driver.c @@ -0,0 +1,1477 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80driver.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Driver +// This file contains the methods used to create a linux device driver which provides +// the services of a Z80 CPU emulation and the control of an underlying Z80'less host +// system. In essence this driver is the host Z80 CPU. +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of this driver and in all ways, is compatible with +// the original Z80. +// Copyright: (c) 2019-2022 Philip Smart +// (c) 1999-2022 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" +#include "z80menu.h" +#include "z80driver.h" + +#include +#include +#include + +/* Meta Information */ +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Philip D Smart"); +MODULE_DESCRIPTION("Z80 CPU Emulator and Hardware Interface Driver"); + +/* Global variables for the threads */ +static struct task_struct *kthread_z80; +static int threadId_z80 = 1; + +// Device class and major numbers. +static struct class *class; +static struct device *device; +static int major; + +// CPU Instance. +static Z80 Z80CPU; + +// Z80 Control data. +static t_Z80Ctrl *Z80Ctrl = NULL; + +// Runtime control of the CPU. As the CPU runs in a detached thread on core 1, the cpu needs to be suspended before any external +// operations can take place. This is achieved with the runtime mutex. +enum Z80_RUN_STATES Z80RunMode; +static struct mutex Z80RunModeMutex; +static DEFINE_MUTEX(Z80DRV_MUTEX); + + +//------------------------------------------------------------------------------------------------------------------------------- +// +// Z80 CPU Kernel Logic. +// +// THe Z80 CPU is initialised and set running, processing instructions either from the underlying host hardware or internal +// memory. The configuration and flow is controlled via the Z80Ctrl structure which is User Space accessible. +// +//------------------------------------------------------------------------------------------------------------------------------- + +// Method to read a byte from physical hardware or internal virtual memory/devices. +// The page table indicates the source and the read is processed accordingly. +static zuint8 z80_read(void *context, zuint16 address) +{ + // Locals. + // + zuint8 data; + uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + Z_UNUSED(context) + + // Only read if the address is in physical RAM. + if(isPhysical(address)) + { + // Commence cycle to retrieve the data from Real RAM. + // Optimise SPI according to last address sent to CPLD. + if(addrDiff >=0 && addrDiff < 8) + { + SPI_SEND8((CPLD_CMD_READ_ADDR + addrDiff)); + Z80Ctrl->z80PrevAddr += addrDiff; + } else + { + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = address; + } + while(CPLD_READY() == 0); + data = READ_CPLD_DATA_IN(); + + // Pause until the Last T-State is detected. + while(CPLD_LAST_TSTATE() == 0); + } + else if(isVirtualHW(address)) + { + // Virtual Hardware - call the handler. + switch(realAddress(address)) + { + default: + break; + } + } + else if(isVirtualMemory(address)) + { + // Retrieve data from virtual memory. + data = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + } + + // Keyport data? Store. + if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 8 && (data & 0x41) == 0) + { + Z80Ctrl->keyportShiftCtrl = 0x01; + } else + if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 0 && (data & 0x80) == 0) + { + Z80Ctrl->keyportHotKey = 0x01; + } + return(data); +} + +// Method to write a byte to physical hardware or internal virtual memory or devices. +// The page table indicates the target and the write is processed accordingly. +static void z80_write(void *context, zuint16 address, zuint8 data) +{ + // Locals. + uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + Z_UNUSED(context) + + // To detect Hotkey presses, we need to store the keboard strobe data and on keydata read. + if(isHW(address) && address == 0xE000) + { + Z80Ctrl->keyportStrobe = data; + } + + // Write to physical host? + if(isPhysical(address)) + { + // Commence cycle to write the data to real RAM. + // Optimise SPI according to last address sent to CPLD. + if(addrDiff >=0 && addrDiff < 8) + { + SPI_SEND16((data << 8) | (CPLD_CMD_WRITE_ADDR + addrDiff)); + Z80Ctrl->z80PrevAddr += addrDiff; + } else + { + SPI_SEND32((uint32_t)address << 16 | data << 8 | CPLD_CMD_WRITE_ADDR); + Z80Ctrl->z80PrevAddr = address; + } + + // Write-thru to virtual memory if we update real memory. + // if(isPhysicalRAM(address)) + // writeVirtualRAM(address, data); + + // Pause until the Last T-State is detected. + while(CPLD_LAST_TSTATE() == 0); + } + else if(isVirtualHW(address)) + { + // Virtual Hardware - call the handler. + switch(realAddress(address)) + { + default: + break; + } + } + else if(isVirtualRAM(address)) + { + // Update virtual memory. + writeVirtualRAM(address, data); + } + // Cannot write to virtual ROM so no logic. +} + +// Primary Opcode fetch method. This method is called each time a single or multi-byte opcode is +// encountered. Opcode data is retrieved via the z80_fetch method. +// +// Depending on the address and the configured page map, the opcode is fetched from hardware +// or internal virtual memory. As this method is the primary timing method for Z80 instructions +// (read/write methods dont affect the timing so much as long as they operate in less than the read/write +// cycle of an original Z80). +// Initially the timing on the virtual memory is set by a governor delay but this will be updated to a more +// precise M/T-State cycle per instruction type delay. +static zuint8 z80_fetch_opcode(void *context, zuint16 address) +{ + // Locals. + zuint8 opcode = 0x00; + uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + volatile uint32_t idx; // Leave as volatile otherwise optimiser will optimise out the delay code. + Z_UNUSED(context) + + // Normally only opcode fetches occur in RAM but allow any physical address as it could be a Z80 programming trick. + if(isPhysical(address)) + { + // Commence cycle to fetch the opcode from potentially Real RAM albeit it could be any physical hardware. + // Optimise SPI according to last address sent to CPLD. + if(addrDiff >=0 && addrDiff < 8) + { + SPI_SEND8((CPLD_CMD_FETCH_ADDR + addrDiff)); + Z80Ctrl->z80PrevAddr += addrDiff; + } else + { + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_FETCH_ADDR); + Z80Ctrl->z80PrevAddr = address; + } + while(CPLD_READY() == 0); + opcode = READ_CPLD_DATA_IN(); + + // Pause until the Last T-State is detected. + while(CPLD_LAST_TSTATE() == 0); + } else + // Virtual fetches only occur in memory as we are not emulating original hardware. + if(isVirtualMemory(address)) + { + for(idx=0; idx < Z80Ctrl->cpuGovernorDelay; idx++); + + // Retrieve data from virtual memory. + opcode = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + } + return(opcode); +} + +// Method similar to z80_read, kept seperate to avoid additional what-if logic and doesnt require virtual hardware logic. +// +static zuint8 z80_fetch(void *context, zuint16 address) +{ + // Locals. + // + zuint8 data = 0x00; + uint16_t addrDiff = (uint16_t)address - Z80Ctrl->z80PrevAddr; + Z_UNUSED(context) + + // Normally only opcode fetches occur in RAM but allow any physical address as it could be a Z80 programming trick. + if(isPhysical(address)) + { + // Commence cycle to retrieve the data from Real RAM. + // Optimise SPI according to last address sent to CPLD. + if(addrDiff >=0 && addrDiff < 8) + { + SPI_SEND8((CPLD_CMD_READ_ADDR + addrDiff)); + Z80Ctrl->z80PrevAddr += addrDiff; + } else + { + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = address; + } + while(CPLD_READY() == 0); + data = READ_CPLD_DATA_IN(); + + // Pause until the Last T-State is detected. + while(CPLD_LAST_TSTATE() == 0); + } else + if(isVirtualMemory(address)) + { + // Retrieve data from virtual memory. + data = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + } + +// // Keyport data? Store. +// if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 8 && (data & 0x41) == 0) +// { +// Z80Ctrl->keyportShiftCtrl = 0x01; +// } else +// if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 0 && (data & 0x80) == 0) +// { +// Z80Ctrl->keyportHotKey = 0x01; +// } + return(data); +} + +// Method to perform a Z80 input operation. This normally goes to hardware and the CPLD executes the required cycle. +// Some ports are dedicated virtual ports providing virtual services to the host computer/application. These are intercepted +// and processed in this driver. +static zuint8 z80_in(void *context, zuint16 port) +{ + // Locals. + zuint8 value; + uint16_t portDiff = (uint16_t)port - Z80Ctrl->z80PrevPort; + Z_UNUSED(context) + + printk("z80_in\n"); + // Physical port go direct to hardware to retrieve value. + if(isPhysicalIO(port)) + { + // Commence cycle to retrieve the value from the I/O port. Port contains the 16bit BC value. + // Optimise SPI according to last port sent to CPLD. + if(portDiff >=0 && portDiff < 8) + { + SPI_SEND8((CPLD_CMD_READIO_ADDR + portDiff)); + Z80Ctrl->z80PrevPort += portDiff; + } else + { + SPI_SEND32((uint32_t)port << 16 | CPLD_CMD_READIO_ADDR); + Z80Ctrl->z80PrevPort = port; + } + + // Whilst waiting for the CPLD, we now determine if this is a memory management port and update the memory page if required. + switch(port & 0x00FF) + { + // Port is not a memory management port. + default: + break; + } + + // Finally ensure the data from the port is ready and retrieve it. + while(CPLD_READY() == 0); + value = READ_CPLD_DATA_IN(); + } else + // Virtual I/O Port. + { + // Virtual I/O - call the handler. + switch(realPort(port)) + { + default: + value = 0x00; + break; + } + } + return(value); +} + +// Method to perform a Z80 output operation. This normally goes to hardware and the CPLD executes the required cycle. +// Some ports are dedicated virtual ports providing virtual services to the host computer/application. These are intercepted +// and processed in this driver. +// There are also ports which are both hardware and need mirroring in software. These ports, typically memory mapping ports. +// when activated in the hardware need to be mirrored in the page table so correct virtual memory is used when addressed. +static void z80_out(void *context, zuint16 port, zuint8 value) +{ + // Locals. + uint32_t idx; + uint16_t portDiff = (uint16_t)port - Z80Ctrl->z80PrevPort; + Z_UNUSED(context) + + // Physical port go direct to hardware to retrieve value. + if(isPhysicalIO(port)) + { + // Commence cycle to write the value to the I/O port. Port contains the 16bit BC value. + // Optimise SPI according to last port sent to CPLD. + if(portDiff >=0 && portDiff < 8) + { + SPI_SEND16((value << 8) | (CPLD_CMD_WRITEIO_ADDR + portDiff)); + Z80Ctrl->z80PrevPort += portDiff; +//pr_info("OUT:0x%x(%x)=0x%x\n", port, portDiff, value); + } else + { + SPI_SEND32((uint32_t)port << 16 | value << 8 | CPLD_CMD_WRITEIO_ADDR); + Z80Ctrl->z80PrevPort = port; +//pr_info("OUT:0x%x=0x%x\n", port, value); + } + + // Determine if this is a memory management port and update the memory page if required. + switch(port & 0x00FF) + { + // Enable lower 4K block as DRAM + case IO_ADDR_E0: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + break; + + // Enable upper 12K block, including Video/Memory Mapped peripherals area, as DRAM. + case IO_ADDR_E1: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + // MZ-700 mode we only work in first 64K block. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + } + break; + + // Enable Monitor ROM in lower 4K block + case IO_ADDR_E2: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + break; + + // Enable Video RAM and Memory mapped peripherals in upper 12K block. + case IO_ADDR_E3: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Reset to power on condition memory map. + case IO_ADDR_E4: + // Lower 4K set to Monitor ROM. + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + if(!Z80Ctrl->inhibitMode) + { + // Upper 12K to hardware. + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Inhibit. Backup current page data in region 0xD000-0xFFFF and inhibit it. + case IO_ADDR_E5: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + backupMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_INHIBIT, idx); + } + Z80Ctrl->inhibitMode = 1; + break; + + // Restore D000-FFFF to its original state. + case IO_ADDR_E6: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + restoreMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + } + Z80Ctrl->inhibitMode = 0; + break; + + // Port is not a memory management port. + default: + break; + } + } else + if(isVirtualIO(port)) + { + // MZ700 memory mode switch. + // + // MZ-700 + // |0000:0FFF|1000:CFFF|D000:FFFF + // ------------------------------ + // OUT 0xE0 = |DRAM | | + // OUT 0xE1 = | | |DRAM + // OUT 0xE2 = |MONITOR | | + // OUT 0xE3 = | | |Memory Mapped I/O + // OUT 0xE4 = |MONITOR |DRAM |Memory Mapped I/O + // OUT 0xE5 = | | |Inhibit + // OUT 0xE6 = | | | + // + // = Return to the state prior to the complimentary command being invoked. + + // Determine if this is a memory management port and update the memory page if required. + switch(port & 0x00FF) + { + // Enable lower 4K block as DRAM + case IO_ADDR_E0: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + break; + + // Enable upper 12K block, including Video/Memory Mapped peripherals area, as DRAM. + case IO_ADDR_E1: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + // MZ-700 mode we only work in first 64K block. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + } + break; + + // Enable MOnitor ROM in lower 4K block + case IO_ADDR_E2: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + break; + + // Enable Video RAM and Memory mapped peripherals in upper 12K block. + case IO_ADDR_E3: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Reset to power on condition memory map. + case IO_ADDR_E4: + // Lower 4K set to Monitor ROM. + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + if(!Z80Ctrl->inhibitMode) + { + // Upper 12K to hardware. + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Inhibit. Backup current page data in region 0xD000-0xFFFF and inhibit it. + case IO_ADDR_E5: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + backupMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_INHIBIT, idx); + } + Z80Ctrl->inhibitMode = 1; + break; + + // Restore D000-FFFF to its original state. + case IO_ADDR_E6: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + restoreMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + } + Z80Ctrl->inhibitMode = 0; + break; + + // Port is not a memory management port. + default: + break; + } + } else + { + // Virtual I/O - call the handler. + switch(realPort(port)) + { + default: + break; + } + } +} + +// NOP - No Operation method. This instruction is used for timing, padding out an application or during +// HALT cycles to ensure Refresh occurs. +// If the address is configured as hardware (via the page table) then a refresh cycle is requested otherwise +// nothing to be done. +static zuint8 z80_nop(void *context, zuint16 address) +{ + // Locals. + Z_UNUSED(context) + + if(isPhysical(address)) + { + // If autorefresh is not enabled, send a single refresh request. + if(Z80Ctrl->refreshDRAM == 0) + SPI_SEND8(CPLD_CMD_REFRESH); + } + return 0x00; +} + +// HALT - CPU executes a HALT instruction which results in the HALT line going active low and then it enters +// a state executing NOP instructions to ensure DRAM refresh until a reset or INT event. +static void z80_halt(void *context, zboolean state) +{ + // Locals. + Z_UNUSED(context) Z_UNUSED(state) + + // Inform CPLD of halt state. + printk("z80_halt\n"); + SPI_SEND8(CPLD_CMD_HALT); + Z80CPU.cycles = Z80_MAXIMUM_CYCLES; +} + +// Methods below are not yet implemented, Work In Progress! +static zuint8 z80_context(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_context\n"); + return 0x00; +} +static zuint8 z80_nmia(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_nmia\n"); + return 0x00; +} +static zuint8 z80_inta(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_inta\n"); + return 0x00; +} +static zuint8 z80_intFetch(void *context, zuint16 address) +{ + Z_UNUSED(context) + printk("z80_int_fetch\n"); + return 0x00; +} +static void z80_ldia(void *context) +{ + Z_UNUSED(context) + printk("z80_ldia\n"); +} +static void z80_ldra(void *context) +{ + Z_UNUSED(context) + printk("z80_ldra\n"); +} +static void z80_reti(void *context) +{ + Z_UNUSED(context) + printk("z80_reti\n"); +} +static void z80_retn(void *context) +{ + Z_UNUSED(context) + printk("z80_retn\n"); +} +static zuint8 z80_illegal(void *context, zuint8 opcode) +{ + Z_UNUSED(context) + printk("z80_illegal\n"); + return 0x00; +} + +// Z80 CPU Emulation Thread +// ------------------------ +// This is a kernel thread, bound to CPU 1 with IRQ's disabled. +// The Z80 is controlled by a mutex protected variable to define run, stop, pause and terminate modes. +int thread_z80(void * thread_nr) +{ + // Locals. + uint8_t canRun = 0; + int t_nr = *(int *) thread_nr; + //struct sched_param param = {.sched_priority = 99}; + spinlock_t spinLock; + unsigned long flags; + + // Initialise spinlock and disable IRQ's. We should be the only process running on core 1. + spin_lock_init(&spinLock); + spin_lock_irqsave(&spinLock, flags); + + // Assign this emulation to high priority realtime scheduling. Also the task will be assigned to an isolated CPU. + //sched_setscheduler(current, SCHED_RR, ¶m); + + // Run the CPU forever or until a stop occurs. + while(!kthread_should_stop()) + { + // Run the Z80 emulation if enabled. + if(canRun) z80_run(&Z80CPU, 100); + + // Reset pressed? + if(CPLD_RESET()) + { + z80_instant_reset(&Z80CPU); + setupMemory(Z80Ctrl->defaultPageMode); + + // Wait for release before restarting CPU. + while(CPLD_RESET()); + } else + { + // Update state to indicate request has been actioned. + mutex_lock(&Z80RunModeMutex); + if(Z80RunMode == Z80_STOP) Z80RunMode = Z80_STOPPED; + if(Z80RunMode == Z80_PAUSE) Z80RunMode = Z80_PAUSED; + if(Z80RunMode == Z80_CONTINUE) Z80RunMode = Z80_RUNNING; + if(Z80RunMode == Z80_RUNNING) canRun=1; else canRun=0; + mutex_unlock(&Z80RunModeMutex); + + // Hotkey pressed? Bring up user menu. + if(Z80Ctrl->keyportShiftCtrl && Z80Ctrl->keyportHotKey) + { + z80menu(); + Z80Ctrl->keyportShiftCtrl = 0; + Z80Ctrl->keyportHotKey = 0; + } + } + } + + // Release spinlock as we are unloading driver. + spin_unlock_irqrestore(&spinLock, flags); + printk("kthread - Z80 Thread %d finished execution!\n", t_nr); + return 0; +} + + +//------------------------------------------------------------------------------------------------------------------------------- +// +// User space driver access. +// +//------------------------------------------------------------------------------------------------------------------------------- + + +// Device close. +// When a user space application terminates or closes the z80drv device driver, this function is called +// to close any open connections, memory and variables required to handle the user space application +// requests. +static int z80drv_release(struct inode *inodep, struct file *filep) +{ + // Locals. + + mutex_unlock(&Z80DRV_MUTEX); + //pr_info("z80drv: Device successfully closed\n"); + + return(0); +} + +// Device open. +// When a user space application open's the z80drv device driver, this function is called +// to initialise and allocate any required memory or devices prior to servicing requests from the +// user space application. +static int z80drv_open(struct inode *inodep, struct file *filep) +{ + // Locals. + int ret = 0; + + if(!mutex_trylock(&Z80DRV_MUTEX)) + { + pr_alert("z80drv: device busy!\n"); + ret = -EBUSY; + goto out; + } + + //pr_info("z80drv: Device opened\n"); + +out: + return(ret); +} + +// Map shared memory. +// The z80drv allocates on the stack a chunk of memory and control variables which is used to control the Z80 Emulation state +// and provide it with internal 'virtual memory'. This virtual memory is either used as the core Z80 memory or as banked extensions +// to the host DRAM. +// The user space application is able to bind with the shared memory to perform tasks such as load/save of applications. +static int z80drv_mmap(struct file *filp, struct vm_area_struct *vma) +{ + // Locals. + int ret = 0; + struct page *page = NULL; + unsigned long size = (unsigned long)(vma->vm_end - vma->vm_start); + + // Make sure requested size is within range of the Z80 control structure. The kernel may page align it so the size may be bigger than + // the structure. + if(size < sizeof(t_Z80Ctrl) || size > sizeof(t_Z80Ctrl)*2) + { + ret = -EINVAL; + goto out; + } + + // Map the memory and exit. + page = virt_to_page((unsigned long)Z80Ctrl + (vma->vm_pgoff << PAGE_SHIFT)); + ret = remap_pfn_range(vma, vma->vm_start, page_to_pfn(page), size, vma->vm_page_prot); + if (ret != 0) + { + goto out; + } + +out: + return ret; +} + +// Device read. +// This method allows an application which opens the z80drv driver to read data in a stream. It is here for +// possible future use. +static ssize_t z80drv_read(struct file *filep, char *buffer, size_t len, loff_t *offset) +{ + // Locals. + int ret; + + if (len > Z80_VIRTUAL_RAM_SIZE) + { + pr_info("read overflow!\n"); + ret = -EFAULT; + goto out; + } + + if (copy_to_user(buffer, Z80Ctrl, len) == 0) + { + pr_info("z80drv: copy %u char to the user\n", len); + ret = len; + } else + { + ret = -EFAULT; + } + +out: + return ret; +} + +// Device write. +// This method allows an application which opens the z80drv driver to write stream data. It is here for +// possible future use. +static ssize_t z80drv_write(struct file *filep, const char *buffer, size_t len, loff_t *offset) +{ + // Locals. + int ret; + + if (copy_from_user(Z80Ctrl, buffer, len)) + { + pr_err("z80drv: write fault!\n"); + ret = -EFAULT; + goto out; + } + pr_info("z80drv: copy %d char from the user\n", len); + ret = len; + +out: + return ret; +} + +// Function to dump out a given section of the physical host memory. +// +int memoryDump(uint32_t memaddr, uint32_t memsize, uint32_t dispaddr, uint8_t dispwidth) +{ + uint8_t displayWidth = dispwidth; + uint32_t pnt = memaddr; + uint32_t endAddr = memaddr + memsize; + uint32_t addr = dispaddr; + uint8_t data; + uint32_t i = 0; + int result = -1; + char c = 0; + + // If not set, calculate output line width according to connected display width. + // + if(displayWidth == 0) + { + switch(MAX_SCREEN_WIDTH) + { + case 40: + displayWidth = 8; + break; + case 80: + displayWidth = 16; + break; + default: + displayWidth = 32; + break; + } + } + + while (1) + { + printk(KERN_INFO "%08X", addr); // print address + printk(KERN_CONT ": "); + + // print hexadecimal data + for (i=0; i < displayWidth; ) + { + if(pnt+i < endAddr) + { + SPI_SEND32((uint16_t)(pnt+i) << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = pnt+i; + while(CPLD_READY() == 0); + data = READ_CPLD_DATA_IN(); + printk(KERN_CONT "%02X", data); + } + else + printk(KERN_CONT " "); + i++; + + printk(KERN_CONT " "); + } + + // print ascii data + printk(KERN_CONT " |"); + + // print single ascii char + for (i=0; i < displayWidth; i++) + { + SPI_SEND32((uint16_t)(pnt+i) << 16 | CPLD_CMD_READ_ADDR); + Z80Ctrl->z80PrevAddr = pnt+i; + while(CPLD_READY() == 0); + c = (char)READ_CPLD_DATA_IN(); + if ((pnt+i < endAddr) && (c >= ' ') && (c <= '~')) + printk(KERN_CONT "%c", (char)c); + else + printk(KERN_CONT " "); + } + + printk(KERN_CONT "|\n"); + + // Move on one row. + pnt += displayWidth; + addr += displayWidth; + + // End of buffer, exit the loop. + if(pnt >= (memaddr + memsize)) + { + break; + } + } + + return(result); +} + +// Method to setup a default memory/IO profile. This profile will be changed by the host processing and also can be tweaked +// by the z80ctrl application. +// +void setupMemory(enum Z80_MEMORY_PROFILE mode) +{ + // Locals. + uint32_t idx; + + if(mode == USE_PHYSICAL_RAM) + { + // Initialise the page pointers and memory to use physical RAM. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x1000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + else if(idx >= 0x1000 && idx < 0xD000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + + // Video RAM labelled as HW as we dont want to cache it. + else if(idx >= 0xD000 && idx < 0xE000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + for(idx=0x0000; idx < 0x10000; idx++) + { + Z80Ctrl->iopage[idx] = idx | IO_TYPE_PHYSICAL_HW; + } + // Cancel refresh as using physical RAM for program automatically refreshes DRAM. + Z80Ctrl->refreshDRAM = 0; + } + else if(mode == USE_VIRTUAL_RAM) + { + // Initialise the page pointers and memory to use virtual RAM. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x1000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + else if(idx >= 0x1000 && idx < 0xD000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + + // Video RAM labelled as HW as we dont want to cache it. + else if(idx >= 0xD000 && idx < 0xE000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + for(idx=0x0000; idx < 0x10000; idx++) + { + if((idx & 0x00FF) >= IO_ADDR_E0 && (idx & 0x00FF) < IO_ADDR_E7) + Z80Ctrl->iopage[idx] = idx | IO_TYPE_VIRTUAL_HW; + else + Z80Ctrl->iopage[idx] = idx | IO_TYPE_PHYSICAL_HW; + } + // Enable refresh as using virtual RAM stops refresh of host DRAM. + Z80Ctrl->refreshDRAM = 1; + } + + // Enable autorefresh if refreshDRAM is set. + SPI_SEND8(Z80Ctrl->refreshDRAM == 1 ? CPLD_CMD_SET_AUTO_REFRESH : CPLD_CMD_CLEAR_AUTO_REFRESH); + + // Inhibit mode disabled. + Z80Ctrl->inhibitMode = 0; + return; +} + +// IOCTL Method +// This method allows User Space application to control the Z80 CPU and internal functionality of the +// device driver. This is the preferred control method along with the shared memory segment for the driver. +static long int z80drv_ioctl(struct file *file, unsigned cmd, unsigned long arg) +{ + // Locals. + struct ioctlCmd ioctlCmd; + uint16_t idx; + uint32_t tmp; + enum Z80_RUN_STATES currentRunMode; + enum Z80_RUN_STATES nextRunMode; + + // Get current running mode so any operations on the Z80 return it to original mode unless action overrides it. + mutex_lock(&Z80RunModeMutex); currentRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + + switch(cmd) + { + // Basic commands. + case IOCTL_CMD_SEND: + if(copy_from_user(&ioctlCmd, (int32_t *)arg, sizeof(ioctlCmd))) + printk("IOCTL - Couldnt retrieve command!\n"); + else + { + //printk("IOCTL - Command (%08x)\n", ioctlCmd.cmd); + switch(ioctlCmd.cmd) + { + // Command to stop the Z80 CPU and power off. + case IOCTL_CMD_Z80_STOP: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + z80_power(&Z80CPU, FALSE); + Z80_PC(Z80CPU) = 0; + printk("Z80 stopped.\n"); + break; + + // Command to power on and start the Z80 CPU. + case IOCTL_CMD_Z80_START: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_RUNNING; mutex_unlock(&Z80RunModeMutex); + + z80_power(&Z80CPU, TRUE); + printk("Z80 started.\n"); + break; + + // Command to pause the Z80. + case IOCTL_CMD_Z80_PAUSE: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_PAUSE; mutex_unlock(&Z80RunModeMutex); + printk("Z80 paused.\n"); + break; + + // Command to release a paused Z80. + case IOCTL_CMD_Z80_CONTINUE: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_CONTINUE; mutex_unlock(&Z80RunModeMutex); + printk("Z80 running.\n"); + break; + + // Command to perform a CPU reset. + case IOCTL_CMD_Z80_RESET: + // Stop the CPU prior to reset. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + z80_instant_reset(&Z80CPU); + setupMemory(Z80Ctrl->defaultPageMode); + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Reset.\n"); + break; + + // Command to setup the page table to use host memory and physical hardware. + case IOCTL_CMD_USE_HOST_RAM: + // Stop the CPU prior to memory reconfiguration. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80Ctrl->defaultPageMode = USE_PHYSICAL_RAM; + setupMemory(Z80Ctrl->defaultPageMode); + z80_instant_reset(&Z80CPU); + + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Set to use Host Memory.\n"); + break; + + // Command to setup the page table to use virtual memory, only physical hardware is accessed on the host. + case IOCTL_CMD_USE_VIRTUAL_RAM: + // Stop the CPU prior to memory reconfiguration. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80Ctrl->defaultPageMode = USE_VIRTUAL_RAM; + setupMemory(Z80Ctrl->defaultPageMode); + z80_instant_reset(&Z80CPU); + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Set to use Virtual Memory.\n"); + break; + + // Command to synchronise virtual memory to host DRAM. + case IOCTL_CMD_SYNC_TO_HOST_RAM: + // Stop the CPU prior to memory sync. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Copy virtual memory to host DRAM. + for(idx=0x1000; idx < 0xD000; idx++) + { + SPI_SEND32((uint32_t)idx << 16 | Z80Ctrl->memory[idx] << 8 | CPLD_CMD_WRITE_ADDR); + } + + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Z80 Host DRAM syncd with Virtual Memory.\n"); + break; + + // Command to dump out host memory. + case IOCTL_CMD_DUMP_MEMORY: + // Need to suspend the Z80 otherwise we will get memory clashes. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_PAUSE; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_PAUSE); + + // Dump out the physical memory address. + memoryDump(ioctlCmd.addr.start, ioctlCmd.addr.end - ioctlCmd.addr.start, ioctlCmd.addr.start, 0); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to set the governor delay to approximate real Z80 cpu frequencies when running in virtual memory. + case IOCTL_CMD_Z80_CPU_FREQ: + switch(ioctlCmd.speed.speedMultiplier) + { + case 2: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_7MHZ; + break; + + case 4: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_14MHZ; + break; + + case 8: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_28MHZ; + break; + + case 16: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_56MHZ; + break; + + case 32: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_112MHZ; + break; + + case 64: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_224MHZ; + break; + + case 128: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_448MHZ; + break; + + case 1: + default: + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_3_54MHZ; + break; + } + break; + + // Command to set the Z80 CPU Program Counter value. + case IOCTL_CMD_SETPC: + // Stop the CPU prior to PC change. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80_PC(Z80CPU) = ioctlCmd.z80.pc; + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + printk("Set PC to %04x\n", ioctlCmd.z80.pc); + break; + + // Method to send adhoc commands to the CPLD, ie for switching active display etc. + case IOCTL_CMD_CPLD_CMD: + // Stop the CPU prior to sending a direct command to the CPLD. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Send the command, small delay then send NOP to retrieve the response. + SPI_SEND32(ioctlCmd.cpld.cmd); + udelay(10); + z80io_SPI_Send32(0x00000000, &tmp); + pr_info("CPLD RX:%08x\n", tmp); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of SOM to CPLD SPI tests. + case IOCTL_CMD_SPI_TEST: + // Stop the CPU prior to SPI testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform SPI Tests. + z80io_SPI_Test(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of SOM to CPLD Parallel Bus tests. + case IOCTL_CMD_PRL_TEST: + // Stop the CPU prior to SPI testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform Parallel Bus tests. + z80io_PRL_Test(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of Z80 host memory tests to assess the performance of the SOM->CPLD interface. + case IOCTL_CMD_Z80_MEMTEST: + // Stop the CPU prior to Host memory testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform host memory tests. + z80io_Z80_TestMemory(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + default: + break; + } + } + break; + + default: + printk("IOCTL - Unhandled Command (%08x)\n", ioctlCmd.cmd); + break; + + } + return 0; +} + +// Structure to declare public API methods. +// Standard Linux device driver structure to declare accessible methods within the driver. +static const struct file_operations z80drv_fops = { + .open = z80drv_open, + .read = z80drv_read, + .write = z80drv_write, + .release = z80drv_release, + .mmap = z80drv_mmap, + .unlocked_ioctl = z80drv_ioctl, + .owner = THIS_MODULE, +}; + +// Initialisation. +// This is the entry point into the device driver when loaded into the kernel. +// The method intialises any required hardware (ie. GPIO's, SPI etc), memory and the Z80 +// Emulation. It also allocates the Major and Minor device numbers and sets up the +// device in /dev. +static int __init ModuleInit(void) +{ + // Locals. + int idx; + int ret = 0; + + // Setup the Z80 handlers. + Z80CPU.context = z80_context; + Z80CPU.fetch = z80_fetch; + Z80CPU.fetch_opcode = z80_fetch_opcode; + Z80CPU.read = z80_read; + Z80CPU.write = z80_write; + Z80CPU.nop = z80_nop; + Z80CPU.in = z80_in; + Z80CPU.out = z80_out; + Z80CPU.halt = z80_halt; + Z80CPU.nmia = z80_nmia; + Z80CPU.inta = z80_inta; + Z80CPU.int_fetch = z80_intFetch; + Z80CPU.ld_i_a = z80_ldia; + Z80CPU.ld_r_a = z80_ldra; + Z80CPU.reti = z80_reti; + Z80CPU.retn = z80_retn; + Z80CPU.illegal = z80_illegal; + + mutex_init(&Z80DRV_MUTEX); + + // Get device Major number. + major = register_chrdev(0, DEVICE_NAME, &z80drv_fops); + if (major < 0) { + pr_info("z80drv: fail to register major number!"); + ret = major; + goto initExit; + } + + class = class_create(THIS_MODULE, CLASS_NAME); + if (IS_ERR(class)){ + unregister_chrdev(major, DEVICE_NAME); + pr_info("z80drv: failed to register device class"); + ret = PTR_ERR(class); + goto initExit; + } + + device = device_create(class, NULL, MKDEV(major, 0), NULL, DEVICE_NAME); + if (IS_ERR(device)) { + class_destroy(class); + unregister_chrdev(major, DEVICE_NAME); + ret = PTR_ERR(device); + goto initExit; + } + + // Allocate the Z80 memory to be shared between this kernel space driver and the controlling user space application. + Z80Ctrl = (t_Z80Ctrl *)kmalloc(sizeof(t_Z80Ctrl), GFP_KERNEL); + if (Z80Ctrl == NULL) + { + pr_info("z80drv: failed to allocate memory!"); + ret = -ENOMEM; + goto initExit; + } + + // Initialise the hardware to host interface. + z80io_init(); + + // Initialise the virtual RAM from the HOST DRAM. This is to maintain compatibility as some applications (in my experience) have + // bugs, which Im putting down to not initialising variables. The host DRAM is in a pattern of 0x00..0x00, 0xFF..0xFF repeating + // when first powered on. + for(idx=0; idx < Z80_VIRTUAL_RAM_SIZE; idx++) + { + if(idx >= 0x1000 && idx < 0xD000) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->memory[idx] = z80io_PRL_Read8(1); + } else + { + Z80Ctrl->memory[idx] = 0x00; + } + } + Z80Ctrl->memory[0x1200] = 0x01; + Z80Ctrl->memory[0x1201] = 0x86; + Z80Ctrl->memory[0x1202] = 0xf2; + Z80Ctrl->memory[0x1203] = 0x3e; + Z80Ctrl->memory[0x1204] = 0x15; + Z80Ctrl->memory[0x1205] = 0x3d; + Z80Ctrl->memory[0x1206] = 0x20; + Z80Ctrl->memory[0x1207] = 0xfd; + Z80Ctrl->memory[0x1208] = 0x0b; + Z80Ctrl->memory[0x1209] = 0x78; + Z80Ctrl->memory[0x120a] = 0xb1; + Z80Ctrl->memory[0x120b] = 0x20; + Z80Ctrl->memory[0x120c] = 0xf6; + Z80Ctrl->memory[0x120d] = 0xc3; + Z80Ctrl->memory[0x120e] = 0x00; + Z80Ctrl->memory[0x120f] = 0x00; + + // Copy the host BIOS into the Virtual RAM. + for(idx=0; idx < 0x1000; idx++) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->memory[Z80_VIRTUAL_RAM_SIZE+idx] = z80io_PRL_Read8(1); + } + + // Setup Refresh so that an automatic refresh mode is performed by the CPLD whilst running in Virtual memory. This is necessary as opcode fetches from + // host memory, by the CPLD, normally performs the refresh and when running in virtual memory, these refresh cycles arent performed. + Z80Ctrl->refreshDRAM = 1; + + // Setup the governor delay, it is the delay per opcode fetch to restrict the Z80 CPU to a given speed. + Z80Ctrl->cpuGovernorDelay = MZ700_INSTRUCTION_DELAY_3_54MHZ; + + // Setup the default Page Mode. This is needed if an event such as a reset occurs which needs to return the page and iotable back to default. + Z80Ctrl->defaultPageMode = USE_VIRTUAL_RAM; + + // Setup memory profile to use internal virtual RAM (SOM kernel RAM rather than HOST DRAM). + setupMemory(Z80Ctrl->defaultPageMode); + + // Initialse run control. + mutex_init(&Z80RunModeMutex); + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + + // Setup the address and port history for communicating addresses to the CPLD. Used to shorten the instruction length to increase latency. + Z80Ctrl->z80PrevAddr = 0xFFFF; + Z80Ctrl->z80PrevPort = 0xFFFF; + + // Initialse hotkey detection variables. + Z80Ctrl->keyportStrobe = 0x00; + Z80Ctrl->keyportShiftCtrl = 0x00; + Z80Ctrl->keyportHotKey = 0x00; + + // PC to start and power on the CPU + Z80_PC(Z80CPU) = 0; + z80_power(&Z80CPU, TRUE); + + // Create thread to run the Z80 cpu. + kthread_z80 = kthread_create(thread_z80, &threadId_z80, "kthread_z80"); + if(kthread_z80 != NULL) + { + printk("kthread - Thread Z80 was created, waking...!\n"); + kthread_bind(kthread_z80, 1); + wake_up_process(kthread_z80); + } + else { + printk("kthread - Thread Z80 could not be created!\n"); + ret = -1; + goto initExit; + } + +initExit: + return ret; +} + +// Exit +// This method is called when the device driver is removed from the kernel with the rmmod command. +// It is responsible for closing and freeing all allocated memory, terminating all threads and removing +// the device from the /dev directory. +static void __exit ModuleExit(void) +{ + // Stop the internal threads. + //printk("kthread - Stop Z80 thread\n"); + kthread_stop(kthread_z80); + + // Return the memory used for the Z80 'virtual memory' and control variables. + kfree(Z80Ctrl); + + // Nothing to be done for the hardware. + + // Cleanup and remove the device. + mutex_destroy(&Z80DRV_MUTEX); + device_destroy(class, MKDEV(major, 0)); + class_unregister(class); + class_destroy(class); + unregister_chrdev(major, DEVICE_NAME); + + //pr_info("z80drv: unregistered!\n"); +} + +module_init(ModuleInit); +module_exit(ModuleExit); diff --git a/software/FusionX/src/driver/MZ700/z80driver.h b/software/FusionX/src/driver/MZ700/z80driver.h new file mode 100644 index 000000000..ede3d0db0 --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80driver.h @@ -0,0 +1,284 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80driver.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Driver +// This file contains the declarations used in the z80drv device driver. +// +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of this driver and in all ways, is compatible with +// the original Z80. +// Copyright: (c) 2019-2022 Philip Smart +// (c) 1999-2022 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80DRIVER_H +#define Z80DRIVER_H + +// Constants. +#define Z80_VIRTUAL_ROM_SIZE 16384 // Sized to maximum ROM which is the MZ-800 ROM. +#define Z80_VIRTUAL_RAM_SIZE (65536 * 8) // (PAGE_SIZE * 2) // max size mmaped to userspace +#define Z80_VIRTUAL_MEMORY_SIZE Z80_VIRTUAL_RAM_SIZE + Z80_VIRTUAL_ROM_SIZE +#define Z80_MEMORY_PAGE_SIZE 16 +#define MAX_SCREEN_WIDTH 132 +#define DEVICE_NAME "z80drv" +#define CLASS_NAME "mogu" + +// Memory and IO page types. Used to create a memory page which maps type of address space to real address space on host or virtual memory. +#define MEMORY_TYPE_VIRTUAL_MASK 0x00FFFFFF +#define MEMORY_TYPE_REAL_MASK 0x0000FFFF +#define IO_TYPE_MASK 0x0000FFFF +#define MEMORY_TYPE_INHIBIT 0x00000000 +#define MEMORY_TYPE_PHYSICAL_RAM 0x80000000 +#define MEMORY_TYPE_PHYSICAL_ROM 0x40000000 +#define MEMORY_TYPE_PHYSICAL_VRAM 0x20000000 +#define MEMORY_TYPE_PHYSICAL_HW 0x10000000 +#define MEMORY_TYPE_VIRTUAL_RAM 0x08000000 +#define MEMORY_TYPE_VIRTUAL_ROM 0x04000000 +#define MEMORY_TYPE_VIRTUAL_HW 0x02000000 +#define IO_TYPE_PHYSICAL_HW 0x80000000 +#define IO_TYPE_VIRTUAL_HW 0x40000000 + + +// Approximate governor delays to regulate emulated CPU speed. +#define MZ700_INSTRUCTION_DELAY_3_54MHZ 253 +#define MZ700_INSTRUCTION_DELAY_7MHZ 126 +#define MZ700_INSTRUCTION_DELAY_14MHZ 63 +#define MZ700_INSTRUCTION_DELAY_28MHZ 32 +#define MZ700_INSTRUCTION_DELAY_56MHZ 16 +#define MZ700_INSTRUCTION_DELAY_112MHZ 8 +#define MZ700_INSTRUCTION_DELAY_224MHZ 4 +#define MZ700_INSTRUCTION_DELAY_448MHZ 1 + +// IOCTL commands. Passed from user space using the IOCTL method to command the driver to perform an action. +#define IOCTL_CMD_Z80_STOP 's' +#define IOCTL_CMD_Z80_START 'S' +#define IOCTL_CMD_Z80_PAUSE 'P' +#define IOCTL_CMD_Z80_RESET 'R' +#define IOCTL_CMD_Z80_CONTINUE 'C' +#define IOCTL_CMD_USE_HOST_RAM 'x' +#define IOCTL_CMD_USE_VIRTUAL_RAM 'X' +#define IOCTL_CMD_DUMP_MEMORY 'M' +#define IOCTL_CMD_Z80_CPU_FREQ 'F' +#define IOCTL_CMD_CPLD_CMD 'z' +#define IOCTL_CMD_SEND _IOW('c', 'c', int32_t *) +#define IOCTL_CMD_SETPC _IOW('p', 'p', int32_t *) +#define IOCTL_CMD_SYNC_TO_HOST_RAM 'V' +#define IOCTL_CMD_SPI_TEST '1' +#define IOCTL_CMD_PRL_TEST '2' +#define IOCTL_CMD_Z80_MEMTEST '3' + + + +// Chip Select map MZ80K-MZ700. +// +// 0000 - 0FFF = CS_ROMni : R/W : MZ80K/A/700 = Monitor ROM or RAM (MZ80A rom swap) +// 1000 - CFFF = CS_RAMni : R/W : MZ80K/A/700 = RAM +// C000 - CFFF = CS_ROMni : R/W : MZ80A = Monitor ROM (MZ80A rom swap) +// D000 - D7FF = CS_VRAMni : R/W : MZ80K/A/700 = VRAM +// D800 - DFFF = CS_VRAMni : R/W : MZ700 = Colour VRAM (MZ700) +// E000 - E003 = CS_8255n : R/W : MZ80K/A/700 = 8255 +// E004 - E007 = CS_8254n : R/W : MZ80K/A/700 = 8254 +// E008 - E00B = CS_LS367n : R/W : MZ80K/A/700 = LS367 +// E00C - E00F = CS_ESWPn : R : MZ80A = Memory Swap (MZ80A) +// E010 - E013 = CS_ESWPn : R : MZ80A = Reset Memory Swap (MZ80A) +// E014 = CS_E5n : R/W : MZ80A/700 = Normal CRT display (in Video Controller) +// E015 = CS_E6n : R/W : MZ80A/700 = Reverse CRT display (in Video Controller) +// E200 - E2FF = : R/W : MZ80A/700 = VRAM roll up/roll down. +// E800 - EFFF = : R/W : MZ80K/A/700 = User ROM socket or DD Eprom (MZ700) +// F000 - F7FF = : R/W : MZ80K/A/700 = Floppy Disk interface. +// F800 - FFFF = : R/W : MZ80K/A/700 = Floppy Disk interface. +// +// Chip Select map MZ800 +// +// FC - FF = CS_PIOn : R/W : MZ800/MZ1500 = Z80 PIO Printer Interface +// F2 = CS_PSG0n : W : MZ800/MZ1500 = Programable Sound Generator, MZ-800 = Mono, MZ-1500 = Left Channel +// F3 = CS_PSG1n : W : MZ1500 = Programable Sound Generator, MZ-1500 = Right Channel +// E9 = CS_PSG(X)n: W : MZ1500 = Simultaneous write to both PSG's. +// F0 - F1 = CS_JOYSTK : R : MZ800 = Joystick 1 and 2 +// CC = CS_GWF : W : MZ800 = CRTC GWF Write format Register +// CD = CS_GRF : W : MZ800 = CRTC GRF Read format Register +// CE = CS_GDMD : W : MZ800 = CRTC GDMD Mode Register +// CF = CS_GCRTC : W : MZ800 = CRTC GCRTC Control Register +// D4 - D7 = CS +// D000 - DFFF + +// MZ700/MZ800 memory mode switch? +// +// MZ-700 MZ-800 +// |0000:0FFF|1000:1FFF|1000:CFFF|C000:CFFF|D000:FFFF |0000:7FFF|1000:1FFF|2000:7FFF|8000:BFFF|C000:CFFF|C000:DFFF|E000:FFFF +// -------------------------------------------------- ---------------------------------------------------------------------- +// OUT 0xE0 = |DRAM | | | | |DRAM | | | | | | +// OUT 0xE1 = | | | | |DRAM | | | | | | |DRAM +// OUT 0xE2 = |MONITOR | | | | |MONITOR | | | | | | +// OUT 0xE3 = | | | | |Memory Mapped I/O | | | | | | |Upper MONITOR ROM +// OUT 0xE4 = |MONITOR | |DRAM | |Memory Mapped I/O |MONITOR |CGROM |DRAM |VRAM | |DRAM |Upper MONITOR ROM +// OUT 0xE5 = | | | | |Inhibit | | | | | | |Inhibit +// OUT 0xE6 = | | | | | | | | | | | | +// IN 0xE0 = | |CGROM* | |VRAM* | | |CGROM | |VRAM | | | +// IN 0xE1 = | |DRAM | |DRAM | | | | |DRAM | | | +// +// = Return to the state prior to the complimentary command being invoked. +// * = MZ-800 host only. + +// Macros to lookup and test to see if a given memory block or IO byte is of a given type. Also macros to read/write to the memory block and IO byte. +#define MEMORY_BLOCK_GRANULARITY 0x800 +#define MEMORY_BLOCK_SLOTS (0x10000 / MEMORY_BLOCK_GRANULARITY) +#define MEMORY_BLOCK_MASK (0x10000 - MEMORY_BLOCK_GRANULARITY) +#define MEMORY_BLOCK_SHIFT 11 +#define getPageData(a) (Z80Ctrl->page[(a & 0xF800) >> MEMORY_BLOCK_SHIFT]) +#define getIOPageData(a) (Z80Ctrl->iopage[(a & 0xFFFF]) +#define getPageType(a, mask) (getPageData(a) & mask) +#define getPageAddr(a, mask) ((getPageData(a) & mask) + (a & (MEMORY_BLOCK_GRANULARITY-1))) +#define getIOPageType(a, mask) (getIOPageData(a) & mask) +#define getIOPageAddr(a, mask) (getIOPageData(a) & mask) +#define realAddress(a) (Z80Ctrl->page[getPageAddr(a, MEMORY_TYPE_REAL_MASK)]) +#define realPort(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_MASK) +#define isPhysicalRAM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_RAM)) +#define isPhysicalVRAM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_VRAM)) +#define isPhysicalROM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_ROM)) +#define isPhysicalMemory(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_ROM | MEMORY_TYPE_PHYSICAL_RAM | MEMORY_TYPE_PHYSICAL_VRAM))]) +#define isPhysicalHW(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_HW)) +#define isPhysical(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_HW | MEMORY_TYPE_PHYSICAL_ROM | MEMORY_TYPE_PHYSICAL_RAM | MEMORY_TYPE_PHYSICAL_VRAM))) +#define isPhysicalIO(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_PHYSICAL_HW) +#define isVirtualRAM(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_RAM)) +#define isVirtualROM(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_ROM)) +#define isVirtualMemory(a) (getPageType(a, (MEMORY_TYPE_VIRTUAL_ROM | MEMORY_TYPE_VIRTUAL_RAM))) +#define isVirtualHW(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_HW)) +#define isVirtualIO(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_VIRTUAL_HW) +#define isHW(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_HW | MEMORY_TYPE_VIRTUAL_HW))) +#define readVirtualRAM(a) (Z80Ctrl->memory[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) ]) +#define readVirtualROM(a) (Z80Ctrl->memory[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) + Z80_VIRTUAL_RAM_SIZE ]) +#define writeVirtualRAM(a, d) { Z80Ctrl->memory[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) ] = d; } +#define setMemoryType(_block_,_type_,_addr_) { Z80Ctrl->page[_block_] = _type_ | _addr_; } +#define backupMemoryType(_block_) { Z80Ctrl->shadowPage[_block_] = Z80Ctrl->page[_block_]; } +#define restoreMemoryType(_block_) { Z80Ctrl->page[_block_] = Z80Ctrl->shadowPage[_block_]; } + +#define IO_ADDR_E0 0xE0 +#define IO_ADDR_E1 0xE1 +#define IO_ADDR_E2 0xE2 +#define IO_ADDR_E3 0xE3 +#define IO_ADDR_E4 0xE4 +#define IO_ADDR_E5 0xE5 +#define IO_ADDR_E6 0xE6 +#define IO_ADDR_E7 0xE7 + + +enum Z80_RUN_STATES { + Z80_STOP = 0x00, + Z80_STOPPED = 0x01, + Z80_PAUSE = 0x02, + Z80_PAUSED = 0x03, + Z80_CONTINUE = 0x04, + Z80_RUNNING = 0x05, +}; +enum Z80_MEMORY_PROFILE { + USE_PHYSICAL_RAM = 0x00, + USE_VIRTUAL_RAM = 0x01 +}; + +typedef struct { + // Main memory, linear but indexed as though it were banks in 1K pages. + uint8_t memory[Z80_VIRTUAL_MEMORY_SIZE]; + + // Page pointer map. + // + // Each pointer points to a byte or block of bytes in the Z80 Memory frame, 64K Real + Banked. + // This is currently set at a block of size 0x800 per memory pointer for the MZ-700. + // The LSB of the pointer is a direct memory index to a byte or block of bytes, the upper byte of the pointer indicates type of memory space. + // 0x80 - physical host RAM + // 0x40 - physical host ROM + // 0x20 - physical host VRAM + // 0x10 - physical host hardware + // 0x08 - virtual host RAM + // 0x04 - virtual host ROM + // 0x02 - virtual host hardware + // 16bit Input Address -> map -> Pointer to 24bit memory address + type flag. + // -> Pointer+ to 24bit memory address + type flag. + uint32_t page[MEMORY_BLOCK_SLOTS]; + uint32_t shadowPage[MEMORY_BLOCK_SLOTS]; + + // I/O Page map. + // + // This is a map to indicate the use of the I/O page and allow any required remapping. + // <0x80>FF - physical host hardware + // <0x40>FF - virtual host hardware + // 16bit Input Address -> map -> Actual 16bit address to use + type flag. + uint32_t iopage[65536]; + + // Default page mode configured. This value reflects the default page and iotable map. + uint8_t defaultPageMode; + + // Refresh DRAM mode. 1 = Refresh, 0 = No refresh. Only applicable when running code in virtual Kernel RAM. + uint8_t refreshDRAM; + + // Inhibit mode is where certain memory ranges are inhibitted. The memory page is set to inhibit and this flag + // blocks actions which arent allowed during inhibit. + uint8_t inhibitMode; + + // Address caching. Used to minimise instruction length sent to CPLD. + uint16_t z80PrevAddr; + uint16_t z80PrevPort; + + // Keyboard strobe and data. Required to detect hotkey press. + uint8_t keyportStrobe; + uint8_t keyportShiftCtrl; + uint8_t keyportHotKey; + + // Governor is the delay in a 32bit loop per Z80 opcode, used to govern execution speed when using virtual memory. + // This mechanism will eventually be tied into the M/T-state calculation for a more precise delay, but at the moment, + // with the Z80 assigned to an isolated CPU, it allows time sensitive tasks such as the tape recorder to work. + // The lower the value the faster the CPU speed. + uint32_t cpuGovernorDelay; +} t_Z80Ctrl; + +// IOCTL structure for passing data from user space to driver to perform commands. +// +struct z80_addr { + uint32_t start; + uint32_t end; + uint32_t size; +}; +struct z80_ctrl { + uint16_t pc; +}; +struct speed { + uint32_t speedMultiplier; +}; +struct cpld_ctrl { + uint32_t cmd; +}; +struct ioctlCmd { + int32_t cmd; + union { + struct z80_addr addr; + struct z80_ctrl z80; + struct speed speed; + struct cpld_ctrl cpld; + }; +}; + + +// Prototypes. +void setupMemory(enum Z80_MEMORY_PROFILE mode); + + +#endif diff --git a/software/FusionX/src/driver/MZ700/z80io.c b/software/FusionX/src/driver/MZ700/z80io.c new file mode 100644 index 000000000..08286199d --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80io.c @@ -0,0 +1,428 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface +// This file contains the methods used in interfacing the SOM to the Z80 socket +// and host hardware via a CPLD. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + +//#include +//#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" + +#include +#include +#include +#include + +//------------------------------------------------------------------------------------------------------------------------------- +// +// User space driver access. +// +//------------------------------------------------------------------------------------------------------------------------------- + + + +// Initialise the SOM hardware used to communicate with the z80 socket and host hardware. +// The SOM interfaces to a CPLD which provides voltage level translation and also encapsulates the Z80 timing cycles as recreating +// them within the SOM is much more tricky. +// +// As this is an embedded device and performance/latency are priorities, minimal structured code is used to keep call stack and +// generated code to a mimimum without relying on the optimiser. +int z80io_init(void) +{ + // Locals. + int ret = 0; + + // Initialise GPIO. We call the HAL api to minimise time but for actual bit set/reset and read we go directly to registers to save time, increase throughput and minimise latency. + // Initialise the HAL. + MHal_GPIO_Init(); + + // Set the pads as GPIO devices. The HAL takes care of allocating and deallocating the padmux resources. + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_0); // Word (16bit) bidirectional bus. Default is read with data set. + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_1); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_2); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_3); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_4); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_5); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_6); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_7); + MHal_GPIO_Pad_Set(PAD_Z80IO_HIGH_BYTE); + //MHal_GPIO_Pad_Set(PAD_GPIO8); // SPIO 4wire control lines setup by the spidev driver but controlled directly in this driver. + //MHal_GPIO_Pad_Set(PAD_GPIO9); + //MHal_GPIO_Pad_Set(PAD_GPIO10); + //MHal_GPIO_Pad_Set(PAD_GPIO11); + MHal_GPIO_Pad_Set(PAD_Z80IO_READY); + MHal_GPIO_Pad_Set(PAD_Z80IO_LTSTATE); + MHal_GPIO_Pad_Set(PAD_Z80IO_BUSRQ); + MHal_GPIO_Pad_Set(PAD_Z80IO_BUSACK); + MHal_GPIO_Pad_Set(PAD_Z80IO_INT); + MHal_GPIO_Pad_Set(PAD_Z80IO_NMI); + MHal_GPIO_Pad_Set(PAD_Z80IO_WAIT); + MHal_GPIO_Pad_Set(PAD_Z80IO_RESET); + MHal_GPIO_Pad_Set(PAD_Z80IO_RSV1); +#ifdef NOTNEEDED + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_0); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_1); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_2); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_3); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_4); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_5); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_6); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_7); + MHal_GPIO_Pad_Set(PAD_Z80IO_WRITE); +#endif + + // Set required input pads. + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_0); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_1); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_2); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_3); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_4); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_5); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_6); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_7); + MHal_GPIO_Pad_Odn(PAD_Z80IO_READY); + MHal_GPIO_Pad_Odn(PAD_Z80IO_LTSTATE); + MHal_GPIO_Pad_Odn(PAD_Z80IO_BUSRQ); + MHal_GPIO_Pad_Odn(PAD_Z80IO_BUSACK); + MHal_GPIO_Pad_Odn(PAD_Z80IO_INT); + MHal_GPIO_Pad_Odn(PAD_Z80IO_NMI); + MHal_GPIO_Pad_Odn(PAD_Z80IO_WAIT); + MHal_GPIO_Pad_Odn(PAD_Z80IO_RESET); + MHal_GPIO_Pad_Odn(PAD_Z80IO_RSV1); + + // Set required output pads. +#ifdef NOTNEEDED + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_0); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_1); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_2); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_3); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_4); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_5); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_6); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_7); + MHal_GPIO_Pad_Oen(PAD_Z80IO_WRITE); + MHal_GPIO_Pull_High(PAD_Z80IO_WRITE); +#endif + + // Control signals. + MHal_GPIO_Pad_Oen(PAD_Z80IO_HIGH_BYTE); + MHal_GPIO_Pull_High(PAD_Z80IO_HIGH_BYTE); + + // Setup the MSPI0 device. + // + // Setup control, interrupts are not used. + MSPI_WRITE(MSPI_CTRL_OFFSET, MSPI_CPU_CLOCK_1_2 | MSPI_CTRL_CPOL_LOW | MSPI_CTRL_CPHA_HIGH | MSPI_CTRL_RESET | MSPI_CTRL_ENABLE_SPI); + + // Setup LSB First mode. + MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, 0x0); + + // Setup clock. + CLK_WRITE(MSPI0_CLK_CFG, 0x1100) + + // Setup the frame size (all buffers to 8bits). + MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xfff); + MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+1, 0xfff); + MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xfff); + MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+1, 0xfff); + + // Setup Chip Selects to inactive. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Switch Video and Audio to host. + z80io_SPI_Send16(0x00f0, NULL); + + return ret; +} + + +//-------------------------------------------------------- +// Parallel bus Methods. +//-------------------------------------------------------- + +// Methods to read data from the parallel bus. +// The CPLD returns status and Z80 data on the 8bit bus as it is marginally quicker than retrieving it over the SPI bus. +// +inline uint8_t z80io_PRL_Read8(uint8_t dataFlag) +{ + // Locals. + uint8_t result = 0; + + // Byte according to flag. + if(dataFlag) + SET_CPLD_READ_DATA() + else + SET_CPLD_READ_STATUS() + + // Read the input registers and set value accordingly. + result = READ_CPLD_DATA_IN(); + + // Return 16bit value read from CPLD. + return(result); +} + +inline uint16_t z80io_PRL_Read16(void) +{ + // Locals. + uint16_t result = 0; + + // Low byte first. + CLEAR_CPLD_HIGH_BYTE(); + + // Read the input registers and set value accordingly. + result = (uint16_t)READ_CPLD_DATA_IN(); + + // High byte next. + SET_CPLD_HIGH_BYTE(); + + // Read the input registers and set value accordingly. + result |= (uint16_t)(READ_CPLD_DATA_IN() << 8); + + // Return 16bit value read from CPLD. + return(result); +} + + +// Parallel Bus methods were tried and tested but due to the GPIO bits being controlled by individual registers per bit, the setup time was longer +// than the transmission time of SPI. These methods are thus deprecated and a fusion of SPI and 8bit parallel is now used. +#ifdef NOTNEEDED +inline uint8_t z80io_PRL_Send8(uint8_t txData) +{ + // Locals. + // + + // Low byte only. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE].r_out) &= (~gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out); + + // Setup data. + if(txData & 0x0080) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x0040) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x0020) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x0010) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0008) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0004) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0002) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0001) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + return(0); +} + +inline uint8_t z80io_PRL_Send16(uint16_t txData) +{ + // Locals. + // + + // Low byte first. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE].r_out) &= (~gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out); + + // Setup data. + if(txData & 0x0080) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x0040) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x0020) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x0010) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0008) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0004) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0002) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0001) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + // High byte next. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + + // Setup high byte. + if(txData & 0x8000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x4000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x2000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x1000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0800) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0400) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0200) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0100) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + return(0); +} +#endif + + +//-------------------------------------------------------- +// SPI Methods. +//-------------------------------------------------------- + +// Methods to send 8,16 or 32 bits. Each method is seperate to minimise logic and execution time, 8bit being most sensitive. +// Macros have also been defined for inline inclusion which dont read back the response data. +// +uint8_t z80io_SPI_Send8(uint8_t txData, uint8_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)txData); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 1); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = (uint8_t)MSPI_READ(MSPI_FULL_DEPLUX_RD00); + + // Done. + return(timeout == 0); +} +uint8_t z80io_SPI_Send16(uint16_t txData, uint16_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, txData); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 2); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = MSPI_READ(MSPI_FULL_DEPLUX_RD00); + + // Done. + return(timeout == 0); +} +uint8_t z80io_SPI_Send32(uint32_t txData, uint32_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)txData); + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)(txData >> 16)); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = (uint32_t)(MSPI_READ(MSPI_FULL_DEPLUX_RD00) | (MSPI_READ(MSPI_FULL_DEPLUX_RD02) << 16)); + + // Done. + return(timeout == 0); +} + +//-------------------------------------------------------- +// Test Methods. +//-------------------------------------------------------- +#ifdef INCLUDE_TEST_METHODS +#include "z80io_test.c" +#else +uint8_t z80io_Z80_TestMemory(void) +{ + pr_info("Z80 Test Memory functionality not built-in.\n"); + return(0); +} +uint8_t z80io_SPI_Test(void) +{ + pr_info("SPI Test functionality not built-in.\n"); + return(0); +} +uint8_t z80io_PRL_Test(void) +{ + pr_info("Parallel Bus Test functionality not built-in.\n"); + return(0); +} +#endif diff --git a/software/FusionX/src/driver/MZ700/z80io.h b/software/FusionX/src/driver/MZ700/z80io.h new file mode 100755 index 000000000..9e5c1b0f2 --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80io.h @@ -0,0 +1,483 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface +// This file contains the declarations used in interfacing the SOM to the Z80 socket +// and host hardware via a CPLD. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80IO_H +#define Z80IO_H + +#ifdef __cplusplus + extern "C" { +#endif + +// Definitions to control compilation. +#define INCLUDE_TEST_METHODS 1 + +// CPLD Commands. +#define CPLD_CMD_FETCH_ADDR 0x10 +#define CPLD_CMD_FETCH_ADDR_P1 0x11 +#define CPLD_CMD_FETCH_ADDR_P2 0x12 +#define CPLD_CMD_FETCH_ADDR_P3 0x13 +#define CPLD_CMD_FETCH_ADDR_P4 0x14 +#define CPLD_CMD_FETCH_ADDR_P5 0x15 +#define CPLD_CMD_FETCH_ADDR_P6 0x16 +#define CPLD_CMD_FETCH_ADDR_P7 0x17 +#define CPLD_CMD_WRITE_ADDR 0x18 +#define CPLD_CMD_WRITE_ADDR_P1 0x19 +#define CPLD_CMD_WRITE_ADDR_P2 0x1A +#define CPLD_CMD_WRITE_ADDR_P3 0x1B +#define CPLD_CMD_WRITE_ADDR_P4 0x1C +#define CPLD_CMD_WRITE_ADDR_P5 0x1D +#define CPLD_CMD_WRITE_ADDR_P6 0x1E +#define CPLD_CMD_WRITE_ADDR_P7 0x1F +#define CPLD_CMD_READ_ADDR 0x20 +#define CPLD_CMD_READ_ADDR_P1 0x21 +#define CPLD_CMD_READ_ADDR_P2 0x22 +#define CPLD_CMD_READ_ADDR_P3 0x23 +#define CPLD_CMD_READ_ADDR_P4 0x24 +#define CPLD_CMD_READ_ADDR_P5 0x25 +#define CPLD_CMD_READ_ADDR_P6 0x26 +#define CPLD_CMD_READ_ADDR_P7 0x27 +#define CPLD_CMD_WRITEIO_ADDR 0x28 +#define CPLD_CMD_WRITEIO_ADDR_P1 0x29 +#define CPLD_CMD_WRITEIO_ADDR_P2 0x2A +#define CPLD_CMD_WRITEIO_ADDR_P3 0x2B +#define CPLD_CMD_WRITEIO_ADDR_P4 0x2C +#define CPLD_CMD_WRITEIO_ADDR_P5 0x2D +#define CPLD_CMD_WRITEIO_ADDR_P6 0x2E +#define CPLD_CMD_WRITEIO_ADDR_P7 0x2F +#define CPLD_CMD_READIO_ADDR 0x30 +#define CPLD_CMD_READIO_ADDR_P1 0x31 +#define CPLD_CMD_READIO_ADDR_P2 0x32 +#define CPLD_CMD_READIO_ADDR_P3 0x33 +#define CPLD_CMD_READIO_ADDR_P4 0x34 +#define CPLD_CMD_READIO_ADDR_P5 0x35 +#define CPLD_CMD_READIO_ADDR_P6 0x36 +#define CPLD_CMD_READIO_ADDR_P7 0x37 +#define CPLD_CMD_HALT 0x50 +#define CPLD_CMD_REFRESH 0x51 +#define CPLD_CMD_SET_SIGROUP1 0xF0 +#define CPLD_CMD_SET_AUTO_REFRESH 0xF1 +#define CPLD_CMD_CLEAR_AUTO_REFRESH 0xF2 +#define CPLD_CMD_SET_SPI_LOOPBACK 0xFE +#define CPLD_CMD_NOP1 0x00 +#define CPLD_CMD_NOP2 0xFF + + +// Pad numbers for using the MHal GPIO library. +#define PAD_Z80IO_IN_DATA_0 PAD_GPIO0 +#define PAD_Z80IO_IN_DATA_1 PAD_GPIO1 +#define PAD_Z80IO_IN_DATA_2 PAD_GPIO2 +#define PAD_Z80IO_IN_DATA_3 PAD_GPIO3 +#define PAD_Z80IO_IN_DATA_4 PAD_GPIO4 +#define PAD_Z80IO_IN_DATA_5 PAD_GPIO5 +#define PAD_Z80IO_IN_DATA_6 PAD_GPIO6 +#define PAD_Z80IO_IN_DATA_7 PAD_GPIO7 +#define PAD_SPIO_0 PAD_GPIO8 +#define PAD_SPIO_1 PAD_GPIO9 +#define PAD_SPIO_2 PAD_GPIO10 +#define PAD_SPIO_3 PAD_GPIO11 +#define PAD_Z80IO_HIGH_BYTE PAD_SAR_GPIO2 // Byte requiured, 0 = Low Byte, 1 = High Byte. +#define PAD_Z80IO_READY PAD_GPIO12 +#define PAD_Z80IO_LTSTATE PAD_PM_IRIN // IRIN +#define PAD_Z80IO_BUSRQ PAD_GPIO13 +#define PAD_Z80IO_BUSACK PAD_GPIO14 +#define PAD_Z80IO_INT PAD_UART0_RX // GPIO47 +#define PAD_Z80IO_NMI PAD_UART0_TX // GPIO48 +#define PAD_Z80IO_WAIT PAD_HSYNC_OUT // GPIO85 +#define PAD_Z80IO_RESET PAD_VSYNC_OUT // GPIO86 +#define PAD_Z80IO_RSV1 PAD_SATA_GPIO // GPIO90 + +// Physical register addresses. +#define PAD_Z80IO_IN_DATA_0_ADDR 0x103C00 +#define PAD_Z80IO_IN_DATA_1_ADDR 0x103C02 +#define PAD_Z80IO_IN_DATA_2_ADDR 0x103C04 +#define PAD_Z80IO_IN_DATA_3_ADDR 0x103C06 +#define PAD_Z80IO_IN_DATA_4_ADDR 0x103C08 +#define PAD_Z80IO_IN_DATA_5_ADDR 0x103C0A +#define PAD_Z80IO_IN_DATA_6_ADDR 0x103C0C +#define PAD_Z80IO_IN_DATA_7_ADDR 0x103C0E +#define PAD_SPIO_0_ADDR 0x103C10 +#define PAD_SPIO_1_ADDR 0x103C12 +#define PAD_SPIO_2_ADDR 0x103C14 +#define PAD_SPIO_3_ADDR 0x103C16 +#define PAD_Z80IO_HIGH_BYTE_ADDR 0x1425 +#define PAD_Z80IO_READY_ADDR 0x103C18 +#define PAD_Z80IO_LTSTATE_ADDR 0xF28 // IRIN +#define PAD_Z80IO_BUSRQ_ADDR 0x103C1A +#define PAD_Z80IO_BUSACK_ADDR 0x103C1C +#define PAD_Z80IO_INT_ADDR 0x103C30 // GPIO47 +#define PAD_Z80IO_NMI_ADDR 0x103C32 // GPIO48 +#define PAD_Z80IO_WAIT_ADDR 0x103C80 // GPIO85 +#define PAD_Z80IO_RESET_ADDR 0x103C82 // GPIO86 +#define PAD_Z80IO_RSV1_ADDR 0x103C8A // GPIO90 + +#ifdef NOTNEEDED +#define PAD_Z80IO_OUT_DATA_0 PAD_GPIO12 +#define PAD_Z80IO_OUT_DATA_1 PAD_GPIO13 +#define PAD_Z80IO_OUT_DATA_2 PAD_GPIO14 +#define PAD_Z80IO_OUT_DATA_3 PAD_UART0_RX // GPIO47 +#define PAD_Z80IO_OUT_DATA_4 PAD_UART0_TX // GPIO48 +#define PAD_Z80IO_OUT_DATA_5 PAD_HSYNC_OUT // GPIO85 +#define PAD_Z80IO_OUT_DATA_6 PAD_VSYNC_OUT // GPIO86 +#define PAD_Z80IO_OUT_DATA_7 PAD_SATA_GPIO // GPIO90 +#define PAD_Z80IO_WRITE PAD_PM_IRIN // Write data clock. +#endif + +//------------------------------------------------------------------------------------------------- +// The definitions below come from SigmaStar kernel drivers. No header file exists hence the +// duplication. +//------------------------------------------------------------------------------------------------- + +#define SUPPORT_SPI_1 0 +#define MAX_SUPPORT_BITS 16 + +#define BANK_TO_ADDR32(b) (b<<9) +#define BANK_SIZE 0x200 + +#define MS_BASE_REG_RIU_PA 0x1F000000 +#define gChipBaseAddr 0xFD203C00 +#define gPmSleepBaseAddr 0xFD001C00 +#define gSarBaseAddr 0xFD002800 +#define gRIUBaseAddr 0xFD000000 +#define gMOVDMAAddr 0xFD201600 +#define gClkBaseAddr 0xFD207000 +#define gMspBaseAddr 0xfd222000 + +#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) + + +#define MSPI0_BANK_ADDR 0x1110 +#define MSPI1_BANK_ADDR 0x1111 +#define CLK__BANK_ADDR 0x1038 +#define CHIPTOP_BANK_ADDR 0x101E +#define MOVDMA_BANK_ADDR 0x100B + +#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) +#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) +#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) +#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) + +//------------------------------------------------------------------------------------------------- +// Hardware Register Capability +//------------------------------------------------------------------------------------------------- +#define MSPI_WRITE_BUF_OFFSET 0x40 +#define MSPI_READ_BUF_OFFSET 0x44 +#define MSPI_WBF_SIZE_OFFSET 0x48 +#define MSPI_RBF_SIZE_OFFSET 0x48 + // read/ write buffer size +#define MSPI_RWSIZE_MASK 0xFF +#define MSPI_RSIZE_BIT_OFFSET 0x8 +#define MAX_READ_BUF_SIZE 0x8 +#define MAX_WRITE_BUF_SIZE 0x8 +// CLK config +#define MSPI_CTRL_OFFSET 0x49 +#define MSPI_CLK_CLOCK_OFFSET 0x49 +#define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 +#define MSPI_CLK_CLOCK_MASK 0xFF +#define MSPI_CLK_PHASE_MASK 0x40 +#define MSPI_CLK_PHASE_BIT_OFFSET 0x06 +#define MSPI_CLK_POLARITY_MASK 0x80 +#define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 +#define MSPI_CLK_PHASE_MAX 0x1 +#define MSPI_CLK_POLARITY_MAX 0x1 +#define MSPI_CLK_CLOCK_MAX 0x7 +#define MSPI_CTRL_CPOL_LOW 0x00 +#define MSPI_CTRL_CPOL_HIGH 0x80 +#define MSPI_CTRL_CPHA_LOW 0x00 +#define MSPI_CTRL_CPHA_HIGH 0x40 +#define MSPI_CTRL_3WIRE 0x10 +#define MSPI_CTRL_INTEN 0x04 +#define MSPI_CTRL_RESET 0x02 +#define MSPI_CTRL_ENABLE_SPI 0x01 +// DC config +#define MSPI_DC_MASK 0xFF +#define MSPI_DC_BIT_OFFSET 0x08 +#define MSPI_DC_TR_START_OFFSET 0x4A +#define MSPI_DC_TRSTART_MAX 0xFF +#define MSPI_DC_TR_END_OFFSET 0x4A +#define MSPI_DC_TREND_MAX 0xFF +#define MSPI_DC_TB_OFFSET 0x4B +#define MSPI_DC_TB_MAX 0xFF +#define MSPI_DC_TRW_OFFSET 0x4B +#define MSPI_DC_TRW_MAX 0xFF +// Frame Config +#define MSPI_FRAME_WBIT_OFFSET 0x4C +#define MSPI_FRAME_RBIT_OFFSET 0x4E +#define MSPI_FRAME_BIT_MAX 0x07 +#define MSPI_FRAME_BIT_MASK 0x07 +#define MSPI_FRAME_BIT_FIELD 0x03 +#define MSPI_LSB_FIRST_OFFSET 0x50 +#define MSPI_TRIGGER_OFFSET 0x5A +#define MSPI_DONE_OFFSET 0x5B +#define MSPI_DONE_CLEAR_OFFSET 0x5C +#define MSPI_CHIP_SELECT_OFFSET 0x5F +#define MSPI_CS1_DISABLE 0x01 +#define MSPI_CS1_ENABLE 0x00 +#define MSPI_CS2_DISABLE 0x02 +#define MSPI_CS2_ENABLE 0x00 +#define MSPI_CS3_DISABLE 0x04 +#define MSPI_CS3_ENABLE 0x00 +#define MSPI_CS4_DISABLE 0x08 +#define MSPI_CS4_ENABLE 0x00 +#define MSPI_CS5_DISABLE 0x10 +#define MSPI_CS5_ENABLE 0x00 +#define MSPI_CS6_DISABLE 0x20 +#define MSPI_CS6_ENABLE 0x00 +#define MSPI_CS7_DISABLE 0x40 +#define MSPI_CS7_ENABLE 0x00 +#define MSPI_CS8_DISABLE 0x80 +#define MSPI_CS8_ENABLE 0x00 + +#define MSPI_FULL_DEPLUX_RD_CNT (0x77) +#define MSPI_FULL_DEPLUX_RD00 (0x78) +#define MSPI_FULL_DEPLUX_RD01 (0x78) +#define MSPI_FULL_DEPLUX_RD02 (0x79) +#define MSPI_FULL_DEPLUX_RD03 (0x79) +#define MSPI_FULL_DEPLUX_RD04 (0x7a) +#define MSPI_FULL_DEPLUX_RD05 (0x7a) +#define MSPI_FULL_DEPLUX_RD06 (0x7b) +#define MSPI_FULL_DEPLUX_RD07 (0x7b) + +#define MSPI_FULL_DEPLUX_RD08 (0x7c) +#define MSPI_FULL_DEPLUX_RD09 (0x7c) +#define MSPI_FULL_DEPLUX_RD10 (0x7d) +#define MSPI_FULL_DEPLUX_RD11 (0x7d) +#define MSPI_FULL_DEPLUX_RD12 (0x7e) +#define MSPI_FULL_DEPLUX_RD13 (0x7e) +#define MSPI_FULL_DEPLUX_RD14 (0x7f) +#define MSPI_FULL_DEPLUX_RD15 (0x7f) + +//chip select bit map +#define MSPI_CHIP_SELECT_MAX 0x07 + +// control bit +#define MSPI_DONE_FLAG 0x01 +#define MSPI_TRIGGER 0x01 +#define MSPI_CLEAR_DONE 0x01 +#define MSPI_INT_ENABLE 0x04 +#define MSPI_RESET 0x02 +#define MSPI_ENABLE 0x01 + +// clk_mspi0 +#define MSPI0_CLK_CFG 0x33 //bit 2 ~bit 3 +#define MSPI0_CLK_108M 0x00 +#define MSPI0_CLK_54M 0x04 +#define MSPI0_CLK_12M 0x08 +#define MSPI0_CLK_MASK 0x0F + +// clk_mspi1 +#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 +#define MSPI1_CLK_108M 0x0000 +#define MSPI1_CLK_54M 0x0400 +#define MSPI1_CLK_12M 0x0800 +#define MSPI1_CLK_MASK 0x0F00 + +// clk_mspi +#define MSPI_CLK_CFG 0x33 +#define MSPI_SELECT_0 0x0000 +#define MSPI_SELECT_1 0x4000 +#define MSPI_CLK_MASK 0xF000 + +// Clock settings +#define MSPI_CPU_CLOCK_1_2 0x0000 +#define MSPI_CPU_CLOCK_1_4 0x0100 +#define MSPI_CPU_CLOCK_1_8 0x0200 +#define MSPI_CPU_CLOCK_1_16 0x0300 +#define MSPI_CPU_CLOCK_1_32 0x0400 +#define MSPI_CPU_CLOCK_1_64 0x0500 +#define MSPI_CPU_CLOCK_1_128 0x0600 +#define MSPI_CPU_CLOCK_1_256 0x0700 + +//CHITOP 101E mspi mode select +#define MSPI0_MODE 0x0C //bit0~bit1 +#define MSPI0_MODE_MASK 0x07 +#define MSPI1_MODE 0x0C //bit4~bit5 +#define MSPI1_MODE_MASK 0x70 +#define EJTAG_MODE 0xF +#define EJTAG_MODE_1 0x01 +#define EJTAG_MODE_2 0x02 +#define EJTAG_MODE_3 0x03 +#define EJTAG_MODE_MASK 0x03 + +//MOVDMA 100B +#define MOV_DMA_SRC_ADDR_L 0x03 +#define MOV_DMA_SRC_ADDR_H 0x04 +#define MOV_DMA_DST_ADDR_L 0x05 +#define MOV_DMA_DST_ADDR_H 0x06 +#define MOV_DMA_BYTE_CNT_L 0x07 +#define MOV_DMA_BYTE_CNT_H 0x08 +#define DMA_MOVE0_IRQ_CLR 0x28 +#define MOV_DMA_IRQ_FINAL_STATUS 0x2A +#define DMA_MOVE0_ENABLE 0x00 +#define DMA_RW 0x50 //0 for dma write to device, 1 for dma read from device +#define DMA_READ 0x01 +#define DMA_WRITE 0x00 +#define DMA_DEVICE_MODE 0x51 +#define DMA_DEVICE_SEL 0x52 + +//spi dma +#define MSPI_DMA_DATA_LENGTH_L 0x30 +#define MSPI_DMA_DATA_LENGTH_H 0x31 +#define MSPI_DMA_ENABLE 0x32 +#define MSPI_DMA_RW_MODE 0x33 +#define MSPI_DMA_WRITE 0x00 +#define MSPI_DMA_READ 0x01 + +#define MSTAR_SPI_TIMEOUT_MS 30000 +#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) + + +//------------------------------------------------------------------------------------------------- +// Macros +//------------------------------------------------------------------------------------------------- + + +#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) +#define READ_WORD(_reg) (*(volatile u16*)(_reg)) +#define READ_LONG(_reg) (*(volatile u32*)(_reg)) +#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } +#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } +#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } +#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } +#define READ_CPLD_DATA_IN() ((MHal_RIU_REG(PAD_Z80IO_IN_DATA_7_ADDR) & 0x1) << 7 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_6_ADDR) & 0x1) << 6 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_5_ADDR) & 0x1) << 5 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_4_ADDR) & 0x1) << 4 |\ + (MHal_RIU_REG(PAD_Z80IO_IN_DATA_3_ADDR) & 0x1) << 3 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_2_ADDR) & 0x1) << 2 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_1_ADDR) & 0x1) << 1 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_0_ADDR) & 0x1)) +#define SET_CPLD_READ_DATA() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;} +#define SET_CPLD_READ_STATUS() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;} +#define SET_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;} +#define CLEAR_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;} +#define CPLD_READY() (MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) +#define CPLD_RESET() (MHal_RIU_REG(PAD_Z80IO_RESET_ADDR) & 0x1) +#define CPLD_LAST_TSTATE() (MHal_RIU_REG(PAD_Z80IO_LTSTATE_ADDR) & 0x4) +#define SPI_SEND8(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 1); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE);\ + } +#define SPI_SEND16(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 2); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \ + } +#define SPI_SEND32(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)((_d_) >> 16)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \ + } + +// read 2 byte +#define MSPI_READ(_reg_) READ_WORD(gMspBaseAddr + ((_reg_)<<2)) +// write 2 byte +//#define MSPI_WRITE(_reg_, _val_) {pr_info("PDS: MSPI_WRITE(0x%x, 0x%x, 0x%x)\n", _reg_, _val_, gMspBaseAddr + ((_reg_)<<2)); WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_)); } +#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_)); +//write 2 byte mask +//#define MSPI_WRITE_MASK(_reg_, _val_, mask) {pr_info("PDS: WRITE_LONG(0x%x, 0x%x, mask=0x%x)\n", _reg_, _val_, mask); WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask)); } +#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask)); + +#define CLK_READ(_reg_) READ_WORD(gClkBaseAddr + ((_reg_)<<2)) +//#define CLK_WRITE(_reg_, _val_) {pr_info("PDS: CLK_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_)); } +#define CLK_WRITE(_reg_, _val_) WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_)); + +#define CHIPTOP_READ(_reg_) READ_WORD(gChipBaseAddr + ((_reg_)<<2)) +//#define CHIPTOP_WRITE(_reg_, _val_) {pr_info("PDS: CHIPTOP_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_)); } +#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_)); + +#define MOVDMA_READ(_reg_) READ_WORD(gMOVDMAAddr + ((_reg_)<<2)) +//#define MOVDMA_WRITE(_reg_, _val_) {pr_info("PDS: MOVDMA_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_)); } +#define MOVDMA_WRITE(_reg_, _val_) WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_)); + +#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) +#define MAX_CHECK_CNT 2000 + +#define MSPI_READ_INDEX 0x0 +#define MSPI_WRITE_INDEX 0x1 + +#define SPI_MIU0_BUS_BASE 0x20000000 +#define SPI_MIU1_BUS_BASE 0xFFFFFFFF + + +// Function definitions. +// +int z80io_init(void); +uint8_t z80io_SPI_Send8(uint8_t txData, uint8_t *rxData); +uint8_t z80io_SPI_Send16(uint16_t txData, uint16_t *rxData); +uint8_t z80io_SPI_Send32(uint32_t txData, uint32_t *rxData); +#ifdef NOTNEEDED +uint8_t z80io_PRL_Send8(uint8_t txData); +uint8_t z680io_PRL_Send16(uint16_t txData); +#endif +uint8_t z80io_PRL_Read8(uint8_t dataFlag); +uint16_t z80io_PRL_Read16(void); +uint8_t z80io_SPI_Test(void); +uint8_t z80io_PRL_Test(void); +uint8_t z80io_Z80_TestMemory(void); + +extern void MHal_GPIO_Init(void); +extern void MHal_GPIO_Pad_Set(uint8_t u8IndexGPIO); +extern int MHal_GPIO_PadGroupMode_Set(uint32_t u32PadMode); +extern int MHal_GPIO_PadVal_Set(uint8_t u8IndexGPIO, uint32_t u32PadMode); +extern void MHal_GPIO_Pad_Oen(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pad_Odn(uint8_t u8IndexGPIO); +extern uint8_t MHal_GPIO_Pad_Level(uint8_t u8IndexGPIO); +extern uint8_t MHal_GPIO_Pad_InOut(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pull_High(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pull_Low(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_High(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_Low(uint8_t u8IndexGPIO); +extern void MHal_Enable_GPIO_INT(uint8_t u8IndexGPIO); +extern int MHal_GPIO_To_Irq(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_POLARITY(uint8_t u8IndexGPIO, uint8_t reverse); +extern void MHal_GPIO_Set_Driving(uint8_t u8IndexGPIO, uint8_t setHigh); +extern void MHal_GPIO_PAD_32K_OUT(uint8_t u8Enable); + +#ifdef __cplusplus +} +#endif +#endif // Z80IO_H diff --git a/software/FusionX/src/driver/MZ700/z80io_test.c b/software/FusionX/src/driver/MZ700/z80io_test.c new file mode 100644 index 000000000..a0b6899cf --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80io_test.c @@ -0,0 +1,541 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io_test.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface Test Methods +// This file contains the methods used to test the SOM to CPLD interface and evaluate +// it's performance. Production builds wont include these methods. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include + +//-------------------------------------------------------- +// Test Methods. +//-------------------------------------------------------- +uint8_t z80io_Z80_TestMemory(void) +{ + // Locals. + // + uint32_t addr; + uint32_t fullCmd; + uint8_t cmd; + struct timeval start, stop; + uint32_t iterations = 100; + uint32_t errorCount; + uint32_t idx; + long totalTime; + long bytesMSec; + uint8_t result; + spinlock_t spinLock; + unsigned long flags; + + SPI_SEND8(CPLD_CMD_CLEAR_AUTO_REFRESH); + + SPI_SEND32(0x00E30000 | (0x07 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E80000 | (0x82 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E20000 | (0x58 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E00000 | (0xF7 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E90000 | (0x0F << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00EB0000 | (0xCF << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00EB0000 | (0xFF << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + pr_info("Z80 Host Test - IO.\n"); + for(idx=0; idx < 1000000; idx++) + { + SPI_SEND32(0x00E80000 | (0xD3 << 8) | CPLD_CMD_WRITEIO_ADDR); + SPI_SEND32(0xD0000000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); + SPI_SEND32(0xD0100000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); + SPI_SEND32(0xD0200000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); + SPI_SEND32(0xD0300000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); + SPI_SEND32(0xD0400000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); + SPI_SEND32(0xD0500000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); + } + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing IO Write performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + for(addr=0x0000; addr < 0x10000; addr++) + { + fullCmd = 0x00000000| ((uint8_t)addr) << 8 | CPLD_CMD_WRITEIO_ADDR; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing IO Read performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible IO ports and write to it. + for(addr=0x0000; addr < 0x10000; addr++) + { + fullCmd = 0x00000000 | ((uint8_t)addr) << 8 | CPLD_CMD_READIO_ADDR; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing RAM Write performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x1000; addr < 0xD000; addr++) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write performance (opt).\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write/Fetch performance (opt).\n"); + errorCount = 0; + SET_CPLD_READ_DATA(); + //MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x8000; addr < 0xD000; addr++) + { + if(addr == 0x8000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + + // Read back the same byte. + cmd = 0x10; + SPI_SEND8(cmd); + while(CPLD_READY() == 0); + + result = READ_CPLD_DATA_IN(); + if(result != (uint8_t)addr) + { + if(errorCount < 50) pr_info("Read byte:0x%x, Written:0x%x\n", result, (uint8_t)addr); + errorCount++; + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, errorCount=%d, %ldBytes/sec\n", totalTime/1000, errorCount, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write/Read performance (opt).\n"); + errorCount = 0; + SET_CPLD_READ_DATA(); + //MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x8000; addr < 0xD000; addr++) + { + if(addr == 0x8000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + + // Read back the same byte. + cmd = 0x20; + SPI_SEND8(cmd); + while(CPLD_READY() == 0); + + result = READ_CPLD_DATA_IN(); + if(result != (uint8_t)addr) + { + if(errorCount < 50) pr_info("Read byte:0x%x, Written:0x%x\n", result, (uint8_t)addr); + errorCount++; + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, errorCount=%d, %ldBytes/sec\n", totalTime/1000, errorCount, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Fetch performance.\n"); + SET_CPLD_READ_DATA(); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and read from it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x10; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x11; + SPI_SEND8(cmd); + } + while(CPLD_READY() == 0); + result = READ_CPLD_DATA_IN(); + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Read performance (opt).\n"); + SET_CPLD_READ_DATA(); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and read from it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x20; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x21; + SPI_SEND8(cmd); + } + while(CPLD_READY() == 0); + result = READ_CPLD_DATA_IN(); + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + // Go through all the accessible attribute VRAM and initialise it. + pr_info("Z80 Host Test - Testing VRAM Write performance.\n"); + SPI_SEND32(0x00E80000 | (0xD3 << 8) | CPLD_CMD_WRITEIO_ADDR); + iterations = 256*10; + do_gettimeofday(&start); + for(addr=0xD800; addr < 0xE000; addr++) + { + //while(CPLD_READY() == 0); + if(addr == 0xD800) + { + fullCmd = (addr << 16) |(0x71 << 8) | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND8(cmd); + } + } + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible VRAM and write to it. + for(addr=0xD000; addr < 0xD800; addr++) + { + //while(CPLD_READY() == 0); + if(addr == 0xD000) + { + fullCmd = (addr << 16) | ((uint8_t)idx << 8) | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND8(cmd); + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)((1*iterations*0x800)+0x800)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + return(0); +} + + +// A simple test to verify the SOM to CPLD SPI connectivity and give an estimate of its performance. +// The performance is based on the SPI setup and transmit time along with the close and received data processing. +// In real use, the driver will just send a command and generally ignore received data so increased throughput can be achieved. +// +uint8_t z80io_SPI_Test(void) +{ + // Locals. + // + struct timeval start, stop; + uint32_t iterations = 10000000; + uint32_t idx; + uint8_t rxData8; + uint16_t rxData16; + uint16_t rxData16Last; + uint32_t rxData32; + uint32_t rxData32Last; + uint32_t errorCount; + long totalTime; + long bytesMSec; + + // Place the CPLD into echo test mode. + z80io_SPI_Send8(0xfe, &rxData8); + + // 1st. test, 8bit. + pr_info("SPI Test - Testing 8 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + z80io_SPI_Send8((uint8_t)idx, &rxData8); + if(idx > 1 && (uint8_t)(idx-1) != rxData8) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint8_t)(idx-1), rxData8 ); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 2nd. test, 16bit. + pr_info("SPI Test - Testing 16 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Byte re-ordering required as the CPLD echo's back the last 8bits received, it doesnt know if a transmission is 8/16/32bits. + z80io_SPI_Send16((uint16_t)idx, &rxData16); + if(idx > 0 && (uint16_t)(idx-1) != (uint16_t)(((rxData16&0x00ff) << 8) | ((rxData16Last & 0xff00) >> 8))) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint16_t)(idx-1), (uint16_t)(((rxData16&0x00ff) << 8) | ((rxData16Last & 0xff00) >> 8))); + errorCount++; + } + rxData16Last = rxData16; + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 3rd. test, 32bit. + pr_info("SPI Test - Testing 32 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + z80io_SPI_Send32((uint32_t)idx, &rxData32); + if(idx > 0 && (uint32_t)(idx-1) != (uint32_t)(((rxData32&0x00ff) << 8) | ((rxData32Last & 0xff000000) >> 8) | ((rxData32Last & 0xff0000) >> 8) | ((rxData32Last & 0xff00) >> 8))) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint32_t)(idx-1), (uint32_t)(((rxData32&0x00ff) << 8) | ((rxData32Last & 0xff000000) >> 8) | ((rxData32Last & 0xff0000) >> 8) | ((rxData32Last & 0xff00) >> 8))); + errorCount++; + } + rxData32Last = rxData32; + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(4*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + pr_info("Press host RESET button Once to reset the CPLD.\n"); + return(0); +} + +// Method to test the parallel bus, verifying integrity and assessing performance. +uint8_t z80io_PRL_Test(void) +{ + // Locals. + // + struct timeval start, stop; + uint32_t iterations = 10000000; + uint32_t idx; + uint8_t rxData8; + uint16_t rxData16; + long totalTime; + long bytesMSec; +#ifdef NOTNEEDED + uint32_t errorCount; +#endif + + // Place the CPLD into echo test mode. + + // 1st. test, 8bit RW. +#ifdef NOTNEEDED + pr_info("Parallel Test - Testing 8 bit r/w performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write byte and readback to compare. + z80io_PRL_Send8((uint8_t)idx); + rxData8 = z80io_PRL_Read8(); + if((uint8_t)idx != rxData8) + { + pr_info("0x%x: Written(0x%x) /= Read(0x%x)\n", idx, (uint8_t)(idx), rxData8); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 2nd. test, 8bit Write. + pr_info("Parallel Test - Testing 8 bit write performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write byte. + z80io_PRL_Send8((uint8_t)idx); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); +#endif + + // 3rd. test, 8bit Read. + pr_info("Parallel Test - Testing 8 bit read performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Read byte. + rxData8 = z80io_PRL_Read8(0); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + +#ifdef NOTNEEDED + // 4th test, 16bit. + pr_info("Parallel Test - Testing 16 bit r/w performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Byte re-ordering required as the CPLD echo's back the last 8bits received, it doesnt know if a transmission is 8/16/32bits. + z80io_PRL_Send16((uint16_t)idx); + rxData16 = z80io_PRL_Read16(); + if((uint16_t)idx != rxData16) + { + pr_info("0x%x: Written(0x%x) /= Read(0x%x)\n", idx, (uint16_t)(idx), rxData16); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 5th test, 16bit Write. + pr_info("Parallel Test - Testing 16 bit write performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write word. + z80io_PRL_Send16((uint16_t)idx); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); +#endif + + // 6th test, 16bit Read. + pr_info("Parallel Test - Testing 16 bit read performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Read word. + rxData16 = z80io_PRL_Read16(); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Press host RESET button Once to reset the CPLD.\n"); + return(0); +} diff --git a/software/FusionX/src/driver/MZ700/z80menu.c b/software/FusionX/src/driver/MZ700/z80menu.c new file mode 100644 index 000000000..bcc28a2ca --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80menu.c @@ -0,0 +1,57 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80menu.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 User Menu +// This file contains the methods used to present a menu of options to a user to aid +// in configuration and load/save of applications and data. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" +#include "z80menu.h" + +#include +#include +#include +#include + +void z80menu(void) +{ + // Locals. + +} diff --git a/software/FusionX/src/driver/MZ700/z80menu.h b/software/FusionX/src/driver/MZ700/z80menu.h new file mode 100755 index 000000000..107583682 --- /dev/null +++ b/software/FusionX/src/driver/MZ700/z80menu.h @@ -0,0 +1,44 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80menu.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 User Interface Menu +// This file contains the declarations required to provide a menu system allowing a +// user to configure and load/save applications/data. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80MENU_H +#define Z80MENU_H + +#ifdef __cplusplus + extern "C" { +#endif + +// Function definitions. +// +void z80menu(void); + +#ifdef __cplusplus +} +#endif +#endif // Z80MENU_H diff --git a/software/FusionX/src/driver/Makefile b/software/FusionX/src/driver/Makefile new file mode 100644 index 000000000..bd8db1c71 --- /dev/null +++ b/software/FusionX/src/driver/Makefile @@ -0,0 +1,23 @@ +MODEL := MZ2000 +KERNEL := /srv/dvlp/Projects/tzpu/FusionX/software/linux/kernel +CROSS := arm-linux-gnueabihf- +ccflags-y += -O2 -I${src}/Z80/Zeta/API -I${src}/Z80/API -I${KERNEL}/drivers/sstar/include -I${KERNEL}/drivers/sstar/include/infinity2m -I${KERNEL}/drivers/sstar/gpio/infinity2m +CTRLINC += -IZ80/Zeta/API -IZ80/API + +obj-m += z80drv.o +z80drv-objs += $(MODEL)/z80driver.o Z80.o $(MODEL)/z80io.o $(MODEL)/z80menu.o # emumz.o sharpmz.o osd.o +z80drv-objs += ../../../linux/kernel/drivers/sstar/gpio/infinity2m/gpio_table.o +z80drv-objs += ../../../linux/kernel/drivers/sstar/gpio/infinity2m/mhal_gpio.o +z80drv-objs += ../../../linux/kernel/drivers/sstar/gpio/infinity2m/mhal_pinmux.o +z80drv-objs += ../../../linux/kernel/drivers/sstar/gpio/infinity2m/padmux_tables.o + + +all: + @echo "Build driver for host: $(MODEL)" + @echo "" + make -C $(KERNEL) ARCH=arm CROSS_COMPILE=$(CROSS) M=$(PWD) modules + $(CROSS)gcc $(CTRLINC) $(MODEL)/z80ctrl.c -o z80ctrl + +clean: + make -C $(KERNEL) M=$(PWD) clean + diff --git a/software/FusionX/src/driver/README.txt b/software/FusionX/src/driver/README.txt new file mode 100644 index 000000000..5d582eb7a --- /dev/null +++ b/software/FusionX/src/driver/README.txt @@ -0,0 +1,9 @@ +Development Cycle +----------------- + +To avoid changes for one host affecting another the driver is split into seperate hosts containing almost identical code. +The idea, after development is complete, is to merge them into a single drive which autodetects, via the CPLD, the host model +and selects the code accordingly. + +Please edit Makefile and set the model prior to changing the Model source. In theory this file will be deleted once the source is +merged. diff --git a/software/FusionX/src/driver/Z80.c b/software/FusionX/src/driver/Z80.c new file mode 100644 index 000000000..e9d713537 --- /dev/null +++ b/software/FusionX/src/driver/Z80.c @@ -0,0 +1,2636 @@ +/* Z80 v0.2 + ______ ______ ______ + /\___ \/\ __ \\ __ \ + ____ \/__/ /\_\ __ \\ \/\ \ ________________________________________________ +| /\_____\\_____\\_____\ | +| Zilog \/_____//_____//_____/ CPU Emulator | +| Copyright (C) 1999-2022 Manuel Sainz de Baranda y Goñi. | +| | +| This emulator is free software: you can redistribute it and/or modify it | +| under the terms of the GNU Lesser General Public License as published by | +| the Free Software Foundation, either version 3 of the License, or (at your | +| option) any later version. | +| | +| This emulator is distributed in the hope that it will be useful, but | +| WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | +| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public | +| License for more details. | +| | +| You should have received a copy of the GNU Lesser General Public License | +| along with this emulator. If not, see . | +| | +| -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- | +| | +| A NOTE FROM THE ORIGINAL AUTHOR | +| | +| Those familiar with the official documentation of the Zilog Z80 CPU will | +| find this source code quite intuitive. The purpose has not been to write | +| the fastest possible emulator, although the speed aspect is not neglected, | +| but a portable, hackable and well | +| .----._.----. structured piece of software; | +| A11 <-01--|1 o|--40-> A10 something small, solid and elegant | +| A12 <-02--| |--39-> A09 that can stand the test of time | +| A13 <-03--| |--38-> A08 with no need for major changes. | +| A14 <-04--| |--37-> A07 | +| A15 <-05--| |--36-> A06 Some of the main design decisions | +| CLK --06->| |--35-> A05 have been the following: | +| D4 <-07->| |--34-> A04 | +| D3 <-08->|.---------.|--33-> A03 1. Opcode partial decoding keeps | +| D5 <-09->|| ZILOG ||--32-> A02 the code small and maintainable. | +| D6 <-10->|| Z80 ||--31-> A01 | +| +5V --11--|| CPU ||--30-> A00 2. Function pointer tables for | +| D2 <-12->|| ||--29-- GND opcode selection allow easy reuse | +| D7 <-13->|'---------'|--28-> RFSH of almost all instruction code | +| D0 <-14->| |--27-> M1 in the interrupt mode 0. | +| D1 <-15->| |<-26-- RESET | +| INT --16->| |<-25-- BUSREQ 3. Avoiding conditional statements | +| NMI --17->| |<-24-- WAIT as much as possible reduces the | +| HALT <-18--| |--23-> BUSACK branch penalty in modern pipelined | +| MREQ <-19--| |--22-> WR processors. | +| IORQ <-20--| |--21-> RD | +| '-----------' | +| Zilog Z80 CPU, May 1976 version | +| 40-pin ceramic DIP pinout Manuel | +| | +'=============================================================================*/ + +#ifndef Z80_DEPENDENCIES_HEADER +# include +# include +#endif + +#ifdef Z80_STATIC +# define Z80_API +#else +# define Z80_API Z_API_EXPORT +#endif + +#ifdef Z80_WITH_LOCAL_HEADER +# include "Z80.h" +#else +# include +#endif + + +/* MARK: - Types */ + +typedef zuint8 (* Instruction)(Z80 *self); + +#ifdef Z80_WITH_FULL_IM0 + typedef struct { + Z80* z80; + void* context; + Z80Read fetch; + Z80Read read; + Z80Write write; + Z80Read in; + Z80Write out; + Z80Notify ld_i_a; + Z80Notify ld_r_a; + Z80Notify reti; + Z80Notify retn; + zuint16 pc; + } IM0; +#endif + + +/* MARK: - External Macros */ + +#define REGISTER_OFFSET(member) (zusize)Z_MEMBER_OFFSET(Z80, member) +#define ROL(value) Z_UINT8_ROTATE_LEFT (value, 1) +#define ROR(value) Z_UINT8_ROTATE_RIGHT(value, 1) + + +/* MARK: - Instance Variable and Callback Shortcuts */ + +#define MEMPTR self->memptr.uint16_value +#define PC self->pc.uint16_value +#define SP self->sp.uint16_value +#define XY self->xy.uint16_value +#define IX self->ix_iy[0].uint16_value +#define IY self->ix_iy[1].uint16_value +#define AF self->af.uint16_value +#define BC self->bc.uint16_value +#define DE self->de.uint16_value +#define HL self->hl.uint16_value +#define AF_ self->af_.uint16_value +#define BC_ self->bc_.uint16_value +#define DE_ self->de_.uint16_value +#define HL_ self->hl_.uint16_value +#define MEMPTRH self->memptr.uint8_values.at_1 +#define MEMPTRL self->memptr.uint8_values.at_0 +#define PCH self->pc.uint8_values.at_1 +#define A self->af.uint8_values.at_1 +#define F self->af.uint8_values.at_0 +#define B self->bc.uint8_values.at_1 +#define C self->bc.uint8_values.at_0 +#define E self->de.uint8_values.at_0 +#define L self->hl.uint8_values.at_0 +#define I self->i +#define R self->r +#define R7 self->r7 +#define Q self->q +#define IFF1 self->iff1 +#define IFF2 self->iff2 +#define IM self->im +#define HALT_LINE self->halt_line +#define INT_LINE self->int_line +#define DATA self->data.uint8_array +#define REQUEST self->request +#define RESUME self->resume +#define OPTIONS self->options +#define CONTEXT self->context + +#define FETCH_OPCODE(address) self->fetch_opcode(CONTEXT, address) +#define FETCH(address) self->fetch(CONTEXT, address) +#define READ(address) self->read (CONTEXT, address) +#define WRITE(address, value) self->write(CONTEXT, address, value) +#define IN(port) self->in (CONTEXT, port) +#define OUT(port, value) self->out(CONTEXT, port, value) +#define NOTIFY(callback) if (self->callback != Z_NULL) self->callback(CONTEXT) +#define INTA self->inta(CONTEXT, PC) + + +/* MARK: - Callbacks: 16-bit Operations */ + +static Z_INLINE zuint16 fetch_16(Z80 const *self, zuint16 address) + { + zuint8 t = FETCH(address); + return (zuint16)(t | ((zuint16)FETCH(address + 1) << 8)); + } + + +static Z_INLINE zuint16 read_16(Z80 const *self, zuint16 address) + { + zuint8 t = READ(address); + return (zuint16)(t | ((zuint16)READ(address + 1) << 8)); + } + + +static Z_INLINE void write_16f(Z80 const *self, zuint16 address, zuint16 value) + { + WRITE(address, (zuint8)value); + WRITE(address + 1, (zuint8)(value >> 8)); + } + + +static Z_INLINE void write_16b(Z80 const *self, zuint16 address, zuint16 value) + { + WRITE(address + 1, (zuint8)(value >> 8)); + WRITE(address, (zuint8)value); + } + + +#ifndef Z80_WITH_FULL_IM0 + static Z_INLINE zuint16 int_fetch_16(Z80 const *self) + { + zuint8 t = self->int_fetch(CONTEXT, PC); + return (zuint16)(t | ((zuint16)self->int_fetch(CONTEXT, PC) << 8)); + } +#endif + + +#define FETCH_16(address) fetch_16 (self, address) +#define READ_16(address) read_16 (self, address) +#define WRITE_16F(address, value) write_16f(self, address, value) +#define WRITE_16B(address, value) write_16b(self, address, value) + + +/* MARK: - Flags */ + +/*----------------. +| 7 6 5 4 3 2 1 0 | +| S Z Y H X P N C | +'-|-|-|-|-|-|-|-|-' + | | | | | | | '-- carry / borrow + | | | | | | '---- addition / subtraction + | | | | | '------ parity (P) / two's complement signed overflow (V) + | | | | '-------- result's bit 3 (undocumented) + | | | '---------- half carry / half borrow + | | '------------ result's bit 5 (undocumented) + | '-------------- zero + '---------------- sign */ + +#define SF 128 +#define ZF 64 +#define YF 32 +#define HF 16 +#define XF 8 +#define PF 4 +#define NF 2 +#define CF 1 + +#define SZPCF (SF | ZF | PF | CF) +#define SZPF (SF | ZF | PF ) +#define SZCF (SF | ZF | CF ) +#define SYXF (SF | YF | XF ) +#define ZPF (ZF | PF ) +#define YXCF (YF | XF | CF ) +#define YXF (YF | XF ) +#define HCF (HF | CF ) + +#define F_SZPC (F & SZPCF) +#define F_SZP (F & SZPF) +#define F_SZC (F & SZCF) +#define F_C (F & CF) +#define A_SYX (A & SYXF) +#define A_YX (A & YXF) + +#define ZF_ZERO(value) (!(value) << 6) + +#ifdef Z80_WITH_Q +# define FLAGS Q = F +# define Q_0 Q = 0; +#else +# define FLAGS F +# define Q_0 +#endif + + +/* MARK: - P/V Flag Computation */ + +static zuint8 const pf_parity_table[256] = { +/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ +/* 0 */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4, +/* 1 */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* 2 */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* 3 */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4, +/* 4 */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* 5 */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4, +/* 6 */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4, +/* 7 */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* 8 */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* 9 */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4, +/* A */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4, +/* B */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* C */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4, +/* D */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* E */ 0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0, +/* F */ 4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4 +}; + +#define PF_PARITY(value) pf_parity_table[value] + +#define PF_OVERFLOW(bits, result, lhs, rhs) \ + (((zuint##bits)((lhs ^ rhs) & (lhs ^ result)) >> (bits - 3)) & PF) + + +/* MARK: - 8-Bit Register Resolution */ + +/*---------. .---------------------. +| 76543210 | | J / K | O / P | +|----------| |---------+-----------| +| __jjj___ | | 000 = b | 000 = b | +| _____kkk | | 001 = c | 001 = c | +| __ooo___ | | 010 = d | 010 = d | +| _____ppp | | 011 = e | 011 = e | +'----------' | 100 = h | 100 = XYh | + | 101 = l | 101 = XYl | + | 111 = a | 111 = a | + '--------------------*/ + +static zusize const j_k_table[8] = { + REGISTER_OFFSET(bc.uint8_values.at_1), + REGISTER_OFFSET(bc.uint8_values.at_0), + REGISTER_OFFSET(de.uint8_values.at_1), + REGISTER_OFFSET(de.uint8_values.at_0), + REGISTER_OFFSET(hl.uint8_values.at_1), + REGISTER_OFFSET(hl.uint8_values.at_0), + 0, + REGISTER_OFFSET(af.uint8_values.at_1) +}; + +static zusize const o_p_table[8] = { + REGISTER_OFFSET(bc.uint8_values.at_1), + REGISTER_OFFSET(bc.uint8_values.at_0), + REGISTER_OFFSET(de.uint8_values.at_1), + REGISTER_OFFSET(de.uint8_values.at_0), + REGISTER_OFFSET(xy.uint8_values.at_1), + REGISTER_OFFSET(xy.uint8_values.at_0), + 0, + REGISTER_OFFSET(af.uint8_values.at_1) +}; + +#define REGISTER_8(table, offset, shift) \ + *((zuint8 *)self + table[(DATA[offset] shift) & 7]) + +#define J0 REGISTER_8(j_k_table, 0, >> 3 ) +#define J1 REGISTER_8(j_k_table, 1, >> 3 ) +#define K0 REGISTER_8(j_k_table, 0, Z_EMPTY) +#define K1 REGISTER_8(j_k_table, 1, Z_EMPTY) +#define K3 REGISTER_8(j_k_table, 3, Z_EMPTY) +#define O REGISTER_8(o_p_table, 1, >> 3 ) +#define P REGISTER_8(o_p_table, 1, Z_EMPTY) + + +/* MARK: - 16-Bit Register Resolution */ + +/*---------. .-----------------------------. +| 76543210 | | S | T | W | +|----------| |---------+---------+---------| +| __ss____ | | 00 = bc | 00 = bc | 00 = bc | +| __tt____ | | 01 = de | 01 = de | 01 = de | +| __ww____ | | 10 = hl | 10 = hl | 10 = XY | +'----------' | 11 = sp | 11 = af | 11 = sp | + '----------------------------*/ + +static zusize const s_table[4] = { + REGISTER_OFFSET(bc.uint16_value), + REGISTER_OFFSET(de.uint16_value), + REGISTER_OFFSET(hl.uint16_value), + REGISTER_OFFSET(sp) +}; + +static zusize const t_table[4] = { + REGISTER_OFFSET(bc.uint16_value), + REGISTER_OFFSET(de.uint16_value), + REGISTER_OFFSET(hl.uint16_value), + REGISTER_OFFSET(af.uint16_value) +}; + +static zusize const w_table[4] = { + REGISTER_OFFSET(bc.uint16_value), + REGISTER_OFFSET(de.uint16_value), + REGISTER_OFFSET(xy.uint16_value), + REGISTER_OFFSET(sp) +}; + +#define REGISTER_16(table, offset) \ + *(zuint16 *)(void *)((zchar *)self + table[(DATA[offset] >> 4) & 3]) + +#define SS0 REGISTER_16(s_table, 0) +#define SS1 REGISTER_16(s_table, 1) +#define TT REGISTER_16(t_table, 0) +#define WW REGISTER_16(w_table, 1) + + +/* MARK: - Condition Evaluation */ + +/*---------. .----------. +| 76543210 | | Z | +|----------| |----------| +| __zzz___ | | 000 = nz | +| ___zz___ | | 001 = z | +'----------' | 010 = nc | + | 011 = c | + | 100 = po | + | 101 = pe | + | 110 = p | + | 111 = m | + '---------*/ + +static zuint8 const z_table[8] = {ZF, ZF, CF, CF, PF, PF, SF, SF}; + + +static Z_INLINE zsint zzz(Z80 const *self, zuint8 mask) + { + zsint z = (DATA[0] >> 3) & mask; + + return !(F & z_table[z]) ^ (z & 1); + } + + +/* MARK: - 8-Bit Arithmetic and Logical Operations */ + +/*---------. .---------------------. +| 76543210 | | U SZYHXPNC | +|----------| |---------------------| +| __uuu___ | | 000 = add szycxv0c | +| _____10v | | 001 = adc szycxv0c | +'----------' | 010 = sub szybxv1b | + | 011 = sbc szybxv1b | + | 100 = and szy1xp00 | + | 101 = xor szy0xp00 | + | 110 = or szy0xp00 | + | 111 = cp sz*b*v1b | + |---------------------| + | V SZYHXPNC | + |---------------------| + | 100 = inc szycxv0. | + | 101 = dec szybxv1. | + '--------------------*/ + +static void uuu(Z80 *self, zuint8 offset, zuint8 value) + { + zuint8 t, f; + + switch ((DATA[offset] >> 3) & 7) + { + case 0: /* add */ + t = A + value; + + f = ((zuint)A + value > 255) | /* CF = carry */ + PF_OVERFLOW(8, t, A, ~value) | /* PF = overflow */ + ((A ^ value ^ t) & HF); /* HF = half-carry */ + A = t; /* NF = 0 */ + break; + + case 1: /* adc */ + t = A + value + (f = F_C); + + f = ((zuint)A + value + f > 255) | /* CF = carry */ + PF_OVERFLOW(8, t, A, ~value) | /* PF = overflow */ + ((A ^ value ^ t) & HF); /* HF = half-carry */ + /* NF = 0 */ + A = t; + break; + + case 2: /* sub */ + t = A - value; + + f = (A < value) | /* CF = borrow */ + NF | /* NF = 1 */ + PF_OVERFLOW(8, t, A, value) | /* PF = overflow */ + ((A ^ value ^ t) & HF); /* HF = half-borrow */ + A = t; + break; + + case 3: /* sbc */ + t = A - value - (f = F_C); + + f = ((zsint)A - value - f < 0) | /* CF = borrow */ + NF | /* NF = 1 */ + PF_OVERFLOW(8, t, A, value) | /* PF = overflow */ + ((A ^ value ^ t) & HF); /* HF = half-borrow */ + + A = t; + break; + + case 4: /* and */ + A &= value; + f = HF | PF_PARITY(A); /* HF = 1; PF = parity */ + break; /* NF, CF = 0 */ + + case 5: /* xor */ + A ^= value; + f = PF_PARITY(A); /* PF = parity */ + break; /* HF, NF, CF = 0 */ + + case 6: /* or */ + A |= value; + f = PF_PARITY(A); /* PF = parity */ + break; /* HF, NF, CF = 0 */ + + case 7: /* cp */ + t = A - value; + + FLAGS = (zuint8)( + (t & SF) | /* SF = sign */ + ZF_ZERO(t) | /* ZF = zero */ + ((A ^ value ^ t) & HF) | /* HF = half-borrow */ + PF_OVERFLOW(8, t, A, value) | /* PF = overflow */ + (A < value) | /* CF = borrow */ + (value & YXF) | /* YF = rhs.5; XF = rhs.3 */ + NF); /* NF = 1 */ + + return; + } + + FLAGS = (zuint8)( + f | /* HF, PF, NF and CF already computed */ + A_SYX | /* SF = sign; YF = Y; XF = X */ + ZF_ZERO(A)); /* ZF = zero */ + } + + +static zuint8 vvv(Z80 *self, zuint8 offset, zuint8 value) + { + zuint8 t, pnf; + + /* dec */ + if (DATA[offset] & 1) + { + pnf = (zuint8)(((value == 128) << 2) | NF); /* PF = overflow; NF = 1 */ + t = value - 1; + } + + /* inc */ + else { + pnf = (zuint8)((value == 127) << 2); /* PF = overflow; NF = 0 */ + t = value + 1; + } + + FLAGS = (zuint8)( + pnf | /* PF and NF already computed */ + (t & SYXF) | /* SF = sign; YF = Y; XF = X */ + ZF_ZERO(t) | /* ZF = zero */ + ((value ^ t) & HF) | /* HF = half-carry/borrow */ + F_C); /* CF unchanged */ + + return t; + } + + +/* MARK: - Rotation and Shift Operations */ + +/*---------. .-----------. +| 76543210 | | G | +|----------| |-----------| +| __ggg___ | | 000 = rlc | +'----------' | 001 = rrc | + | 010 = rl | + | 011 = rr | + | 100 = sla | + | 101 = sra | + | 110 = sll | + | 111 = srl | + '----------*/ + +static zuint8 ggg(Z80 *self, zuint8 offset, zuint8 value) + { + zuint8 cf; + + switch ((DATA[offset] >> 3) & 7) + { + /* rlc .----------------. + .----. | .---------. | + | CF |<-----| 7 <-- 0 |<--' + '----' '--------*/ + case 0: + cf = (value = ROL(value)) & 1; + break; + + /* rrc .----------------. + | .---------. | .----. + '-->| 7 --> 0 |----->| CF | + '---------' '---*/ + case 1: + cf = value & 1; + value = ROR(value); + break; + + /* rl .-------------------------. + | .----. .---------. | + '--| CF |<--| 7 <-- 0 |<--' + '----' '--------*/ + case 2: + cf = value >> 7; + value = (zuint8)((value << 1) | F_C); + break; + + /* rr .-------------------------. + | .---------. .----. | + '-->| 7 --> 0 |-->| CF |--' + '---------' '---*/ + case 3: + cf = value & 1; + value = (zuint8)((value >> 1) | ((zuint8)F_C << 7)); + break; + + /* sla .----. .---------. + | CF |<--| 7 <-- 0 |<-- 0 + '----' '--------*/ + case 4: + cf = value >> 7; + value <<= 1; + break; + + /* sra .---------. .----. + .-->| 7 --> 0 |-->| CF | + | '---------' '----' + | | + '----*/ + case 5: + cf = value & 1; + value = (zuint8)((value & 128) | (value >> 1)); + break; + + /* sll .----. .---------. + | CF |<--| 7 <-- 0 |<-- 1 + '----' '--------*/ + case 6: + cf = value >> 7; + value = (zuint8)((value << 1) | 1); + break; + + /* srl .---------. .----. + 0 -->| 7 --> 0 |-->| CF | + '---------' '---*/ + case 7: + cf = value & 1; + value >>= 1; + break; + + /* Uncoment to avoid compiler warnings */ + /*default: cf = 0;*/ + } + + FLAGS = (zuint8)( + (value & SYXF) | /* SF = sign; YF = Y; XF = X */ + ZF_ZERO(value) | /* ZF = zero */ + PF_PARITY(value) | /* PF = parity */ + cf); /* CF already computed */ + /* HF, NF = 0 */ + return value; + } + + +/* MARK: - Bit Set and Reset Operations */ + +/*---------. .---------. +| 76543210 | | M | +|----------| |---------| +| _m______ | | 0 = res | +'----------' | 1 = set | + '--------*/ + +static Z_INLINE zuint8 m(Z80 *self, zuint8 offset, zuint8 value) + { + zuint8 t; + + Q_0 + t = DATA[offset]; + + return (zuint8)((t & 64) + ? value | (1U << ((t >> 3) & 7)) + : value & ~(1U << ((t >> 3) & 7))); + } + + +/* MARK: - Function Shortcuts and Reusable Code */ + +#define N(index) ((DATA[index] >> 3) & 7) +#define Z(mask) zzz(self, mask) +#define U0(value) uuu(self, 0, value) +#define U1(value) uuu(self, 1, value) +#define V0(value) vvv(self, 0, value) +#define V1(value) vvv(self, 1, value) +#define G1(value) ggg(self, 1, value) +#define G3(value) ggg(self, 3, value) +#define M1(value) m (self, 1, value) +#define M3(value) m (self, 3, value) +#define PUSH(value) WRITE_16B(SP -= 2, value) +#define R_ALL ((R & 127) | (R7 & 128)) +#define RET MEMPTR = PC = READ_16(SP); SP += 2 +#define FETCH_XY_EA(address) MEMPTR = (zuint16)(XY + (zsint8)FETCH(address)) +#define INSTRUCTION(name) static zuint8 name(Z80 *self) +#define IS_XY_PREFIX(opcode) ((opcode) & 0xDF) == 0xDD +#define EX(a, b) t = a; a = b; b = t + + +#define LD_A_IR(rhs) \ + A = rhs; \ + \ + FLAGS = (zuint8)( /* HF, NF = 0 */ \ + A_SYX | /* SF = sign; YF = Y; XF = X */ \ + ZF_ZERO(A) | /* ZF = zero */ \ + (IFF2 << 2) | /* PF = IFF2 */ \ + F_C); /* CF unchanged */ \ + \ + PC += 2; \ + return 9 + + +#define LDX(operator) \ + zuint8 t = READ(HL operator); \ + \ + WRITE(DE operator, t); \ + t += A; \ + \ + FLAGS = (zuint8)( /* HF, NF = 0 */ \ + F_SZC | /* SF, ZF, CF unchanged */ \ + ((t & 2) << 4) | /* YF = (A + [HLi]).1 */ \ + (t & XF) | /* XF = (A + [HLi]).3 */ \ + (!!(--BC) << 2)); /* PF = !!BCo */ \ + \ + PC += 2; \ + return 16 + + +#define LDXR(operator) \ + zuint8 t = READ(HL operator); \ + \ + WRITE(DE operator, t); \ + t += A; \ + \ + if (--BC) \ + { /* HF, NF = 0 */ \ + FLAGS = F_SZC | /* SF, ZF, CF unchanged */ \ + ((PC >> 8) & YXF) | /* YF = PCi.13; XF = PCi.11 */ \ + PF; /* PF = 1 */ \ + \ + MEMPTR = PC + 1; \ + return 21; \ + } \ + \ + FLAGS = (zuint8)( /* HF, PF, NF = 0 */ \ + F_SZC | /* SF, ZF, CF unchanged */ \ + ((t & 2) << 4) | /* YF = (A + [HLi]).1 */ \ + (t & XF)); /* XF = (A + [HLi]).3 */ \ + \ + PC += 2; \ + return 16 + + +#define CPX(operator) \ + zuint8 n = READ(HL operator); \ + zuint8 t0 = A - n; \ + zuint8 hf = (A ^ n ^ t0) & HF; \ + zuint8 t1 = t0 - (hf >> 4); \ + \ + FLAGS = (zuint8)( \ + (t0 & SF) | /* SF = sign */ \ + ZF_ZERO(t0) | /* ZF = zero */ \ + hf | /* HF = half-borrow */ \ + ((t1 & 2) << 4) | /* YF = (A - [HLi] - HFo).1 */ \ + (t1 & XF) | /* XF = (A - [HLi] - HFo).3 */ \ + (!!(--BC) << 2) | /* PF = !!BCo */ \ + NF | /* NF = 1 */ \ + F_C); /* CF unchanged */ \ + \ + MEMPTR operator; \ + PC += 2; \ + return 16 + + +#define CPXR(operator) \ + zuint8 n = READ(HL operator); \ + zuint8 t0 = A - n; \ + zuint8 hf = (A ^ n ^ t0) & HF; \ + zuint8 t1 = t0 - (hf >> 4); \ + \ + zuint8 f = (zuint8)( \ + (t0 & SF) | /* SF = sign */ \ + ZF_ZERO(t0) | /* ZF = zero */ \ + hf | /* HF = half-borrow */ \ + (!!(--BC) << 2) | /* PF = !!BCo */ \ + NF | /* NF = 1 */ \ + F_C); /* CF unchanged */ \ + \ + if (t0 && BC) \ + { \ + /* YF = PCi.13; XF = PCi.11 */ \ + FLAGS = f | ((PC >> 8) & YXF); \ + MEMPTR = PC + 1; \ + return 21; \ + } \ + \ + FLAGS = (zuint8)( \ + f | \ + ((t1 & 2) << 4) | /* YF = (A - [HLi] - HFo).1 */ \ + (t1 & XF)); /* XF = (A - [HLi] - HFo).3 */ \ + \ + MEMPTR operator; \ + PC += 2; \ + return 16 + + +#define ADD_RR_NN(RR, NN) \ + zuint16 nn = NN; \ + zuint16 t = RR + nn; \ + \ + FLAGS = F_SZP | /* SF, ZF, PF unchanged */ \ + ((t >> 8) & YXF) | /* YF = high-Y; XF = high-X */ \ + (((zuint16)(RR ^ nn ^ t) >> 8) & HF) | /* HF = high-half-carry */ \ + ((zuint32)RR + nn > 65535); /* CF = carry */ \ + /* NF = 0 */ \ + MEMPTR = RR + 1; \ + RR = t + + +#define ADC_SBC_HL_SS(operator, pf_test_rhs, cf_test, set_nf) \ + zuint8 fc = F_C; \ + zuint16 ss = SS1; \ + zuint16 t = HL operator ss operator fc; \ + \ + FLAGS = (zuint8)( \ + ((t >> 8) & SYXF) /* SF = sign; YF = high-Y; XF = high-X */ \ + | ZF_ZERO(t) /* ZF = zero */ \ + /* HF = high-half-carry (adc), high-half-borrow (sbc) */ \ + | (((zuint16)(HL ^ ss ^ t) >> 8) & HF) \ + | PF_OVERFLOW(16, t, HL, pf_test_rhs) /* PF = overflow */ \ + | ((zuint32)cf_test) /* CF = carry (adc), borrow (sbc) */ \ + set_nf); /* NF = 0 (adc), 1 (sbc) */ \ + \ + MEMPTR = HL + 1; \ + HL = t; \ + PC += 2; \ + return 15 + + +#define RXA(a_to_cf, operator, fc_to_a) \ + zuint8 cf = a_to_cf; \ + \ + A = (zuint8)((A operator 1) | fc_to_a); \ + \ + FLAGS = F_SZP | /* SF, ZF, PF unchanged */ \ + A_YX | /* YF = Y; XF = X */ \ + cf; /* CF = Ai.7 (rla), Ai.0 (rra) */ \ + /* HF, NF = 0 */ \ + PC++; \ + return 4 + + +#define RXD(vhl_to_vhl, a_to_vhl, vhl_to_a) \ + zuint8 t = READ(HL); \ + \ + MEMPTR = HL + 1; \ + WRITE(HL, (zuint8)((t vhl_to_vhl) | (A a_to_vhl))); \ + A = (A & 0xF0) | (t vhl_to_a); \ + \ + FLAGS = (zuint8)( /* HF, NF = 0; */ \ + A_SYX | /* SF = sign; YF = Y; XF = X */ \ + ZF_ZERO(A) | /* ZF = zero */ \ + PF_PARITY(A) | /* PF = parity */ \ + F_C); /* CF unchanged */ \ + \ + PC += 2; \ + return 18 + + +#define DJNZ_JR_Z_OFFSET(condition, cycles_if_true, cycles_if_false) \ + zsint8 offset; \ + \ + Q_0 \ + offset = (zsint8)FETCH(PC + 1); /* always */ \ + \ + if (condition) \ + { \ + MEMPTR = (PC += 2 + offset); \ + return cycles_if_true; \ + } \ + \ + PC += 2; \ + return cycles_if_false + + +#define RETX(mnemonic) \ + NOTIFY(mnemonic); \ + Q_0 \ + DATA[2] = IFF1; \ + if ((IFF1 = IFF2) && INT_LINE) REQUEST |= Z80_REQUEST_INT; \ + RET; \ + return 14 + + +#define IN_VC \ + zuint8 t; \ + \ + MEMPTR = BC + 1; \ + t = IN(BC); \ + \ + FLAGS = (zuint8)( /* HF, NF = 0 */ \ + (t & SYXF) | /* SF = sign; YF = Y; XF = X */ \ + ZF_ZERO(t) | /* ZF = zero */ \ + PF_PARITY(t) | /* PF = parity */ \ + F_C) /* CF unchanged */ + + +#define INX_OUTX(io) \ + FLAGS = (zuint8)( \ + (B & SYXF) | /* SF = Bo.7; YF = Bo.5; XF = Bo.3 */ \ + ZF_ZERO(B) | /* ZF = !Bo */ \ + PF_PARITY((t & 7) ^ B) | /* PF = ((T & 7) ^ Bo).parity */ \ + ((t > 255) ? HCF : 0) | /* HF, CF = T > 255 */ \ + ((io >> 6) & NF)); /* NF = IO.7 */ \ + \ + PC += 2; \ + return 16 + + +#define INX(hl_operator, memptr_operator) \ + zuint8 in = IN(BC); \ + zuint t = (zuint)in + (zuint8)(C memptr_operator 1); \ + \ + WRITE(HL hl_operator, in); \ + MEMPTR = BC memptr_operator 1; \ + B--; \ + INX_OUTX(in) \ + + +#define OUTX(hl_operator, memptr_operator) \ + zuint8 out = READ(HL hl_operator); \ + zuint t = (zuint)out + L; \ + \ + B--; \ + MEMPTR = BC memptr_operator 1; \ + OUT(BC, out); \ + INX_OUTX(out) + + +#define INXR_OTXR(io) \ + if (B) { \ + FLAGS = (zuint8)( /* ZF = 0 */ \ + (B & SF) | /* SF = Bo.7 */ \ + (PCH & YXF) | /* YF = PCi.13; XF = PCi.11 */ \ + nf | /* NF = IO.7 */ \ + (hcf ? \ + CF | \ + (nf ? \ + (!(B & 0xF) << 4) | \ + PF_PARITY(p ^ ((B - 1) & 7)) \ + : \ + (((B & 0xF) == 0xF) << 4) | \ + PF_PARITY(p ^ ((B + 1) & 7))) \ + : PF_PARITY(p ^ (B & 7)))); \ + \ + return 21; \ + } \ + \ + FLAGS = ZF | /* ZF = 1; SF, YF, XF = 0 */ \ + hcf | /* HF, CF = T > 255 */ \ + PF_PARITY(p) | /* PF = ((T & 7) ^ Bo).parity */ \ + nf; /* NF = IO.7 */ \ + \ + PC += 2; \ + return 16 + + +#define INXR(hl_operator, memptr_operator) \ + zuint8 in = IN(BC); \ + zuint8 nf = (in >> 6) & NF; \ + zuint t = (zuint)in + (zuint8)(C memptr_operator 1); \ + zuint8 hcf = (t > 255) ? HCF : 0; \ + zuint8 p; \ + \ + WRITE(HL hl_operator, in); \ + MEMPTR = BC memptr_operator 1; \ + p = (t & 7) ^ --B; \ + INXR_OTXR(in) + + +#define OTXR(hl_operator, memptr_operator) \ + zuint8 out = READ(HL hl_operator); \ + zuint8 nf = (out >> 6) & NF; \ + zuint t = (zuint)out + L; \ + zuint8 hcf = (t > 255) ? HCF : 0; \ + zuint8 p = (t & 7) ^ --B; \ + \ + MEMPTR = BC memptr_operator 1; \ + OUT(BC, out); \ + INXR_OTXR(out) + + +#define SET_HALT_LINE(state) \ + HALT_LINE = state; \ + if (self->halt != Z_NULL) self->halt(CONTEXT, state) + + +/* MARK: - Instructions: 8-Bit Load Group */ +/*----------------------------------------------------------------------------. +| 0 1 2 3 Flags T-states | +| Assembly 76543210765432107654321076543210 SZYHXPNC 12345 | +| ------------------- -------------------------------- -------- -------- | +| ld J,K 01jjjkkk ........ 4:4 | +|* ld O,P <--XY-->01oooppp ........ 8:44 | +| ld J,BYTE 00jjj110<-BYTE-> ........ 7:43 | +|* ld O,BYTE <--XY-->00ooo110<-BYTE-> ........ 11:443 | +| ld J,(hl) 01jjj110 ........ 7:43 | +| ld J,(XY+OFFSET) <--XY-->01jjj110 ........ 19:44353 | +| ld (hl),K 01110kkk ........ 7:43 | +| ld (XY+OFFSET),K <--XY-->01110kkk ........ 19:44353 | +| ld (hl),BYTE <--36--><-BYTE-> ........ 10:433 | +| ld (XY+OFFSET),BYTE <--XY--><--36--><-BYTE-> ........ 19:44353 | +| ld a,(bc) <--0A--> ........ 7:43 | +| ld a,(de) <--1A--> ........ 7:43 | +| ld a,(WORD) <--3A--><-----WORD-----> ........ 13:4333 | +| ld (bc),a <--02--> ........ 7:43 | +| ld (de),a <--12--> ........ 7:43 | +| ld (WORD),a <--32--><-----WORD-----> ........ 13:4333 | +| ld a,i <--ED--><--57--> szy0x*0. 9:45 | +| ld a,r <--ED--><--5F--> szy0x*0. 9:45 | +| ld i,a <--ED--><--47--> ........ 9:45 | +| ld r,a <--ED--><--4F--> ........ 9:45 | +|-----------------------------------------------------------------------------| +| (*) Undocumented instruction. | +'============================================================================*/ + +INSTRUCTION(ld_J_K ) {Q_0 J0 = K0; PC++; return 4;} +INSTRUCTION(ld_O_P ) {Q_0 O = P; PC += 2; return 4;} +INSTRUCTION(ld_J_BYTE ) {Q_0 J0 = FETCH((PC += 2) - 1); return 7;} +INSTRUCTION(ld_O_BYTE ) {Q_0 O = FETCH((PC += 3) - 1); return 7;} +INSTRUCTION(ld_J_vhl ) {Q_0 J0 = READ(HL); PC++; return 7;} +INSTRUCTION(ld_J_vXYpOFFSET) {Q_0 J1 = READ(FETCH_XY_EA((PC += 3) - 1)); return 15;} +INSTRUCTION(ld_vhl_K ) {Q_0 WRITE(HL, K0); PC++; return 7;} +INSTRUCTION(ld_vXYpOFFSET_K) {Q_0 WRITE(FETCH_XY_EA((PC += 3) - 1), K1); return 15;} +INSTRUCTION(ld_vhl_BYTE ) {Q_0 WRITE(HL, FETCH((PC += 2) - 1)); return 10;} +INSTRUCTION(ld_a_vbc ) {Q_0 MEMPTR = BC + 1; A = READ(BC); PC++; return 7;} +INSTRUCTION(ld_a_vde ) {Q_0 MEMPTR = DE + 1; A = READ(DE); PC++; return 7;} +INSTRUCTION(ld_a_vWORD ) {Q_0 MEMPTR = FETCH_16((PC += 3) - 2); A = READ(MEMPTR++); return 13;} +INSTRUCTION(ld_vbc_a ) {Q_0 MEMPTRL = C + 1; WRITE(BC, MEMPTRH = A); PC++; return 7;} +INSTRUCTION(ld_vde_a ) {Q_0 MEMPTRL = E + 1; WRITE(DE, MEMPTRH = A); PC++; return 7;} +INSTRUCTION(ld_a_i ) {LD_A_IR(I); } +INSTRUCTION(ld_a_r ) {LD_A_IR(R_ALL); } +INSTRUCTION(ld_i_a ) {NOTIFY(ld_i_a); Q_0 I = A; PC += 2; return 9;} +INSTRUCTION(ld_r_a ) {NOTIFY(ld_r_a); Q_0 R = R7 = A; PC += 2; return 9;} + + +INSTRUCTION(ld_vXYpOFFSET_BYTE) + { + zuint16 ea; + + Q_0 + ea = FETCH_XY_EA((PC += 4) - 2); + WRITE(ea, FETCH(PC - 1)); + return 15; + } + + +INSTRUCTION(ld_vWORD_a) + { + zuint16 ea; + + Q_0 + MEMPTRL = (zuint8)((ea = FETCH_16((PC += 3) - 2)) + 1); + WRITE(ea, MEMPTRH = A); + return 13; + } + + +/* MARK: - Instructions: 16-Bit Load Group */ +/*----------------------------------------------------------------------. +| 0 1 2 3 Flags T-states | +| Assembly 76543210765432107654321076543210 SZYHXPNC 123456 | +| ------------ -------------------------------- -------- --------- | +| ld SS,WORD 00ss0001<-----WORD-----> ........ 10:433 | +| ld XY,WORD <--XY--><--21--><-----WORD-----> ........ 14:4433 | +| ld hl,(WORD) <--2A--><-----WORD-----> ........ 16:43333 | +| ld SS,(WORD) <--ED-->01ss1011<-----WORD-----> ........ 20:443333 | +| ld XY,(WORD) <--XY--><--2A--><-----WORD-----> ........ 20:443333 | +| ld (WORD),hl <--22--><-----WORD-----> ........ 16:43333 | +| ld (WORD),SS <--ED-->01ss0011<-----WORD-----> ........ 20:443333 | +| ld (WORD),XY <--XY--><--22--><-----WORD-----> ........ 20:443333 | +| ld sp,hl <--F9--> ........ 6:6 | +| ld sp,XY <--XY--><--F9--> ........ 10:46 | +| push TT 11tt0101 ........ 11:533 | +| push XY <--XY--><--E5--> ........ 15:4533 | +| pop TT 11tt0001 ........ 10:433 | +| pop XY <--XY--><--E1--> ........ 14:4433 | +'======================================================================*/ + +INSTRUCTION(ld_SS_WORD ) {Q_0 SS0 = FETCH_16((PC += 3) - 2); return 10;} +INSTRUCTION(ld_XY_WORD ) {Q_0 XY = FETCH_16((PC += 4) - 2); return 10;} +INSTRUCTION(ld_hl_vWORD) {Q_0 MEMPTR = FETCH_16((PC += 3) - 2); HL = READ_16(MEMPTR++); return 16;} +INSTRUCTION(ld_SS_vWORD) {Q_0 MEMPTR = FETCH_16((PC += 4) - 2); SS1 = READ_16(MEMPTR++); return 20;} +INSTRUCTION(ld_XY_vWORD) {Q_0 MEMPTR = FETCH_16((PC += 4) - 2); XY = READ_16(MEMPTR++); return 16;} +INSTRUCTION(ld_vWORD_hl) {Q_0 MEMPTR = FETCH_16((PC += 3) - 2); WRITE_16F(MEMPTR++, HL ); return 16;} +INSTRUCTION(ld_vWORD_SS) {Q_0 MEMPTR = FETCH_16((PC += 4) - 2); WRITE_16F(MEMPTR++, SS1); return 20;} +INSTRUCTION(ld_vWORD_XY) {Q_0 MEMPTR = FETCH_16((PC += 4) - 2); WRITE_16F(MEMPTR++, XY ); return 16;} +INSTRUCTION(ld_sp_hl ) {Q_0 SP = HL; PC++; return 6;} +INSTRUCTION(ld_sp_XY ) {Q_0 SP = XY; PC += 2; return 6;} +INSTRUCTION(push_TT ) {Q_0 WRITE_16B(SP -= 2, TT); PC++; return 11;} +INSTRUCTION(push_XY ) {Q_0 WRITE_16B(SP -= 2, XY); PC += 2; return 11;} +INSTRUCTION(pop_TT ) {Q_0 TT = READ_16(SP); SP += 2; PC++; return 10;} +INSTRUCTION(pop_XY ) {Q_0 XY = READ_16(SP); SP += 2; PC += 2; return 10;} + + +/* MARK: - Instructions: Exchange, Block Transfer and Search Groups */ +/*-------------------------------------------------------------. +| 0 1 Flags T-states | +| Assembly 7654321076543210 SZYHXPNC !0 123456 =0 1234 | +| ---------- ---------------- -------- ------------------ | +| ex de,hl <--EB--> ........ 4:4 | +| ex af,af' <--08--> ........ 4:4 | +| exx <--D9--> ........ 4:4 | +| ex (sp),hl <--E3--> ........ 19:43435 | +| ex (sp),XY <--XY--><--E3--> ........ 23:443435 | +| ldi <--ED--><--A0--> ..*0**0. 16:4435 | +| ldir <--ED--><--B0--> ..*0*00. 21:44355 16:4435 | +| ldd <--ED--><--A8--> ..*0**0. 16:4435 | +| lddr <--ED--><--B8--> ..*0*00. 21:44355 16:4435 | +| cpi <--ED--><--A1--> sz*b**1. 16:4435 | +| cpir <--ED--><--B1--> sz*b**1. 21:44355 16:4435 | +| cpd <--ED--><--A9--> sz*b**1. 16:4435 | +| cpdr <--ED--><--B9--> sz*b**1. 21:44355 16:4435 | +'=============================================================*/ + +INSTRUCTION(ex_de_hl ) {zuint16 t; Q_0 EX(DE, HL ); PC++; return 4;} +INSTRUCTION(ex_af_af_) {zuint16 t; Q_0 EX(AF, AF_); PC++; return 4;} +INSTRUCTION(exx ) {zuint16 t; Q_0 EX(BC, BC_); EX(DE, DE_); EX(HL, HL_); PC++; return 4;} +INSTRUCTION(ex_vsp_hl) {Q_0 MEMPTR = READ_16(SP); WRITE_16B(SP, HL); HL = MEMPTR; PC++; return 19;} +INSTRUCTION(ex_vsp_XY) {Q_0 MEMPTR = READ_16(SP); WRITE_16B(SP, XY); XY = MEMPTR; PC += 2; return 19;} +INSTRUCTION(ldi ) {LDX (++); } +INSTRUCTION(ldir ) {LDXR(++); } +INSTRUCTION(ldd ) {LDX (--); } +INSTRUCTION(lddr ) {LDXR(--); } +INSTRUCTION(cpi ) {CPX (++); } +INSTRUCTION(cpir ) {CPXR(++); } +INSTRUCTION(cpd ) {CPX (--); } +INSTRUCTION(cpdr ) {CPXR(--); } + + +/* MARK: - Instructions: 8-Bit Arithmetic and Logical Group */ +/*-------------------------------------------------------------------. +| 0 1 2 Flags T-states | +| Assembly 765432107654321076543210 SZYHXPNC 123456 | +| ----------------- ------------------------ -------- --------- | +| U [a,]K 10uuukkk sz|||||| 4:4 | +|* U [a,]P <--XY-->10uuuppp sz|||||| 8:44 | +| U [a,]BYTE 11uuu110<-BYTE-> sz|||||| 7:43 | +| U [a,](hl) 10uuu110 sz|||||| 7:43 | +| U [a,](XY+OFFSET) <--XY-->10uuu110 sz|||||| 19:44353 | +| V J 00jjj10v szy|xv|. 4:4 | +|* V O <--XY-->00ooo10v szy|xv|. 8:44 | +| V (hl) 0011010v szy|xv|. 11:443 | +| V (XY+OFFSET) <--XY-->0011010v szy|xv|. 23:443543 | +|--------------------------------------------------------------------| +| (*) Undocumented instruction. | +| (|) The flag is explained in a previous table. | +'===================================================================*/ + +INSTRUCTION(U_a_K ) {U0(K0); PC++; return 4;} +INSTRUCTION(U_a_P ) {U1(P); PC += 2; return 4;} +INSTRUCTION(U_a_BYTE ) {U0(FETCH((PC += 2) - 1)); return 7;} +INSTRUCTION(U_a_vhl ) {U0(READ(HL)); PC++; return 7;} +INSTRUCTION(U_a_vXYpOFFSET) {U1(READ(FETCH_XY_EA((PC += 3) - 1))); return 15;} +INSTRUCTION(V_J ) {zuint8 *j = &J0; *j = V0(*j); PC++; return 4;} +INSTRUCTION(V_O ) {zuint8 *o = &O; *o = V1(*o); PC += 2; return 4;} +INSTRUCTION(V_vhl ) {WRITE(HL, V0(READ(HL))); PC++; return 11;} +INSTRUCTION(V_vXYpOFFSET ) {zuint16 ea = FETCH_XY_EA((PC += 3) - 1); WRITE(ea, V1(READ(ea))); return 19;} + + +/* MARK: - Instructions: General-Purpose Arithmetic and CPU Control Groups */ +/*-------------------------------------------------. +| 0 1 Flags T-states | +| Assembly 7654321076543210 SZYHXPNC 12 | +| -------- ---------------- -------- -------- | +| daa <--27--> szy^xp.* 4:4 | +| cpl <--2F--> ..y1x.1. 4:4 | +|+ neg <--ED-->01***100 szybxv1b 8:44 | +| ccf <--3F--> ..***.0~ 4:4 | +| scf <--37--> ..*0*.01 4:4 | +| nop <--00--> ........ 4:4 | +| halt <--76--> ........ 4:4 | +| di <--F3--> ........ 4:4 | +| ei <--FB--> ........ 4:4 | +|+ im 0 <--ED-->01*0*110 ........ 8:44 | +|+ im 1 <--ED-->01*10110 ........ 8:44 | +|+ im 2 <--ED-->01*11110 ........ 8:44 | +|--------------------------------------------------| +| (+) The instruction has undocumented opcodes. | +'=================================================*/ + +INSTRUCTION(nop ) {Q_0 PC++; return 4;} +INSTRUCTION(im_0) {Q_0 IM = 0; PC += 2; return 8;} +INSTRUCTION(im_1) {Q_0 IM = 1; PC += 2; return 8;} +INSTRUCTION(im_2) {Q_0 IM = 2; PC += 2; return 8;} + + +INSTRUCTION(daa) + { + zuint8 cf = A > 0x99, t = ((F & HF) || (A & 0xF) > 9) ? 6 : 0; + + if (F_C || cf) t |= 0x60; + t = (F & NF) ? A - t : A + t; + + FLAGS = (zuint8)( + (F & (NF | CF)) | /* NF unchanged; CF dominant */ + (t & SYXF) | /* SF = sign; YF = Y; XF = X */ + ZF_ZERO(t) | /* ZF = zero */ + ((A ^ t) & HF) | /* HF = Ai.4 != Ao.4 */ + PF_PARITY(t) | /* PF = parity */ + cf); /* CF |= 1 (if BCD carry) */ + + A = t; + PC++; + return 4; + } + + +INSTRUCTION(cpl) + { + FLAGS = F_SZPC | /* SF, ZF, PF, CF unchanged */ + ((A = ~A) & YXF) | /* YF = Y; XF = X */ + HF | NF; /* HF, NF = 1 */ + + PC++; + return 4; + } + + +INSTRUCTION(neg) + { + zuint8 t = (zuint8)-A; + + FLAGS = (zuint8)( + (t & SYXF) | /* SF = sign; YF = Y; XF = X */ + ZF_ZERO(t) | /* ZF = zero */ + ((A ^ t) & HF) | /* HF = half-borrow */ + ((t == 128) << 2) | /* PF = overflow */ + NF | /* NF = 1 */ + !!A); /* CF = borrow (not 0) */ + + A = t; + PC += 2; + return 8; + } + + +/*---------------------------------------------------------------------------. +| `ccf` and `scf` are the only instructions in which Q affects the flags. | +| Patrik Rak cracked the behavior of YF and XF in 2012, confirming that they | +| are taken, respectively, from bits 5 and 3 of the result of "(Q ^ F) | A" | +| [1,2]. This applies to all Zilog Z80 models, both NMOS and CMOS. In 2018, | +| David Banks (AKA hoglet) found that ST CMOS models do not set XF according | +| to this formula, but take this flag from bit 3 of A, while NEC NMOS models | +| take both flags from A [3]. | +| | +| References: | +| 1. https://worldofspectrum.org/forums/discussion/20345 | +| 2. https://worldofspectrum.org/forums/discussion/41704 | +| 3. Banks, David (2018-08-21). "Undocumented Z80 Flags" revision 1.0. | +| * https://github.com/hoglet67/Z80Decoder/wiki/Undocumented-Flags | +| * https://stardot.org.uk/forums/download/file.php?id=39831 | +'===========================================================================*/ + +INSTRUCTION(ccf) + { + FLAGS = (zuint8)( + (F_SZPC ^ CF) | /* SF, ZF, PF unchanged; CF = ~CFi */ + /* Zilog: YF = A.5 | (YFi ^ YQi); XF = A.3 | (XFi ^ XQi) */ + /* ST CMOS: YF = A.5 | (YFi ^ YQi); XF = A.3 */ + /* NEC NMOS: YF = A.5; XF = A.3 */ +# ifdef Z80_WITH_Q + ((((F ^ Q) & OPTIONS) | A) & YXF) | +# else + (A & YXF) | +# endif + (F_C << 4)); /* HF = CFi */ + /* NF = 0 */ + PC++; + return 4; + } + + +INSTRUCTION(scf) + { + FLAGS = F_SZP | /* SF, ZF, PF unchanged */ + /* Zilog: YF = A.5 | (YFi ^ YQi); XF = A.3 | (XFi ^ XQi) */ + /* ST CMOS: YF = A.5 | (YFi ^ YQi); XF = A.3 */ + /* NEC NMOS: YF = A.5; XF = A.3 */ +# ifdef Z80_WITH_Q + ((((F ^ Q) & OPTIONS) | A) & YXF) | +# else + (A & YXF) | +# endif + CF; /* CF = 1 */ + /* HF, NF = 0 */ + PC++; + return 4; + } + + +/*-----------------------------------------------------------------------------. +| The `halt` instruction enables the HALT state after PC is incremented during | +| the opcode fetch. The CPU neither decrements nor avoids incrementing PC "so | +| that the instruction is re-executed" as Sean Young writes in section 5.4 of | +| "The Undocumented Z80 Documented". During the HALT state, the CPU repeatedly | +| executes an internal NOP operation. Each NOP consists of 1 M1 cycle of 4 | +| T-states that fetches and disregards the next opcode after `halt` without | +| incrementing PC. This opcode is read again and again until an exit condition | +| occurs (i.e., INT, NMI or RESET). | +| | +| This was first documented by Tony Brewer in 2014, and was later re-confirmed | +| by the HALT2INT test written by Mark Woodmass (AKA Woody) in 2021. | +| | +| References: | +| * Brewer, Tony (2014-12). "Z80 Special Reset". | +| * http://primrosebank.net/computers/z80/z80_special_reset.htm | +| * https://stardot.org.uk/forums/viewtopic.php?p=357136#p357136 | +'=============================================================================*/ + +#ifdef Z80_WITH_SPECIAL_RESET + static Instruction const instruction_table[256]; +#endif + +INSTRUCTION(halt) + { + if (!HALT_LINE) + { + if (!RESUME) + { + Q_0 + PC++; + if (REQUEST) return 4; + RESUME = Z80_RESUME_HALT; + if ((self->cycles += 4) >= self->cycle_limit) return 0; + } + + SET_HALT_LINE(TRUE); + } + + if (self->nop == Z_NULL || (OPTIONS & Z80_OPTION_HALT_SKIP)) + { + zusize nop_cycles = self->cycle_limit - self->cycles; + + nop_cycles += (4 - (nop_cycles & 3)) & 3; + R += (zuint8)(nop_cycles >> 2); + self->cycles += nop_cycles; + } + +# ifdef Z80_WITH_SPECIAL_RESET + else { + zuint8 opcode; + + do { + R++; /* M1 */ + opcode = self->nop(CONTEXT, PC); + self->cycles += 4; + + if (REQUEST) + { + RESUME = FALSE; + + if (REQUEST & Z80_REQUEST_SPECIAL_RESET) + { + HALT_LINE = FALSE; + + if (self->halt != Z_NULL) + self->halt(CONTEXT, Z80_HALT_EARLY_EXIT); + + if ((DATA[0] = opcode) != 0x76) + { + self->cycles -= 4; + PC--; + return instruction_table[opcode](self); + } + } + + return 0; + } + } + while (self->cycles < self->cycle_limit); + + DATA[2] = opcode; + } + +# else + else do { + R++; /* M1 */ + (void)self->nop(CONTEXT, PC); + self->cycles += 4; + + if (REQUEST) + { + RESUME = FALSE; + return 0; + } + } + while (self->cycles < self->cycle_limit); +# endif + + return 0; + } + + +INSTRUCTION(di) + { + Q_0 + IFF1 = IFF2 = 0; + REQUEST &= ~(zuint8)Z80_REQUEST_INT; + PC++; + return 4; + } + + +INSTRUCTION(ei) + { + Q_0 + IFF1 = IFF2 = 1; + if (INT_LINE) REQUEST |= Z80_REQUEST_INT; + PC++; + return 4; + } + + +/* MARK: - Instructions: 16-Bit Arithmetic Group */ +/*--------------------------------------------------. +| 0 1 Flags T-states | +| Assembly 7654321076543210 SZYHXPNC 1234 | +| --------- ---------------- -------- -------- | +| add hl,SS 00ss1001 ..YCX.0c 11:443 | +| adc hl,SS <--ED-->01ss1010 szYCXv0c 15:4443 | +| sbc hl,SS <--ED-->01ss0010 szYBXv1b 15:4443 | +| add XY,WW <--XY-->00ww1001 ..YCX.0c 15:4443 | +| inc SS 00ss0011 ........ 6:6 | +| inc XY <--XY--><--23--> ........ 10:46 | +| dec SS 00ss1011 ........ 6:6 | +| dec XY <--XY--><--2B--> ........ 10:46 | +'==================================================*/ + +INSTRUCTION(add_hl_SS) {ADD_RR_NN(HL, SS0); PC++; return 11;} +INSTRUCTION(adc_hl_SS) {ADC_SBC_HL_SS(+, ~ss, ss + fc + HL > 65535, Z_EMPTY);} +INSTRUCTION(sbc_hl_SS) {ADC_SBC_HL_SS(-, ss, ss + fc > HL, | NF );} +INSTRUCTION(add_XY_WW) {ADD_RR_NN(XY, WW); PC += 2; return 11;} +INSTRUCTION(inc_SS ) {Q_0 (SS0)++; PC++; return 6;} +INSTRUCTION(inc_XY ) {Q_0 XY++; PC += 2; return 6;} +INSTRUCTION(dec_SS ) {Q_0 (SS0)--; PC++; return 6;} +INSTRUCTION(dec_XY ) {Q_0 XY--; PC += 2; return 6;} + + +/* MARK: - Instructions: Rotate and Shift Group */ +/*-------------------------------------------------------------------------. +| 0 1 2 3 Flags T-states | +| Assembly 76543210765432107654321076543210 SZYHXPNC 123456 | +| --------------- -------------------------------- -------- --------- | +| rlca <--07--> ..y0x.0= 4:4 | +| rla <--17--> ..y0x.0= 4:4 | +| rrca <--0F--> ..y0x.0= 4:4 | +| rra <--1F--> ..y0x.0= 4:4 | +|+ G K <--CB-->00gggkkk szy0xp0= 8:44 | +|+ G (hl) <--CB-->00ggg110 szy0xp0= 15:4443 | +|+ G (XY+OFFSET) <--XY--><--CB-->00ggg110 szy0xp0= 23:443543 | +|* G (XY+OFFSET),K <--XY--><--CB-->00gggkkk szy0xp0= 23:443543 | +| rld <--ED--><--6F--> szy0xp0. 18:44343 | +| rrd <--ED--><--67--> szy0xp0. 18:44343 | +|--------------------------------------------------------------------------| +| (+) Some forms of the instruction are undocumented. | +| (*) Undocumented instruction. | +'=========================================================================*/ + +INSTRUCTION(rlca ) {A = ROL(A); FLAGS = F_SZP | (A & YXCF); PC++; return 4;} +INSTRUCTION(rla ) {RXA(A >> 7, <<, F_C); } +INSTRUCTION(rrca ) {A = ROR(A); FLAGS = F_SZP | A_YX | (A >> 7); PC++; return 4;} +INSTRUCTION(rra ) {RXA(A & 1, >>, (F << 7)); } +INSTRUCTION(G_K ) {zuint8 *k = &K1; *k = G1(*k); return 8;} +INSTRUCTION(G_vhl ) {WRITE(HL, G1(READ(HL))); return 15;} +INSTRUCTION(G_vXYpOFFSET ) {zuint16 ea = MEMPTR; WRITE(ea, G3(READ(ea))); return 19;} +INSTRUCTION(G_vXYpOFFSET_K) {zuint16 ea = MEMPTR; WRITE(ea, K3 = G3(READ(ea))); return 19;} +INSTRUCTION(rld ) {RXD(<< 4, & 0xF, >> 4); } +INSTRUCTION(rrd ) {RXD(>> 4, << 4, & 0xF); } + + +/* MARK: - Instructions: Bit Set, Reset and Test Group */ +/*---------------------------------------------------------------------------. +| 0 1 2 3 Flags T-states | +| Assembly 76543210765432107654321076543210 SZYHXPNC 123456 | +| ----------------- -------------------------------- -------- --------- | +| bit N,K <--CB-->01nnnkkk sz*1*z0. 8:44 | +| bit N,(hl) <--CB-->01nnn110 sz*1*z0. 12:444 [1] +|+ bit N,(XY+OFFSET) <--XY--><--CB-->01nnn*** sz*1*z0. 20:44354 | +| M N,K <--CB-->1mnnnkkk ........ 8:44 | +| M N,(hl) <--CB-->1mnnn110 ........ 15:4443 | +| M N,(XY+OFFSET) <--XY--><--CB-->1mnnn110 ........ 23:443543 | +|* M N,(XY+OFFSET),K <--XY--><--CB-->1mnnnkkk ........ 23:443543 | +|----------------------------------------------------------------------------| +| (+) Some forms of the instruction are undocumented. | +| (*) Undocumented instruction. | +|----------------------------------------------------------------------------| +| 1. All versions of Zilog's "Z80 CPU User Manual" contain a typo in the | +| M-cycles of this instruction: an additional M-cycle of 4 T-states. | +'===========================================================================*/ + +INSTRUCTION(M_N_K ) {zuint8 *k = &K1; *k = M1(*k); return 8;} +INSTRUCTION(M_N_vhl ) {WRITE(HL, M1(READ(HL))); return 15;} +INSTRUCTION(M_N_vXYpOFFSET ) {zuint16 ea = MEMPTR; WRITE(ea, M3(READ(ea))); return 19;} +INSTRUCTION(M_N_vXYpOFFSET_K) {zuint16 ea = MEMPTR; WRITE(ea, K3 = M3(READ(ea))); return 19;} + + +INSTRUCTION(bit_N_K) + { + zuint8 k = K1; + zuint8 t = k & (1U << N(1)); + + /*----------------------------------------------------------. + | In section 4.1 of "The Undocumented Z80 Documented" (all | + | versions), Sean Young says that YF and XF are taken from | + | the value resulting from the bit test operation, but this | + | seems not to be true. They are copies of bits 5 and 3 of | + | the register containing the value to be tested (K). | + '==========================================================*/ + FLAGS = (t ? t & SF : ZPF) | /* SF = sign; ZF, PF = zero */ + (k & YXF) | /* YF = K.5; XF = K.3 */ + HF | /* HF = 1 */ + F_C; /* CF unchanged */ + /* NF = 0 */ + return 8; + } + + +INSTRUCTION(bit_N_vhl) + { + zuint8 t = READ(HL) & (1U << N(1)); + + /*----------------------------------------------------------------. + | This is the only instruction in which MEMPTR affects the flags. | + | YF and XF are taken, respectively, from bits 13 and 11 of this | + | internal register whose behavior was cracked in 2006 by boo_boo | + | and Vladimir Kladov. Official schematics refer to this register | + | as WZ, but this emulator uses the name "MEMPTR" to honour those | + | who cracked it. | + | | + | References: | + | * https://zxpress.ru/zxnet/zxnet.pc/5909 | + | * boo_boo; Kladov, Vladimir (2006-03-29). "MEMPTR, Esoteric | + | Register of the Zilog Z80 CPU". | + | * http://zx.pk.ru/showpost.php?p=43688 | + | * http://zx.pk.ru/attachment.php?attachmentid=2984 | + | * http://zx.pk.ru/showpost.php?p=43800 | + | * http://zx.pk.ru/attachment.php?attachmentid=2989 | + '================================================================*/ + FLAGS = (t ? t & SF : ZPF) | /* SF = sign; ZF, PF = zero */ + (MEMPTRH & YXF) | /* YF = MEMPTRH.5; XF = MEMPTRH.3 */ + HF | /* HF = 1 */ + F_C; /* CF unchanged */ + /* NF = 0 */ + return 12; + } + + +INSTRUCTION(bit_N_vXYpOFFSET) + { + zuint8 t = READ(MEMPTR) & (1U << N(3)); + + FLAGS = (t ? t & SF : ZPF) | /* SF sign; ZF, PF = zero */ + (MEMPTRH & YXF) | /* YF = EA.13; XF = EA.11 */ + HF | /* HF = 1 */ + F_C; /* CF unchanged */ + /* NF = 0 */ + return 16; + } + + +/* MARK: - Instructions: Jump Group */ +/*----------------------------------------------------------------. +| 0 1 2 Flags T-states | +| Assembly 765432107654321076543210 SZYHXPNC Y 123 N 12 | +| ----------- ------------------------ -------- ------------ | +| jp WORD <--C3--><-----WORD-----> ........ 10:433 | +| jp Z,WORD 11zzz010<-----WORD-----> ........ 10:433 | +| jr OFFSET <--18--> ........ 12:435 | +| jr Z,OFFSET 001zz000 ........ 12:435 7:43 | +| jp (hl) <--E9--> ........ 4:4 | +| jp (XY) <--XY--><--E9--> ........ 8:44 | +| djnz OFFSET <--10--> ........ 13:535 8:53 | +'================================================================*/ + +INSTRUCTION(jp_WORD ) {Q_0 MEMPTR = PC = FETCH_16(PC + 1); return 10;} +INSTRUCTION(jp_Z_WORD ) {Q_0 MEMPTR = FETCH_16(PC + 1); PC = Z(7) ? MEMPTR : PC + 3; return 10;} +INSTRUCTION(jr_OFFSET ) {Q_0 MEMPTR = (PC += 2 + (zsint8)FETCH(PC + 1)); return 12;} +INSTRUCTION(jr_Z_OFFSET) {DJNZ_JR_Z_OFFSET(Z(3), 12, 7); } +INSTRUCTION(jp_hl ) {Q_0 PC = HL; return 4;} +INSTRUCTION(jp_XY ) {Q_0 PC = XY; return 4;} +INSTRUCTION(djnz_OFFSET) {DJNZ_JR_Z_OFFSET(--B, 13, 8); } + + +/* MARK: - Instructions: Call and Return Group */ +/*--------------------------------------------------------------------. +| 0 1 2 Flags T-states | +| Assembly 765432107654321076543210 SZYHXPNC Y 123 N 123 | +| ----------- ------------------------ -------- ---------------- | +| call WORD <--CD--><-----WORD-----> ........ 17:43433 | +| call Z,WORD 11zzz100<-----WORD-----> ........ 17:43433 10:433 | +| ret <--C9--> ........ 10:433 | +| ret Z 11zzz000 ........ 11:533 5:5 | +|+ reti/retn <--ED-->01***101 ........ 14:4433 | +| rst N 11nnn111 ........ 11:533 | +|---------------------------------------------------------------------| +| (+) The instruction has undocumented opcodes. The `reti` mnemonic | +| is used to represent the ED4Dh opcode, which is recognized by | +| the Z80 CTC chip. All other opcodes are represented as `retn`. | +'====================================================================*/ + +INSTRUCTION(call_WORD) {Q_0 MEMPTR = FETCH_16(PC + 1); PUSH(PC + 3); PC = MEMPTR; return 17;} +INSTRUCTION(ret ) {Q_0 RET; return 10;} +INSTRUCTION(ret_Z ) {Q_0 if (Z(7)) {RET; return 11;} PC++; return 5;} +INSTRUCTION(reti ) {RETX(reti); } +INSTRUCTION(retn ) {RETX(retn); } +INSTRUCTION(rst_N ) {Q_0 PUSH(PC + 1); MEMPTR = PC = DATA[0] & 56; return 11;} + + +INSTRUCTION(call_Z_WORD) + { + Q_0 + MEMPTR = FETCH_16(PC + 1); /* always */ + + if (Z(7)) + { + PUSH(PC + 3); + PC = MEMPTR; + return 17; + } + + PC += 3; + return 10; + } + + +/* MARK: - Instructions: Input and Output Group */ +/*--------------------------------------------------------------. +| 0 1 Flags T-states | +| Assembly 7654321076543210 SZYHXPNC !0 12345 =0 1234 | +| ------------ ---------------- -------- ----------------- | +| in a,(BYTE) <--DB--><-BYTE-> ........ 11:434 | +| in J,(c) <--ED-->01jjj000 szy0xp0. 12:444 | +|* in (c) <--ED--><--70--> szy0xp0. 12:444 | +| ini <--ED--><--A2--> ******** 16:4543 [1] +| inir <--ED--><--B2--> ******** 21:45435 16:4543 [1] +| ind <--ED--><--AA--> ******** 16:4543 [1] +| indr <--ED--><--BA--> ******** 21:45435 16:4543 [1] +| out (BYTE),a <--D3--><-BYTE-> ........ 11:434 | +| out (c),J <--ED-->01jjj001 ........ 12:444 | +|* out (c),0 <--ED--><--71--> ........ 12:444 | +| outi <--ED--><--A3--> ******** 16:4534 | +| otir <--ED--><--B3--> ******** 21:45345 16:4534 | +| outd <--ED--><--AB--> ******** 16:4534 | +| otdr <--ED--><--BB--> ******** 21:45345 16:4534 | +|---------------------------------------------------------------| +| (*) Undocumented instruction. | +|---------------------------------------------------------------| +| 1. All versions of Zilog's "Z80 CPU User Manual" have a typo | +| in the M-cycles of these instructions: the T-states of the | +| 3rd and 4th M-cycles are swapped. | +'==============================================================*/ + +INSTRUCTION(in_J_vc ) {IN_VC; J1 = t; PC += 2; return 12;} +INSTRUCTION(in_vc ) {IN_VC; PC += 2; return 12;} +INSTRUCTION(ini ) {INX (++, +); } +INSTRUCTION(inir ) {INXR(++, +); } +INSTRUCTION(ind ) {INX (--, -); } +INSTRUCTION(indr ) {INXR(--, -); } +INSTRUCTION(out_vc_J) {Q_0 MEMPTR = BC + 1; OUT(BC, J1); PC += 2; return 12;} +INSTRUCTION(outi ) {OUTX(++, +); } +INSTRUCTION(otir ) {OTXR(++, +); } +INSTRUCTION(outd ) {OUTX(--, -); } +INSTRUCTION(otdr ) {OTXR(--, -); } + + +INSTRUCTION(in_a_vBYTE) + { + zuint16 t; + + Q_0 + + /*--------------------------------------------------------------------. + | In "MEMPTR, Esoteric Register of the Zilog Z80 CPU", boo_boo says | + | that MEMPTR is set to `((A << 8) | BYTE) + 1`, which causes a carry | + | from the LSbyte of the resulting port number if BYTE is 255. This | + | differs from all other instructions where MEMPTRH is set to A, but | + | it has been confirmed to be correct by the IN-MEMPTR test. | + '====================================================================*/ + MEMPTR = (t = (zuint16)(((zuint16)A << 8) | FETCH((PC += 2) - 1))) + 1; + + A = IN(t); + return 11; + } + + +INSTRUCTION(out_vBYTE_a) + { + zuint8 t; + + Q_0 + MEMPTRL = (t = FETCH((PC += 2) - 1)) + 1; + MEMPTRH = A; + OUT((zuint16)(((zuint16)A << 8) | t), A); + return 11; + } + + +/*----------------------------------------------------------------------------. +| The `out (c),0` instruction behaves as `out (c),255` on the Zilog Z80 CMOS. | +| This was first discovered by Simon Cooke, who reported it on Usenet in 1996 | +| [1]. Later, in 2004, Colin Piggot rediscovered it with his SAM Coupé when | +| running a demo for SCPDU 6, coincidentally written by Simon Cooke [2]. In | +| 2008, this was once again rediscovered by the MSX community [3]. | +| | +| References: | +| 1. https://groups.google.com/g/comp.os.cpm/c/HfSTFpaIkuU/m/KotvMWu3bZoJ | +| 2. https://sinclair.wiki.zxnet.co.uk/wiki/Z80 | +| 3. https://msx.org/forum/development/msx-development/bug-z80-emulation-or- | +| tr-hw | +'============================================================================*/ + +INSTRUCTION(out_vc_0) + { + Q_0 + PC += 2; + MEMPTR = BC + 1; + OUT(BC, (OPTIONS & Z80_OPTION_OUT_VC_255) ? 255 : 0); + return 12; + } + + +/* MARK: - Instructions: Optimizations */ + +INSTRUCTION(nop_nop) {Q_0; PC += 2; return 4;} + + +/* MARK: - Instruction Function Tables */ + +INSTRUCTION(cb_prefix ); +INSTRUCTION(ed_prefix ); +INSTRUCTION(dd_prefix ); +INSTRUCTION(fd_prefix ); +INSTRUCTION(xy_cb_prefix); +INSTRUCTION(xy_xy ); +INSTRUCTION(ed_illegal ); +INSTRUCTION(xy_illegal ); +INSTRUCTION(hook ); + +#ifdef Z80_WITH_UNOFFICIAL_RETI +# define reti_retn reti +#else +# define reti_retn retn +#endif + +static Instruction const instruction_table[256] = { +/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ +/* 0 */ nop, ld_SS_WORD, ld_vbc_a, inc_SS, V_J, V_J, ld_J_BYTE, rlca, ex_af_af_, add_hl_SS, ld_a_vbc, dec_SS, V_J, V_J, ld_J_BYTE, rrca, +/* 1 */ djnz_OFFSET, ld_SS_WORD, ld_vde_a, inc_SS, V_J, V_J, ld_J_BYTE, rla, jr_OFFSET, add_hl_SS, ld_a_vde, dec_SS, V_J, V_J, ld_J_BYTE, rra, +/* 2 */ jr_Z_OFFSET, ld_SS_WORD, ld_vWORD_hl, inc_SS, V_J, V_J, ld_J_BYTE, daa, jr_Z_OFFSET, add_hl_SS, ld_hl_vWORD, dec_SS, V_J, V_J, ld_J_BYTE, cpl, +/* 3 */ jr_Z_OFFSET, ld_SS_WORD, ld_vWORD_a, inc_SS, V_vhl, V_vhl, ld_vhl_BYTE, scf, jr_Z_OFFSET, add_hl_SS, ld_a_vWORD, dec_SS, V_J, V_J, ld_J_BYTE, ccf, +/* 4 */ nop, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_vhl, ld_J_K, ld_J_K, nop, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_vhl, ld_J_K, +/* 5 */ ld_J_K, ld_J_K, nop, ld_J_K, ld_J_K, ld_J_K, ld_J_vhl, ld_J_K, ld_J_K, ld_J_K, ld_J_K, nop, ld_J_K, ld_J_K, ld_J_vhl, ld_J_K, +/* 6 */ ld_J_K, ld_J_K, ld_J_K, ld_J_K, hook, ld_J_K, ld_J_vhl, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_K, nop, ld_J_vhl, ld_J_K, +/* 7 */ ld_vhl_K, ld_vhl_K, ld_vhl_K, ld_vhl_K, ld_vhl_K, ld_vhl_K, halt, ld_vhl_K, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_K, ld_J_vhl, nop, +/* 8 */ U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, +/* 9 */ U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, +/* A */ U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, +/* B */ U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_K, U_a_vhl, U_a_K, +/* C */ ret_Z, pop_TT, jp_Z_WORD, jp_WORD, call_Z_WORD, push_TT, U_a_BYTE, rst_N, ret_Z, ret, jp_Z_WORD, cb_prefix, call_Z_WORD, call_WORD, U_a_BYTE, rst_N, +/* D */ ret_Z, pop_TT, jp_Z_WORD, out_vBYTE_a, call_Z_WORD, push_TT, U_a_BYTE, rst_N, ret_Z, exx, jp_Z_WORD, in_a_vBYTE, call_Z_WORD, dd_prefix, U_a_BYTE, rst_N, +/* E */ ret_Z, pop_TT, jp_Z_WORD, ex_vsp_hl, call_Z_WORD, push_TT, U_a_BYTE, rst_N, ret_Z, jp_hl, jp_Z_WORD, ex_de_hl, call_Z_WORD, ed_prefix, U_a_BYTE, rst_N, +/* F */ ret_Z, pop_TT, jp_Z_WORD, di, call_Z_WORD, push_TT, U_a_BYTE, rst_N, ret_Z, ld_sp_hl, jp_Z_WORD, ei, call_Z_WORD, fd_prefix, U_a_BYTE, rst_N +}; + +static Instruction const cb_instruction_table[256] = { +/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ +/* 0 */ G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, +/* 1 */ G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, +/* 2 */ G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, +/* 3 */ G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, G_K, G_K, G_K, G_K, G_K, G_K, G_vhl, G_K, +/* 4 */ bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, +/* 5 */ bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, +/* 6 */ bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, +/* 7 */ bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_K, bit_N_vhl, bit_N_K, +/* 8 */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, +/* 9 */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, +/* A */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, +/* B */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, +/* C */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, +/* D */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, +/* E */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, +/* F */ M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_K, M_N_vhl, M_N_K +}; + +static Instruction const ed_instruction_table[256] = { +/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ +/* 0 */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* 1 */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* 2 */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* 3 */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* 4 */ in_J_vc, out_vc_J, sbc_hl_SS, ld_vWORD_SS, neg, retn, im_0, ld_i_a, in_J_vc, out_vc_J, adc_hl_SS, ld_SS_vWORD, neg, reti, im_0, ld_r_a, +/* 5 */ in_J_vc, out_vc_J, sbc_hl_SS, ld_vWORD_SS, neg, retn, im_1, ld_a_i, in_J_vc, out_vc_J, adc_hl_SS, ld_SS_vWORD, neg, reti_retn, im_2, ld_a_r, +/* 6 */ in_J_vc, out_vc_J, sbc_hl_SS, ld_vWORD_SS, neg, retn, im_0, rrd, in_J_vc, out_vc_J, adc_hl_SS, ld_SS_vWORD, neg, reti_retn, im_0, rld, +/* 7 */ in_vc, out_vc_0, sbc_hl_SS, ld_vWORD_SS, neg, retn, im_1, ed_illegal, in_J_vc, out_vc_J, adc_hl_SS, ld_SS_vWORD, neg, reti_retn, im_2, ed_illegal, +/* 8 */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* 9 */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* A */ ldi, cpi, ini, outi, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ldd, cpd, ind, outd, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* B */ ldir, cpir, inir, otir, ed_illegal, ed_illegal, ed_illegal, ed_illegal, lddr, cpdr, indr, otdr, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* C */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* D */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* E */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, +/* F */ ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal, ed_illegal +}; + +static Instruction const xy_instruction_table[256] = { +/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ +/* 0 */ nop_nop, xy_illegal, xy_illegal, xy_illegal, V_O, V_O, ld_O_BYTE, xy_illegal, xy_illegal, add_XY_WW, xy_illegal, xy_illegal, V_O, V_O, ld_O_BYTE, xy_illegal, +/* 1 */ xy_illegal, xy_illegal, xy_illegal, xy_illegal, V_O, V_O, ld_O_BYTE, xy_illegal, xy_illegal, add_XY_WW, xy_illegal, xy_illegal, V_O, V_O, ld_O_BYTE, xy_illegal, +/* 2 */ xy_illegal, ld_XY_WORD, ld_vWORD_XY, inc_XY, V_O, V_O, ld_O_BYTE, xy_illegal, xy_illegal, add_XY_WW, ld_XY_vWORD, dec_XY, V_O, V_O, ld_O_BYTE, xy_illegal, +/* 3 */ xy_illegal, xy_illegal, xy_illegal, xy_illegal, V_vXYpOFFSET, V_vXYpOFFSET, ld_vXYpOFFSET_BYTE, xy_illegal, xy_illegal, add_XY_WW, xy_illegal, xy_illegal, V_O, V_O, ld_O_BYTE, xy_illegal, +/* 4 */ nop_nop, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_J_vXYpOFFSET, ld_O_P, ld_O_P, nop_nop, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_J_vXYpOFFSET, ld_O_P, +/* 5 */ ld_O_P, ld_O_P, nop_nop, ld_O_P, ld_O_P, ld_O_P, ld_J_vXYpOFFSET, ld_O_P, ld_O_P, ld_O_P, ld_O_P, nop_nop, ld_O_P, ld_O_P, ld_J_vXYpOFFSET, ld_O_P, +/* 6 */ ld_O_P, ld_O_P, ld_O_P, ld_O_P, nop_nop, ld_O_P, ld_J_vXYpOFFSET, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_O_P, nop_nop, ld_J_vXYpOFFSET, ld_O_P, +/* 7 */ ld_vXYpOFFSET_K, ld_vXYpOFFSET_K, ld_vXYpOFFSET_K, ld_vXYpOFFSET_K, ld_vXYpOFFSET_K, ld_vXYpOFFSET_K, xy_illegal, ld_vXYpOFFSET_K, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_O_P, ld_J_vXYpOFFSET, nop_nop, +/* 8 */ U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, +/* 9 */ U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, +/* A */ U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, +/* B */ U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_P, U_a_vXYpOFFSET, U_a_P, +/* C */ xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_cb_prefix, xy_illegal, xy_illegal, xy_illegal, xy_illegal, +/* D */ xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_xy, xy_illegal, xy_illegal, +/* E */ xy_illegal, pop_XY, xy_illegal, ex_vsp_XY, xy_illegal, push_XY, xy_illegal, xy_illegal, xy_illegal, jp_XY, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, +/* F */ xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, xy_illegal, ld_sp_XY, xy_illegal, xy_illegal, xy_illegal, xy_xy, xy_illegal, xy_illegal +}; + +static Instruction const xy_cb_instruction_table[256] = { +/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ +/* 0 */ G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, +/* 1 */ G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, +/* 2 */ G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, +/* 3 */ G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET_K, G_vXYpOFFSET, G_vXYpOFFSET_K, +/* 4 */ bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, +/* 5 */ bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, +/* 6 */ bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, +/* 7 */ bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, bit_N_vXYpOFFSET, +/* 8 */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, +/* 9 */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, +/* A */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, +/* B */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, +/* C */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, +/* D */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, +/* E */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, +/* F */ M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET_K, M_N_vXYpOFFSET, M_N_vXYpOFFSET_K +}; + + +/* MARK: - Instructions: Prefix Handling */ + +INSTRUCTION(cb_prefix) + { + R++; + return cb_instruction_table[DATA[1] = FETCH_OPCODE((PC += 2) - 1)](self); + } + + +INSTRUCTION(ed_prefix) + { + R++; + return ed_instruction_table[DATA[1] = FETCH_OPCODE(PC + 1)](self); + } + + +#define XY_PREFIX(register) \ + zuint8 cycles; \ + \ + if ((self->cycles += 4) >= self->cycle_limit) \ + { \ + RESUME = Z80_RESUME_XY; \ + return 0; \ + } \ + \ + R++; \ + XY = register; \ + cycles = xy_instruction_table[DATA[1] = FETCH_OPCODE(PC + 1)](self); \ + register = XY; \ + return cycles; + + +INSTRUCTION(dd_prefix) {XY_PREFIX(IX)} +INSTRUCTION(fd_prefix) {XY_PREFIX(IY)} + + +/*------------------------------------------------------------------------. +| Instructions with DDCBh or FDCBh prefix increment R by 2, as only the | +| bytes of the prefix are fetched by opcode fetch operations (M1 cycles). | +| The remaining 2 bytes are fetched by normal memory read operations. | +'========================================================================*/ + +INSTRUCTION(xy_cb_prefix) + { + FETCH_XY_EA((PC += 4) - 2); + return xy_cb_instruction_table[DATA[3] = FETCH(PC - 1)](self); + } + + +/*-----------------------------------------------------------------------------. +| In a sequence of DDh and/or FDh prefixes, it is the last one that counts, as | +| each prefix disables and replaces the previous one. No matter how long the | +| sequence is, interrupts can only be responded after all prefixes are fetched | +| and the final instruction is executed. Each prefix consumes 4 T-states. | +'=============================================================================*/ + +INSTRUCTION(xy_xy) + { + zuint8 cycles; + zuint8 first_prefix = DATA[0]; + + do { + PC++; + DATA[0] = DATA[1]; + + if ((self->cycles += 4) >= self->cycle_limit) + { + RESUME = Z80_RESUME_XY; + return 0; + } + + R++; + } + while (IS_XY_PREFIX(DATA[1] = FETCH_OPCODE(PC + 1))); + + if (DATA[0] == first_prefix) return xy_instruction_table[DATA[1]](self); + + if (first_prefix == 0xFD) + { + XY = IX; + cycles = xy_instruction_table[DATA[1]](self); + IX = XY; + XY = IY; + } + + else { + XY = IY; + cycles = xy_instruction_table[DATA[1]](self); + IY = XY; + XY = IX; + } + + return cycles; + } + + +/* MARK: - Instructions: Illegal */ + +/*------------------------------------------------------------------. +| The CPU ignores illegal instructions with EDh prefix; in practice | +| they are all equivalent to two `nop` instructions (8 T-states). | +'==================================================================*/ + +INSTRUCTION(ed_illegal) + { + if (self->illegal != Z_NULL) return self->illegal(CONTEXT, DATA[0]); + Q_0 + PC += 2; + return 8; + } + + +/*------------------------------------------------------------------------. +| Illegal instructions with DDh or FDh prefix cause the CPU to ignore the | +| prefix, i.e., the byte immediately following the prefix is interpreted | +| as the first byte of a new instruction. The prefix consumes 4 T-states. | +'========================================================================*/ + +INSTRUCTION(xy_illegal) + { + PC++; + return instruction_table[DATA[0] = DATA[1]](self); + } + + +/* MARK: - Instructions: Hooking */ + +INSTRUCTION(hook) + { + if (self->hook == Z_NULL) + { + Q_0 + PC++; + return 4; + } + + if ((DATA[0] = self->hook(CONTEXT, PC)) != Z80_HOOK) + return instruction_table[DATA[0]](self); + + R--; + return 0; + } + + +/* MARK: - Interrupt Mode 0: PC Decrements for Unprefixed Instructions */ + +#ifdef Z80_WITH_FULL_IM0 + static zuint8 const im0_pc_decrement_table[256] = { + /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ + /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 1 */ 2, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, + /* 2 */ 2, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, + /* 3 */ 2, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, + /* 4 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 5 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 6 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 7 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 9 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* A */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* B */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* C */ 1, 0, 3, 0, 3, 0, 0, 1, 1, 0, 3, 0, 3, 3, 0, 1, + /* D */ 1, 0, 3, 0, 3, 0, 0, 1, 1, 0, 3, 0, 3, 0, 0, 1, + /* E */ 1, 0, 3, 0, 3, 0, 0, 1, 1, 0, 3, 0, 3, 0, 0, 1, + /* F */ 1, 0, 3, 0, 3, 0, 0, 1, 1, 0, 3, 0, 3, 0, 0, 1 + }; +#endif + + +/* MARK: - Interrupt Mode 0: Callback Trampolines */ + +#ifdef Z80_WITH_FULL_IM0 + static zuint8 im0_fetch(IM0 *self, zuint16 address) + { + Z_UNUSED(address) + return self->z80->int_fetch(CONTEXT, self->pc); + } + + + static zuint8 im0_read(IM0 *self, zuint16 address) + {return READ(address);} + + + static void im0_write(IM0 *self, zuint16 address, zuint8 value) + {WRITE(address, value);} + + + static zuint8 im0_in(IM0 *self, zuint16 port) + {return IN(port);} + + + static void im0_out(IM0 *self, zuint16 port, zuint8 value) + {OUT(port, value);} + + + static void im0_ld_i_a(IM0 *self) {NOTIFY(ld_i_a);} + static void im0_ld_r_a(IM0 *self) {NOTIFY(ld_r_a);} + static void im0_reti (IM0 *self) {NOTIFY(reti );} + static void im0_retn (IM0 *self) {NOTIFY(retn );} +#endif + + +/* MARK: - Public Functions */ + +/*----------------------------------------------------------------------. +| On POWER-ON, the CPU zeroes PC, I, and R, sets SP, IX, IY, AF, BC, | +| DE, HL, AF', BC', DE' and HL' to to FFFFh [1,2], resets the interrupt | +| enable flip-flops (IFF1 and IFF2) and selects interrupt mode 0 [3]. | +| On Zilog NMOS models, F is sometimes set to FDh (NF reset) [1]. | +| | +| There is no information about the initial state of MEMPTR and Q, so | +| they are assumed to be 0. | +| | +| References: | +| 1. https://baltazarstudios.com/webshare/Z80-undocumented-behavior.htm | +| 2. https://worldofspectrum.org/forums/discussion/34574 | +| 3. Young, Sean (2005-09-18). "Undocumented Z80 Documented, The" | +| v0.91, p. 20. | +'======================================================================*/ + +Z80_API void z80_power(Z80 *self, zboolean state) + { + MEMPTR = PC = R = I = IFF1 = IFF2 = IM = Q = + DATA[0] = HALT_LINE = INT_LINE = RESUME = REQUEST = 0; + + SP = IX = IY = AF = BC = DE = HL = AF_ = BC_ = DE_ = HL_ = + state ? Z_UINT16(0xFFFF) : 0; + } + + +/*--------------------------------------------------------------------------. +| The normal RESET zeroes PC, I, and R [1,2,3,4,5,6], resets the interrupt | +| enable flip-flops (IFF1 and IFF2) [1,2,3,4,5] and selects the interrupt | +| mode 0 [1,2,3,4,7]. | +| | +| References: | +| 1. Zilog (2016-09). "Z80 CPU User Manual" revision 11, p. 6. | +| 2. SGS-Thomson (1990-01). "Z80 Microprocessor Family" 1st edition, p. 33. | +| 3. Brewer, Tony (2014-12). "Z80 Special Reset". | +| * http://primrosebank.net/computers/z80/z80_special_reset.htm | +| 4. Flammenkamp, Achim. "Interrupt Behaviour of the Z80 CPU". | +| * http://z80.info/interrup.htm | +| 5. https://baltazarstudios.com/webshare/Z80-undocumented-behavior.htm | +| 6. https://worldofspectrum.org/forums/discussion/34574 | +| 7. Zilog (1978-05). "Z80 Family Program Interrupt Structure, The", p. 8. | +'==========================================================================*/ + +Z80_API void z80_instant_reset(Z80 *self) + { + if (HALT_LINE) {SET_HALT_LINE(FALSE);} + + PC = R = I = IFF1 = IFF2 = IM = + DATA[0] = HALT_LINE = RESUME = REQUEST = 0; + } + + +#ifdef Z80_WITH_SPECIAL_RESET + Z80_API void z80_special_reset(Z80 *self) + {REQUEST |= Z80_REQUEST_SPECIAL_RESET;} +#endif + + +Z80_API void z80_int(Z80 *self, zboolean state) + { + if (!(INT_LINE = state)) REQUEST &= ~(zuint8)Z80_REQUEST_INT; + else if (IFF1) REQUEST |= Z80_REQUEST_INT; + } + + +Z80_API void z80_nmi(Z80 *self) + {REQUEST |= Z80_REQUEST_NMI;} + + +#ifdef Z80_WITH_EXECUTE + Z80_API zusize z80_execute(Z80 *self, zusize cycles) + { + ZInt16 *xy; + + R7 = R; + self->cycles = 0; + self->cycle_limit = cycles; + + if (RESUME && cycles) switch (RESUME) + { + case Z80_RESUME_HALT: + (void)halt(self); + break; + + case Z80_RESUME_XY: + RESUME = FALSE; + R++; /* M1 */ + XY = (xy = &self->ix_iy[(DATA[0] >> 5) & 1])->uint16_value; + self->cycles += xy_instruction_table[DATA[1] = FETCH_OPCODE(PC + 1)](self); + xy->uint16_value = XY; + break; + } + + while (self->cycles < cycles) + { + R++; /* M1 */ + self->cycles += instruction_table[DATA[0] = FETCH_OPCODE(PC)](self); + } + + R = R_ALL; /* restore R7 bit */ + return self->cycles; /* return consumed cycles */ + } +#endif + + +Z80_API zusize z80_run(Z80 *self, zusize cycles) + { + ZInt16 *xy; + zuint8 ird; + + /*---------------------------------------------------------------------. + | The CPU increments R during each M1 cycle without altering the most | + | significant bit, commonly known as R7. This behavior is not emulated | + | in every increment for obvious speed reasons. Instead, a copy of R | + | is used to preserve R7, which is restored before returning from this | + | function. The emulation of `ld {a,r|r,a}` takes this into account. | + '=====================================================================*/ + R7 = R; + + self->cycles = 0; + self->cycle_limit = cycles; + + if (RESUME && cycles) switch (RESUME) + { + /*----------------------------------------------------------------. + | The CPU is halted. In order to avoid affecting the speed of the | + | main execution loop, this state is executed by a dedicated loop | + | within the function that emulates the `halt` instruction. | + '================================================================*/ + case Z80_RESUME_HALT: + if (REQUEST) + { + RESUME = FALSE; + +# ifdef Z80_WITH_SPECIAL_RESET + if ((REQUEST & Z80_REQUEST_SPECIAL_RESET) && HALT_LINE) + { + zuint8 opcode; + + HALT_LINE = FALSE; + + if (self->halt != Z_NULL) + self->halt(CONTEXT, Z80_HALT_EARLY_EXIT); + + if (IS_XY_PREFIX(DATA[0] = opcode = DATA[2])) + self->cycles += instruction_table[FETCH_OPCODE(PC)](self); + + else if (opcode != 0x76) + { + PC--; + self->cycles += instruction_table[opcode](self) - 4; + } + } +# endif + } + + else (void)halt(self); + break; + + /*--------------------------------------------------------------. + | The CPU is in normal operation state; the emulator ran out of | + | clock cycles by fetching a DDh or FDh prefix. | + '==============================================================*/ + case Z80_RESUME_XY: + RESUME = FALSE; + R++; + XY = (xy = &self->ix_iy[(DATA[0] >> 5) & 1])->uint16_value; + self->cycles += xy_instruction_table[DATA[1] = FETCH_OPCODE(PC + 1)](self); + xy->uint16_value = XY; + break; + + /*----------------------------------------------------------------. + | The CPU is responding to an INT in mode 0; the emulator ran out | + | clock cycles by fetching a DDh or FDh prefix. | + '================================================================*/ +# ifdef Z80_WITH_FULL_IM0 + case Z80_RESUME_IM0_XY: + ird = DATA[0]; + goto im0_begin; +# endif + } + + while (self->cycles < cycles) /* main execution loop */ + { + if (REQUEST) + { + /*-------------------------------------------------------------------------. + | After detecting a special RESET signal, the CPU completes the ongoing | + | instruction or interrupt response and then zeroes PC during the falling | + | edge of the next M1T1. The special RESET can be used in conjunction with | + | an interrupt, in which case PC is zeroed during the subsequent interrupt | + | acknowledge M-cycle. Otherwise, if no interrupt has been accepted at TL | + | of the instruction or interrupt response in which the special RESET has | + | been detected, the CPU produces an M1 cycle of 4 T-states to allow for | + | the fetch-execute overlap to take place, during which it fetches the | + | next opcode and zeroes PC. | + | | + | References: | + | * Brewer, Tony (2014-12). "Z80 Special Reset". | + | * http://primrosebank.net/computers/z80/z80_special_reset.htm | + | * US Patent 4486827 | + | * Checked with "Visual Z80 Remix". | + '=========================================================================*/ +# ifdef Z80_WITH_SPECIAL_RESET + zuint8 special_reset = REQUEST & Z80_REQUEST_SPECIAL_RESET; +# endif + + /*-------------------------------------------------------------------------. + | NMI Response: Execute `rst 66h` | T-states: 11:533 | + |--------------------------------------------------------------------------| + | The non-maskable interrupt takes priority over the maskable interrupt | + | and cannot be disabled under software control. Its usual function is to | + | provide immediate response to important signals. The CPU responds to an | + | NMI by storing PC on the stack and jumping to the ISR located at address | + | 0066h. The interrupt enable flip-flop 1 (IFF1) is reset to prevent any | + | INT from being accepted during the execution of this routine, which is | + | usually exited by using a `reti` or `retn` instruction to restore the | + | original state of IFF1 [1]. | + | | + | Some technical documents from Zilog include an erroneous timing diagram | + | showing an NMI acknowledge cycle of 4 T-states. However, documents from | + | other manufacturers and third parties specify that this M-cycle has 5 | + | T-states, as has been confirmed by low-level tests [2] and electronic | + | simulations [3]. | + | | + | The CPU does not accept a second NMI during the NMI response. Therefore, | + | it is not possible to chain two NMI responses in a row without executing | + | at least one instruction between them [3,4,5]. | + | | + | References: | + | 1. Zilog (1978-05). "Z80 Family Program Interrupt Structure, The", | + | pp. 4,5. | + | 2. https://baltazarstudios.com/webshare/Z80-undocumented-behavior.htm | + | 3. Checked with "Visual Z80 Remix". | + | 4. https://spectrumcomputing.co.uk/forums/viewtopic.php?t=7086 | + | 5. https://stardot.org.uk/forums/viewtopic.php?t=24662 | + '=========================================================================*/ + if (REQUEST & Z80_REQUEST_REJECT_NMI) + REQUEST = 0; + + else if (REQUEST & Z80_REQUEST_NMI) + { + REQUEST = Z80_REQUEST_REJECT_NMI; + IFF1 = 0; + if (HALT_LINE) {SET_HALT_LINE(FALSE);} + R++; /* M1 */ + if (self->nmia != Z_NULL) (void)self->nmia(CONTEXT, PC); + DATA[0] = 0; + Q_0 + +# ifdef Z80_WITH_SPECIAL_RESET + PUSH(PC >> special_reset); +# else + PUSH(PC); +# endif + + PC = MEMPTR = 0x66; + self->cycles += 11; + continue; + } + + /*-------------------------------------------------------------------------. + | INT Response | + |--------------------------------------------------------------------------| + | The maskable interrupt can be enabled and disabled by using the `ei` and | + | `di` instructions respectively, which control the state of the interrupt | + | enable flip-flops (IFF1 and IFF2). The CPU does not accept this kind of | + | interrupt directly after an `ei` instruction, but only after the one | + | following `ei` is executed. This is so that ISRs can return without the | + | danger of being interrupted immediately after re-enabling interrupts if | + | the /INT line is still active, which could cause a stack overflow. | + | | + | As in `ei`, all forms of `reti` and `retn` defer the acceptance of the | + | maskable interrupt for one instruction, but this only occurs when IFF1 | + | and IFF2 do not have the same state prior to the execution of either of | + | these instructions, which can only be caused by an earlier NMI response | + | [1,2,3]. | + | | + | References: | + | 1. https://floooh.github.io/2021/12/17/cycle-stepped-z80.html | + | 2. https://spectrumcomputing.co.uk/forums/viewtopic.php?t=7086 | + | 3. https://stardot.org.uk/forums/viewtopic.php?t=24662 | + '=========================================================================*/ + else if ( +# ifdef Z80_WITH_SPECIAL_RESET + (REQUEST & Z80_REQUEST_INT) && +# endif + /* if the previous instruction is not `ei` */ + DATA[0] != 0xFB && + /* if the previous instruction is not `reti/retn` or IFF1 has not changed */ + (self->data.uint32_value & Z_UINT32_BIG_ENDIAN(Z_UINT32(0xFFC7FF00))) + != Z_UINT32_BIG_ENDIAN(Z_UINT32(0xED450000)) + ) + { +# ifdef Z80_WITH_FULL_IM0 + Z80Read hook; + IM0 im0; +# endif + + REQUEST = IFF1 = IFF2 = 0; + if (HALT_LINE) {SET_HALT_LINE(FALSE);} + + /*-------------------------------------------------------------------. + | Due to a bug, the Zilog Z80 NMOS resets PF when an INT is accepted | + | during the execution of the `ld a,{i|r}` instructions. | + '===================================================================*/ +# ifdef Z80_WITH_ZILOG_NMOS_LD_A_IR_BUG + if ( (OPTIONS & Z80_OPTION_LD_A_IR_BUG) && + (self->data.uint16_array[0] & Z_UINT16_BIG_ENDIAN(Z_UINT16(0xFFF7))) + == Z_UINT16_BIG_ENDIAN(Z_UINT16(0xED57)) + ) + FLAGS = F & ~(zuint8)PF; +# endif + + /*---------------------------------------------------------------------. + | The INT acknowledge cycle (INTA) indicates that the interrupting I/O | + | device can write to the data bus. 2 wait T-states are automatically | + | added to this M-cycle, allowing sufficient time to identify which | + | device must insert the interrupt response data (IRD). The first and | + | posibly sole byte of the IRD is read from the data bus during this | + | special M1 cycle. | + | | + | The value FFh is assumed when the `inta` callback is not used. This | + | is the most desirable behavior, since the `rst 38h` instruction will | + | be executed if the interrupt mode is 0. | + '=====================================================================*/ + R++; /* M1 */ + ird = (self->inta != Z_NULL) ? INTA : 0xFF; + +# ifdef Z80_WITH_SPECIAL_RESET + PC >>= special_reset; +# endif + + switch (IM) /* response */ + { + /*-------------------------------------------------------------------------. + | Interrupt Mode 0: Execute Instruction | T-states: 2*n + instruction | + |--------------------------------------------------------------------------| + | An instruction supplied via the data bus is executed. Its first byte is | + | read during the INT acknowledge cycle (INTA). If it is an opcode prefix, | + | additional M-cycles of this kind are produced until the final opcode of | + | the instruction is fetched [1]. Each INT acknowledge cycle consumes as | + | many T-states as its normal M1 counterpart (the opcode fech M-cycle) | + | plus the 2 wait T-states mentioned above [1]. Subsequent bytes of the | + | instruction are fetched by using normal memory read M-cycles [1,2], | + | during which the interrupting I/O device must still supply the data [2]. | + | The PC register, however, remains at its pre-interrupt state, not being | + | incremented as a result of the instruction fetch [1,2]. | + | | + | References: | + | 1. Checked with "Visual Z80 Remix". | + | 2. Zilog (1978-05). "Z80 Family Program Interrupt Structure, The", | + | pp. 6,8. | + '=========================================================================*/ + case 0: + DATA[0] = ird; + +# ifdef Z80_WITH_FULL_IM0 + im0_begin: + hook = self->hook; + im0.z80 = self; + im0.context = self->context; + im0.fetch = self->fetch; + im0.read = self->read; + im0.write = self->write; + im0.in = self->in; + im0.out = self->out; + im0.pc = PC; + self->context = &im0; + self->fetch = (Z80Read )im0_fetch; + self->read = (Z80Read )im0_read; + self->write = (Z80Write)im0_write; + self->in = (Z80Read )im0_in; + self->out = (Z80Write)im0_out; + self->hook = Z_NULL; + + im0_execute: + + if (im0_pc_decrement_table[ird]) + { + PC -= im0_pc_decrement_table[ird]; + self->cycles += 2 + instruction_table[ird](self); + } + + /* halt */ + else if (ird == 0x76) HALT_LINE = TRUE; + + /* instructions with CBh prefix */ + else if (ird == 0xCB) + { + R++; + self->cycles += 4 + cb_instruction_table[DATA[1] = INTA](self); + } + + /* instructions with EDh prefix */ + else if (ird == 0xED) + { + Instruction instruction; + + R++; + + if ((instruction = ed_instruction_table[DATA[1] = ird = INTA]) != ed_illegal) + { + im0.ld_i_a = self->ld_i_a; + im0.ld_r_a = self->ld_r_a; + im0.reti = self->reti; + im0.retn = self->retn; + self->ld_i_a = (Z80Notify)im0_ld_i_a; + self->ld_r_a = (Z80Notify)im0_ld_r_a; + self->reti = (Z80Notify)im0_reti; + self->retn = (Z80Notify)im0_retn; + + self->cycles += 4 + instruction(self); + + self->ld_i_a = im0.ld_i_a; + self->ld_r_a = im0.ld_r_a; + self->reti = im0.reti; + self->retn = im0.retn; + + /* All except: reti / retn */ + if ((ird & 0xC7) != 0x45) PC -= ((ird & 0xC7) == 0x43) + ? 4 /* ld SS,(WORD) / ld (WORD),SS */ + : 2 /* all others */; + } + + else self->cycles += (self->illegal == Z_NULL) + ? 4 + 8 + : 4 + self->illegal(CONTEXT, ird); + } + + /* instructions with DDh, FDh, DDCBh or FDCBh prefix */ + else if (IS_XY_PREFIX(ird)) + { + Instruction instruction; + + if (RESUME) RESUME = FALSE; + + else { + im0_advance_xy: + if ((self->cycles += 6) >= self->cycle_limit) + { + RESUME = Z80_RESUME_IM0_XY; + goto im0_finalize; + } + } + + R++; + + if (IS_XY_PREFIX(ird = INTA)) + { + DATA[0] = ird; + goto im0_advance_xy; + } + + if ((instruction = xy_instruction_table[ird]) == xy_illegal) + { + DATA[0] = ird; + PC++; + goto im0_execute; + } + + XY = (xy = &self->ix_iy[((DATA[1] = ird) >> 5) & 1])->uint16_value; + self->cycles += 2 + instruction(self); + xy->uint16_value = XY; + + /* all except: jp (XY) */ + if (ird != 0xE9) PC = im0.pc; + } + + else { + cycles += 2 + instruction_table[ird](self); + + /* all except: jp WORD / jp (hl)> / ret */ + if (ird != 0xC3 && (ird & 0xDF) != 0xC9) PC = im0.pc; + } + + im0_finalize: + self->context = im0.context; + self->fetch = im0.fetch; + self->read = im0.read; + self->write = im0.write; + self->in = im0.in; + self->out = im0.out; + self->hook = hook; + + if (HALT_LINE) + { + if (self->halt != Z_NULL) self->halt(im0.context, TRUE); + RESUME = Z80_RESUME_HALT; + Q_0 + self->cycles += 6; + (void)halt(self); + } + + continue; + +# else + switch (ird) + { + case 0xC3: /* jp WORD */ + Q_0 + MEMPTR = PC = int_fetch_16(self); + self->cycles += 2 + 10; + continue; + + case 0xCD: /* call WORD */ + Q_0 + MEMPTR = int_fetch_16(self); + PUSH(PC); + PC = MEMPTR; + self->cycles += 2 + 17; + continue; + + default: /* `rst N` is assumed for other instructions */ + Q_0 + PUSH(PC); + MEMPTR = PC = ird & 56; + self->cycles += 2 + 11; + continue; + } +# endif + + /*----------------------------------------------------------. + | Interrupt Mode 1: Execute `rst 38h` | T-states: 13:733 | + |-----------------------------------------------------------| + | An internal `rst 38h` is executed. The interrupt response | + | data read from the data bus is disregarded. | + '==========================================================*/ + case 1: + DATA[0] = 0; + Q_0 + PUSH(PC); + MEMPTR = PC = 0x38; + self->cycles += 13; + continue; + + /*---------------------------------------------------------------------. + | Interrupt Mode 2: Execute `call (i:BYTE)` | T-states: 19:73333 | + |----------------------------------------------------------------------| + | An indirect call is executed. The pointer to the ISR is loaded from | + | the memory address formed by taking the I register as the most | + | significant byte, and the interrupt response vector read from the | + | data bus as the least significant byte. | + | | + | Zilog's official documentation states that the least significant bit | + | of the interrupt response vector "must be a zero", since the address | + | formed "is used to get two adjacent bytes to form a complete 16-bit | + | service routine starting address and the addresses must always start | + | in even locations" [1]. However, Sean Young's experiments confirmed | + | that there is no such limitation [2]; any vector works whether it is | + | odd or even. | + | | + | References: | + | 1. Zilog (2005-03). "Z80 CPU User Manual" revision 5, pp. 25,26. | + | 2. Young, Sean (2005-09-18). "Undocumented Z80 Documented, The" | + | v0.91, p. 20. | + '=====================================================================*/ + case 2: + DATA[0] = 0; + Q_0 + PUSH(PC); + MEMPTR = PC = READ_16((zuint16)(((zuint16)I << 8) | ird)); + self->cycles += 19; + continue; + } + } + +# ifdef Z80_WITH_SPECIAL_RESET + if (special_reset) + { + REQUEST = 0; + + /*-------------------------------------------------------------------. + | The /HALT line quickly goes low and then high in TL when a special | + | RESET is detected during the execution of the `halt` instruction. | + '===================================================================*/ + if (DATA[0] == 0x76 && self->halt != Z_NULL) + self->halt(CONTEXT, Z80_HALT_CANCEL); + + R++; /* M1 */ + if (self->nop != Z_NULL) (void)self->nop(CONTEXT, PC); + DATA[0] = 0; + PC = 0; + self->cycles += 4; + continue; + } +# endif + } + + R++; /* M1 */ + self->cycles += instruction_table[DATA[0] = FETCH_OPCODE(PC)](self); + } + + R = R_ALL; /* restore R7 bit */ + return self->cycles; /* return consumed cycles */ + } + + +#ifdef Z80_WITH_WINDOWS_DLL_MAIN + int Z_MICROSOFT_STD_CALL _DllMainCRTStartup(void *hDllHandle, unsigned long dwReason, void *lpReserved) + {return TRUE;} +#endif + + +/* Z80.c EOF */ diff --git a/software/FusionX/src/spitools/Makefile b/software/FusionX/src/spitools/Makefile new file mode 100644 index 000000000..27a05df88 --- /dev/null +++ b/software/FusionX/src/spitools/Makefile @@ -0,0 +1,150 @@ +# Makefile +# Created by Rico Castelo +# Free to Use + +PRJ_ROOT_DIR := $(shell pwd)/ +LINUX_HEADERS := ../../../linux/project/kbuild/4.9.84/i2m/include/uapi/linux/spi + + +# Target Name +TARGET_NAME := mspi_main +PROJECT_TYPE := app + +#Version Number +MAJOR := 0 +MINOR := 08 + +#Include directories +INCLUDES_SRC = -I. -I./include -I$(LINUX_HEADERS) + +#Libraries +#LIBRARIES := -lboost_filesystem -lboost_thread -lboost_system -ldl -L. -lpthread +LIBRARIES := -ldl -L. -lpthread + +#Add more App Object files +OBJFILES := + +#Add more Dependency files +#These files are generated automatically. This is only needed to delete them all +DEPFILES := + +# Doxygen Configuration file +DOXYGEN_CONFIG := doxyfile + +# ---------------------------------------------------------------------------- +# DO NOT MODIFY BELOW +# ---------------------------------------------------------------------------- +#Set for Debug mode or non-debug +BUILD := rel + +#Set Architecture +ARCH := arm + +#Compilers +ifeq ($(ARCH),arm) +CPP := /opt/gcc-arm-eabihf/bin/arm-linux-gnueabihf-g++ +CC := /opt/gcc-arm-eabihf/bin/arm-linux-gnueabihf-gcc +else +CPP := g++ +CC := gcc +endif + +#Set the file extension and prefix if lib +ifeq ($(PROJECT_TYPE),lib) +TARGET_PREFIX = lib +TARGET_POSTFIX = .so +CC += -shared +else +TARGET_PREFIX = +TARGET_POSTFIX = +endif + +#BuildTool flags +ifeq ($(BUILD),devel) +DEBUGFLAGS_Assembler = -g +DEBUGFLAGS_C++-Compiler = -g -O0 -fno-omit-frame-pointer -pipe -Wall -DDEBUG +DEBUGFLAGS_C++-Linker = -g +DEBUGFLAGS_C-Compiler = -g -O2 -fno-omit-frame-pointer -pipe -Wall +DEBUGFLAGS_C-Linker = -g +DEBUGFLAGS_Librarian = -g +DEBUGFLAGS_Shared-Library-Linker = -g +TARGET_VER = $(TARGET_PREFIX)$(TARGET_NAME)_$(MAJOR).$(MINOR)_debug$(TARGET_POSTFIX) +TARGET = $(TARGET_PREFIX)$(TARGET_NAME)_debug$(TARGET_POSTFIX) +else +DEBUGFLAGS_Assembler = +DEBUGFLAGS_C++-Compiler = -O3 -Wall -Werror +DEBUGFLAGS_C++-Linker = +DEBUGFLAGS_C-Compiler = -O2 -fomit-frame-pointer -D__USE_STRING_INLINES -pipe -Wall +DEBUGFLAGS_C-Linker = +DEBUGFLAGS_Librarian = +DEBUGFLAGS_Shared-Library-Linker = +TARGET = $(TARGET_PREFIX)$(TARGET_NAME)_$(MAJOR).$(MINOR)$(TARGET_POSTFIX) +TARGET_VER = $(TARGET_PREFIX)$(TARGET_NAME)$(TARGET_POSTFIX) +endif + +#Global Build Macros +DEFINES += + +#Global Include directories +INCLUDES_SRC += -I$(PRJ_ROOT_DIR)/include + +#Global Libraries +LIBRARIES += + +#Global App Object files +OBJFILES += $(patsubst %.cpp,%.o,$(wildcard *.cpp)) $(patsubst %.cpp,%.o,$(wildcard src/*.cpp)) +OBJFILES += $(patsubst %.c,%.o,$(wildcard *.c)) $(patsubst %.c,%.o,$(wildcard src/*.c)) + +#Global Dependency files +#These files are generated automatically. This is only needed to delete them all +DEPFILES += $(patsubst %.cpp,%.d,$(wildcard *.cpp)) $(patsubst %.cpp,%.d,$(wildcard src/*.cpp)) +DEPFILES += $(patsubst %.c,%.d,$(wildcard *.c)) $(patsubst %.c,%.d,$(wildcard src/*.c)) + +#Compile object files +%.o: %.cpp + $(CPP) $(DEBUGFLAGS_C++-Compiler) $(INCLUDES_SRC) $(DEFINES) -c -fmessage-length=0 -Wold-style-cast -Woverloaded-virtual -o $@ $< + +#Compile object files +#May need to replace $(CC) with $(GCC) +%.o: %.c + $(CC) $(DEBUGFLAGS_C-Compiler) $(INCLUDES_SRC) $(DEFINES) -c -fmessage-length=0 -o $@ $< + +#Build application +#Create two version of the file so when including the library you do not have to worry about a version +all: $(OBJFILES) + $(CC) -o $(TARGET) $(OBJFILES) $(LIBRARIES) + $(CC) -o $(TARGET_VER) $(OBJFILES) $(LIBRARIES) + +#Clean files +clean: + rm -f $(OBJFILES) rm -f $(DEPFILES) rm -f $(TARGET) rm -rf $(TARGET_VER) + +#Make Doxygen files +doxygen: + cd docs && \ + doxygen $(DOXYGEN_CONFIG) + +#Clean Doxygen files +clean_doxygen: + rm -rf docs/html + rm -rf docs/latex + +#Help option +help: + @echo + @echo " make [target] [OPTIONS]" + @echo + @echo " Targets:" + @echo " all Builds the app. This is the default target." + @echo " clean Clean all the objects, apps and dependencies." + @echo " help Prints this message." + @echo " doxygen Create doxygen files" + @echo " doxygen_clean Clean doxygen files" + @echo " Options:" + @echo " BUILD=rel Build a release build (default)" + @echo " BUILD=devel Build a debug build" + @echo " " + @echo " ARCH=arm Build an ARM build (default)" + @echo " ARCH=x86 Build an X86 build" + @echo " " + @echo diff --git a/software/FusionX/src/spitools/mspi_main b/software/FusionX/src/spitools/mspi_main new file mode 100755 index 000000000..1f4ef7049 Binary files /dev/null and b/software/FusionX/src/spitools/mspi_main differ diff --git a/software/FusionX/src/spitools/mspi_main.c b/software/FusionX/src/spitools/mspi_main.c new file mode 100644 index 000000000..3d34bb873 --- /dev/null +++ b/software/FusionX/src/spitools/mspi_main.c @@ -0,0 +1,1152 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FRAME_MAX_SIZE 8 +#define SYSFS_GPIO_DIR "/sys/class/gpio" +#define MAX_BUF (64) +#define GPIO_HIGH (1) +#define GPIO_LOW (0) + +/** + * mode: 0 -- CPOL=0,CPHA=0 + * 1 -- CPOL=0,CPHA=1 + * 2 -- CPOL=1,CPHA=0 + * 3 -- CPOL=1,CPHA=1 + */ +static uint8_t mode = 1; + +/** + * bits: 1 ~ 16 + */ +static uint8_t bits = 8; + +/** + * speed: <= 72MHz + */ +static uint32_t speed = 30 * 1000 * 1000; + +/** + * device: 0/1 + */ +static const char *device = "/dev/spidev0.0"; + +static uint16_t delay = 0; + +static int spi_fd = -1; + +// Number of iterations for loopback test. +static int iterations = 1000000; + +// Debug flag. +static int debug = 0; + + +/** + * function: gpio export + */ +int ss_gpio_export(unsigned int gpio) +{ + int fd, len; + char buf[MAX_BUF]; + + fd = open(SYSFS_GPIO_DIR "/export", O_WRONLY); + if (fd < 0) { + perror("gpio/export"); + return fd; + } + + len = snprintf(buf, sizeof(buf), "%d", gpio); + write(fd, buf, len); + close(fd); + + return 0; +} + +/** + * function: gpio unexport + */ +int ss_gpio_unexport(unsigned int gpio) +{ + int fd, len; + char buf[MAX_BUF]; + + fd = open(SYSFS_GPIO_DIR "/unexport", O_WRONLY); + if (fd < 0) { + perror("gpio/export"); + return fd; + } + + len = snprintf(buf, sizeof(buf), "%d", gpio); + write(fd, buf, len); + close(fd); + return 0; +} + +/** + * function: gpio set direction + * parameter: out_flag = 1 -- out + * out_flag = 0 -- in + */ +int ss_gpio_set_dir(unsigned int gpio, unsigned int out_flag) +{ + int fd; + char buf[MAX_BUF]; + + snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR "/gpio%d/direction", gpio); + + fd = open(buf, O_WRONLY); + if (fd < 0) { + perror("gpio/direction"); + return fd; + } + + if (out_flag) + write(fd, "out", 4); + else + write(fd, "in", 3); + + close(fd); + return 0; +} + +/** + * function: gpio set value + * parameter: value = 1 -- high + * value = 0 -- low + */ +int ss_gpio_set_value(unsigned int gpio, unsigned int value) +{ + int fd; + char buf[MAX_BUF]; + + snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR "/gpio%d/value", gpio); + + fd = open(buf, O_WRONLY); + if (fd < 0) { + perror("gpio/set-value"); + return fd; + } + + if (value) + write(fd, "1", 2); + else + write(fd, "0", 2); + + close(fd); + return 0; +} + + +/** + * function: gpio get value + */ +int ss_gpio_get_value(unsigned int gpio, unsigned int *value) +{ + int fd; + char buf[MAX_BUF]; + char ch; + + snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR "/gpio%d/value", gpio); + + fd = open(buf, O_RDONLY); + if (fd < 0) { + perror("gpio/get-value"); + return fd; + } + + read(fd, &ch, 1); + + if (ch != '0') { + *value = 1; + } else { + *value = 0; + } + + close(fd); + return 0; +} + + +/** + * function: gpio_set edge + * parameter: edge = "none", "rising", "falling", "both" + */ +int ss_gpio_set_edge(unsigned int gpio, char *edge) +{ + int fd; + char buf[MAX_BUF]; + + snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR "/gpio%d/edge", gpio); + + fd = open(buf, O_WRONLY); + if (fd < 0) { + perror("gpio/set-edge"); + return fd; + } + + write(fd, edge, strlen(edge) + 1); + close(fd); + return 0; +} + +/** + * function: gpio open fd + */ +int ss_gpio_open(unsigned int gpio) +{ + int fd; + char buf[MAX_BUF]; + + snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR "/gpio%d/value", gpio); + + fd = open(buf, O_RDONLY | O_NONBLOCK ); + if (fd < 0) { + perror("gpio/fd_open"); + } + return fd; +} + +/** + * function: gpio close fd + */ +int ss_gpio_close(int fd) +{ + return close(fd); +} + + +/** + * function: open mspi device + */ +int ss_mspi_open(void) +{ + int ret = 0; + uint8_t lsb; + + if (spi_fd >= 0) + return -1; + + spi_fd = open(device, O_RDWR); + if (spi_fd < 0) + { + printf("can't open %s\n", device); + return -1; + } + + //set mspi mode + ret = ioctl(spi_fd, SPI_IOC_WR_MODE, &mode); + if (ret < 0) + { + printf("can't set spi mode\n"); + close(spi_fd); + return -1; + } + + ret = ioctl(spi_fd, SPI_IOC_RD_MODE, &mode); + if (ret < 0) + { + printf("can't get spi mode\n"); + close(spi_fd); + return -1; + } + + //set bits per word + ret = ioctl(spi_fd, SPI_IOC_WR_BITS_PER_WORD, &bits); + if (ret < 0) + { + printf("can't set bits per word\n"); + close(spi_fd); + return -1; + } + + ret = ioctl(spi_fd, SPI_IOC_RD_BITS_PER_WORD, &bits); + if (ret < 0) + { + printf("can't get bits per word\n"); + close(spi_fd); + return -1; + } + + //set mspi speed hz + ret = ioctl(spi_fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + if (ret < 0) + { + printf("can't set max speed hz\n"); + close(spi_fd); + return -1; + } + + ret = ioctl(spi_fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed); + if (ret < 0) + { + printf("can't get max speed hz\n"); + close(spi_fd); + return -1; + } + + //ret = ioctl(spi_fd, SPI_IOC_WR_LSB_FIRST, &lsb); + //if (ret < 0) + //{ + // printf("mspi set lsb first falid!\n"); + // close(spi_fd); + // return -1; + //} + + ret = ioctl(spi_fd, SPI_IOC_RD_LSB_FIRST, &lsb); + if (ret < 0) + { + printf("mspi get lsb first falid!\n"); + close(spi_fd); + return -1; + } + + printf("mspi mode: %d\n", mode); + printf("mspi bits per word: %d\n", bits); + printf("mspi speed: %d Hz\n", speed); + printf("mspi transmit is lsb first: %d\n", lsb); + + return 0; +} + + +/** + * function: close mspi device + */ +int ss_mspi_close(void) +{ + if (spi_fd < 0) + return -1; + + close(spi_fd); + spi_fd = -1; + + printf("close %s success\n", device); + + return 0; +} + +/** + * function: mspi send data + */ +int ss_mspi_write(uint8_t *wr_buf, int size) +{ + int i, j, ret; + uint16_t tx[FRAME_MAX_SIZE] = {0}; //max 8 + int frame_cnt = size / sizeof(tx), data_cnt = size % sizeof(tx); + + if (spi_fd < 0) + return -1; + + struct spi_ioc_transfer tr = { + .tx_buf = (unsigned long)tx, + .rx_buf = NULL, + .len = sizeof(tx), + .delay_usecs = delay, + .speed_hz = speed, + .bits_per_word = bits, + }; + + for (i = 0; i < frame_cnt; i ++) + { + tr.len = sizeof(tx); + memcpy((uint8_t *)tx, (uint8_t *)wr_buf + i * sizeof(tx), sizeof(tx)); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + } + + if (data_cnt) + { + tr.len = data_cnt; + memset((uint8_t *)tx, 0x0, sizeof(tx)); + memcpy((uint8_t *)tx, (uint8_t *)wr_buf + size - data_cnt, data_cnt); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + } + + return 0; +} + + +/** + * function: mspi read data + */ +int ss_mspi_read(uint8_t *rd_buf, int size) +{ + int i, j, ret; + uint16_t rx[FRAME_MAX_SIZE] = {0}; + int frame_cnt = size / sizeof(rx), data_cnt = size % sizeof(rx); + + if (spi_fd < 0) + return -1; + + struct spi_ioc_transfer tr = { + .tx_buf = NULL, + .rx_buf = (unsigned long)rx, + .len = sizeof(rx), + .delay_usecs = delay, + .speed_hz = speed, + .bits_per_word = bits, + }; + + for (i = 0; i < frame_cnt; i ++) + { + tr.len = sizeof(rx); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + memcpy((uint8_t *)rd_buf + i * sizeof(rx), (uint8_t *)rx, sizeof(rx)); + } + + if (data_cnt) + { + tr.len = data_cnt; + memset((uint8_t *)rx, 0x0, sizeof(rx)); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + memcpy((uint8_t *)rd_buf + size - data_cnt, (uint8_t *)rx, data_cnt); + } + + return 0; +} + +/** + * function: mspi lookback test + */ +int ss_mspi_lookback(uint8_t *wr_buf, uint8_t *rd_buf, int size, uint8_t loopTest) +{ + int i, j, ret; + uint16_t rx[FRAME_MAX_SIZE+2] = {0}; + uint16_t tx[FRAME_MAX_SIZE+2] = {0}; + int frame_cnt = size / sizeof(tx), data_cnt = size % sizeof(tx); + printf("frame count: %d, data count: %d\n", frame_cnt, data_cnt); + + if (spi_fd < 0) + return -1; + + struct spi_ioc_transfer tr = { + .tx_buf = (unsigned long)tx, + .rx_buf = (unsigned long)rx, + .len = sizeof(tx), + .delay_usecs = delay, + .speed_hz = speed, + .bits_per_word = bits, + }; + + // Loop Test sends a repeated pattern to the CPLD and expects to get the same data echoed back. + if(!loopTest) + { + memcpy((uint8_t *)tx, (uint8_t *)wr_buf + i * sizeof(tx), sizeof(tx)); + for (i = 0; i < frame_cnt; i ++) + { + tr.len = sizeof(tx); + memcpy((uint8_t *)tx, (uint8_t *)wr_buf + i * sizeof(tx), sizeof(tx)); + printf("mspi tx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", tx[0], tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]); + + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + memcpy((uint8_t *)rd_buf + i * sizeof(rx), (uint8_t *)rx, sizeof(rx)); + printf("mspi rx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", rx[0], rx[1], rx[2], rx[3], rx[4], rx[5], rx[6], rx[7]); + } + + if(data_cnt) + { + memset((uint8_t *)tx, 0x0, sizeof(tx)); + memset((uint8_t *)rx, 0x0, sizeof(rx)); + memcpy((uint8_t *)tx, (uint8_t *)wr_buf + size - data_cnt, data_cnt); + printf("mspi tx_buf(dc): %04x %04x %04x %04x %04x %04x %04x %04x\n", tx[0], tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]); + + for(int idx2=0; idx2 < data_cnt; idx2 += 4) + { + if(data_cnt - idx2 > 2) + { + tr.len = 4; + } else + { + tr.len = 2; + } + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + if(data_cnt - idx2 > 2) + { + tr.tx_buf += 4; + tr.rx_buf += 4; + } else + { + tr.tx_buf += 2; + tr.rx_buf += 2; + } + } + // Shift out the last loop message. + tr.len = (data_cnt > 2 ? 4 : 4); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + memcpy((uint8_t *)rd_buf + size - data_cnt, (uint8_t *)rx, data_cnt); + printf("mspi rx_buf(dc): %04x %04x %04x %04x %04x %04x %04x %04x\n", rx[0], rx[1], rx[2], rx[3], rx[4], rx[5], rx[6], rx[7]); + } + } else + { + uint32_t errorCount = 0; + struct timeval start, stop; + + memset((uint8_t *)tx, 0x0, sizeof(tx)); + memset((uint8_t *)rx, 0x0, sizeof(rx)); + + // Send the command to switch CPLD into loopback test mode. + uint16_t setmodeBuf[2] = {0xFE, 0x00}; + tr.len = 2; + memcpy((uint8_t *)tx, (uint8_t *)setmodeBuf, 2); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + gettimeofday(&start, NULL); + for(int idx=0; idx < iterations; idx++) + { + memcpy((uint8_t *)tx, (uint8_t *)wr_buf + size - data_cnt, data_cnt); + if(debug) printf("mspi tx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", tx[0], tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]); + for(int idx2=0; idx2 < data_cnt; idx2 += 4) + { + if(data_cnt - idx2 > 2) + { + tr.len = 4; + } else + { + tr.len = 2; + } + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + if(data_cnt - idx2 > 2) + { + tr.tx_buf += 4; + tr.rx_buf += 4; + } else + { + tr.tx_buf += 2; + tr.rx_buf += 2; + } + } + // Shift out the last loop message. + tr.len = 2; + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + tr.tx_buf = (unsigned long)tx; + tr.rx_buf = (unsigned long)rx; + + // Check data in = data out, shifted by one as the return data is tx-1. + memcpy((uint8_t *)rd_buf + size - data_cnt, (uint8_t *)rx, data_cnt+2); + //if(memcmp((uint8_t *)tx, (uint8_t *)rx+2, data_cnt) != 0) + if(memcmp((uint8_t *)tx, (uint8_t *)rd_buf + size - data_cnt +2, data_cnt) != 0) + { + errorCount++; + } + //for(uint32_t idx2=0; idx2 < data_cnt; idx2++) + //{ + // if(tx[idx2] != rx[idx2+1]) + // errorCount++; + //} + if(debug) printf("mspi rx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", rx[1], rx[2], rx[3], rx[4], rx[5], rx[6], rx[7], rx[8]); + } + gettimeofday(&stop, NULL); + long totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + float bytesSec = (float)((data_cnt+2)*iterations*2)/((float)totalTime/1000000); + printf("Loop mode errorCount: %d, time=%ldms, %8.02fbytes/sec\n", errorCount, totalTime/1000, bytesSec ); + } + + return 0; +} + +int ss_mspi_screenblank(void) +{ + int i, j, ret; + uint16_t rx[FRAME_MAX_SIZE+2] = {0}; + uint16_t tx[FRAME_MAX_SIZE+2] = {0}; + unsigned int READY; + + if (spi_fd < 0) + return -1; + + struct spi_ioc_transfer tr = { + .tx_buf = (unsigned long)tx, + .rx_buf = (unsigned long)rx, + .len = sizeof(tx), + .delay_usecs = delay, + .speed_hz = speed, + .bits_per_word = bits, + }; + + // Initialise GPIO. + ss_gpio_export(12); + ss_gpio_set_dir(12, 0); + + memset((uint8_t *)tx, 0x0, sizeof(tx)); + memset((uint8_t *)rx, 0x0, sizeof(rx)); + for(uint8_t dispchar=0x00; dispchar < 255; dispchar++) + { + for(uint16_t idx=0xd800, idxd=0xd000; idx < 0xdc00; idx++, idxd++) + { + for(int idx2=0; idx2 < 2; idx2++) + { + // CPLD FSM Ready? + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tx[0] = (idx2 == 0 ? idx : idxd); + tx[1] = (idx2 == 0 ? 0x1871 : 0x1800 | dispchar); + tr.len = 4; + //printf("mspi tx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", tx[0], tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]); + + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + //printf("mspi rx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", rx[1], rx[2], rx[3], rx[4], rx[5], rx[6], rx[7], rx[8]); + + //do { + // ss_gpio_get_value(12, &READY); + //} while(READY == 0); + //tx[0] = 0x0000; + //rx[0] = 0xffff; + //tr.len = 2; + //while(rx[0] & 0x8000) + // { + // ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + // if (ret < 0) + // { + // printf("can't send spi message"); + // return -1; + // } + // } + } + } + + // Read back test. + for(uint16_t idx=0xd000; idx < 0xd400; idx++) + { + // CPLD FSM Ready? + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tx[0] = idx; + tx[1] = 0x2000; + tr.len = 4; + //printf("mspi tx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", tx[0], tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]); + + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tr.len = 2; + memset((uint8_t *)tx, 0x0, sizeof(tx)); + memset((uint8_t *)rx, 0x0, sizeof(rx)); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + if((rx[0]&0x00ff) != dispchar) + { + //printf("mspi tx_buf: %04x %04x %04x %04x %04x %04x %04x %04x\n", tx[0], tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]); + printf("%04x:%04x->%02x\n", idx, rx[0], dispchar); + } + } + } + + return 0; +} + +int ss_mspi_memorydump(void) +{ + int ret; + uint16_t rx[FRAME_MAX_SIZE+2] = {0}; + uint16_t tx[FRAME_MAX_SIZE+2] = {0}; + unsigned int READY; + uint8_t displayWidth = 32; + uint32_t pnt = 0x0000; + uint32_t endAddr = 0x0000 + 0xE000; + uint32_t addr = 0x0000; + uint32_t i = 0; + //uint32_t data; + int8_t keyIn; + int result = -1; + char c = 0; + + if (spi_fd < 0) + return -1; + + struct spi_ioc_transfer tr = { + .tx_buf = (unsigned long)tx, + .rx_buf = (unsigned long)rx, + .len = sizeof(tx), + .delay_usecs = delay, + .speed_hz = speed, + .bits_per_word = bits, + }; + + // Initialise GPIO. + ss_gpio_export(12); + ss_gpio_set_dir(12, 0); + + while (1) + { + printf("%08lX", addr); // print address + printf(": "); + + // print hexadecimal data + for (i=0; i < displayWidth; ) + { + // CPLD FSM Ready? + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tx[0] = pnt+i; + tx[1] = 0x2000; + tr.len = 4; + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tr.len = 2; + memset((uint8_t *)tx, 0x0, sizeof(tx)); + memset((uint8_t *)rx, 0x0, sizeof(rx)); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + if(pnt+i < endAddr) + printf("%02X", (rx[0]&0x00ff)); + else + printf(" "); + i++; + fputc((char)' ', stdout); + } + + // print ascii data + printf(" |"); + + // print single ascii char + for (i=0; i < displayWidth; i++) + { + // CPLD FSM Ready? + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tx[0] = pnt+i; + tx[1] = 0x2000; + tr.len = 4; + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tr.len = 2; + memset((uint8_t *)tx, 0x0, sizeof(tx)); + memset((uint8_t *)rx, 0x0, sizeof(rx)); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + if ((pnt+i < endAddr) && ((rx[0]&0x00ff) >= ' ') && ((rx[0]&0x00ff) <= '~')) + fputc((char)(rx[0]&0x00ff), stdout); + else + fputc((char)' ', stdout); + } + + printf("|\r\n"); + fflush(stdout); + + // Move on one row. + pnt += displayWidth; + addr += displayWidth; + + // End of buffer, exit the loop. + if(pnt >= (0x0000 + 0xE000)) + { + break; + } + } + + // Normal exit, return -1 to show no key pressed. +memoryDumpExit: + return 0; +} + +int ss_mspi_memoryspeed(void) +{ + int ret; + uint16_t rx[FRAME_MAX_SIZE+2] = {0}; + uint16_t tx[FRAME_MAX_SIZE+2] = {0}; + unsigned int READY; + uint32_t pnt = 0x0000; + uint32_t endAddr = 0x0000 + 0xE000; + uint32_t addr = 0x0000; + uint32_t i = 0; + //uint32_t data; + int8_t keyIn; + int result = -1; + char c = 0; + struct timeval start, stop; + + if (spi_fd < 0) + return -1; + + struct spi_ioc_transfer tr = { + .tx_buf = (unsigned long)tx, + .rx_buf = (unsigned long)rx, + .len = sizeof(tx), + .delay_usecs = delay, + .speed_hz = speed, + .bits_per_word = bits, + }; + + // Initialise GPIO. + ss_gpio_export(12); + ss_gpio_set_dir(12, 0); + + pnt = 0x1000; + memset((uint8_t *)tx, 0x0, sizeof(tx)); + gettimeofday(&start, NULL); + for(i=0x1000; i < 0xD000; i++) + { + // CPLD FSM Ready? + // do { + // ss_gpio_get_value(12, &READY); + // } while(READY == 0); + + if(i == 0) + { + tx[0] = i; + tx[1] = 0x2000; + tr.len = 4; + } else + { + tx[0] = i; + tx[1] = 0x2100; + tr.len = 2; + } + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + // do { + // ss_gpio_get_value(12, &READY); + // } while(READY == 0); +// +// tr.len = 2; +// //memset((uint8_t *)rx, 0x0, sizeof(rx)); +// ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); +// if (ret < 0) +// { +// printf("can't send spi message"); +// return -1; +// } + } + gettimeofday(&stop, NULL); + long totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + float bytesSec = (float)(0xC000)/((float)totalTime/1000000); + printf("RAM 0x1000:0xD000, time=%ldms, %8.02fbytes/sec\n", totalTime/1000, bytesSec ); + + gettimeofday(&start, NULL); + for(i=0xD000; i < 0xE000; i++) + { + // CPLD FSM Ready? + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tx[0] = i; + tx[1] = 0x2000; + tr.len = 4; + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + + do { + ss_gpio_get_value(12, &READY); + } while(READY == 0); + + tr.len = 2; + memset((uint8_t *)rx, 0x0, sizeof(rx)); + ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 0) + { + printf("can't send spi message"); + return -1; + } + } + gettimeofday(&stop, NULL); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesSec = (float)(0x1000)/((float)totalTime/1000000); + printf("VRAM 0xD000:0xE000, time=%ldms, %8.02fbytes/sec\n", totalTime/1000, bytesSec ); + + return 0; +} + +int main(int argc, char *argv[]) +{ + int i, ret, len; + uint8_t tmp_buf[64]; + uint8_t wr_buf[64], rd_buf[64]; + uint8_t loopTest = 0; + + if (argc < 3) + { + printf("please inpu such as: ./mspi_main bits string\n"); + printf("eg: ./mspi_main 8 FF [speed MHz] [clock mode 0-3] [debug] [loop] [loopback test iterations]\n"); + printf("eg: ./mspi_main 9 01FF [speed MHz] [clock mode 0-3] [debug] [loop] [loopback test iterations]\n"); + // 0 1 2 3 4 5 6 7 + return -1; + } + + printf("mspi test start!\n"); + + //set mspi transmit bits + bits = atoi(argv[1]); + + // Loop test? + if(argc >= 6 && strcasecmp(argv[6], "loop") == 0) + { + loopTest = 1; + printf("loop test enabled#n"); + } + + // Speed override? + if(argc >= 4) + { + speed = atoi(argv[3]) * 1000 * 1000; + printf("speed override: %dHz\n", speed); + } + if(speed == 0) + { + printf("Speed invalid (%d), cannot run test\n", speed); + return(-1); + } + if(argc >= 5) + { + mode = atoi(argv[4]); + printf("mode override: %d\n", mode); + } + if(mode >= 4) + { + printf("Mode invalid (%d), cannot run test\n", mode); + return(-1); + } + if(argc >= 8) + { + iterations = atoi(argv[7]); + printf("iteration override: %d\n", iterations); + } + if(iterations == 0) + { + printf("Iterations invalid (%d), cannot run test\n", iterations); + return(-1); + } + if(argc >= 6) + { + debug = atoi(argv[5]); + } + + ret = ss_mspi_open(); + if (ret < 0) + return -1; + + memset(wr_buf, 0x0, sizeof(wr_buf)); + memset(rd_buf, 0x0, sizeof(rd_buf)); + memset(tmp_buf, 0x0, sizeof(rd_buf)); + + //receive shell '0'~'F' string and convert to char data + uint8_t *cp = argv[2]; + uint8_t tmp = 0; + if(strcasecmp(cp, "BLANK") == 0) + { + ret = ss_mspi_screenblank(); + if (ret < 0) + { + ss_mspi_close(); + return -1; + } + } else + if(strcasecmp(cp, "DUMP") == 0) + { + ret = ss_mspi_memorydump(); + if (ret < 0) + { + ss_mspi_close(); + return -1; + } + } else + if(strcasecmp(cp, "RAMSPEED") == 0) + { + ret = ss_mspi_memoryspeed(); + if (ret < 0) + { + ss_mspi_close(); + return -1; + } + } else + { + for (i = 0; *cp; i ++, cp ++) + { + tmp = *cp - '0'; + if (tmp > 9) + tmp -= ('A' - '0') - 10; + if (tmp > 15) + tmp -= ('a' - 'A'); + if (tmp > 15) + { + printf("invalid hex data on %c!\n", *cp); + ss_mspi_close(); + return -1; + } + + if (i % 2) + tmp_buf[i / 2] |= tmp; + else + tmp_buf[i / 2] = tmp << 4; + } + len = i / 2; + printf("test len: %d, bits: %d, in data: %s\n", len, bits, argv[2]); + + if(loopTest && (len % 4 != 0 && len != 2)) + { + printf("Invalid data length, either 16 bit single value or single/multiple 32bit values required.t\n", iterations); + return(-1); + } + + //save data to an array + if (bits <= 8) + { + //save data to uint8_t + for (i = 0; i < len; i ++) + { + wr_buf[i] = tmp_buf[i]; + } + } + else + { + //need to convert to uint16_t, high bits save to high address + for (i = 0; i < len; i += 2) + { + wr_buf[i + 1] = tmp_buf[i]; + wr_buf[i + 0] = tmp_buf[i + 1]; + } + } + + for (i = 0; i < len; i ++) + { + if (!(i % 8)) + printf("input data: "); + printf("0x%02x ", wr_buf[i]); + } + //printf("\n\n"); + + ret = ss_mspi_lookback(wr_buf, rd_buf, len, loopTest); + if (ret < 0) + { + ss_mspi_close(); + return -1; + } + + for (i = 0; i < len; i ++) + { + if (!(i % 8)) + printf("\noutput data: "); + printf("0x%02x ", rd_buf[i]); + } + printf("\n"); + } + + ss_mspi_close(); + + return 0; +} + diff --git a/software/FusionX/start_FusionX.sh b/software/FusionX/start_FusionX.sh new file mode 100644 index 000000000..0d5c4bdc8 --- /dev/null +++ b/software/FusionX/start_FusionX.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +ROOTDIR=/apps/FusionX + +cd ${ROOTDIR} +#nohup ${ROOTDIR}/bin/FusionX & diff --git a/software/WebServer/Makefile b/software/WebServer/Makefile new file mode 100644 index 000000000..06b9ed612 --- /dev/null +++ b/software/WebServer/Makefile @@ -0,0 +1,39 @@ +# +# Copyright (c) 2013 No Face Press, LLC +# License http://opensource.org/licenses/mit-license.php MIT License +# + +#This makefile is used to test the other Makefiles + + +PROG = WebServer +SRC = WebServer.cpp + +TOP = ../../../../civetweb +CIVETWEB_LIB = libcivetweb.a + +CFLAGS = -I$(TOP)/include $(COPT) +LIBS = -lpthread + +include $(TOP)/resources/Makefile.in-os + +ifeq ($(TARGET_OS),LINUX) + LIBS += -ldl -lrt +endif +ifdef WITH_ZLIB + LIBS += -lz +endif + +all: $(PROG) + +$(PROG): $(CIVETWEB_LIB) $(SRC) + $(CXX) -o $@ $(CFLAGS) $(LDFLAGS) $(SRC) $(CIVETWEB_LIB) $(LIBS) + +$(CIVETWEB_LIB): + $(MAKE) -C $(TOP) clean lib WITH_CPP=1 + cp $(TOP)/$(CIVETWEB_LIB) . + +clean: + rm -f $(CIVETWEB_LIB) $(PROG) + +.PHONY: all clean diff --git a/software/WebServer/WebServer.cpp b/software/WebServer/WebServer.cpp new file mode 100644 index 000000000..b6738202d --- /dev/null +++ b/software/WebServer/WebServer.cpp @@ -0,0 +1,446 @@ +/* Copyright (c) 2013-2018 the Civetweb developers + * Copyright (c) 2013 No Face Press, LLC + * License http://opensource.org/licenses/mit-license.php MIT License + */ + +// Simple example program on how to use Embedded C++ interface. + +#include "CivetServer.h" +#include + +#ifdef _WIN32 +#include +#else +#include +#endif + +#define DOCUMENT_ROOT "webfs/" +#define PORT "80" +#define EXAMPLE_URI "/example" +#define EXIT_URI "/exit" + + +/* Exit flag for main loop */ +volatile bool exitNow = false; + + +class ExampleHandler : public CivetHandler +{ + public: + bool + handleGet(CivetServer *server, struct mg_connection *conn) + { + mg_printf(conn, + "HTTP/1.1 200 OK\r\nContent-Type: " + "text/html\r\nConnection: close\r\n\r\n"); + mg_printf(conn, "\r\n"); + mg_printf(conn, + "

This is an example text from a C++ handler

\r\n"); + mg_printf(conn, + "

To see a page from the A handler click here

\r\n"); + mg_printf(conn, + "
" + "To see a page from the A handler with a parameter " + " (GET)
\r\n"); + mg_printf(conn, + "
" + "To see a page from the A handler with a parameter " + " (POST)
\r\n"); + mg_printf(conn, + "

To see a page from the A/B handler click here

\r\n"); + mg_printf(conn, + "

To see a page from the *.foo handler click here

\r\n"); + mg_printf(conn, + "

To see a page from the WebSocket handler click here

\r\n"); + mg_printf(conn, + "

To exit click here

\r\n", + EXIT_URI); + mg_printf(conn, "\r\n"); + return true; + } +}; + +class ExitHandler : public CivetHandler +{ + public: + bool + handleGet(CivetServer *server, struct mg_connection *conn) + { + mg_printf(conn, + "HTTP/1.1 200 OK\r\nContent-Type: " + "text/plain\r\nConnection: close\r\n\r\n"); + mg_printf(conn, "Bye!\n"); + exitNow = true; + return true; + } +}; + +class AHandler : public CivetHandler +{ + private: + bool + handleAll(const char *method, + CivetServer *server, + struct mg_connection *conn) + { + std::string s = ""; + mg_printf(conn, + "HTTP/1.1 200 OK\r\nContent-Type: " + "text/html\r\nConnection: close\r\n\r\n"); + mg_printf(conn, ""); + mg_printf(conn, "

This is the A handler for \"%s\" !

", method); + if (CivetServer::getParam(conn, "param", s)) { + mg_printf(conn, "

param set to %s

", s.c_str()); + } else { + mg_printf(conn, "

param not set

"); + } + mg_printf(conn, "\n"); + return true; + } + + public: + bool + handleGet(CivetServer *server, struct mg_connection *conn) + { + return handleAll("GET", server, conn); + } + bool + handlePost(CivetServer *server, struct mg_connection *conn) + { + return handleAll("POST", server, conn); + } +}; + +class ABHandler : public CivetHandler +{ + public: + bool + handleGet(CivetServer *server, struct mg_connection *conn) + { + mg_printf(conn, + "HTTP/1.1 200 OK\r\nContent-Type: " + "text/html\r\nConnection: close\r\n\r\n"); + mg_printf(conn, ""); + mg_printf(conn, "

This is the AB handler!!!

"); + mg_printf(conn, "\n"); + return true; + } +}; + +class FooHandler : public CivetHandler +{ + public: + bool + handleGet(CivetServer *server, struct mg_connection *conn) + { + /* Handler may access the request info using mg_get_request_info */ + const struct mg_request_info *req_info = mg_get_request_info(conn); + + mg_printf(conn, + "HTTP/1.1 200 OK\r\nContent-Type: " + "text/html\r\nConnection: close\r\n\r\n"); + + mg_printf(conn, "\n"); + mg_printf(conn, "

This is the Foo GET handler!!!

\n"); + mg_printf(conn, + "

The request was:

%s %s HTTP/%s

\n", + req_info->request_method, + req_info->request_uri, + req_info->http_version); + mg_printf(conn, "\n"); + + return true; + } + bool + handlePost(CivetServer *server, struct mg_connection *conn) + { + /* Handler may access the request info using mg_get_request_info */ + const struct mg_request_info *req_info = mg_get_request_info(conn); + long long rlen, wlen; + long long nlen = 0; + long long tlen = req_info->content_length; + char buf[1024]; + + mg_printf(conn, + "HTTP/1.1 200 OK\r\nContent-Type: " + "text/html\r\nConnection: close\r\n\r\n"); + + mg_printf(conn, "\n"); + mg_printf(conn, "

This is the Foo POST handler!!!

\n"); + mg_printf(conn, + "

The request was:

%s %s HTTP/%s

\n", + req_info->request_method, + req_info->request_uri, + req_info->http_version); + mg_printf(conn, "

Content Length: %li

\n", (long)tlen); + mg_printf(conn, "
\n");
+
+		while (nlen < tlen) {
+			rlen = tlen - nlen;
+			if (rlen > sizeof(buf)) {
+				rlen = sizeof(buf);
+			}
+			rlen = mg_read(conn, buf, (size_t)rlen);
+			if (rlen <= 0) {
+				break;
+			}
+			wlen = mg_write(conn, buf, (size_t)rlen);
+			if (wlen != rlen) {
+				break;
+			}
+			nlen += wlen;
+		}
+
+		mg_printf(conn, "\n
\n"); + mg_printf(conn, "\n"); + + return true; + } + + #define fopen_recursive fopen + + bool + handlePut(CivetServer *server, struct mg_connection *conn) + { + /* Handler may access the request info using mg_get_request_info */ + const struct mg_request_info *req_info = mg_get_request_info(conn); + long long rlen, wlen; + long long nlen = 0; + long long tlen = req_info->content_length; + FILE * f; + char buf[1024]; + int fail = 0; + +#ifdef _WIN32 + _snprintf(buf, sizeof(buf), "D:\\somewhere\\%s\\%s", req_info->remote_user, req_info->local_uri); + buf[sizeof(buf)-1] = 0; + if (strlen(buf)>255) { + /* Windows will not work with path > 260 (MAX_PATH), unless we use + * the unicode API. However, this is just an example code: A real + * code will probably never store anything to D:\\somewhere and + * must be adapted to the specific needs anyhow. */ + fail = 1; + f = NULL; + } else { + f = fopen_recursive(buf, "wb"); + } +#else + snprintf(buf, sizeof(buf), "~/somewhere/%s/%s", req_info->remote_user, req_info->local_uri); + buf[sizeof(buf)-1] = 0; + if (strlen(buf)>1020) { + /* The string is too long and probably truncated. Make sure an + * UTF-8 string is never truncated between the UTF-8 code bytes. + * This example code must be adapted to the specific needs. */ + fail = 1; + f = NULL; + } else { + f = fopen_recursive(buf, "w"); + } +#endif + + if (!f) { + fail = 1; + } else { + while (nlen < tlen) { + rlen = tlen - nlen; + if (rlen > sizeof(buf)) { + rlen = sizeof(buf); + } + rlen = mg_read(conn, buf, (size_t)rlen); + if (rlen <= 0) { + fail = 1; + break; + } + wlen = fwrite(buf, 1, (size_t)rlen, f); + if (wlen != rlen) { + fail = 1; + break; + } + nlen += wlen; + } + fclose(f); + } + + if (fail) { + mg_printf(conn, + "HTTP/1.1 409 Conflict\r\n" + "Content-Type: text/plain\r\n" + "Connection: close\r\n\r\n"); + } else { + mg_printf(conn, + "HTTP/1.1 201 Created\r\n" + "Content-Type: text/plain\r\n" + "Connection: close\r\n\r\n"); + } + + return true; + } +}; + +class WsStartHandler : public CivetHandler +{ + public: + bool + handleGet(CivetServer *server, struct mg_connection *conn) + { + + mg_printf(conn, + "HTTP/1.1 200 OK\r\nContent-Type: text/html\r\nConnection: " + "close\r\n\r\n"); + + mg_printf(conn, "\n"); + mg_printf(conn, "\n\n"); + mg_printf(conn, "\n"); + mg_printf(conn, "Embedded websocket example\n"); + +#ifdef USE_WEBSOCKET + /* mg_printf(conn, "\n"); ... xhtml style */ + mg_printf(conn, "\n"); + mg_printf(conn, "\n\n"); + mg_printf( + conn, + "
No websocket connection yet
\n"); +#else + mg_printf(conn, "\n\n"); + mg_printf(conn, "Example not compiled with USE_WEBSOCKET\n"); +#endif + mg_printf(conn, "\n\n"); + + return 1; +} +}; + + +#ifdef USE_WEBSOCKET +class WebSocketHandler : public CivetWebSocketHandler { + + virtual bool handleConnection(CivetServer *server, + const struct mg_connection *conn) { + printf("WS connected\n"); + return true; + } + + virtual void handleReadyState(CivetServer *server, + struct mg_connection *conn) { + printf("WS ready\n"); + + const char *text = "Hello from the websocket ready handler"; + mg_websocket_write(conn, MG_WEBSOCKET_OPCODE_TEXT, text, strlen(text)); + } + + virtual bool handleData(CivetServer *server, + struct mg_connection *conn, + int bits, + char *data, + size_t data_len) { + printf("WS got %lu bytes: ", (long unsigned)data_len); + fwrite(data, 1, data_len, stdout); + printf("\n"); + + mg_websocket_write(conn, MG_WEBSOCKET_OPCODE_TEXT, data, data_len); + return (data_len<4); + } + + virtual void handleClose(CivetServer *server, + const struct mg_connection *conn) { + printf("WS closed\n"); + } +}; +#endif + + +int +main(int argc, char *argv[]) +{ + mg_init_library(0); + + const char *options[] = { + "document_root", DOCUMENT_ROOT, "listening_ports", PORT, 0}; + + std::vector cpp_options; + for (int i=0; i<(sizeof(options)/sizeof(options[0])-1); i++) { + cpp_options.push_back(options[i]); + } + + // CivetServer server(options); // <-- C style start + CivetServer server(cpp_options); // <-- C++ style start + + ExampleHandler h_ex; + server.addHandler(EXAMPLE_URI, h_ex); + + ExitHandler h_exit; + server.addHandler(EXIT_URI, h_exit); + + AHandler h_a; + server.addHandler("/a", h_a); + + ABHandler h_ab; + server.addHandler("/a/b", h_ab); + + WsStartHandler h_ws; + server.addHandler("/ws", h_ws); + +#ifdef NO_FILES + /* This handler will handle "everything else", including + * requests to files. If this handler is installed, + * NO_FILES should be set. */ + FooHandler h_foo; + server.addHandler("", h_foo); + + printf("See a page from the \"all\" handler at http://localhost:%s/\n", PORT); +#else + FooHandler h_foo; + server.addHandler("**.foo", h_foo); + printf("Browse files at http://localhost:%s/\n", PORT); +#endif + +#ifdef USE_WEBSOCKET + WebSocketHandler h_websocket; + server.addWebSocketHandler("/websocket", h_websocket); + printf("Run websocket example at http://localhost:%s/ws\n", PORT); +#endif + + printf("Run example at http://localhost:%s%s\n", PORT, EXAMPLE_URI); + printf("Exit at http://localhost:%s%s\n", PORT, EXIT_URI); + + while (!exitNow) { +#ifdef _WIN32 + Sleep(1000); +#else + sleep(1); +#endif + } + + printf("Bye!\n"); + mg_exit_library(); + + return 0; +} diff --git a/software/WebServer/build_webfs.sh b/software/WebServer/build_webfs.sh new file mode 100755 index 000000000..c2c2e829e --- /dev/null +++ b/software/WebServer/build_webfs.sh @@ -0,0 +1,63 @@ +#!/bin/bash + +SRCDIR=`pwd`/webserver +WEBFSDIR=`pwd`/webfs +echo "Building into:$WEBFSDIR from $SRCDIR..." + +mkdir -p ${WEBFSDIR}/css +mkdir -p ${WEBFSDIR}/js +mkdir -p ${WEBFSDIR}/font-awesome +mkdir -p ${WEBFSDIR}/font-awesome/css +mkdir -p ${WEBFSDIR}/font-awesome/fonts +mkdir -p ${WEBFSDIR}/images + +(cd ${SRCDIR}/; +cp favicon.ico ${WEBFSDIR}/ +cp version.txt ${WEBFSDIR}/ +cp index.html ${WEBFSDIR}/ +cp keymap.html ${WEBFSDIR}/keymap.html +cp mouse.html ${WEBFSDIR}/mouse.html +cp ota.html ${WEBFSDIR}/ota.html +cp wifimanager.html ${WEBFSDIR}/wifimanager.html + + +(cd ${SRCDIR}/css; +cp bootstrap.min.css.gz ${WEBFSDIR}/css/ +gzip -c jquery.edittable.min.css > ${WEBFSDIR}/css/jquery.edittable.min.css.gz +gzip -c sb-admin.css > ${WEBFSDIR}/css/sb-admin.css.gz +gzip -c sharpkey.css > ${WEBFSDIR}/css/sharpkey.css.gz +gzip -c style.css > ${WEBFSDIR}/css/style.css.gz +gzip -c styles.css > ${WEBFSDIR}/css/styles.css.gz +) + +(cd ${SRCDIR}/font-awesome +) + +(cd ${SRCDIR}/font-awesome/css +#cp font-awesome.min.css.gz ${WEBFSDIR}/font-awesome/css/ +gzip -c font-awesome.css > ${WEBFSDIR}/font-awesome/css/font-awesome.min.css.gz +) + +(cd ${SRCDIR}/font-awesome/fonts +gzip -c fontawesome-webfont.woff > ${WEBFSDIR}/font-awesome/fonts/fontawesome-webfont.woff.gz +#cp fontawesome-webfont.ttf.gz ${WEBFSDIR}/font-awesome/fonts/ +#cp fontawesome-webfont.woff.gz ${WEBFSDIR}/font-awesome/fonts/ +) + +(cd ${SRCDIR}/images; +) + +(cd ${SRCDIR}/js; +cp 140medley.min.js ${WEBFSDIR}/js/ +cp bootstrap.min.js.gz ${WEBFSDIR}/js/ +gzip -c index.js > ${WEBFSDIR}/js/index.js.gz +gzip -c jquery.edittable.js > ${WEBFSDIR}/js/jquery.edittable.js.gz +gzip -c jquery.edittable.min.js > ${WEBFSDIR}/js/jquery.edittable.min.j.gz +cp jquery.min.js.gz ${WEBFSDIR}/js/ +gzip -c keymap.js > ${WEBFSDIR}/js/keymap.js.gz +gzip -c mouse.js > ${WEBFSDIR}/js/mouse.js.gz +gzip -c ota.js > ${WEBFSDIR}/js/ota.js.gz +gzip -c wifimanager.js > ${WEBFSDIR}/js/wifimanager.js.gz +) + +) diff --git a/software/WebServer/conf/civetweb.conf b/software/WebServer/conf/civetweb.conf new file mode 100644 index 000000000..c1ecc6428 --- /dev/null +++ b/software/WebServer/conf/civetweb.conf @@ -0,0 +1,86 @@ +# Instructions to run (on Linux) to reproduce test results: +# +# 1) copy civetweb executable here (examples/https directory) +# 2) sudo ./civetweb +# +# Instructions to adapt to your own server: +# +# 1) generate your own server cert +# 2) generate at least one backup server cert +# in case you want a self signed cert, you can use the script +# in resources/cert for both steps +# 3) copy the content of the *.pin files into the Public-Key-Pins +# header config (the base64 encoded certificate hash) +# 4) set the document root, and all other required http server settings +# 5) Run the tests from the three websites below. They will tell you +# also what clients are compatible with your settings. The settings +# here are very strict and lock out most older clients/browsers. +# You will find some hints for fine tuning there as well. +# 6) If you know all your clients, and give them client certificates in +# advance, you can significantly improve security by setting +# "ssl_verify_peer" to "yes" and specifying a client cert (directory) +# using "ssl_ca_file/path". This will lock out all clients without a +# proper certificate. Don't use it for your public home page, but +# consider it for your private remote access server. +# 7) run civetweb, like above - or better create your own start script +# You are welcome to share your thoughts and experience on GitHub +# (see README.md in CivetWeb main directory). + +# Don't run as super user, switch back to a regular user +run_as_user user + +# The standard HTTP port 80 should redirect to the standard HTTPS port 443 +listening_ports 80r,443s + +# Don't forget to set the document root and domain +#document_root tdb +#authentication_domain mydomain.com + +# Set the a certificate +ssl_certificate ../../resources/cert/server.pem + +# Require a client cert for your private server (see above) +#ssl_verify_peer yes +#ssl_ca_file ../../resources/cert/client.pem + +# Enforce TLS1.2 and some strong cipher(s) +ssl_protocol_version 4 +ssl_cipher_list ECDH+AESGCM+AES256:!aNULL:!MD5:!DSS + +# Tell all browsers to access this site only as HTTPS for the next 180 days +strict_transport_security_max_age 15552000 + +# Set some HTTP security header, see https://securityheaders.io +additional_header Content-Security-Policy: script-src 'self' +additional_header X-Frame-Options: SAMEORIGIN +additional_header X-Xss-Protection: 1; mode=block +additional_header X-Content-Type-Options: nosniff +additional_header Referrer-Policy: same-origin +additional_header Public-Key-Pins: pin-sha256="uz1UTAPen+xb+UoQqkVlEx4H653LbMjfRJcZx5OrjbI="; pin-sha256="pf3px1MBPmlTGAPoiHWqaSJ9L9Z+DKfwgsU7LfLnmsk="; max-age=7776000 +#additional_header Expect-CT: max-age=86400,report-uri="https://mydomain.com/report" + + +# Ratings from 2017-09-03 (tests performed later may require more +# strict security settings) +# +# Headers rated A+ from https://securityheaders.io/ +# +# SSL rated B from https://www.htbridge.com/ssl when using a self signed +# certificate, but no other weaknesses for modern browsers. +# Site remarks some older TLS versions and some weaker ciphers are not +# supported (but that's accessibility, not security). +# +# HTTPS rated A+ from https://www.htbridge.com/websec/ when using a self +# signed certificate, generated with make_certs.sh in resources/cert/ +# and adding the server.pin and server_bkup.pin content into the +# Public-Key-Pins header above. +# +# A rating of "T / If trust issues are ignored: A" (ignoring self-signed cert) +# from https://www.ssllabs.com/ssltest/, https://www.qualys.com/forms/freescan/ +# (Note: this test is runs with reverse DNS name, while all others use the +# IP address). +# +# Note: This settings are very strict and prevent some older but still common +# versions of major browsers to access this site. The test web sites will give +# you an overview. Test, before you use this settings. + diff --git a/software/WebServer/conf/server.crt b/software/WebServer/conf/server.crt new file mode 100644 index 000000000..2226a62af --- /dev/null +++ b/software/WebServer/conf/server.crt @@ -0,0 +1,14 @@ +-----BEGIN CERTIFICATE----- +MIICHDCCAYUCFGkCyCGW5oP6L+eDHT4wZi1NQGb7MA0GCSqGSIb3DQEBCwUAME0x +CzAJBgNVBAYTAkdCMRMwEQYDVQQIDApTb21lLVN0YXRlMRcwFQYDVQQKDA5lbmdp +bmVlcnNAd29yazEQMA4GA1UEAwwHZWF3LmFwcDAeFw0yMjA5MTUxMzUxNTRaFw0z +MjA5MTIxMzUxNTRaME0xCzAJBgNVBAYTAkdCMRMwEQYDVQQIDApTb21lLVN0YXRl +MRcwFQYDVQQKDA5lbmdpbmVlcnNAd29yazEQMA4GA1UEAwwHZWF3LmFwcDCBnzAN +BgkqhkiG9w0BAQEFAAOBjQAwgYkCgYEA6WvBDkVGMa5fYEke2jM3ydnA+SJD+PO/ +nDP68uIWrzqmu4lMeEt5iw5EvcKJePVzbP567z2MLrxyQZEvF3QArWxnlZVKgzMm +vE+WdOq+TBgehWr/si/RnDQhnq/pSF7K89k0ZwzqEiETDeQw64SBtVwZEl+gB2VJ +70p4atfS4xECAwEAATANBgkqhkiG9w0BAQsFAAOBgQDDzPd3zQ4UHyvSMBBjgWlq +41y9lTg7sukQqSSULHGqsLsZ8DSXtXyzqMV0EDy+k0Hns8+gwqStpr/GKxHLOgo5 +EjfB/IJwFKxzFkboDwoLPbPib6REw1o0DT8io7sBIZwawua47UF/gLtvSYNBOlfj +OV0444A20JaDYutEpn9weg== +-----END CERTIFICATE----- diff --git a/software/WebServer/conf/server.csr b/software/WebServer/conf/server.csr new file mode 100644 index 000000000..dbf73b502 --- /dev/null +++ b/software/WebServer/conf/server.csr @@ -0,0 +1,11 @@ +-----BEGIN CERTIFICATE REQUEST----- +MIIBjDCB9gIBADBNMQswCQYDVQQGEwJHQjETMBEGA1UECAwKU29tZS1TdGF0ZTEX +MBUGA1UECgwOZW5naW5lZXJzQHdvcmsxEDAOBgNVBAMMB2Vhdy5hcHAwgZ8wDQYJ +KoZIhvcNAQEBBQADgY0AMIGJAoGBAOlrwQ5FRjGuX2BJHtozN8nZwPkiQ/jzv5wz ++vLiFq86pruJTHhLeYsORL3CiXj1c2z+eu89jC68ckGRLxd0AK1sZ5WVSoMzJrxP +lnTqvkwYHoVq/7Iv0Zw0IZ6v6UheyvPZNGcM6hIhEw3kMOuEgbVcGRJfoAdlSe9K +eGrX0uMRAgMBAAGgADANBgkqhkiG9w0BAQsFAAOBgQCVJ44RrkgQMAKKQKYbHAwW +6T8sYQhDk9ko0daxFdDan9HifohZMHGfNYB5kpZRevV6zQFyP5npApK5S5akpL/G +hmdi2G3qJKuX2LgKTC7cUk8qgTlhgihNElZZHZlmPG4TG2BJlfEJMOnXZNInoUkO +q6/Yq0vAWzUaMKOmS8t4zg== +-----END CERTIFICATE REQUEST----- diff --git a/software/WebServer/conf/server.key b/software/WebServer/conf/server.key new file mode 100644 index 000000000..6fcbe5338 --- /dev/null +++ b/software/WebServer/conf/server.key @@ -0,0 +1,15 @@ +-----BEGIN RSA PRIVATE KEY----- +MIICXgIBAAKBgQDpa8EORUYxrl9gSR7aMzfJ2cD5IkP487+cM/ry4havOqa7iUx4 +S3mLDkS9wol49XNs/nrvPYwuvHJBkS8XdACtbGeVlUqDMya8T5Z06r5MGB6Fav+y +L9GcNCGer+lIXsrz2TRnDOoSIRMN5DDrhIG1XBkSX6AHZUnvSnhq19LjEQIDAQAB +AoGAQ+vE62AhAsfYnO3p+lg4/ZVNX7Em0kQrF0rQ1OgQ7cBFUACtrbtYjKwEOKto +0Teq9KZAI2lnZxoSrR2P9GUe5MmHR9CrXiTczmRM7uND7t/ardW3gT0RbjaCr9oH +Exp4YKFKv24LMdcgkVe8JwJOZhB8VvnB0WQMDyFYsy8hAjkCQQD3CNCQR65MOEjy +vE3G+WRLtOWvzuNzAN9FMFNj5pH5oz6skDts7Yvj0DWyb5FHlBwpItNs9rJd2UyC +UQWaxhZXAkEA8eR09UnxOV7LaShmchoX/otuKeVMATdcyjOonM/fiHfBSZefW6YS +675lEGqRfGfjXpXQQBvMbQq67TUAISbg1wJBANU7/Jut5BvSsdUlCZXpC9P1kBXT +Za2NYSwd7L1c90Ae0yitTz5VRd0dilw9xY+dnzk64Hk78PblbQ9H1Kimt/0CQQCC +CAuPaGZSLtEuAFfB8qD/ZribsPWAmeA5mjeDxIMneyjehLFXtRjqvXjasE7xD2+8 +gtBmBguIeoItzZX6PEoVAkEApwW7FNmNwUYuklu7WtS1HXOKvQzp+BZrDZAdnIPY +xEeTiJDvBsxDLBptzLS8I0elHE/7zHtQSr8mDqQifiT2Rw== +-----END RSA PRIVATE KEY----- diff --git a/software/WebServer/conf/server.key.orig b/software/WebServer/conf/server.key.orig new file mode 100644 index 000000000..8173b34ee --- /dev/null +++ b/software/WebServer/conf/server.key.orig @@ -0,0 +1,18 @@ +-----BEGIN RSA PRIVATE KEY----- +Proc-Type: 4,ENCRYPTED +DEK-Info: DES-EDE3-CBC,B353E67B85AB5B84 + +oD/257rCCOkKvU5nqMdJjbcdILvGb+JTBtBy4Hzk8eoiq2idENQE86W34faYG+ho +wMosr5J+80hkrQI9ct+s5xb8/GTVFJPG3ek1aghL0ToDyNUmdWGqAK/+VbNptcLE +j5HNDttaKkDIqiiiIPDUWEJsIzOXU9NZF86bOsORU4q83lZk56sAhdvkgfRlBmso +BClwG/ABVxPc4vR+9N3Vbu9fWHEkRedqVoWju7vDLFoNPIO418lk0fzdgrVri6ah ++nOsSpjZxjjkDc5rJhqBreK1EaR1+Y2DzJ3r6944bPuwjwHXbhEzQz8y/xsjAsYl +bF+zrSaQN0ncyj4XjvNaAc0WXx0CEHEpC0OKwA4+zUYIC9utlVkt1CzGCN9FJYrk +8JtDfhaok4zlVBCowTpdkjhc6FXXicxIiaenSTOu9WzHjx1/TgRWt+SAERr7zCD0 +no0pV3mA3ObUCg1HCcda9qQ9J+z6crXE7hep7m2T161ebg1h8N9gkdMjtnzvV+AA +U6Xxq4fqafG/Jjj8+2YZZZZ/osOBPU4D6FVr+XoqW7rqEGvOT6lhO1AVwZG/Wgbx +eimOniQfdjAwtMdjSbfS8EqawUhZfJ3QlV8rDbrhTJIwcWpVJEI20V1bvRf/DQwj +js2paPPs01xKROL6H5oegn4BMV66OTD0km/cqu52MONLnsGDdQJJAGmmftguxRh1 ++jFO2iNeJ91jLfUObFyun5qOWi2I6lwkHtGG6M34h+14tniOA6C8NmbxXBhXDPa/ +UHyJFGDQJnnRgZTPxsnXly1Vc7/I23/MVkIXNp/w4jX7FM4CP8jVaw== +-----END RSA PRIVATE KEY----- diff --git a/software/WebServer/conf/server.pem b/software/WebServer/conf/server.pem new file mode 100644 index 000000000..2226a62af --- /dev/null +++ b/software/WebServer/conf/server.pem @@ -0,0 +1,14 @@ +-----BEGIN CERTIFICATE----- +MIICHDCCAYUCFGkCyCGW5oP6L+eDHT4wZi1NQGb7MA0GCSqGSIb3DQEBCwUAME0x +CzAJBgNVBAYTAkdCMRMwEQYDVQQIDApTb21lLVN0YXRlMRcwFQYDVQQKDA5lbmdp +bmVlcnNAd29yazEQMA4GA1UEAwwHZWF3LmFwcDAeFw0yMjA5MTUxMzUxNTRaFw0z +MjA5MTIxMzUxNTRaME0xCzAJBgNVBAYTAkdCMRMwEQYDVQQIDApTb21lLVN0YXRl +MRcwFQYDVQQKDA5lbmdpbmVlcnNAd29yazEQMA4GA1UEAwwHZWF3LmFwcDCBnzAN +BgkqhkiG9w0BAQEFAAOBjQAwgYkCgYEA6WvBDkVGMa5fYEke2jM3ydnA+SJD+PO/ +nDP68uIWrzqmu4lMeEt5iw5EvcKJePVzbP567z2MLrxyQZEvF3QArWxnlZVKgzMm +vE+WdOq+TBgehWr/si/RnDQhnq/pSF7K89k0ZwzqEiETDeQw64SBtVwZEl+gB2VJ +70p4atfS4xECAwEAATANBgkqhkiG9w0BAQsFAAOBgQDDzPd3zQ4UHyvSMBBjgWlq +41y9lTg7sukQqSSULHGqsLsZ8DSXtXyzqMV0EDy+k0Hns8+gwqStpr/GKxHLOgo5 +EjfB/IJwFKxzFkboDwoLPbPib6REw1o0DT8io7sBIZwawua47UF/gLtvSYNBOlfj +OV0444A20JaDYutEpn9weg== +-----END CERTIFICATE----- diff --git a/software/WebServer/libcivetweb.a b/software/WebServer/libcivetweb.a new file mode 100644 index 000000000..1878125ba Binary files /dev/null and b/software/WebServer/libcivetweb.a differ diff --git a/software/WebServer/start_WebServer.sh b/software/WebServer/start_WebServer.sh new file mode 100644 index 000000000..5a2fba9b5 --- /dev/null +++ b/software/WebServer/start_WebServer.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +ROOTDIR=/apps/WebServer + +cd ${ROOTDIR} +nohup ${ROOTDIR}/WebServer & diff --git a/software/WebServer/webserver/css/bootstrap.min.css.gz b/software/WebServer/webserver/css/bootstrap.min.css.gz new file mode 100644 index 000000000..f5196567d Binary files /dev/null and b/software/WebServer/webserver/css/bootstrap.min.css.gz differ diff --git a/software/WebServer/webserver/css/jquery.edittable.min.css b/software/WebServer/webserver/css/jquery.edittable.min.css new file mode 100644 index 000000000..b77cb4484 --- /dev/null +++ b/software/WebServer/webserver/css/jquery.edittable.min.css @@ -0,0 +1,18 @@ +table.inputtable{width:100%;border:1px solid #ddd;border-collapse:collapse;border-spacing:0;-moz-box-shadow:0 1px 3px rgba(0,0,0,.075);-webkit-box-shadow:0 1px 3px rgba(0,0,0,.075);box-shadow:0 1px 3px rgba(0,0,0,.075);margin:15px 0} +table.inputtable a.icon-button{background-color:#ccc;display:inline-block;width:18px;height:18px;text-decoration:none;color:#fff;font-weight:800;line-height:16px;text-align:center;font-size:14px;-moz-border-radius:1px;-webkit-border-radius:1px;border-radius:1px;-moz-box-shadow:0 0 1px rgba(0,0,0,0.2);-webkit-box-shadow:0 0 1px rgba(0,0,0,0.2);box-shadow:0 0 1px rgba(0,0,0,0.2)} +table.inputtable a.icon-button.addcol,table.inputtable a.icon-button.addrow{background-color:#81b71a} +table.inputtable a.icon-button.delcol,table.inputtable a.icon-button.delrow{background-color:#db4a39} +table.inputtable a.icon-button.disabled{background-color:#eee} +table.inputtable td:last-child,table.inputtable th:last-child{width:54px;border:1px solid #eee;border-right:thick;} +table.inputtable td,table.inputtable th{border:1px solid #eee;text-align:center;height:40px;vertical-align:middle;font-size:14px} +table.inputtable th{background-color:#f1f1f1;border-top:none;border-bottom:2px solid #ddd;border-color:#ddd} +table.inputtable td input[type=text]{border:0;width:90%;height:100%;text-align:center;padding:0 5%} +table.inputtable tr td input:focus{background-color:#fafafa} +table.inputtable.wh tbody tr:nth-child(1),table.inputtable.wh tbody tr:nth-child(1) input{background-color:#fdfdfd;font-weight:800} +table.inputtable th:first-child,table.inputtable td:first-child{border-left:none} +table.inputtable tr:last-child td{border-bottom:none} +@media only screen and max-width 480px { +table.inputtable td,table.inputtable th{min-width:40px;height:80px} +table.inputtable a.icon-button{width:40px;height:40px;font-size:18px;min-width:40px;line-height:40px;margin:3px 0} +table.inputtable td input{height:80px} +} diff --git a/software/WebServer/webserver/css/sb-admin.css b/software/WebServer/webserver/css/sb-admin.css new file mode 100644 index 000000000..f371f0780 --- /dev/null +++ b/software/WebServer/webserver/css/sb-admin.css @@ -0,0 +1,159 @@ +/* +Author: Start Bootstrap - http://startbootstrap.com +'SB Admin' HTML Template by Start Bootstrap + +All Start Bootstrap themes are licensed under Apache 2.0. +For more info and more free Bootstrap 3 HTML themes, visit http://startbootstrap.com! +*/ + +/* ATTN: This is mobile first CSS - to update 786px and up screen width use the media query near the bottom of the document! */ + +/* Global Styles */ + +body { + margin-top: 50px; +} + +#wrapper { + padding-left: 0; +} + +#page-wrapper { + width: 100%; + padding: 5px 15px; +} + +/* Nav Messages */ + +.messages-dropdown .dropdown-menu .message-preview .avatar, +.messages-dropdown .dropdown-menu .message-preview .name, +.messages-dropdown .dropdown-menu .message-preview .message, +.messages-dropdown .dropdown-menu .message-preview .time { + display: block; +} + +.messages-dropdown .dropdown-menu .message-preview .avatar { + float: left; + margin-right: 15px; +} + +.messages-dropdown .dropdown-menu .message-preview .name { + font-weight: bold; +} + +.messages-dropdown .dropdown-menu .message-preview .message { + font-size: 12px; +} + +.messages-dropdown .dropdown-menu .message-preview .time { + font-size: 12px; +} + + +/* Nav Announcements */ + +.announcement-heading { + font-size: 50px; + margin: 0; +} + +.announcement-text { + margin: 0; +} + +/* Table Headers */ + +table.tablesorter thead { + cursor: pointer; +} + +table.tablesorter thead tr th:hover { + background-color: #f5f5f5; +} + +/* Flot Chart Containers */ + +.flot-chart { + display: block; + height: 400px; +} + +.flot-chart-content { + width: 100%; + height: 100%; +} + +/* Edit Below to Customize Widths > 768px */ +@media (min-width:768px) { + + /* Wrappers */ + + #wrapper { + padding-left: 225px; + } + + #page-wrapper { + padding: 15px 25px; + } + + /* Side Nav */ + + .side-nav { + margin-left: -225px; + left: 225px; + width: 225px; + position: fixed; + top: 50px; + height: 100%; + border-radius: 0; + border: none; + background-color: #222222; + overflow-y: auto; + } + + /* Bootstrap Default Overrides - Customized Dropdowns for the Side Nav */ + + .side-nav>li.dropdown>ul.dropdown-menu { + position: relative; + min-width: 225px; + margin: 0; + padding: 0; + border: none; + border-radius: 0; + background-color: transparent; + box-shadow: none; + -webkit-box-shadow: none; + } + + .side-nav>li.dropdown>ul.dropdown-menu>li>a { + color: #999999; + padding: 15px 15px 15px 25px; + } + + .side-nav>li.dropdown>ul.dropdown-menu>li>a:hover, + .side-nav>li.dropdown>ul.dropdown-menu>li>a.active, + .side-nav>li.dropdown>ul.dropdown-menu>li>a:focus { + color: #fff; + background-color: #080808; + } + + .side-nav>li>a { + width: 225px; + } + + .navbar-inverse .navbar-nav>li>a:hover, + .navbar-inverse .navbar-nav>li>a:focus { + background-color: #080808; + } + + /* Nav Messages */ + + .messages-dropdown .dropdown-menu { + min-width: 300px; + } + + .messages-dropdown .dropdown-menu li a { + white-space: normal; + } + +} diff --git a/software/WebServer/webserver/css/sharpkey.css b/software/WebServer/webserver/css/sharpkey.css new file mode 100644 index 000000000..9bd439e1b --- /dev/null +++ b/software/WebServer/webserver/css/sharpkey.css @@ -0,0 +1,266 @@ +.wm-button { + width: 95px; + height: 25px; + background: blue; + border: none; + vertical-align: top; + margin-left: 25px; + cursor: pointer; + color: white; + transition: 2s; + border-radius: 12px; +} + +.wm-button:disabled { + background: #999; + color: #555; + cursor: not-allowed; +} + +.wm-button:hover { + background-color: #81ecec; + border: 2px solid #00cec9; +} + +input[type="file"] { + display: none; +} + +.firmware-file-upload { + width: 95px; + height: 25px; + background: blue; + border: none; + vertical-align: middle; + text-align: center; + line-height: 25px; + margin-left: 35px; + margin-bottom: 0px; + cursor: pointer; + color: white; + transition: 2s; + border-radius: 12px; +} + +.firmware-file-upload:hover { + background-color: #81ecec; + border: 2px solid #00cec9; +} + + +.keymap-file-upload { + width: 95px; + height: 25px; + background: blue; + border: none; + vertical-align: middle; + text-align: center; + line-height: 25px; + margin-left: 35px; + margin-bottom: 0px; + cursor: pointer; + color: white; + transition: 2s; + border-radius: 12px; +} + +.keymap-file-upload:hover { + background-color: #81ecec; + border: 2px solid #00cec9; +} + +input[type=file]::file-selector-button { + border: 2px solid #6c5ce7; + padding: .2em .4em; + border-radius: .2em; + background-color: #a29bfe; + transition: 1s; +} + +input[type=file]::file-selector-button:hover { + background-color: #81ecec; + border: 2px solid #00cec9; +} + +.sk-modules-table { + border: none; + border-collapse: collapse; +} +.sk-modules-table caption { + padding-bottom: 0.5em; +} +.sk-modules-table th, .sk-modules-table td { + border: none; + padding: 0.2rem 2rem; +} +.sk-modules-table td { + white-space: nowrap; +} +.sk-modules-table th { + font-weight: normal; +} +.sk-modules-table td { + border-style: none; + vertical-align: top; +} +.sk-modules-table th { + padding: 0.2em; + vertical-align: middle; + text-align: center; +} + +.sk-modules-table tbody td:first-child::after { + content: leader(". "); +} + +.sk-client-wifi-config-table { + border: none; + border-collapse: collapse; + width: 1px !important; + table-layout: auto !important; +} +.sk-client-wifi-config-table caption { + padding-bottom: 0.5em; +} +.sk-client-wifi-config-table th, .sk-client-wifi-config-table td { + border: none; + padding: 0.2rem 2rem; + padding-left: 0; + padding-right: 4rem; +} +.sk-client-wifi-config-table td { + white-space: nowrap; + overflow: hidden; + border-style: none; + vertical-align: top; + width: auto !important; +} +.sk-client-wifi-config-table th { + font-weight: normal; + padding: 0.2em; + vertical-align: middle; + text-align: center; + width: auto !important; +} + +#client-wifi-config-area { + overflow-x: scroll; + width: fit-content; +} + +#firmware-revision-area { + overflow-x: scroll; + width: fit-content; +} + +#esp32-partitions-area { + overflow-x: scroll; + width: fit-content; +} + +.sk-partitions-table { + border: none; + border-collapse: collapse; +} +.sk-partitions-table caption { + padding-bottom: 0.5em; +} +.sk-partitions-table th, .sk-partitions-table td { + border: none; + padding: 0.2rem 2rem; +} +.sk-partitions-table td { + white-space: nowrap; + border-style: none; + vertical-align: top; +} +.sk-partitions-table th { + font-weight: normal; + padding: 0.2em; + vertical-align: middle; + text-align: center; +} + +.sk-partitions-table tbody td:first-child::after { + content: leader(". "); +} + +.sk-partitions-table tbody td:nth-child(4) { + text-align: right; +} +.sk-partitions-table tbody td:nth-child(5) { + text-align: right; +} +.sk-partitions-table tbody td:nth-child(6) { + text-align: center; +} +.sk-partitions-table tbody td:nth-child(8) { + text-align: center; +} + +.table-condensed .progress { + margin-bottom: 0 !important; + width: 400px; + display: none; +} + +.table-borderless > tbody > tr > td, +.table-borderless > thead > tr > td, +.table-borderless { + border-bottom: 0; + border-top: 0; + padding: 4px; + padding-top: 2px; + padding-bottom: 0; + white-space: nowrap; +} + +.table-responsive { + border-bottom: 0; + border-top: 0; + border-left: 0; + border-right: 0; + padding: 4px; + padding-top: 2px; + padding-bottom: 0; + white-space: nowrap; + table-layout: auto; +} + +.table { + margin-bottom: 10px; +} + +.justify { + text-align: justify; + text-justify: inter-word; +} + +.keymap { + max-height: 36.2em; + overflow: auto; +} + +.hr_no_margin { + margin-top: 0.2em; + margin-bottom: 0.2em; +} + +fieldset { + overflow: hidden; +} +.radio-mouse { + padding-right: 1em; +} +.radio-mouse label { + float: left; + clear: none; + display: block; + padding: 0px 1em 0px 8px; +} +input[type=radio] .radio-mouse, +input.radio .radio-mouse { + float: left; + clear: none; + margin: 2px 0 0 2px; +} diff --git a/software/WebServer/webserver/css/style.css b/software/WebServer/webserver/css/style.css new file mode 100644 index 000000000..11e816658 --- /dev/null +++ b/software/WebServer/webserver/css/style.css @@ -0,0 +1,253 @@ +/* +body { + margin: 0; +} +*/ + +/* +h1 { + text-align: center; + font-family: Tahoma, Arial, sans-serif; + color: #06D85F; + margin: 10px; +} + +*/ +.box { + width: 40%; + margin: 0 auto; + background: rgba(255,255,255,0.2); + padding: 35px; + border: 2px solid #fff; + border-radius: 20px/50px; + background-clip: padding-box; + text-align: center; +} + +.overlay { + position: fixed; + top: 0; + bottom: 0; + left: 0; + right: 0; + background: rgba(0, 0, 0, 0.7); + //transition: opacity 500ms; + visibility: hidden; + opacity: 0; +} +.overlay:target { + visibility: visible; + opacity: 1; +} + +.popup { + margin: 70px auto; + padding: 20px; + background: #fff; + border-radius: 5px; + width: 30%; + position: relative; + transition: all 5s ease-in-out; +} + +.popup h2 { + margin-top: 0; + color: #333; + font-family: Tahoma, Arial, sans-serif; +} +.popup .close { + position: absolute; + top: 20px; + right: 30px; + transition: all 200ms; + font-size: 30px; + font-weight: bold; + text-decoration: none; + color: #333; +} +.popup .close:hover { + color: #06D85F; +} +.popup .content { + max-height: 30%; + overflow: auto; +} + +@media screen and (max-width: 700px){ + .box{ + width: 90%; + } + .popup{ + width: 90%; + } +} + +/* +html { + font-family: Arial, Helvetica, sans-serif; + display: inline-block; + text-align: center; +} + +h1 { + font-size: 1.8rem; + color: white; +} + +p { + font-size: 1.1rem; +} +*/ + +.topnav { + overflow: hidden; + background-color: #0A1128; +} + +.content { + padding: 5%; +} + +.card-grid { + max-width: 800px; + margin: 0 auto; + display: grid; + grid-gap: 2rem; + grid-template-columns: repeat(auto-fit, minmax(300px, 1fr)); +} + +.card { + background-color: lightyellow; + box-shadow: 2px 2px 12px 1px rgba(140,140,140,.5); +} + +.card-title { + font-size: 1.1rem; + font-weight: bold; + color: #034078 +} +/* +input[type=submit] { + border: none; + color: #FEFCFB; + background-color: #034078; + padding: 15px 15px; + text-align: center; + text-decoration: none; + display: inline-block; + font-size: 18px; + width: 30%; + margin-right: 10px; + border-radius: 4px; + transition-duration: 0.4s; + } + +input[type=submit]:hover { + background-color: #1282A2; +} + +input[type=text], input[type=number], select { + width: 40%; + padding: 8px 10px; + margin: 12px; + display: inline-block; + border: 1px solid #ccc; + border-radius: 4px; + box-sizing: border-box; +} + +input[type=url], input[type=number], select { + width: 50%; + padding: 12px 20px; + margin: 18px; + display: inline-block; + border: 1px solid #ccc; + border-radius: 4px; + box-sizing: border-box; +} + +label { + font-size: 1rem; +} +*/ +.value{ + font-size: 1rem; + color: #1282A2; +} +.state { + font-size: 1rem; + color: #1282A2; +} + +.button { + font-size: 2em; + padding: 3px; + color: #dbd75e; + border: 1px solid #000; + border-radius: 5px; + text-decoration: none; + cursor: pointer; + transition: all 1s ease-out; + + background: #1b06d8; +} +.button:hover { + background: #06D85F; +} + +/* +button { + //border: none; + // color: #FEFCFB; + // padding: 15px 32px; + // text-align: center; + // font-size: 30px; + // width: 100px; + // border-radius: 4px; + transition-duration: 0.4s; +} +.button-on { + // background-color: #034078; +} +.button-on:hover { + // background-color: #1282A2; +} +.button-off { + // background-color: #858585; +} +.button-off:hover { + // background-color: #252524; +} +*/ +#sk-modules-table { + border: solid thin; + border-collapse: collapse; +} +#sk-modules-table caption { + padding-bottom: 0.5em; +} +#sk-modules-table th, +#sk-modules-table td { + border: solid thin; + padding: 0.5rem 2rem; +} +#sk-modules-table td { + white-space: nowrap; +} +#sk-modules-table th { + font-weight: normal; +} +#sk-modules-table td { + border-style: none solid; + vertical-align: top; +} +#sk-modules-table th { + padding: 0.2em; + vertical-align: middle; + text-align: center; +} + +#sk-modules-table tbody td:first-child::after { + content: leader(". "); +} + diff --git a/software/WebServer/webserver/css/styles.css b/software/WebServer/webserver/css/styles.css new file mode 100644 index 000000000..e36236199 --- /dev/null +++ b/software/WebServer/webserver/css/styles.css @@ -0,0 +1 @@ +body { padding-bottom: 70px; } diff --git a/software/WebServer/webserver/favicon.ico b/software/WebServer/webserver/favicon.ico new file mode 100644 index 000000000..0babb7db7 Binary files /dev/null and b/software/WebServer/webserver/favicon.ico differ diff --git a/software/WebServer/webserver/font-awesome/css/font-awesome.css b/software/WebServer/webserver/font-awesome/css/font-awesome.css new file mode 100644 index 000000000..43b43caf3 --- /dev/null +++ b/software/WebServer/webserver/font-awesome/css/font-awesome.css @@ -0,0 +1,2337 @@ +/*! + * Font Awesome 4.7.0 by @davegandy - http://fontawesome.io - @fontawesome + * License - http://fontawesome.io/license (Font: SIL OFL 1.1, CSS: MIT License) + */ +/* FONT PATH + * -------------------------- */ +@font-face { + font-family: 'FontAwesome'; + src: url('../fonts/fontawesome-webfont.eot?v=4.7.0'); + src: url('../fonts/fontawesome-webfont.woff?v=4.7.0') format('woff'); + font-weight: normal; + font-style: normal; +} +.fa { + display: inline-block; + font: normal normal normal 14px/1 FontAwesome; + font-size: inherit; + text-rendering: auto; + -webkit-font-smoothing: antialiased; + -moz-osx-font-smoothing: grayscale; +} +/* makes the font 33% larger relative to the icon container */ +.fa-lg { + font-size: 1.33333333em; + line-height: 0.75em; + vertical-align: -15%; +} +.fa-2x { + font-size: 2em; +} +.fa-3x { + font-size: 3em; +} +.fa-4x { + font-size: 4em; +} +.fa-5x { + font-size: 5em; +} +.fa-fw { + width: 1.28571429em; + text-align: center; +} +.fa-ul { + padding-left: 0; + margin-left: 2.14285714em; + list-style-type: none; +} +.fa-ul > li { + position: relative; +} +.fa-li { + position: absolute; + left: -2.14285714em; + width: 2.14285714em; + top: 0.14285714em; + text-align: center; +} +.fa-li.fa-lg { + left: -1.85714286em; +} +.fa-border { + padding: .2em .25em .15em; + border: solid 0.08em #eeeeee; + border-radius: .1em; +} +.fa-pull-left { + float: left; +} +.fa-pull-right { + float: right; +} +.fa.fa-pull-left { + margin-right: .3em; +} +.fa.fa-pull-right { + margin-left: .3em; +} +/* Deprecated as of 4.4.0 */ +.pull-right { + float: right; +} +.pull-left { + float: left; +} +.fa.pull-left { + margin-right: .3em; +} +.fa.pull-right { + margin-left: .3em; +} +.fa-spin { + -webkit-animation: fa-spin 2s infinite linear; + animation: fa-spin 2s infinite linear; +} +.fa-pulse { + -webkit-animation: fa-spin 1s infinite steps(8); + animation: fa-spin 1s infinite steps(8); +} +@-webkit-keyframes fa-spin { + 0% { + -webkit-transform: rotate(0deg); + transform: rotate(0deg); + } + 100% { + -webkit-transform: rotate(359deg); + transform: rotate(359deg); + } +} +@keyframes fa-spin { + 0% { + -webkit-transform: rotate(0deg); + transform: rotate(0deg); + } + 100% { + -webkit-transform: rotate(359deg); + transform: rotate(359deg); + } +} +.fa-rotate-90 { + -ms-filter: "progid:DXImageTransform.Microsoft.BasicImage(rotation=1)"; + -webkit-transform: rotate(90deg); + -ms-transform: rotate(90deg); + transform: rotate(90deg); +} +.fa-rotate-180 { + -ms-filter: "progid:DXImageTransform.Microsoft.BasicImage(rotation=2)"; + -webkit-transform: rotate(180deg); + -ms-transform: rotate(180deg); + transform: rotate(180deg); +} +.fa-rotate-270 { + -ms-filter: "progid:DXImageTransform.Microsoft.BasicImage(rotation=3)"; + -webkit-transform: rotate(270deg); + -ms-transform: rotate(270deg); + transform: rotate(270deg); +} +.fa-flip-horizontal { + -ms-filter: "progid:DXImageTransform.Microsoft.BasicImage(rotation=0, mirror=1)"; + -webkit-transform: scale(-1, 1); + -ms-transform: scale(-1, 1); + transform: scale(-1, 1); +} +.fa-flip-vertical { + -ms-filter: "progid:DXImageTransform.Microsoft.BasicImage(rotation=2, mirror=1)"; + -webkit-transform: scale(1, -1); + -ms-transform: scale(1, -1); + transform: scale(1, -1); +} +:root .fa-rotate-90, +:root .fa-rotate-180, +:root .fa-rotate-270, +:root .fa-flip-horizontal, +:root .fa-flip-vertical { + filter: none; +} +.fa-stack { + position: relative; + display: inline-block; + width: 2em; + height: 2em; + line-height: 2em; + vertical-align: middle; +} +.fa-stack-1x, +.fa-stack-2x { + position: absolute; + left: 0; + width: 100%; + text-align: center; +} +.fa-stack-1x { + line-height: inherit; +} +.fa-stack-2x { + font-size: 2em; +} +.fa-inverse { + color: #ffffff; +} +/* Font Awesome uses the Unicode Private Use Area (PUA) to ensure screen + readers do not read off random characters that represent icons */ +.fa-glass:before { + content: "\f000"; +} +.fa-music:before { + content: "\f001"; +} +.fa-search:before { + content: "\f002"; +} +.fa-envelope-o:before { + content: "\f003"; +} +.fa-heart:before { + content: "\f004"; +} +.fa-star:before { + content: "\f005"; +} +.fa-star-o:before { + content: "\f006"; +} +.fa-user:before { + content: "\f007"; +} +.fa-film:before { + content: "\f008"; +} +.fa-th-large:before { + content: "\f009"; +} +.fa-th:before { + content: "\f00a"; +} +.fa-th-list:before { + content: "\f00b"; +} +.fa-check:before { + content: "\f00c"; +} +.fa-remove:before, +.fa-close:before, +.fa-times:before { + content: "\f00d"; +} +.fa-search-plus:before { + content: "\f00e"; +} +.fa-search-minus:before { + content: "\f010"; +} +.fa-power-off:before { + content: "\f011"; +} +.fa-signal:before { + content: "\f012"; +} +.fa-gear:before, +.fa-cog:before { + content: "\f013"; +} +.fa-trash-o:before { + content: "\f014"; +} +.fa-home:before { + content: "\f015"; +} +.fa-file-o:before { + content: "\f016"; +} +.fa-clock-o:before { + content: "\f017"; +} +.fa-road:before { + content: "\f018"; +} +.fa-download:before { + content: "\f019"; +} +.fa-arrow-circle-o-down:before { + content: "\f01a"; +} +.fa-arrow-circle-o-up:before { + content: "\f01b"; +} +.fa-inbox:before { + content: "\f01c"; +} +.fa-play-circle-o:before { + content: "\f01d"; +} +.fa-rotate-right:before, +.fa-repeat:before { + content: "\f01e"; +} +.fa-refresh:before { + content: "\f021"; +} +.fa-list-alt:before { + content: "\f022"; +} +.fa-lock:before { + content: "\f023"; +} +.fa-flag:before { + content: "\f024"; +} +.fa-headphones:before { + content: "\f025"; +} +.fa-volume-off:before { + content: "\f026"; +} +.fa-volume-down:before { + content: "\f027"; +} +.fa-volume-up:before { + content: "\f028"; +} +.fa-qrcode:before { + content: "\f029"; +} +.fa-barcode:before { + content: "\f02a"; +} +.fa-tag:before { + content: "\f02b"; +} +.fa-tags:before { + content: "\f02c"; +} +.fa-book:before { + content: "\f02d"; +} +.fa-bookmark:before { + content: "\f02e"; +} +.fa-print:before { + content: "\f02f"; +} +.fa-camera:before { + content: "\f030"; +} +.fa-font:before { + content: "\f031"; +} +.fa-bold:before { + content: "\f032"; +} +.fa-italic:before { + content: "\f033"; +} +.fa-text-height:before { + content: "\f034"; +} +.fa-text-width:before { + content: "\f035"; +} +.fa-align-left:before { + content: "\f036"; +} +.fa-align-center:before { + content: "\f037"; +} +.fa-align-right:before { + content: "\f038"; +} +.fa-align-justify:before { + content: "\f039"; +} +.fa-list:before { + content: "\f03a"; +} +.fa-dedent:before, +.fa-outdent:before { + content: "\f03b"; +} +.fa-indent:before { + content: "\f03c"; +} +.fa-video-camera:before { + content: "\f03d"; +} +.fa-photo:before, +.fa-image:before, +.fa-picture-o:before { + content: "\f03e"; +} +.fa-pencil:before { + content: "\f040"; +} +.fa-map-marker:before { + content: "\f041"; +} +.fa-adjust:before { + content: "\f042"; +} +.fa-tint:before { + content: "\f043"; +} +.fa-edit:before, +.fa-pencil-square-o:before { + content: "\f044"; +} +.fa-share-square-o:before { + content: "\f045"; +} +.fa-check-square-o:before { + content: "\f046"; +} +.fa-arrows:before { + content: "\f047"; +} +.fa-step-backward:before { + content: "\f048"; +} +.fa-fast-backward:before { + content: "\f049"; +} +.fa-backward:before { + content: "\f04a"; +} +.fa-play:before { + content: "\f04b"; +} +.fa-pause:before { + content: "\f04c"; +} +.fa-stop:before { + content: "\f04d"; +} +.fa-forward:before { + content: "\f04e"; +} +.fa-fast-forward:before { + content: "\f050"; +} +.fa-step-forward:before { + content: "\f051"; +} +.fa-eject:before { + content: "\f052"; +} +.fa-chevron-left:before { + content: "\f053"; +} +.fa-chevron-right:before { + content: "\f054"; +} +.fa-plus-circle:before { + content: "\f055"; +} +.fa-minus-circle:before { + content: "\f056"; +} +.fa-times-circle:before { + content: "\f057"; +} +.fa-check-circle:before { + content: "\f058"; +} +.fa-question-circle:before { + content: "\f059"; +} +.fa-info-circle:before { + content: "\f05a"; +} +.fa-crosshairs:before { + content: "\f05b"; +} +.fa-times-circle-o:before { + content: "\f05c"; +} +.fa-check-circle-o:before { + content: "\f05d"; +} +.fa-ban:before { + content: "\f05e"; +} +.fa-arrow-left:before { + content: "\f060"; +} +.fa-arrow-right:before { + content: "\f061"; +} +.fa-arrow-up:before { + content: "\f062"; +} +.fa-arrow-down:before { + content: "\f063"; +} +.fa-mail-forward:before, +.fa-share:before { + content: "\f064"; +} +.fa-expand:before { + content: "\f065"; +} +.fa-compress:before { + content: "\f066"; +} +.fa-plus:before { + content: "\f067"; +} +.fa-minus:before { + content: "\f068"; +} +.fa-asterisk:before { + content: "\f069"; +} +.fa-exclamation-circle:before { + content: "\f06a"; +} +.fa-gift:before { + content: "\f06b"; +} +.fa-leaf:before { + content: "\f06c"; +} +.fa-fire:before { + content: "\f06d"; +} +.fa-eye:before { + content: "\f06e"; +} +.fa-eye-slash:before { + content: "\f070"; +} +.fa-warning:before, +.fa-exclamation-triangle:before { + content: "\f071"; +} +.fa-plane:before { + content: "\f072"; +} +.fa-calendar:before { + content: "\f073"; +} +.fa-random:before { + content: "\f074"; +} +.fa-comment:before { + content: "\f075"; +} +.fa-magnet:before { + content: "\f076"; +} +.fa-chevron-up:before { + content: "\f077"; +} +.fa-chevron-down:before { + content: "\f078"; +} +.fa-retweet:before { + content: "\f079"; +} +.fa-shopping-cart:before { + content: "\f07a"; +} +.fa-folder:before { + content: "\f07b"; +} +.fa-folder-open:before { + content: "\f07c"; +} +.fa-arrows-v:before { + content: "\f07d"; +} +.fa-arrows-h:before { + content: "\f07e"; +} +.fa-bar-chart-o:before, +.fa-bar-chart:before { + content: "\f080"; +} +.fa-twitter-square:before { + content: "\f081"; +} +.fa-facebook-square:before { + content: "\f082"; +} +.fa-camera-retro:before { + content: "\f083"; +} +.fa-key:before { + content: "\f084"; +} +.fa-gears:before, +.fa-cogs:before { + content: "\f085"; +} +.fa-comments:before { + content: "\f086"; +} +.fa-thumbs-o-up:before { + content: "\f087"; +} +.fa-thumbs-o-down:before { + content: "\f088"; +} +.fa-star-half:before { + content: "\f089"; +} +.fa-heart-o:before { + content: "\f08a"; +} +.fa-sign-out:before { + content: "\f08b"; +} +.fa-linkedin-square:before { + content: "\f08c"; +} +.fa-thumb-tack:before { + content: "\f08d"; +} +.fa-external-link:before { + content: "\f08e"; +} +.fa-sign-in:before { + content: "\f090"; +} +.fa-trophy:before { + content: "\f091"; +} +.fa-github-square:before { + content: "\f092"; +} +.fa-upload:before { + content: "\f093"; +} +.fa-lemon-o:before { + content: "\f094"; +} +.fa-phone:before { + content: "\f095"; +} +.fa-square-o:before { + content: "\f096"; +} +.fa-bookmark-o:before { + content: "\f097"; +} +.fa-phone-square:before { + content: "\f098"; +} +.fa-twitter:before { + content: "\f099"; +} +.fa-facebook-f:before, +.fa-facebook:before { + content: "\f09a"; +} +.fa-github:before { + content: "\f09b"; +} +.fa-unlock:before { + content: "\f09c"; +} +.fa-credit-card:before { + content: "\f09d"; +} +.fa-feed:before, +.fa-rss:before { + content: "\f09e"; +} +.fa-hdd-o:before { + content: "\f0a0"; +} +.fa-bullhorn:before { + content: "\f0a1"; +} +.fa-bell:before { + content: "\f0f3"; +} +.fa-certificate:before { + content: "\f0a3"; +} +.fa-hand-o-right:before { + content: "\f0a4"; +} +.fa-hand-o-left:before { + content: "\f0a5"; +} +.fa-hand-o-up:before { + content: "\f0a6"; +} +.fa-hand-o-down:before { + content: "\f0a7"; +} +.fa-arrow-circle-left:before { + content: "\f0a8"; +} +.fa-arrow-circle-right:before { + content: "\f0a9"; +} +.fa-arrow-circle-up:before { + content: "\f0aa"; +} +.fa-arrow-circle-down:before { + content: "\f0ab"; +} +.fa-globe:before { + content: "\f0ac"; +} +.fa-wrench:before { + content: "\f0ad"; +} +.fa-tasks:before { + content: "\f0ae"; +} +.fa-filter:before { + content: "\f0b0"; +} +.fa-briefcase:before { + content: "\f0b1"; +} +.fa-arrows-alt:before { + content: "\f0b2"; +} +.fa-group:before, +.fa-users:before { + content: "\f0c0"; +} +.fa-chain:before, +.fa-link:before { + content: "\f0c1"; +} +.fa-cloud:before { + content: "\f0c2"; +} +.fa-flask:before { + content: "\f0c3"; +} +.fa-cut:before, +.fa-scissors:before { + content: "\f0c4"; +} +.fa-copy:before, +.fa-files-o:before { + content: "\f0c5"; +} +.fa-paperclip:before { + content: "\f0c6"; +} +.fa-save:before, +.fa-floppy-o:before { + content: "\f0c7"; +} +.fa-square:before { + content: "\f0c8"; +} +.fa-navicon:before, +.fa-reorder:before, +.fa-bars:before { + content: "\f0c9"; +} +.fa-list-ul:before { + content: "\f0ca"; +} +.fa-list-ol:before { + content: "\f0cb"; +} +.fa-strikethrough:before { + content: "\f0cc"; +} +.fa-underline:before { + content: "\f0cd"; +} +.fa-table:before { + content: "\f0ce"; +} +.fa-magic:before { + content: "\f0d0"; +} +.fa-truck:before { + content: "\f0d1"; +} +.fa-pinterest:before { + content: "\f0d2"; +} +.fa-pinterest-square:before { + content: "\f0d3"; +} +.fa-google-plus-square:before { + content: "\f0d4"; +} +.fa-google-plus:before { + content: "\f0d5"; +} +.fa-money:before { + content: "\f0d6"; +} +.fa-caret-down:before { + content: "\f0d7"; +} +.fa-caret-up:before { + content: "\f0d8"; +} +.fa-caret-left:before { + content: "\f0d9"; +} +.fa-caret-right:before { + content: "\f0da"; +} +.fa-columns:before { + content: "\f0db"; +} +.fa-unsorted:before, +.fa-sort:before { + content: "\f0dc"; +} +.fa-sort-down:before, +.fa-sort-desc:before { + content: "\f0dd"; +} +.fa-sort-up:before, +.fa-sort-asc:before { + content: "\f0de"; +} +.fa-envelope:before { + content: "\f0e0"; +} +.fa-linkedin:before { + content: "\f0e1"; +} +.fa-rotate-left:before, +.fa-undo:before { + content: "\f0e2"; +} +.fa-legal:before, +.fa-gavel:before { + content: "\f0e3"; +} +.fa-dashboard:before, +.fa-tachometer:before { + content: "\f0e4"; +} +.fa-comment-o:before { + content: "\f0e5"; +} +.fa-comments-o:before { + content: "\f0e6"; +} +.fa-flash:before, +.fa-bolt:before { + content: "\f0e7"; +} +.fa-sitemap:before { + content: "\f0e8"; +} +.fa-umbrella:before { + content: "\f0e9"; +} +.fa-paste:before, +.fa-clipboard:before { + content: "\f0ea"; +} +.fa-lightbulb-o:before { + content: "\f0eb"; +} +.fa-exchange:before { + content: "\f0ec"; +} +.fa-cloud-download:before { + content: "\f0ed"; +} +.fa-cloud-upload:before { + content: "\f0ee"; +} +.fa-user-md:before { + content: "\f0f0"; +} +.fa-stethoscope:before { + content: "\f0f1"; +} +.fa-suitcase:before { + content: "\f0f2"; +} +.fa-bell-o:before { + content: "\f0a2"; +} +.fa-coffee:before { + content: "\f0f4"; +} +.fa-cutlery:before { + content: "\f0f5"; +} +.fa-file-text-o:before { + content: "\f0f6"; +} +.fa-building-o:before { + content: "\f0f7"; +} +.fa-hospital-o:before { + content: "\f0f8"; +} +.fa-ambulance:before { + content: "\f0f9"; +} +.fa-medkit:before { + content: "\f0fa"; +} +.fa-fighter-jet:before { + content: "\f0fb"; +} +.fa-beer:before { + content: "\f0fc"; +} +.fa-h-square:before { + content: "\f0fd"; +} +.fa-plus-square:before { + content: "\f0fe"; +} +.fa-angle-double-left:before { + content: "\f100"; +} +.fa-angle-double-right:before { + content: "\f101"; +} +.fa-angle-double-up:before { + content: "\f102"; +} +.fa-angle-double-down:before { + content: "\f103"; +} +.fa-angle-left:before { + content: "\f104"; +} +.fa-angle-right:before { + content: "\f105"; +} +.fa-angle-up:before { + content: "\f106"; +} +.fa-angle-down:before { + content: "\f107"; +} +.fa-desktop:before { + content: "\f108"; +} +.fa-laptop:before { + content: "\f109"; +} +.fa-tablet:before { + content: "\f10a"; +} +.fa-mobile-phone:before, +.fa-mobile:before { + content: "\f10b"; +} +.fa-circle-o:before { + content: "\f10c"; +} +.fa-quote-left:before { + content: "\f10d"; +} +.fa-quote-right:before { + content: "\f10e"; +} +.fa-spinner:before { + content: "\f110"; +} +.fa-circle:before { + content: "\f111"; +} +.fa-mail-reply:before, +.fa-reply:before { + content: "\f112"; +} +.fa-github-alt:before { + content: "\f113"; +} +.fa-folder-o:before { + content: "\f114"; +} +.fa-folder-open-o:before { + content: "\f115"; +} +.fa-smile-o:before { + content: "\f118"; +} +.fa-frown-o:before { + content: "\f119"; +} +.fa-meh-o:before { + content: "\f11a"; +} +.fa-gamepad:before { + content: "\f11b"; +} +.fa-keyboard-o:before { + content: "\f11c"; +} +.fa-flag-o:before { + content: "\f11d"; +} +.fa-flag-checkered:before { + content: "\f11e"; +} +.fa-terminal:before { + content: "\f120"; +} +.fa-code:before { + content: "\f121"; +} +.fa-mail-reply-all:before, +.fa-reply-all:before { + content: "\f122"; +} +.fa-star-half-empty:before, +.fa-star-half-full:before, +.fa-star-half-o:before { + content: "\f123"; +} +.fa-location-arrow:before { + content: "\f124"; +} +.fa-crop:before { + content: "\f125"; +} +.fa-code-fork:before { + content: "\f126"; +} +.fa-unlink:before, +.fa-chain-broken:before { + content: "\f127"; +} +.fa-question:before { + content: "\f128"; +} +.fa-info:before { + content: "\f129"; +} +.fa-exclamation:before { + content: "\f12a"; +} +.fa-superscript:before { + content: "\f12b"; +} +.fa-subscript:before { + content: "\f12c"; +} +.fa-eraser:before { + content: "\f12d"; +} +.fa-puzzle-piece:before { + content: "\f12e"; +} +.fa-microphone:before { + content: "\f130"; +} +.fa-microphone-slash:before { + content: "\f131"; +} +.fa-shield:before { + content: "\f132"; +} +.fa-calendar-o:before { + content: "\f133"; +} +.fa-fire-extinguisher:before { + content: "\f134"; +} +.fa-rocket:before { + content: "\f135"; +} +.fa-maxcdn:before { + content: "\f136"; +} +.fa-chevron-circle-left:before { + content: "\f137"; +} +.fa-chevron-circle-right:before { + content: "\f138"; +} +.fa-chevron-circle-up:before { + content: "\f139"; +} +.fa-chevron-circle-down:before { + content: "\f13a"; +} +.fa-html5:before { + content: "\f13b"; +} +.fa-css3:before { + content: "\f13c"; +} +.fa-anchor:before { + content: "\f13d"; +} +.fa-unlock-alt:before { + content: "\f13e"; +} +.fa-bullseye:before { + content: "\f140"; +} +.fa-ellipsis-h:before { + content: "\f141"; +} +.fa-ellipsis-v:before { + content: "\f142"; +} +.fa-rss-square:before { + content: "\f143"; +} +.fa-play-circle:before { + content: "\f144"; +} +.fa-ticket:before { + content: "\f145"; +} +.fa-minus-square:before { + content: "\f146"; +} +.fa-minus-square-o:before { + content: "\f147"; +} +.fa-level-up:before { + content: "\f148"; +} +.fa-level-down:before { + content: "\f149"; +} +.fa-check-square:before { + content: "\f14a"; +} +.fa-pencil-square:before { + content: "\f14b"; +} +.fa-external-link-square:before { + content: "\f14c"; +} +.fa-share-square:before { + content: "\f14d"; +} +.fa-compass:before { + content: "\f14e"; +} +.fa-toggle-down:before, +.fa-caret-square-o-down:before { + content: "\f150"; +} +.fa-toggle-up:before, +.fa-caret-square-o-up:before { + content: "\f151"; +} +.fa-toggle-right:before, +.fa-caret-square-o-right:before { + content: "\f152"; +} +.fa-euro:before, +.fa-eur:before { + content: "\f153"; +} +.fa-gbp:before { + content: "\f154"; +} +.fa-dollar:before, +.fa-usd:before { + content: "\f155"; +} +.fa-rupee:before, +.fa-inr:before { + content: "\f156"; +} +.fa-cny:before, +.fa-rmb:before, +.fa-yen:before, +.fa-jpy:before { + content: "\f157"; +} +.fa-ruble:before, +.fa-rouble:before, +.fa-rub:before { + content: "\f158"; +} +.fa-won:before, +.fa-krw:before { + content: "\f159"; +} +.fa-bitcoin:before, +.fa-btc:before { + content: "\f15a"; +} +.fa-file:before { + content: "\f15b"; +} +.fa-file-text:before { + content: "\f15c"; +} +.fa-sort-alpha-asc:before { + content: "\f15d"; +} +.fa-sort-alpha-desc:before { + content: "\f15e"; +} +.fa-sort-amount-asc:before { + content: "\f160"; +} +.fa-sort-amount-desc:before { + content: "\f161"; +} +.fa-sort-numeric-asc:before { + content: "\f162"; +} +.fa-sort-numeric-desc:before { + content: "\f163"; +} +.fa-thumbs-up:before { + content: "\f164"; +} +.fa-thumbs-down:before { + content: "\f165"; +} +.fa-youtube-square:before { + content: "\f166"; +} +.fa-youtube:before { + content: "\f167"; +} +.fa-xing:before { + content: "\f168"; +} +.fa-xing-square:before { + content: "\f169"; +} +.fa-youtube-play:before { + content: "\f16a"; +} +.fa-dropbox:before { + content: "\f16b"; +} +.fa-stack-overflow:before { + content: "\f16c"; +} +.fa-instagram:before { + content: "\f16d"; +} +.fa-flickr:before { + content: "\f16e"; +} +.fa-adn:before { + content: "\f170"; +} +.fa-bitbucket:before { + content: "\f171"; +} +.fa-bitbucket-square:before { + content: "\f172"; +} +.fa-tumblr:before { + content: "\f173"; +} +.fa-tumblr-square:before { + content: "\f174"; +} +.fa-long-arrow-down:before { + content: "\f175"; +} +.fa-long-arrow-up:before { + content: "\f176"; +} +.fa-long-arrow-left:before { + content: "\f177"; +} +.fa-long-arrow-right:before { + content: "\f178"; +} +.fa-apple:before { + content: "\f179"; +} +.fa-windows:before { + content: "\f17a"; +} +.fa-android:before { + content: "\f17b"; +} +.fa-linux:before { + content: "\f17c"; +} +.fa-dribbble:before { + content: "\f17d"; +} +.fa-skype:before { + content: "\f17e"; +} +.fa-foursquare:before { + content: "\f180"; +} +.fa-trello:before { + content: "\f181"; +} +.fa-female:before { + content: "\f182"; +} +.fa-male:before { + content: "\f183"; +} +.fa-gittip:before, +.fa-gratipay:before { + content: "\f184"; +} +.fa-sun-o:before { + content: "\f185"; +} +.fa-moon-o:before { + content: "\f186"; +} +.fa-archive:before { + content: "\f187"; +} +.fa-bug:before { + content: "\f188"; +} +.fa-vk:before { + content: "\f189"; +} +.fa-weibo:before { + content: "\f18a"; +} +.fa-renren:before { + content: "\f18b"; +} +.fa-pagelines:before { + content: "\f18c"; +} +.fa-stack-exchange:before { + content: "\f18d"; +} +.fa-arrow-circle-o-right:before { + content: "\f18e"; +} +.fa-arrow-circle-o-left:before { + content: "\f190"; +} +.fa-toggle-left:before, +.fa-caret-square-o-left:before { + content: "\f191"; +} +.fa-dot-circle-o:before { + content: "\f192"; +} +.fa-wheelchair:before { + content: "\f193"; +} +.fa-vimeo-square:before { + content: "\f194"; +} +.fa-turkish-lira:before, +.fa-try:before { + content: "\f195"; +} +.fa-plus-square-o:before { + content: "\f196"; +} +.fa-space-shuttle:before { + content: "\f197"; +} +.fa-slack:before { + content: "\f198"; +} +.fa-envelope-square:before { + content: "\f199"; +} +.fa-wordpress:before { + content: "\f19a"; +} +.fa-openid:before { + content: "\f19b"; +} +.fa-institution:before, +.fa-bank:before, +.fa-university:before { + content: "\f19c"; +} +.fa-mortar-board:before, +.fa-graduation-cap:before { + content: "\f19d"; +} +.fa-yahoo:before { + content: "\f19e"; +} +.fa-google:before { + content: "\f1a0"; +} +.fa-reddit:before { + content: "\f1a1"; +} +.fa-reddit-square:before { + content: "\f1a2"; +} +.fa-stumbleupon-circle:before { + content: "\f1a3"; +} +.fa-stumbleupon:before { + content: "\f1a4"; +} +.fa-delicious:before { + content: "\f1a5"; +} +.fa-digg:before { + content: "\f1a6"; +} +.fa-pied-piper-pp:before { + content: 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+.fa-copyright:before { + content: "\f1f9"; +} +.fa-at:before { + content: "\f1fa"; +} +.fa-eyedropper:before { + content: "\f1fb"; +} +.fa-paint-brush:before { + content: "\f1fc"; +} +.fa-birthday-cake:before { + content: "\f1fd"; +} +.fa-area-chart:before { + content: "\f1fe"; +} +.fa-pie-chart:before { + content: "\f200"; +} +.fa-line-chart:before { + content: "\f201"; +} +.fa-lastfm:before { + content: "\f202"; +} +.fa-lastfm-square:before { + content: "\f203"; +} +.fa-toggle-off:before { + content: "\f204"; +} +.fa-toggle-on:before { + content: "\f205"; +} +.fa-bicycle:before { + content: "\f206"; +} +.fa-bus:before { + content: "\f207"; +} +.fa-ioxhost:before { + content: "\f208"; +} +.fa-angellist:before { + content: "\f209"; +} +.fa-cc:before { + content: "\f20a"; +} +.fa-shekel:before, +.fa-sheqel:before, +.fa-ils:before { + content: "\f20b"; +} +.fa-meanpath:before { + content: "\f20c"; +} +.fa-buysellads:before { + content: "\f20d"; +} +.fa-connectdevelop:before { + content: "\f20e"; +} +.fa-dashcube:before { + content: "\f210"; +} +.fa-forumbee:before { + content: "\f211"; +} +.fa-leanpub:before { + content: "\f212"; +} +.fa-sellsy:before { + content: "\f213"; +} +.fa-shirtsinbulk:before { + content: "\f214"; +} +.fa-simplybuilt:before { + content: "\f215"; +} +.fa-skyatlas:before { + content: "\f216"; +} +.fa-cart-plus:before { + content: "\f217"; +} +.fa-cart-arrow-down:before { + content: "\f218"; +} +.fa-diamond:before { + content: "\f219"; +} +.fa-ship:before { + content: "\f21a"; +} +.fa-user-secret:before { + content: "\f21b"; +} +.fa-motorcycle:before { + content: "\f21c"; +} +.fa-street-view:before { + content: "\f21d"; +} +.fa-heartbeat:before { + content: "\f21e"; +} +.fa-venus:before { + content: "\f221"; +} +.fa-mars:before { + content: "\f222"; +} +.fa-mercury:before { + content: "\f223"; +} +.fa-intersex:before, +.fa-transgender:before { + content: "\f224"; +} +.fa-transgender-alt:before { + content: "\f225"; +} +.fa-venus-double:before { + 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ntent:"\f065"}.fa-compress:before{content:"\f066"}.fa-plus:before{content:"\f067"}.fa-minus:before{content:"\f068"}.fa-asterisk:before{content:"\f069"}.fa-exclamation-circle:before{content:"\f06a"}.fa-gift:before{content:"\f06b"}.fa-leaf:before{content:"\f06c"}.fa-fire:before{content:"\f06d"}.fa-eye:before{content:"\f06e"}.fa-eye-slash:before{content:"\f070"}.fa-warning:before,.fa-exclamation-triangle:before{content:"\f071"}.fa-plane:before{content:"\f072"}.fa-calendar:before{content:"\f073"}.fa-random:before{content:"\f074"}.fa-comment:before{content:"\f075"}.fa-magnet:before{content:"\f076"}.fa-chevron-up:before{content:"\f077"}.fa-chevron-down:before{content:"\f078"}.fa-retweet:before{content:"\f079"}.fa-shopping-cart:before{content:"\f07a"}.fa-folder:before{content:"\f07b"}.fa-folder-open:before{content:"\f07c"}.fa-arrows-v:before{content:"\f07d"}.fa-arrows-h:before{content:"\f07e"}.fa-bar-chart-o:before{content:"\f080"}.fa-twitter-square:before{content:"\f081"}.fa-facebook-square:before{content:"\f082"}.fa-camera-retro:before{content:"\f083"}.fa-key:before{content:"\f084"}.fa-gears:before,.fa-cogs:before{content:"\f085"}.fa-comments:before{content:"\f086"}.fa-thumbs-o-up:before{content:"\f087"}.fa-thumbs-o-down:before{content:"\f088"}.fa-star-half:before{content:"\f089"}.fa-heart-o:before{content:"\f08a"}.fa-sign-out:before{content:"\f08b"}.fa-linkedin-square:before{content:"\f08c"}.fa-thumb-tack:before{content:"\f08d"}.fa-external-link:before{content:"\f08e"}.fa-sign-in:before{content:"\f090"}.fa-trophy:before{content:"\f091"}.fa-github-square:before{content:"\f092"}.fa-upload:before{content:"\f093"}.fa-lemon-o:before{content:"\f094"}.fa-phone:before{content:"\f095"}.fa-square-o:before{content:"\f096"}.fa-bookmark-o:before{content:"\f097"}.fa-phone-square:before{content:"\f098"}.fa-twitter:before{content:"\f099"}.fa-facebook:before{content:"\f09a"}.fa-github:before{content:"\f09b"}.fa-unlock:before{content:"\f09c"}.fa-credit-card:before{content:"\f09d"}.fa-rss:before{content:"\f09e"}.fa-hdd-o:before{content:"\f0a0"}.fa-bullhorn:before{content:"\f0a1"}.fa-bell:before{content:"\f0f3"}.fa-certificate:before{content:"\f0a3"}.fa-hand-o-right:before{content:"\f0a4"}.fa-hand-o-left:before{content:"\f0a5"}.fa-hand-o-up:before{content:"\f0a6"}.fa-hand-o-down:before{content:"\f0a7"}.fa-arrow-circle-left:before{content:"\f0a8"}.fa-arrow-circle-right:before{content:"\f0a9"}.fa-arrow-circle-up:before{content:"\f0aa"}.fa-arrow-circle-down:before{content:"\f0ab"}.fa-globe:before{content:"\f0ac"}.fa-wrench:before{content:"\f0ad"}.fa-tasks:before{content:"\f0ae"}.fa-filter:before{content:"\f0b0"}.fa-briefcase:before{content:"\f0b1"}.fa-arrows-alt:before{content:"\f0b2"}.fa-group:before,.fa-users:before{content:"\f0c0"}.fa-chain:before,.fa-link:before{content:"\f0c1"}.fa-cloud:before{content:"\f0c2"}.fa-flask:before{content:"\f0c3"}.fa-cut:before,.fa-scissors:before{content:"\f0c4"}.fa-copy:before,.fa-files-o:before{content:"\f0c5"}.fa-paperclip:before{content:"\f0c6"}.fa-save:before,.fa-floppy-o:before{content:"\f0c7"}.fa-square:before{content:"\f0c8"}.fa-bars:before{content:"\f0c9"}.fa-list-ul:before{content:"\f0ca"}.fa-list-ol:before{content:"\f0cb"}.fa-strikethrough:before{content:"\f0cc"}.fa-underline:before{content:"\f0cd"}.fa-table:before{content:"\f0ce"}.fa-magic:before{content:"\f0d0"}.fa-truck:before{content:"\f0d1"}.fa-pinterest:before{content:"\f0d2"}.fa-pinterest-square:before{content:"\f0d3"}.fa-google-plus-square:before{content:"\f0d4"}.fa-google-plus:before{content:"\f0d5"}.fa-money:before{content:"\f0d6"}.fa-caret-down:before{content:"\f0d7"}.fa-caret-up:before{content:"\f0d8"}.fa-caret-left:before{content:"\f0d9"}.fa-caret-right:before{content:"\f0da"}.fa-columns:before{content:"\f0db"}.fa-unsorted:before,.fa-sort:before{content:"\f0dc"}.fa-sort-down:before,.fa-sort-asc:before{content:"\f0dd"}.fa-sort-up:before,.fa-sort-desc:before{content:"\f0de"}.fa-envelope:before{content:"\f0e0"}.fa-linkedin:before{content:"\f0e1"}.fa-rotate-left:before,.fa-undo:before{content:"\f0e2"}.fa-legal:before,.fa-gavel:before{content:"\f0e3"}.fa-dashboard:before,.fa-tachometer:before{content:"\f0e4"}.fa-comment-o:before{content:"\f0e5"}.fa-comments-o:before{content:"\f0e6"}.fa-flash:before,.fa-bolt:before{content:"\f0e7"}.fa-sitemap:before{content:"\f0e8"}.fa-umbrella:before{content:"\f0e9"}.fa-paste:before,.fa-clipboard:before{content:"\f0ea"}.fa-lightbulb-o:before{content:"\f0eb"}.fa-exchange:before{content:"\f0ec"}.fa-cloud-download:before{content:"\f0ed"}.fa-cloud-upload:before{content:"\f0ee"}.fa-user-md:before{content:"\f0f0"}.fa-stethoscope:before{content:"\f0f1"}.fa-suitcase:before{content:"\f0f2"}.fa-bell-o:before{content:"\f0a2"}.fa-coffee:before{content:"\f0f4"}.fa-cutlery:before{content:"\f0f5"}.fa-file-text-o:before{content:"\f0f6"}.fa-building-o:before{content:"\f0f7"}.fa-hospital-o:before{content:"\f0f8"}.fa-ambulance:before{content:"\f0f9"}.fa-medkit:before{content:"\f0fa"}.fa-fighter-jet:before{content:"\f0fb"}.fa-beer:before{content:"\f0fc"}.fa-h-square:before{content:"\f0fd"}.fa-plus-square:before{content:"\f0fe"}.fa-angle-double-left:before{content:"\f100"}.fa-angle-double-right:before{content:"\f101"}.fa-angle-double-up:before{content:"\f102"}.fa-angle-double-down:before{content:"\f103"}.fa-angle-left:before{content:"\f104"}.fa-angle-right:before{content:"\f105"}.fa-angle-up:before{content:"\f106"}.fa-angle-down:before{content:"\f107"}.fa-desktop:before{content:"\f108"}.fa-laptop:before{content:"\f109"}.fa-tablet:before{content:"\f10a"}.fa-mobile-phone:before,.fa-mobile:before{content:"\f10b"}.fa-circle-o:before{content:"\f10c"}.fa-quote-left:before{content:"\f10d"}.fa-quote-right:before{content:"\f10e"}.fa-spinner:before{content:"\f110"}.fa-circle:before{content:"\f111"}.fa-mail-reply:before,.fa-reply:before{content:"\f112"}.fa-github-alt:before{content:"\f113"}.fa-folder-o:before{content:"\f114"}.fa-folder-open-o:before{content:"\f115"}.fa-smile-o:before{content:"\f118"}.fa-frown-o:before{content:"\f119"}.fa-meh-o:before{content:"\f11a"}.fa-gamepad:before{content:"\f11b"}.fa-keyboard-o:before{content:"\f11c"}.fa-flag-o:before{content:"\f11d"}.fa-flag-checkered:before{content:"\f11e"}.fa-terminal:before{content:"\f120"}.fa-code:before{content:"\f121"}.fa-reply-all:before{content:"\f122"}.fa-mail-reply-all:before{content:"\f122"}.fa-star-half-empty:before,.fa-star-half-full:before,.fa-star-half-o:before{content:"\f123"}.fa-location-arrow:before{content:"\f124"}.fa-crop:before{content:"\f125"}.fa-code-fork:before{content:"\f126"}.fa-unlink:before,.fa-chain-broken:before{content:"\f127"}.fa-question:before{content:"\f128"}.fa-info:before{content:"\f129"}.fa-exclamation:before{content:"\f12a"}.fa-superscript:before{content:"\f12b"}.fa-subscript:before{content:"\f12c"}.fa-eraser:before{content:"\f12d"}.fa-puzzle-piece:before{content:"\f12e"}.fa-microphone:before{content:"\f130"}.fa-microphone-slash:before{content:"\f131"}.fa-shield:before{content:"\f132"}.fa-calendar-o:before{content:"\f133"}.fa-fire-extinguisher:before{content:"\f134"}.fa-rocket:before{content:"\f135"}.fa-maxcdn:before{content:"\f136"}.fa-chevron-circle-left:before{content:"\f137"}.fa-chevron-circle-right:before{content:"\f138"}.fa-chevron-circle-up:before{content:"\f139"}.fa-chevron-circle-down:before{content:"\f13a"}.fa-html5:before{content:"\f13b"}.fa-css3:before{content:"\f13c"}.fa-anchor:before{content:"\f13d"}.fa-unlock-alt:before{content:"\f13e"}.fa-bullseye:before{content:"\f140"}.fa-ellipsis-h:before{content:"\f141"}.fa-ellipsis-v:before{content:"\f142"}.fa-rss-square:before{content:"\f143"}.fa-play-circle:before{content:"\f144"}.fa-ticket:before{content:"\f145"}.fa-minus-square:before{content:"\f146"}.fa-minus-square-o:before{content:"\f147"}.fa-level-up:before{content:"\f148"}.fa-level-down:before{content:"\f149"}.fa-check-square:before{content:"\f14a"}.fa-pencil-square:before{content:"\f14b"}.fa-external-link-square:before{content:"\f14c"}.fa-share-square:before{content:"\f14d"}.fa-compass:before{content:"\f14e"}.fa-toggle-down:before,.fa-caret-square-o-down:before{content:"\f150"}.fa-toggle-up:before,.fa-caret-square-o-up:before{content:"\f151"}.fa-toggle-right:before,.fa-caret-square-o-right:before{content:"\f152"}.fa-euro:before,.fa-eur:before{content:"\f153"}.fa-gbp:before{content:"\f154"}.fa-dollar:before,.fa-usd:before{content:"\f155"}.fa-rupee:before,.fa-inr:before{content:"\f156"}.fa-cny:before,.fa-rmb:before,.fa-yen:before,.fa-jpy:before{content:"\f157"}.fa-ruble:before,.fa-rouble:before,.fa-rub:before{content:"\f158"}.fa-won:before,.fa-krw:before{content:"\f159"}.fa-bitcoin:before,.fa-btc:before{content:"\f15a"}.fa-file:before{content:"\f15b"}.fa-file-text:before{content:"\f15c"}.fa-sort-alpha-asc:before{content:"\f15d"}.fa-sort-alpha-desc:before{content:"\f15e"}.fa-sort-amount-asc:before{content:"\f160"}.fa-sort-amount-desc:before{content:"\f161"}.fa-sort-numeric-asc:before{content:"\f162"}.fa-sort-numeric-desc:before{content:"\f163"}.fa-thumbs-up:before{content:"\f164"}.fa-thumbs-down:before{content:"\f165"}.fa-youtube-square:before{content:"\f166"}.fa-youtube:before{content:"\f167"}.fa-xing:before{content:"\f168"}.fa-xing-square:before{content:"\f169"}.fa-youtube-play:before{content:"\f16a"}.fa-dropbox:before{content:"\f16b"}.fa-stack-overflow:before{content:"\f16c"}.fa-instagram:before{content:"\f16d"}.fa-flickr:before{content:"\f16e"}.fa-adn:before{content:"\f170"}.fa-bitbucket:before{content:"\f171"}.fa-bitbucket-square:before{content:"\f172"}.fa-tumblr:before{content:"\f173"}.fa-tumblr-square:before{content:"\f174"}.fa-long-arrow-down:before{content:"\f175"}.fa-long-arrow-up:before{content:"\f176"}.fa-long-arrow-left:before{content:"\f177"}.fa-long-arrow-right:before{content:"\f178"}.fa-apple:before{content:"\f179"}.fa-windows:before{content:"\f17a"}.fa-android:before{content:"\f17b"}.fa-linux:before{content:"\f17c"}.fa-dribbble:before{content:"\f17d"}.fa-skype:before{content:"\f17e"}.fa-foursquare:before{content:"\f180"}.fa-trello:before{content:"\f181"}.fa-female:before{content:"\f182"}.fa-male:before{content:"\f183"}.fa-gittip:before{content:"\f184"}.fa-sun-o:before{content:"\f185"}.fa-moon-o:before{content:"\f186"}.fa-archive:before{content:"\f187"}.fa-bug:before{content:"\f188"}.fa-vk:before{content:"\f189"}.fa-weibo:before{content:"\f18a"}.fa-renren:before{content:"\f18b"}.fa-pagelines:before{content:"\f18c"}.fa-stack-exchange:before{content:"\f18d"}.fa-arrow-circle-o-right:before{content:"\f18e"}.fa-arrow-circle-o-left:before{content:"\f190"}.fa-toggle-left:before,.fa-caret-square-o-left:before{content:"\f191"}.fa-dot-circle-o:before{content:"\f192"}.fa-wheelchair:before{content:"\f193"}.fa-vimeo-square:before{content:"\f194"}.fa-turkish-lira:before,.fa-try:before{content:"\f195"}.fa-plus-square-o:before{content:"\f196"} diff --git a/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.ttf.orig b/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.ttf.orig new file mode 100644 index 000000000..e89738de5 Binary files /dev/null and b/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.ttf.orig differ diff --git a/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.woff b/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.woff new file mode 100644 index 000000000..400014a4b Binary files /dev/null and b/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.woff differ diff --git a/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.woff.orig b/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.woff.orig new file mode 100644 index 000000000..8c1748aab Binary files /dev/null and b/software/WebServer/webserver/font-awesome/fonts/fontawesome-webfont.woff.orig differ diff --git a/software/WebServer/webserver/index.html b/software/WebServer/webserver/index.html new file mode 100644 index 000000000..50f393787 --- /dev/null +++ b/software/WebServer/webserver/index.html @@ -0,0 +1,166 @@ + + + + + + + + + Dashboard - SharpKey Admin + + + + + + + + + + + + +
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Status

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  1. Status
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Welcome to the SharpKey embedded browser based configuration App which enables keyboard map changes, mouse configuration, Over The Air firmware updates and more.
No help text is available as NVRAM is at a premium, so please read the documentation if you need help.

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WiFi Configuration

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SSID:%SK_APSSID%
Password:%SK_APPWD%
IP (AP):%SK_CURRENTIP%NETMASK:%SK_CURRENTNM%GATEWAY:%SK_CURRENTGW%
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SSID:%SK_CLIENTSSID%
DHCP:Enabled
IP (assigned):%SK_CURRENTIP%NETMASK:%SK_CURRENTNM%GATEWAY:%SK_CURRENTGW%
IP (fixed):%SK_CURRENTIP%NETMASK:%SK_CURRENTNM%GATEWAY:%SK_CURRENTGW%
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Version Information

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+ %SK_PRODNAME% v%SK_PRODVERSION% © P.D. Smart, 2018-22

+ Modules
+ %SK_MODULES% + File Pack
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+ + +
+ +
+ + + + + + + + diff --git a/software/WebServer/webserver/js/140medley.min.js b/software/WebServer/webserver/js/140medley.min.js new file mode 100644 index 000000000..d1495d120 --- /dev/null +++ b/software/WebServer/webserver/js/140medley.min.js @@ -0,0 +1,2 @@ +var t=function(a,b){return function(c,d){return a.replace(/#{([^}]*)}/g,function(a,f){return Function("x","with(x)return "+f).call(c,d||b||{})})}},s=function(a,b){return b?{get:function(c){return a[c]&&b.parse(a[c])},set:function(c,d){a[c]=b.stringify(d)}}:{}}(this.localStorage||{},JSON),p=function(a,b,c,d){c=c||document;d=c[b="on"+b];a=c[b]=function(e){d=d&&d(e=e||c.event);return(a=a&&b(e))?b:d};c=this},m=function(a,b,c){b=document;c=b.createElement("p");c.innerHTML=a;for(a=b.createDocumentFragment();b= +c.firstChild;)a.appendChild(b);return a},$=function(a,b){a=a.match(/^(\W)?(.*)/);return(b||document)["getElement"+(a[1]?a[1]=="#"?"ById":"sByClassName":"sByTagName")](a[2])},j=function(a){for(a=0;a<4;a++)try{return a?new ActiveXObject([,"Msxml2","Msxml3","Microsoft"][a]+".XMLHTTP"):new XMLHttpRequest}catch(b){}}; diff --git a/software/WebServer/webserver/js/bootstrap.min.js.gz b/software/WebServer/webserver/js/bootstrap.min.js.gz new file mode 100644 index 000000000..99c5170f4 Binary files /dev/null and b/software/WebServer/webserver/js/bootstrap.min.js.gz differ diff --git a/software/WebServer/webserver/js/index.js b/software/WebServer/webserver/js/index.js new file mode 100644 index 000000000..778eeab7f --- /dev/null +++ b/software/WebServer/webserver/js/index.js @@ -0,0 +1,66 @@ +function showIPConfig() +{ + if(document.getElementById("wifiCfg0checked")) + { + document.getElementById("wifiCfg0checked").style.display = 'compact'; + document.getElementById("wifiCfg").style.display = 'none'; + + if(document.getElementById("wifiCfg3checked")) + { + document.getElementById("wifiCfg3checked").style.display = 'compact'; + document.getElementById("wifiCfg3").style.display = 'none'; + } else + { + document.getElementById("wifiCfg3checked").style.display = 'none'; + document.getElementById("wifiCfg3").style.display = 'compact'; + } + + if(document.getElementById("wifiCfg1checked")) + { + document.getElementById("wifiCfg1checked").style.display = 'compact'; + } else + { + document.getElementById("wifiCfg1").style.display = 'none'; + } + } else + { + document.getElementById("wifiCfg0").style.display = 'none'; + document.getElementById("wifiCfgchecked").style.display = 'compact'; + } +} + +// Method to enable the correct side-bar menu for the underlying host interface. +function enableIfConfig() +{ + // Disable keymap if no host is connected to the SharpKey. KeyInterface is the base class which exists when + // no host was detected to invoke a host specific sub-class. + if(activeInterface === "KeyInterface ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + } + // Mouse interface active? + else if(activeInterface === "Mouse ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("keyMapAvailable").style.display = 'compact'; + + // Secondary interface available? + if(secondaryInterface == "Mouse ") + { + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("mouseCfgAvailable").style.display = 'none'; + } + } +} + +// On document load, setup the items viewable on the page according to set values. +document.addEventListener("DOMContentLoaded", function setPageDefaults() +{ + showIPConfig(); + enableIfConfig(); +}); diff --git a/software/WebServer/webserver/js/jquery.edittable.js b/software/WebServer/webserver/js/jquery.edittable.js new file mode 100644 index 000000000..4ec702b56 --- /dev/null +++ b/software/WebServer/webserver/js/jquery.edittable.js @@ -0,0 +1,340 @@ +/*! editTable v0.2.0 by Alessandro Benoit */ +(function ($, window, i) { + + 'use strict'; + + $.fn.editTable = function (options) { + + // Settings + var s = $.extend({ + data: [['']], + tableClass: 'inputtable', + jsonData: false, + headerCols: false, + maxRows: 999, + first_row: true, + row_template: false, + field_templates: false, + validate_field: function (col_id, value, col_type, $element) { + return true; + } + }, options), + $el = $(this), + defaultTableContent = '', + $table = $('', { + class: s.tableClass + ((s.first_row) ? ' wh' : ''), + html: defaultTableContent + }), + addRowCallBack = null, + defaultth = '', + colnumber, + rownumber, + reset, + is_validated = true; + + // Increment for IDs + i = i + 1; + + // Build cell + function buildCell(content, type) { + content = (content === 0) ? "0" : (content || ''); + // Custom type + if (type && 'text' !== type){ + var field = s.field_templates[type]; + return ''; + } + // Default + return ''; + } + + // Build row + function buildRow(data, len) { + + var rowcontent = '', b; + + data = data || ''; + + if (!s.row_template) { + // Without row template + for (b = 0; b < (len || data.length); b += 1) { + rowcontent += buildCell(data[b]); + } + } else { + // With row template + for (b = 0; b < s.row_template.length; b += 1) { + // For each field in the row + rowcontent += buildCell(data[b], s.row_template[b]); + } + } + + return $('', { + html: rowcontent + '' + }); + + } + + // Check button status (enable/disabled) + function checkButtons() { + if (colnumber < 2) { + $table.find('.delcol').addClass('disabled'); + } + if (rownumber < 2) { + $table.find('.delrow').addClass('disabled'); + } + if (s.maxRows && rownumber === s.maxRows) { + $table.find('.addrow').addClass('disabled'); + } + } + + // Extension method to change or set the table header. This method should be called before fillTableData. + function setTableHeader(header) { + s.headerCols = header; + } + + // Extension method to change or set the table column types. This method should be called before fillTableData. + function setTableType(types) { + s.row_template = types; + } + + // Fill table with data + function fillTableData(data) { + + var a, crow = Math.min(s.maxRows, data.length); + + // Clear table + $table.html(defaultTableContent); + + // If headers or row_template are set + if (s.headerCols || s.row_template) { + + // Fixed columns + var col = s.headerCols || s.row_template; + + // Table headers + for (a = 0; a < col.length; a += 1) { + var col_title = s.headerCols[a] || ''; + $table.find('thead tr').append(''); + } + $table.find('thead tr').append(''); + + // Table content + for (a = 0; a < crow; a += 1) { + // For each row in data + buildRow(data[a], col.length).appendTo($table.find('tbody')); + } + + } else if ( data[0] ) { + + // Variable columns + for (a = 0; a < data[0].length; a += 1) { + $table.find('thead tr').append(defaultth); + } + + for (a = 0; a < crow; a += 1) { + buildRow(data[a]).appendTo($table.find('tbody')); + } + + } + + // Append missing th + //$table.find('thead tr').append(''); + + // Count rows and columns + colnumber = $table.find('thead th').length - 1; + rownumber = $table.find('tbody tr').length; + + checkButtons(); + } + + // Export data + function exportData() { + var row = 0, data = [], value; + + is_validated = true; + + $table.find('tbody tr').each(function () { + + row += 1; + data[row] = []; + + $(this).find('td:not(:last-child)').each(function (i, v) { + if ( s.row_template && 'text' !== s.row_template[i] ){ + var field = s.field_templates[s.row_template[i]], + el = $(this).find($(field.html).prop('tagName')); + + value = field.getValue(el); + if ( !s.validate_field(i, value, s.row_template[i], el) ){ + is_validated = false; + } + data[row].push(value); + } else { + value = $(this).find('input[type="text"]').val(); + if ( !s.validate_field(i, value, 'text', v) ){ + is_validated = false; + } + data[row].push(value); + } + }); + + }); + + // Remove undefined + data.splice(0, 1); + + return data; + } + + // Fill the table with data from textarea or given properties + if ($el.is('textarea')) { + + try { + reset = JSON.parse($el.val()); + } catch (e) { + reset = s.data; + } + + $el.after($table); + + // If inside a form set the textarea content on submit + if ($table.parents('form').length > 0) { + $table.parents('form').submit(function () { + $el.val(JSON.stringify(exportData())); + }); + } + + } else { + reset = (JSON.parse(s.jsonData) || s.data); + $el.append($table); + } + + fillTableData(reset); + + // Add column + $table.on('click', '.addcol', function () { + + var colid = parseInt($(this).closest('tr').children().index($(this).parent('th')), 10); + + colnumber += 1; + + $table.find('thead tr').find('th:eq(' + colid + ')').after(defaultth); + + $table.find('tbody tr').each(function () { + $(this).find('td:eq(' + colid + ')').after(buildCell()); + }); + + $table.find('.delcol').removeClass('disabled'); + + return false; + }); + + // Remove column + $table.on('click', '.delcol', function () { + + if ($(this).hasClass('disabled')) { + return false; + } + + var colid = parseInt($(this).closest('tr').children().index($(this).parent('th')), 10); + + colnumber -= 1; + + checkButtons(); + + $(this).parent('th').remove(); + + $table.find('tbody tr').each(function () { + $(this).find('td:eq(' + colid + ')').remove(); + }); + + return false; + }); + + // Add row + $table.on('click', '.addrow', function () { + + if ($(this).hasClass('disabled')) { + return false; + } + + rownumber += 1; + + $(this).closest('tr').after(buildRow(0, colnumber)); + + $table.find('.delrow').removeClass('disabled'); + + checkButtons(); + + // Addition, raise callback after row has been added. + if(addRowCallBack) + { + addRowCallBack(rownumber, $(this).closest('tr').next('tr'), $table); + } + + return false; + }); + + // Delete row + $table.on('click', '.delrow', function () { + + if ($(this).hasClass('disabled')) { + return false; + } + + rownumber -= 1; + + checkButtons(); + + $(this).closest('tr').remove(); + + $table.find('.addrow').removeClass('disabled'); + + return false; + }); + + // Select all content on click + $table.on('click', 'input', function () { + $(this).select(); + }); + + // Return functions + return { + // Get an array of data + getData: function () { + return exportData(); + }, + // Get the JSON rappresentation of data + getJsonData: function () { + return JSON.stringify(exportData()); + }, + // Load an array of data + loadData: function (data) { + reset = data; + fillTableData(data); + }, + // Load a JSON rappresentation of data + loadJsonData: function (data) { + reset = JSON.parse(data); + fillTableData(JSON.parse(data)); + }, + // Extension method to change or set the table header. This method should be called before fillTableData. + setHeaders: function (headers) { + setTableHeader(headers); + }, + // Extension method to change or set the table column types. This method should be called before fillTableData. + setTypes: function (types) { + setTableType(types); + }, + // Reset data to the first instance + reset: function () { + fillTableData(reset); + }, + isValidated: function () { + return is_validated; + }, + addRowCallBack: function (func) { + addRowCallBack = func; + } + }; + }; + +})(jQuery, this, 0); diff --git a/software/WebServer/webserver/js/jquery.edittable.min.js b/software/WebServer/webserver/js/jquery.edittable.min.js new file mode 100644 index 000000000..c2527ec52 --- /dev/null +++ b/software/WebServer/webserver/js/jquery.edittable.min.js @@ -0,0 +1,2 @@ +/*! editTable v0.2.0 by Alessandro Benoit */ +(function(e,t,n){"use strict";e.fn.editTable=function(t){function p(e,t){e=e===0?"0":e||"";if(t&&"text"!==t){var n=r.field_templates[t];return""}return''}function d(t,n){var i="",s;t=t||"";if(!r.row_template){for(s=0;s<(n||t.length);s+=1){i+=p(t[s])}}else{for(s=0;s",{html:i+''})}function v(){if(f<2){u.find(".delcol").addClass("disabled")}if(l<2){u.find(".delrow").addClass("disabled")}if(r.maxRows&&l===r.maxRows){u.find(".addrow").addClass("disabled")}}function m(e){var t,n=Math.min(r.maxRows,e.length);u.html(o);if(r.headerCols||r.row_template){var i=r.headerCols||r.row_template;for(t=0;t"+s+"")}for(t=0;t");f=u.find("thead th").length-1;l=u.find("tbody tr").length;v()}function g(){var t=0,n=[],i;h=true;u.find("tbody tr").each(function(){t+=1;n[t]=[];e(this).find("td:not(:last-child)").each(function(s,o){if(r.row_template&&"text"!==r.row_template[s]){var u=r.field_templates[r.row_template[s]],a=e(this).find(e(u.html).prop("tagName"));i=u.getValue(a);if(!r.validate_field(s,i,r.row_template[s],a)){h=false}n[t].push(i)}else{i=e(this).find('input[type="text"]').val();if(!r.validate_field(s,i,"text",o)){h=false}n[t].push(i)}})});n.splice(0,1);return n}var r=e.extend({data:[[""]],tableClass:"inputtable",jsonData:false,headerCols:false,maxRows:999,first_row:true,row_template:false,field_templates:false,validate_field:function(e,t,n,r){return true}},t),s=e(this),o="",u=e("
' + field.setValue(field.html, content)[0].outerHTML + '
/ ' + col_title + '"+n.setValue(n.html,e)[0].outerHTML+"+ -
",{"class":r.tableClass+(r.first_row?" wh":""),html:o}),a='',f,l,c,h=true;n=n+1;if(s.is("textarea")){try{c=JSON.parse(s.val())}catch(y){c=r.data}s.after(u);if(u.parents("form").length>0){u.parents("form").submit(function(){s.val(JSON.stringify(g()))})}}else{c=JSON.parse(r.jsonData)||r.data;s.append(u)}m(c);u.on("click",".addcol",function(){var t=parseInt(e(this).closest("tr").children().index(e(this).parent("th")),10);f+=1;u.find("thead tr").find("th:eq("+t+")").after(a);u.find("tbody tr").each(function(){e(this).find("td:eq("+t+")").after(p())});u.find(".delcol").removeClass("disabled");return false});u.on("click",".delcol",function(){if(e(this).hasClass("disabled")){return false}var t=parseInt(e(this).closest("tr").children().index(e(this).parent("th")),10);f-=1;v();e(this).parent("th").remove();u.find("tbody tr").each(function(){e(this).find("td:eq("+t+")").remove()});return false});u.on("click",".addrow",function(){if(e(this).hasClass("disabled")){return false}l+=1;e(this).closest("tr").after(d(0,f));u.find(".delrow").removeClass("disabled");v();return false});u.on("click",".delrow",function(){if(e(this).hasClass("disabled")){return false}l-=1;v();e(this).closest("tr").remove();u.find(".addrow").removeClass("disabled");return false});u.on("click","input",function(){e(this).select()});return{getData:function(){return g()},getJsonData:function(){return JSON.stringify(g())},loadData:function(e){m(e)},loadJsonData:function(e){m(JSON.parse(e))},reset:function(){m(c)},isValidated:function(){return h}}}})(jQuery,this,0) \ No newline at end of file diff --git a/software/WebServer/webserver/js/jquery.min.js.gz b/software/WebServer/webserver/js/jquery.min.js.gz new file mode 100644 index 000000000..ccc6d9369 Binary files /dev/null and b/software/WebServer/webserver/js/jquery.min.js.gz differ diff --git a/software/WebServer/webserver/js/keymap.js b/software/WebServer/webserver/js/keymap.js new file mode 100644 index 000000000..9533428a1 --- /dev/null +++ b/software/WebServer/webserver/js/keymap.js @@ -0,0 +1,653 @@ +// Method to display a message in a message field. The existing html is saved and replaced +// with the new html. After a timeout period the original html is restored. +// +$origMessage = null; +$origId = null; +$msgTimerId = null; +function showMessage(timeout, id, message) +{ + // Is this a new message whilst one is active? + if($origMessage !== null) + { + // Cancel timer and restore original message. + clearTimeout($msgTimerId); + $('#' + $origId).html($origMessage); + } + + // Store original message and Id so that on timer expiry it can be replaced.. + $origMessage = $('#' + id).html(); + $origId = id; + + // Change HTML and set timer to restore it. + $('#' + id).html(message); + $msgTimerId = setTimeout(function(msgFieldId) + { + $('#' + msgFieldId).html($origMessage); + $origMessage = null; + }, timeout, id); +} + +// Ajax download function, from user:leo on stackexchange, customised for this application. +// +function downloadFile() +{ + var req = new XMLHttpRequest(); + var downloadUrl = "/keymap"; + req.open("GET", downloadUrl, true); + req.responseType = "blob"; + + req.onload = function (event) + { + var blob = req.response; + var fileName = null; + var contentType = req.getResponseHeader("content-type"); + + // IE/EDGE seems not returning some response header + if (req.getResponseHeader("content-disposition")) + { + var contentDisposition = req.getResponseHeader("content-disposition"); + fileName = contentDisposition.substring(contentDisposition.indexOf("=")+1); + } else + { + fileName = "unnamed." + contentType.substring(contentType.indexOf("/")+1); + } + + if (window.navigator.msSaveOrOpenBlob) + { + // Internet Explorer + window.navigator.msSaveOrOpenBlob(new Blob([blob], {type: contentType}), fileName); + } else + { + var el = document.getElementById("keymapDownloadLink"); + el.href = window.URL.createObjectURL(blob); + el.download = fileName; + el.click(); + } + }; + showMessage(1000, 'keymapMsg', "

Downloading keymap file, please wait...

"); + req.send(); +} + +// Listener for the Download button click. Once clicked commence download via ajax function. +// +document.getElementById('keymapDownload').onclick = function keymapFileDownload(e) +{ + downloadFile(); +} + + +// Listener for an event change on the INPUT file tag 'keymapUpload'. Once pressed and a filename available, this method +// commences transmission via a POST method to the SharpKey server. +document.getElementById('keymapUpload').onchange = function keymapFileUpload(e) +{ + var fileInput = document.getElementById("keymapUpload").files; + + // Reset the last status. Used to track state change. + lastStatus = 0; + + // Client side checks, no point initiating an upload if the file isnt valid! + if (fileInput.length == 0) + { + alert("No file selected!"); + + // Sane size check, a keymap entry is 6-12 bytes long, so a 1000 rows should be the max size. + } else if (fileInput[0].size > 12*1024) + { + alert("File size must be less than 12KB!"); + } else + { + var xhttp; + if(window.XMLHttpRequest) + { + xhttp = new XMLHttpRequest(); + } else + { + xhttp = new ActiveXObject("Microsoft.XMLHTTP"); + } + + // Install listeners to handle state change. + xhttp.onreadystatechange = function() + { + if (xhttp.readyState == 4) + { + lastStatus = xhttp.status; + if (xhttp.status == 200) + { + showMessage(5000, 'keymapMsg', "

Upload complete. Please press Reboot to activate new key map.

"); + } else if (xhttp.status == 500) + { + showMessage(5000, 'keymapMsg', "

Error: " + xhttp.responseText + " - Press Reboot

"); + } + else if (xhttp.status == 0) + { + showMessage(5000, 'keymapMsg', "

Error: Server closed the connection abrubtly, status unknown! - Please retry or press Reboot

"); + } else + { + showMessage(5000, 'keymapMsg', "

Error: " + xhttp.responseText + " - Press Reboot

"); + } + } + }; + showMessage(10000, 'keymapMsg', "

Uploading keymap file, please wait...

"); + xhttp.open("POST", "/keymap", true); + xhttp.send(fileInput[0]); + } +} + + +// Method to enable the correct side-bar menu for the underlying host interface. +function enableIfConfig() +{ + // Disable keymap if no host is connected to the SharpKey. KeyInterface is the base class which exists when + // no host was detected to invoke a host specific sub-class. + if(activeInterface === "KeyInterface ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + } + // Mouse interface active? + else if(activeInterface === "Mouse ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("keyMapAvailable").style.display = 'compact'; + + // Secondary interface available? + if(secondaryInterface == "Mouse ") + { + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("mouseCfgAvailable").style.display = 'none'; + } + } +} + +// Method to validate a hex input field. Basically call hexConvert and it will return a +// valid number, 0 if invalid or 255 if out of range. +function validateHexInput(event) +{ + event.target.value=hexConvert(event.target.value, false); + return true; +}; + +// Use variables to remember last popover and value as the popover mechanism, probably due to race states, isnt uniform. +// Also use the shown/hidden events and toggle as hide doesnt trigger reliably. +var $currentPopover = null; +var $currentPopoverVal = -1; +var $currentClass = null; +var $currentSelectCount = 0; +var $currentTimerId = null; +var $currentDataSetModified = false; + +function updateButtons() +{ + if($currentSelectCount == 2) + { + $('#keymapSwap').removeAttr('disabled'); + } else + { + $('#keymapSwap').attr('disabled', 'disabled'); + } + if($currentSelectCount > 0) + { + $('#keymapDelete').removeAttr('disabled'); + } else + { + $('#keymapDelete').attr('disabled', 'disabled'); + } + if($currentDataSetModified == true) + { + $('#keymapSave').removeAttr('disabled'); + $('#keymapReload').removeAttr('disabled'); + } else + { + $('#keymapSave').attr('disabled', 'disabled'); + $('#keymapReload').attr('disabled', 'disabled'); + } +} + +function addPopover(field, tableRow) +{ + + // Popover auto-hide timer alarm. + const popoverAlarm = { + + setup: function(timerId, timeout) { + if (timerId != null) { + timerId = this.cancel(timerId); + } + + timerId = setTimeout(function() { + + if($currentPopover) { + $currentPopover.popover('toggle'); + } + }, timeout); + + return(timerId); + }, + + cancel: function(timerId) { + clearTimeout(timerId); + timerId = null; + return(timerId); + }, + }; + + // Setup popover menus on each custom field to aid with conversion of a feature into a hex number. + $(field).popover({ + html: true, + title: function () { + + return $('#popover-' + field.className).find('.head').html(); + }, + content: function () { + return $('#popover-' + field.className).find('.content').html(); + } + }) + .on("show.bs.popover", function(e) + { + var className = this.getAttribute('class'); + var $target = $(e.target); + + // Detect a class change, user has gone from one column to another, need to close out current + // popover ready for initialisation of new. + if($currentClass != null && $currentClass != className) + { + if($currentPopover) + { + if($currentTimerId != 0) + { + $currentTimerId = popoverAlarm.cancel($currentTimerId); + } + + if ($currentPopover && ($currentPopover.get(0) != $target.get(0))) { + $currentPopover.popover('toggle'); + } + $currentPopover = null; + } + } + $currentClass = className; + + if($currentPopover) + { + $currentPopoverVal = 0; + $('#popover-' + field.className).find('input').each( function( index ) { + + if($(this).attr("checked") === "checked") + { + $currentPopoverVal += parseInt(this.getAttribute('data-value'), 10); + } + }); + } else + { + $currentPopoverVal = -1; + } + + // Go through all the checkboxes and setup the initial value. + $('#popover-' + field.className).find('input').each( function( index ) { + if((e.target.value & this.getAttribute('data-value')) == this.getAttribute('data-value')) + { + $(this).attr('checked', true); + } else + { + $(this).attr('checked', false); + } + }); + }) + .on("shown.bs.popover", function(e) + { + var $target = $(e.target); + + if ($currentPopover && ($currentPopover.get(0) != $target.get(0))) { + $currentPopover.popover('toggle'); + } + $currentPopover = $target; + + // Setup an alarm to remove a visible popover if not clicked closed. + $currentTimerId = popoverAlarm.setup($currentTimerId, 5000); + }) + .on("hidden.bs.popover", function(e) + { + var $target = $(e.target); + + if ($currentPopover && ($currentPopover.get(0) == $target.get(0))) { + if($currentPopoverVal == -1) + { + $currentPopoverVal = 0; + $('#popover-' + field.className).find('input').each( function( index ) { + + if($(this).attr("checked") === "checked") + { + $currentPopoverVal += parseInt(this.getAttribute('data-value'), 10); + } + }); + } + + if(e.target.value != hexConvert($currentPopoverVal, false)) + { + e.target.value = hexConvert($currentPopoverVal, false); + $currentDataSetModified = true; + updateButtons(); + } + $currentPopover = null; + // Cancel the alarm on the hidden popover. + $currentTimerId = popoverAlarm.cancel($currentTimerId); + } + $currentPopoverVal = -1; + }) + + .on("hide.bs.popover", function(e) + { + // $currentTimerId = popoverAlarm.cancel($currentTimerId); + }) + .on("click", function(e) + { + console.log('click: ' + e.target.value); + }) + .on("change", function(e) + { + if(e.target.className === 'checkbox') + { + if($(e.target).attr('checked') == 'checked') + { + $currentSelectCount += 1; + //$(e.target).attr("checked", true); + } + else if($(e.target).attr('checked') != 'checked') + { + $currentSelectCount -= 1; + //$(e.target).attr("checked", false); + } + } else + { + if(e.target.value != hexConvert($currentPopoverVal, false)) + { + e.target.value = hexConvert(e.target.value, false); + $currentDataSetModified = true; + } + } + updateButtons(); + }) + + .blur(function () { + }); + // End popover definition + + // Only attach popover handlers to classes in the first row, subsequent rows will use the same popover. + // + if(tableRow == 1) + { + var search = '#popover-' + field.className; + $(search + ' input').each(function () { + + $('body').on('click', '#' + this.id, function(e) { + + $currentTimerId = popoverAlarm.setup($currentTimerId, 5000); + + $(search + ' input').each(function() { + if(this.id === e.target.id) + { + $(this).attr("checked", e.target.checked ? true : false); + } + }); + }); + }); + } +} + +// Method to convert a string/numeric into a hex number and range check it to be within and 8bit unsigned range. +function hexConvert(inVal, invert) +{ + if(isNaN(inVal) == true && isNaN('0x' + inVal) == false) + { + inVal = parseInt(inVal, 16); + } + else if(isNaN(inVal) == false && typeof inVal == 'string' && inVal.length > 0) + { + if(inVal.toUpperCase().indexOf("0X") == 0) + { + inVal = parseInt(inVal, 16); + } else + { + inVal = parseInt(inVal, 10); + } + } + else if(isNaN(inVal) == true || inVal.length == 0) + { + inVal = 0; + } + if(inVal < 0) + { + inVal = 0; + } + else if(inVal > 255) + { + inVal = 255; + } + if(invert == true) + { + inVal = (~inVal) & 0xFF; + } + return('0x' + (inVal).toString(16).toUpperCase()); +} + +// Method to swap 2 tables rows. This is necessary as the keymap table has top down priority in mapping. +function swapKeyMapData() +{ + // Locals. + var firstRow = null; + var secondRow = null; + + // Get row numbers of the rows to be swapped. + var rowcnt = 1; + $('.inputtable tr .checkbox').each(function() { + if(firstRow == null && this.checked == true) + { + firstRow = rowcnt; + } else + if(firstRow != null && secondRow == null && this.checked == true) + { + secondRow = rowcnt; + } + rowcnt++; + }); + + // If rows were matched (should be due to count) then perform swap. + if(firstRow != null && secondRow != null) + { + $('.inputtable > tbody > tr:nth-child(' + firstRow + ')').replaceWith($('.inputtable > tbody > tr:nth-child(' + secondRow + ')').after($('.inputtable > tbody > tr:nth-child(' + firstRow + ')').clone(true))); + } + + // Update the modified state and update button state. + $currentDataSetModified = true; + updateButtons(); + + return true; +} + +// Method to delete 1 or multiple rows. An individual row can be deleted by the +/- buttons but multiple requires selection and then running through the table, deleting the selected rows. +function deleteKeyMapData() +{ + // Locals. + var toDeleteRows = []; + + // Get row numbers of the rows to be swapped. + var rowcnt = 1; + $('.inputtable tr .checkbox').each(function() { + if(this.checked == true) + { + toDeleteRows.push(rowcnt); + } + rowcnt++; + }); + + // Iterate through the array of rows to delete and actually perform the deletion. + // We work in reverse order, ie. deleting the last row first due to the index changing if we delete first to last. + for(var idx = toDeleteRows.length; idx > 0; idx--) + { + $('.inputtable > tbody > tr:nth-child(' + toDeleteRows[idx-1] + ')').remove(); + } + + // Reset the select counter and update button state. + $currentSelectCount = 0; + $currentDataSetModified = true; + updateButtons(); + + return true; +} + +// Method to save the current keymap table data to the interface. +function saveKeyMapData() +{ + var data = keymapTable.getData(); + + // Reset the last status. Used to track state change. + lastStatus = 0; + + // Client side checks, no point initiating an upload if the file isnt valid! + if(data.length == 0) + { + alert("No data to save!!"); + + } else + { + var xhttp; + if(window.XMLHttpRequest) + { + xhttp = new XMLHttpRequest(); + } else + { + xhttp = new ActiveXObject("Microsoft.XMLHTTP"); + } + + // Install listeners to handle state change. + xhttp.onreadystatechange = function() + { + if (xhttp.readyState == 4) + { + lastStatus = xhttp.status; + if (xhttp.status == 200) + { + showMessage(5000, 'keymapEditorMsg', "

Upload complete. Please press Reboot to activate new key map.

"); + + // Reset the data modified flag and update button state. + $currentDataSetModified = false; + updateButtons(); + } else if (xhttp.status == 500) + { + showMessage(5000, 'keymapEditorMsg', "

Error: " + xhttp.responseText + " - Press Reboot

"); + } + else if (xhttp.status == 0) + { + showMessage(5000, 'keymapEditorMsg', "

Error: Server closed the connection abrubtly, status unknown! - Please retry Save

"); + } else + { + showMessage(5000, 'keymapEditorMsg', "

Error: " + xhttp.responseText + " - Press Reboot

"); + } + } + }; + showMessage(5000, 'keymapEditorMsg', "

Uploading keymap data, please wait...

"); + xhttp.open("POST", "/keymap/table", true); + xhttp.send(JSON.stringify(data)); + } + + return true; +} + +// Method to reload the initial table data set. +function reloadKeyMapData() +{ + // Request reload of the initial data. + keymapTable.reset(); + + // Re-install the listeners as the old dataset was deleted. + setupTableListeners(); + + // Complete message. + showMessage(5000, 'keymapEditorMsg', "

Reload complete, data reset to initial values.

"); + + // Reset the select counter and update button state. + $currentSelectCount = 0; + $currentDataSetModified = false; + updateButtons(); + return true; +} + +// Callback function triggered after a row has been added to the edittable. Use the event to add popover listeners to the new fields. +// +function tableRowAdded(row, rowHandle, tableHandle) +{ + $(rowHandle).children().children().each(function() { + if(this.className !== "") + { + addPopover(this, 0); + } + }); +} + +// Method to install listeners on the table data for popover aids. +// +function setupTableListeners() +{ + // Setup a popover on each input field where a modal exists. + $('.inputtable >tbody > tr').each(function (tridx) { + + // We seperate out the Row from the input as we want to watch every input but only setup 1 popover per input type. + $(this).find('input').each(function (inpidx) { + if(this.className !== "") + { + addPopover(this, tridx); + } + }); + }); + // + // Setup a callback on new rows added to table. + keymapTable.addRowCallBack(tableRowAdded); +} + +$(document).ready(function() { + + // Load up the table headers, types and data. This is done with JQuery fetch as it is easier. The SharpKey is synchronous + // but fetch order can vary so we nest the requests to ensure all headers and types are in place before the data. + fetch('/data/keymap/table/headers') + .then((response) => { + return(response.json()); + }) + .then((headers) => { + keymapTable.setHeaders(headers); + + fetch('/data/keymap/table/types') + .then((response) => { + return(response.json()); + }) + .then((types) => { + keymapTable.setTypes(types); + + fetch('/data/keymap/table/data') + .then((response) => { + return(response.json()); + }) + .then((data) => { + keymapTable.loadData(data); + setupTableListeners(); + }); + }); + }); + + // Disable buttons, enabled when user action requires them. + $('#keymapSwap').attr('disabled', 'disabled'); + $('#keymapDelete').attr('disabled', 'disabled'); + $('#keymapSave').attr('disabled', 'disabled'); + $('#keymapReload').attr('disabled', 'disabled'); + + // Add listeners to the buttons. + $('#keymapSwap').on('click', function() { swapKeyMapData(); }); + $('#keymapDelete').on('click', function() { deleteKeyMapData(); }); + $('#keymapSave').on('click', function() { saveKeyMapData(); }); + $('#keymapReload').on('click', function() { reloadKeyMapData(); }); + + // Setup the menu options according to underlying interface. + enableIfConfig(); +}); diff --git a/software/WebServer/webserver/js/mouse.js b/software/WebServer/webserver/js/mouse.js new file mode 100644 index 000000000..8c9536ebe --- /dev/null +++ b/software/WebServer/webserver/js/mouse.js @@ -0,0 +1,141 @@ +// Method to display a message in a message field. The existing html is saved and replaced +// with the new html. After a timeout period the original html is restored. +// +$origMessage = null; +$origId = null; +$msgTimerId = null; +function showMessage(timeout, id, message) +{ + // Is this a new message whilst one is active? + if($origMessage !== null) + { + // Cancel timer and restore original message. + clearTimeout($msgTimerId); + $('#' + $origId).html($origMessage); + } + + // Store original message and Id so that on timer expiry it can be replaced.. + $origMessage = $('#' + id).html(); + $origId = id; + + // Change HTML and set timer to restore it. + $('#' + id).html(message); + $msgTimerId = setTimeout(function(msgFieldId) + { + $('#' + msgFieldId).html($origMessage); + $origMessage = null; + }, timeout, id); +} + +// Method to enable the correct side-bar menu for the underlying host interface. +function enableIfConfig() +{ + // Disable keymap if no host is connected to the SharpKey. KeyInterface is the base class which exists when + // no host was detected to invoke a host specific sub-class. + if(activeInterface === "KeyInterface ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + } + // Mouse interface active? + else if(activeInterface === "Mouse ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("keyMapAvailable").style.display = 'compact'; + + // Secondary interface available? + if(secondaryInterface == "Mouse ") + { + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("mouseCfgAvailable").style.display = 'none'; + } + } +} + +// Method to convert a string/numeric into a hex number and range check it to be within and 8bit unsigned range. +function hexConvert(inVal, invert) +{ + if(isNaN(inVal) == true && isNaN('0x' + inVal) == false) + { + inVal = parseInt(inVal, 16); + } + else if(isNaN(inVal) == false && typeof inVal == 'string' && inVal.length > 0) + { + if(inVal.toUpperCase().indexOf("0X") == 0) + { + inVal = parseInt(inVal, 16); + } else + { + inVal = parseInt(inVal, 10); + } + } + else if(isNaN(inVal) == true || inVal.length == 0) + { + inVal = 0; + } + if(inVal < 0) + { + inVal = 0; + } + else if(inVal > 255) + { + inVal = 255; + } + if(invert == true) + { + inVal = (~inVal) & 0xFF; + } + return('0x' + (inVal).toString(16).toUpperCase()); +} + +$(document).ready(function() { + + // Setup the menu options according to underlying interface. + enableIfConfig(); + + // AJAX code to post in a controlled manner so that we can receive back an error/success message to the commit. + $("#mouseHostCfgSave").submit( function(e) + { + var form = $(this); + var actionUrl = form.attr('action'); + + // Prevent default submit action, we want to manually submit and be able to receive a response for errors/success. + e.preventDefault(); + + $.ajax( + { + type: "POST", + url: actionUrl, + data: form.serialize(), // serializes the form's elements. + success: function(data) + { + // Show the message then revert back to original text. + showMessage(10000, "mouseHostCfgMsg", data); + } + }); + }); + $("#mousePS2CfgSave").submit( function(e) + { + var form = $(this); + var actionUrl = form.attr('action'); + + // Prevent default submit action, we want to manually submit and be able to receive a response for errors/success. + e.preventDefault(); + + $.ajax( + { + type: "POST", + url: actionUrl, + data: form.serialize(), // serializes the form's elements. + success: function(data) + { + // Show the message then revert back to original text. + showMessage(10000, "mousePS2CfgMsg", data); + } + }); + }); +}); diff --git a/software/WebServer/webserver/js/ota.js b/software/WebServer/webserver/js/ota.js new file mode 100644 index 000000000..522fc25fc --- /dev/null +++ b/software/WebServer/webserver/js/ota.js @@ -0,0 +1,300 @@ +var lastStatus = 0; + +// Method to display a message in a message field. The existing html is saved and replaced +// with the new html. After a timeout period the original html is restored. +// +$origMessage = null; +$origId = null; +$msgTimerId = null; +function showMessage(timeout, id, message) +{ + // Is this a new message whilst one is active? + if($origMessage !== null) + { + // Cancel timer and restore original message. + clearTimeout($msgTimerId); + $('#' + $origId).html($origMessage); + } + + // Store original message and Id so that on timer expiry it can be replaced.. + $origMessage = $('#' + id).html(); + $origId = id; + + // Change HTML and set timer to restore it. + $('#' + id).html(message); + $msgTimerId = setTimeout(function(msgFieldId) + { + $('#' + msgFieldId).html($origMessage); + $origMessage = null; + }, timeout, id); +} + +// Clear the file input array. +function clearFileInput(ctrl) +{ + try { + ctrl.value = null; + } catch(ex) { } + if (ctrl.value) { + ctrl.parentNode.replaceChild(ctrl.cloneNode(true), ctrl); + } +} + +// Firmware handlers. +document.getElementById('firmwareUpload').onchange = function getFirmwareFileName(e) +{ + var default_path = document.getElementById("firmwareUpload").files[0].name; + + // Put the name of the file into the table cell. + document.getElementById('firmwareName').innerHTML = "=>" + default_path; + document.getElementById('firmwareUpgrade').value = document.getElementById('firmwareUpload').files[0].name; + + // Disable select and enable upgrade/cancel. + document.getElementById('firmwareUploadLabel').style.display = 'none'; + document.getElementById('firmwareUpgrade').disabled = false; + document.getElementById('firmwareUpgrade').style.display = 'block'; + document.getElementById('firmwareCancel').disabled = false; + document.getElementById('firmwareCancel').style.display = 'block'; + document.getElementById('firmwareMsg').innerHTML = "Press Upgrade to upload and flash the firmware into the SharpKey or Cancel to cancel and re-select file."; +} +document.getElementById('firmwareCancel').onclick = function cancelFirmwareUpload(e) +{ + var default_path = document.getElementById("firmwareUpload").files[0].name; + + // Reset the selected filename. + document.getElementById('firmwareName').innerHTML = ""; + document.getElementById('firmwareUpgrade').value = []; + clearFileInput(document.getElementById('firmwareUpload')); + + // Enable select and disable upgrade/cancel. + document.getElementById('firmwareUploadLabel').style.display = 'block'; + document.getElementById('firmwareUpgrade').disabled = true; + document.getElementById('firmwareUpgrade').style.display = 'none'; + document.getElementById('firmwareCancel').disabled = true; + document.getElementById('firmwareCancel').style.display = 'none'; + document.getElementById('firmwareMsg').innerHTML = "Select a firmware image file with which to upgrade the SharpKey Operating System."; +} + +// Firmware upgrade handler. +function firmwareUpdateProgress(e) +{ + if (e.lengthComputable) + { + var percentage = Math.round((e.loaded/e.total)*100); + document.getElementById('firmwareProgressBar').style.width = percentage + '%'; + } + else + { + document.getElementById('firmwareProgressBar').innerHTML = "Unable to compute progress information since the total size is unknown"; + } +} +document.getElementById('firmwareUpgrade').onclick = function firmwareUpload() +{ + var fileInput = document.getElementById("firmwareUpload").files; + + // Reset the last status. Used to track state change. + lastStatus = 0; + + // Client side checks, no point initiating a firmware update if the file isnt valid! + if (fileInput.length == 0) + { + alert("No file selected!"); + } else if (fileInput[0].size > 1664*1024) + { + alert("File size must be less than 1.6MB!"); + } else + { + document.getElementById("firmwareUpload").disabled = true; + document.getElementById("firmwareUploadLabel").style.display = 'none'; + document.getElementById("firmwareUpgrade").disabled = true; + document.getElementById("firmwareUpgrade").style.display = 'none'; + document.getElementById("firmwareCancel").style.display = 'none'; + document.getElementById("firmwareProgress").style.display = 'block'; + + var xhttp; + if(window.XMLHttpRequest) + { + xhttp = new XMLHttpRequest(); + } else + { + xhttp = new ActiveXObject("Microsoft.XMLHTTP"); + } + + // Install listeners to + xhttp.upload.addEventListener("progress", firmwareUpdateProgress, false); + xhttp.onreadystatechange = function() + { + if (xhttp.readyState == 4) + { + lastStatus = xhttp.status; + if (xhttp.status == 200) + { + document.getElementById('firmwareMsg').innerHTML = "

Transfer complete, firmware successfully flashed onto the SharpKey. Please press Reboot to activate.

"; + document.getElementById("firmwareProgress").style.display = 'none'; + document.getElementById('firmwareName').style.display = 'none'; + } else if (xhttp.status == 500) + { + document.getElementById('firmwareMsg').innerHTML = "

Error: " + xhttp.responseText + " - Press Reboot

"; + } + else if (xhttp.status == 0) + { + document.getElementById('firmwareMsg').innerHTML = "

Error: Server closed the connection abrubtly, flash status unknown! - Press Reboot

"; + } else + { + document.getElementById('firmwareMsg').innerHTML = "

Error: " + xhttp.responseText + " - Press Reboot

"; + } + } + }; + document.getElementById('firmwareMsg').innerHTML = "

Uploading and flashing the new firmware, please wait...

"; + xhttp.open("POST", "/ota/firmware", true); + xhttp.send(fileInput[0]); + } +} + +// Filepack handlers. +document.getElementById('filepackUpload').onchange = function getFilepackFileName(e) +{ + var default_path = document.getElementById("filepackUpload").files[0].name; + + // Put the name of the file into the table cell. + document.getElementById('filepackName').innerHTML = "=>" + default_path; + document.getElementById('filepackUpgrade').value = document.getElementById('filepackUpload').files[0].name; + + // Disable select and enable upgrade/cancel. + document.getElementById('filepackUploadLabel').style.display = 'none'; + document.getElementById('filepackUpgrade').disabled = false; + document.getElementById('filepackUpgrade').style.display = 'block'; + document.getElementById('filepackCancel').disabled = false; + document.getElementById('filepackCancel').style.display = 'block'; + document.getElementById('filepackWarning').style.display = 'block'; + document.getElementById('filepackMsg').innerHTML = "Press Upgrade to upload and flash the filepack onto the SharpKey filesystem or Cancel to cancel and re-select file."; +} +document.getElementById('filepackCancel').onclick = function cancelFilepackUpload(e) +{ + var default_path = document.getElementById("filepackUpload").files[0].name; + + // Reset the selected filename. + document.getElementById('filepackName').innerHTML = ""; + clearFileInput(document.getElementById('filepackUpload')); + + // Enable select and disable upgrade/cancel. + document.getElementById('filepackUploadLabel').style.display = 'block'; + document.getElementById('filepackUpgrade').disabled = true; + document.getElementById('filepackUpgrade').style.display = 'none'; + document.getElementById('filepackCancel').disabled = true; + document.getElementById('filepackCancel').style.display = 'none'; + document.getElementById('filepackWarning').style.display = 'none'; + document.getElementById('filepackMsg').innerHTML = "Select a filepack image file with which to upgrade the SharpKey filesystem."; +} + +// Filepack upgrade handler. +function filepackUpdateProgress(e) +{ + if (e.lengthComputable) + { + var percentage = Math.round((e.loaded/e.total)*100); + document.getElementById('filepackProgressBar').style.width = percentage + '%'; + } + else + { + document.getElementById('filepackProgressBar').innerHTML = "Unable to compute progress information since the total size is unknown"; + } +} +document.getElementById('filepackUpgrade').onclick = function filepackUpload() +{ + var fileInput = document.getElementById("filepackUpload").files; + + // Reset the last status. Used to track state change. + lastStatus = 0; + + // Client side checks, no point initiating a filepack update if the file isnt valid! + if (fileInput.length == 0) + { + alert("No file selected!"); + } else if (fileInput[0].size > 640*1024) + { + alert("File size must be less than 640K!"); + } else + { + document.getElementById("filepackUpload").disabled = true; + document.getElementById("filepackUploadLabel").style.display = 'none'; + document.getElementById("filepackUpgrade").disabled = true; + document.getElementById("filepackUpgrade").style.display = 'none'; + document.getElementById("filepackCancel").style.display = 'none'; + document.getElementById("filepackProgress").style.display = 'block'; + + var xhttp; + if(window.XMLHttpRequest) + { + xhttp = new XMLHttpRequest(); + } else + { + xhttp = new ActiveXObject("Microsoft.XMLHTTP"); + } + + // Install listeners to + xhttp.upload.addEventListener("progress", filepackUpdateProgress, false); + xhttp.onreadystatechange = function() + { + if (xhttp.readyState == 4) + { + lastStatus = xhttp.status; + if (xhttp.status == 200) + { + document.getElementById('filepackMsg').innerHTML = "

Transfer complete, filepack successfully flashed onto SharpKey filesystem. Please press Reboot to activate.

"; + document.getElementById("filepackProgress").style.display = 'none'; + document.getElementById('filepackName').style.display = 'none'; + } else if (xhttp.status == 500) + { + document.getElementById('filepackMsg').innerHTML = "

Error: " + xhttp.responseText + " - Press Reboot

"; + } + else if (xhttp.status == 0) + { + document.getElementById('filepackMsg').innerHTML = "

Error: Server closed the connection abrubtly, flash status unknown! - Press Reboot

"; + } else + { + document.getElementById('filepackMsg').innerHTML = "

Error: " + xhttp.responseText + " - Press Reboot

"; + } + } + }; + document.getElementById('filepackMsg').innerHTML = "

Uploading and flashing the new filepack, please wait...

"; + xhttp.open("POST", "/ota/filepack", true); + xhttp.send(fileInput[0]); + } +} + + +// Method to enable the correct side-bar menu for the underlying host interface. +function enableIfConfig() +{ + // Disable keymap if no host is connected to the SharpKey. KeyInterface is the base class which exists when + // no host was detected to invoke a host specific sub-class. + if(activeInterface === "KeyInterface ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + } + // Mouse interface active? + else if(activeInterface === "Mouse ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("keyMapAvailable").style.display = 'compact'; + + // Secondary interface available? + if(secondaryInterface == "Mouse ") + { + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("mouseCfgAvailable").style.display = 'none'; + } + } +} + +// On document load, setup the items viewable on the page according to set values. +document.addEventListener("DOMContentLoaded", function setPageDefaults() +{ + enableIfConfig(); +}); diff --git a/software/WebServer/webserver/js/wifimanager.js b/software/WebServer/webserver/js/wifimanager.js new file mode 100644 index 000000000..7927ed305 --- /dev/null +++ b/software/WebServer/webserver/js/wifimanager.js @@ -0,0 +1,178 @@ +// Method to display a message in a message field. The existing html is saved and replaced +// with the new html. After a timeout period the original html is restored. +// +$origMessage = null; +$origId = null; +$msgTimerId = null; +function showMessage(timeout, id, message) +{ + // Is this a new message whilst one is active? + if($origMessage !== null) + { + // Cancel timer and restore original message. + clearTimeout($msgTimerId); + $('#' + $origId).html($origMessage); + } + + // Store original message and Id so that on timer expiry it can be replaced.. + $origMessage = $('#' + id).html(); + $origId = id; + + // Change HTML and set timer to restore it. + $('#' + id).html(message); + $msgTimerId = setTimeout(function(msgFieldId) + { + $('#' + msgFieldId).html($origMessage); + $origMessage = null; + }, timeout, id); +} + + +function showWiFiAPInput() +{ + document.getElementById('inputWiFiClient').style.display = 'none'; + document.getElementById('inputWiFiAP').style.display = 'block'; + document.getElementById("errorMsgAP").innerHTML = ""; +} + +function showWiFiClientInput() +{ + document.getElementById('inputWiFiClient').style.display = 'block'; + document.getElementById('inputWiFiAP').style.display = 'none'; + document.getElementById("errorMsgClient").innerHTML = ""; +} + +function hideFixedIPInput() +{ + document.getElementById('rowClientIP').style.display = 'none'; + document.getElementById('rowClientNETMASK').style.display = 'none'; + document.getElementById('rowClientGATEWAY').style.display = 'none'; + document.getElementById('dhcpInput').style.display = 'block'; + document.getElementById("errorMsgClient").innerHTML = ""; +} + +function showFixedIPInput() +{ + document.getElementById('rowClientIP').style.display = 'table-row'; + document.getElementById('rowClientNETMASK').style.display = 'table-row'; + document.getElementById('rowClientGATEWAY').style.display = 'table-row'; + document.getElementById('dhcpInput').style.display = 'none'; + document.getElementById("errorMsgClient").innerHTML = ""; +} + +function showIPConfig() +{ + if(document.getElementById("wifiCfg0checked")) + { + document.getElementById("wifiCfg0checked").style.display = 'compact'; + document.getElementById("wifiCfg").style.display = 'none'; + + if(document.getElementById("wifiCfg3checked")) + { + document.getElementById("wifiCfg3checked").style.display = 'compact'; + document.getElementById("wifiCfg3").style.display = 'none'; + } else + { + document.getElementById("wifiCfg3checked").style.display = 'none'; + document.getElementById("wifiCfg3").style.display = 'compact'; + } + + if(document.getElementById("wifiCfg1checked")) + { + document.getElementById("wifiCfg1checked").style.display = 'compact'; + } else + { + document.getElementById("wifiCfg1").style.display = 'none'; + } + } else + { + document.getElementById("wifiCfg0").style.display = 'none'; + document.getElementById("wifiCfgchecked").style.display = 'compact'; + } +} + + +// Method to enable the correct side-bar menu for the underlying host interface. +function enableIfConfig() +{ + // Disable keymap if no host is connected to the SharpKey. KeyInterface is the base class which exists when + // no host was detected to invoke a host specific sub-class. + if(activeInterface === "KeyInterface ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + } + // Mouse interface active? + else if(activeInterface === "Mouse ") + { + document.getElementById("keyMapAvailable").style.display = 'none'; + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("keyMapAvailable").style.display = 'compact'; + + // Secondary interface available? + if(secondaryInterface == "Mouse ") + { + document.getElementById("mouseCfgAvailable").style.display = 'compact'; + } else + { + document.getElementById("mouseCfgAvailable").style.display = 'none'; + } + } +} + +// On document load, setup the items viewable on the page according to set values. +document.addEventListener("DOMContentLoaded", function setPageDefaults() +{ + document.getElementById('wifiModeAccessPoint').onclick = showWiFiAPInput; + document.getElementById('wifiModeClient').onclick = showWiFiClientInput; + document.getElementById('dhcpModeEnabled').onclick = hideFixedIPInput; + document.getElementById('dhcpModeDisabled').onclick = showFixedIPInput; + + // Setup AP/Client display. + if(document.getElementById('wifiModeClient').checked) + { + showWiFiClientInput(); + } else + { + showWiFiAPInput(); + } + if(document.getElementById('dhcpModeEnabled').checked) + { + hideFixedIPInput(); + } else + { + showFixedIPInput(); + } + + // AJAX code to post in a controlled manner so that we can receive back an error/success message to the commit. + $("#wifiman").submit( function(e) + { + var form = $(this); + var actionUrl = form.attr('action'); + + // Prevent default submit action, we want to manually submit and be able to receive a response for errors/success. + e.preventDefault(); + + // Clear message window before making a POST, allows for a new message if one is provided or blank if it isnt. + document.getElementById("errorMsgClient").innerHTML = ""; + document.getElementById("errorMsgAP").innerHTML = ""; + + $.ajax( + { + type: "POST", + url: actionUrl, + data: form.serialize(), // serializes the form's elements. + success: function(data) + { + // JQuery not rendering HTML correcly so revert to DOM. + document.getElementById("errorMsgClient").innerHTML = data; + document.getElementById("errorMsgAP").innerHTML = data; + //form.find('#errorMsg').html(data); + } + }); + }); + + showIPConfig(); + enableIfConfig(); +}); diff --git a/software/WebServer/webserver/keymap.html b/software/WebServer/webserver/keymap.html new file mode 100644 index 000000000..3abf816e7 --- /dev/null +++ b/software/WebServer/webserver/keymap.html @@ -0,0 +1,239 @@ + + + + + + + + + Dashboard - SharpKey Admin + + + + + + + + + + + + + + +
+ + + + +
+ +
+
+

%SK_CURRENTIF%KeyMap

+
    +
  1. Status->%SK_CURRENTIF%KeyMap
    2. +
+
+ +

Configure the keyboard mapping of the interface from PS/2 to %SK_CURRENTIF% via the table below. The priority is top down and a copy can be saved or uploaded to/from your disk for backup or offline editting.

+
+
+
+ + +
+
+
+
+

KeyMap Editor

+
+
+
+%SK_KEYMAPPOPOVER% + +
+
+
+

+

Directly edit the table, click to add a row, to delete, select () 2 rows to Swap or select multiple rows for multi-row Delete.
Press Save to commit changes or Reload to discard changes and reload active i/f map.

+
+
+ -
+ + + + + + + + +
+ + + + + + + +
+ + + + + + + + +
+
+
+
+

Direct KeyMap Access

+
+
+
+
+

The KeyMap for the %SK_CURRENTIF% interface can be directly manipulated via the buttons below. You can download the file for backup or to modify locally then upload to restore or implement changes.

+

Select Upload file (to SharpKey) or Download (to your PC) via the buttons below.

+ + + + + + + +
+ + + + +
+
+
+
+
+
+
+ + + + + + + + + + + diff --git a/software/WebServer/webserver/mouse.html b/software/WebServer/webserver/mouse.html new file mode 100644 index 000000000..dc2322e05 --- /dev/null +++ b/software/WebServer/webserver/mouse.html @@ -0,0 +1,167 @@ + + + + + + + + + Dashboard - SharpKey Admin + + + + + + + + + + + + + + +
+ + + + +
+ +
+
+

Mouse Config

+
    +
  1. Status->Mouse Config
    2. +
+
+ +

Configure the Mouse settings in the panel below. Some of the mouse settings can be configured by the mouse wheel, please refer to the documentation for details.

+
+
+
+ + +
+
+
+
+

Mouse Host Configuration

+
+
+
+

Host Scaling

+
+ %SK_MOUSEHOSTSCALING% +
+
+
+

Setup the host side mouse interface parameters. Commit changes by pressing Save.

+
+
+
+ + + + + + +
+ +
+
+
+
+
+
+
+ +
+
+
+
+

Mouse Configuration

+
+
+
+

Mouse Scaling

+
+ %SK_MOUSEPS2SCALING% +
+

Mouse Resolution

+
+ %SK_MOUSEPS2RESOLUTION% +
+

Mouse Sampling Rate

+
+ %SK_MOUSEPS2SAMPLERATE% +
+
+
+

Setup the mouse parameters which are PS/2 settings, Bluetooth mice will use these parameters via internal mapping.
Commit changes by pressing Save.

+
+
+
+ + + + + + +
+ +
+
+ +
+
+
+
+ +
+ + + + + + + + + diff --git a/software/WebServer/webserver/ota.html b/software/WebServer/webserver/ota.html new file mode 100644 index 000000000..5e81850b3 --- /dev/null +++ b/software/WebServer/webserver/ota.html @@ -0,0 +1,238 @@ + + + + + + + + + Dashboard - SharpKey Admin + + + + + + + + + + + + +
+ + + + +
+ +
+
+

Over The Air Update

+
    +
  1. Status->OTA Update
    2. +
+
+ +

Welcome to the SharpKey OTA Update page.

This page allows you to check current firmware/filepack version information and upgrade them as necessary. Please read the documentation if you need help.

+
+
+
+ +
+
+ +
+
+
+
+

Version Information

+
+
+
+
+ %SK_PRODNAME% v%SK_PRODVERSION% © P.D. Smart, 2018-22

+ Modules
+ %SK_MODULES% + File Pack
+ %SK_FILEPACK% +
+
+
+
+
+
+ +
+
+
+
+

ESP32 Partitions

+
+
+
+
+ + + + + + + + + + + + + + + %SK_PARTITIONS% + +
Partition NameTypeSub-TypeAddressSizeVersionTimestampActive (Running)
+
+
+
+
+
+
+ +
+
+
+
+

Firmware Upload

+
+
+
+
+

Firmware is a binary file containing the latest operating system for the SharpKey interface.

+
+

Select a firmware image file with which to upgrade the SharpKey Operating System.

+
+ + + + + + + + + + +
+ + +
+ 		+ + + + +
+
+
+
+
+
+
+
+
+
+
+ +
+
+
+
+

File Pack Upload

+
+
+
+
+

A filepack is a SharpKey filesystem stored in a binary image file which contains static and template files for the webserver interface.

+ +
+

Select a filepack image file with which to upgrade the SharpKey filesystem.

+
+ + + + + + + + + + +
+ + +
+ 		+ + + + +
+
+
+
+
+
+
+
+
+
+
+ +
+ +
+ + + + + + + + diff --git a/software/WebServer/webserver/ota.html.bak b/software/WebServer/webserver/ota.html.bak new file mode 100644 index 000000000..dd6a328dd --- /dev/null +++ b/software/WebServer/webserver/ota.html.bak @@ -0,0 +1,56 @@ + +Upgrade firmware + + + + + + + +
+

Upgrade Firmware

+ +

+ + + + + + + + + + + + + + +
App Partitions
Partition NamePartition SizeApp VersionApp ValidApp RunningApp Set BootApp Upload

+ +

+ + + + + + + + + + + +
Data Partitions
Partition NamePartition SizeData TypeErase

+ +

Loading...

+
+
+ + diff --git a/software/WebServer/webserver/version.txt b/software/WebServer/webserver/version.txt new file mode 100644 index 000000000..101047359 --- /dev/null +++ b/software/WebServer/webserver/version.txt @@ -0,0 +1 @@ +1.02 diff --git a/software/WebServer/webserver/wifimanager.html b/software/WebServer/webserver/wifimanager.html new file mode 100644 index 000000000..bf4c8e08a --- /dev/null +++ b/software/WebServer/webserver/wifimanager.html @@ -0,0 +1,312 @@ + + + + + + + + + Dashboard - SharpKey Admin + + + + + + + + + + + + + +
+ + + + +
+ +
+
+

WiFi Manager

+
    +
  1. Status->WiFi Manager
    2. +
+
+ +

Welcome to the SharpKey WiFi Manager page.

This page allows you to configure the SharpKey WiFi Access Point (you connect to the SharpKey) or + Client (SharpKey connects to your network) mode.

+
+
+
+ +
+
+ +
+
+
+
+

WiFi Configuration

+
+
+
+
+ +
+ + + + + + + + + + + + + + +
SSID:%SK_APSSID%
Password:%SK_APPWD%
IP (AP):%SK_CURRENTIP%NETMASK:%SK_CURRENTNM%GATEWAY:%SK_CURRENTGW%
+
+
+ + + + + + + + + + + + + + + + + + + +
SSID:%SK_CLIENTSSID%
DHCP:Enabled
IP (assigned):%SK_CURRENTIP%NETMASK:%SK_CURRENTNM%GATEWAY:%SK_CURRENTGW%
IP (fixed):%SK_CURRENTIP%NETMASK:%SK_CURRENTNM%GATEWAY:%SK_CURRENTGW%
+
+
+
+
+
+
+
+ +
+
+
+
+

Configure WiFi

+
+
+
+
+
+ + + + + + + + +
WiFi Mode: +
+ + +
+ 		+
+ + +
+
+
+ + +
+
+ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
Name of Wifi router to use. +
Password of WiFi router.
DHCP Mode: +
+ + +
+ 		+
+ + +
+
Static IP address to assign to SharpKey
Netmask for Static IP
Gateway or router IP Address (if needed).
+
+
+

DHCP Mode enabled.
The SharpKey will use the credentials specified above (SSID/Password) to connect to the router and obtain + an IP address, Netmask and Gateway. Use your router admin page to determine the IP address allocated and connect to the SharpKey via http://<assigned IP>

+
+
+
+ %SK_ERRMSG% +
+
+
+ + + + + + +
+
+
+
+ + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name of this WiFi Access Point. +
Password required by this AP to authenticate clients.
IP address assigned to this Access Point. ie. 192.168.4.1
Netmask of this AP network.
Gateway this AP will assign to a client. Normally same as IP.
+
+
+
+ %SK_ERRMSG% +
+
+
+ + + + + + +
+
+
+
+
+
+
+
+
+
+ +
+ +
+ + + + + + + + diff --git a/software/WebServer/webserver/wifimanager.html.bak b/software/WebServer/webserver/wifimanager.html.bak new file mode 100644 index 000000000..d5f34d0f9 --- /dev/null +++ b/software/WebServer/webserver/wifimanager.html.bak @@ -0,0 +1,96 @@ + + + + + SharpKey Wi-Fi Manager + + + + + + +
+

SharpKey WiFi Manager

+
+
+
+
+
+ Name of Wifi router to use.
+ +
+ Password of WiFi Router.
+ +
+
+ + +
+ + +
+ + +
+ + +
+ + %SK_ERRMSG% +
+
+ + + + + +
+ + + +
+
+
+
+
+
+ + + diff --git a/software/asm/mz2000_ipl.orig.asm b/software/asm/mz2000_ipl.orig.asm new file mode 100644 index 000000000..5853e4a93 --- /dev/null +++ b/software/asm/mz2000_ipl.orig.asm @@ -0,0 +1,891 @@ + ;**************************************************************** + ; + ; MZ-2000 Initial Program Loader Firmware. + ; + ; Disassembled with dz80 v2.1 and comments copied from the + ; MZ-80B IPL disassembly. + ; + ;**************************************************************** + ; +CR EQU 0D8H +TR EQU 0D9H +SCR EQU 0DAH +DR EQU 0DBH +DM EQU 0DCH +HS EQU 0DDH +PPIA EQU 0E0H +PPIB EQU 0E1H +PPIC EQU 0E2H +PPICTL EQU 0E3H +PIOA EQU 0E8H +PIOCTLA EQU 0E9H +PIOB EQU 0EAH +PIOCTLB EQU 0EBH +GRPHCTL EQU 0F4H +IBUFE EQU 0CF00H +ATRB EQU 0CF00H +NAME EQU 0CF01H +SIZE EQU 0CF12H +DTADR EQU 0CF14H +SUMDT EQU 0FFE0H +TMCNT EQU 0FFE2H +IBADR1 EQU 0CF00H +IBADR2 EQU 08000H +NTRACK EQU 0FFE0H +NSECT EQU 0FFE1H +BSIZE EQU 0FFE2H +STTR EQU 0FFE4H +STSE EQU 0FFE5H +MTFG EQU 0FFE6H +CLBF0 EQU 0FFE7H +CLBF1 EQU 0FFE8H +CLBF2 EQU 0FFE9H +CLBF3 EQU 0FFEAH +RETRY EQU 0FFEBH +DRINO EQU 0FFECH +PRGSTART EQU 00000H + + ORG PRGSTART + +L0000: JR START + ; + ; NST RESET + ; +NST: LD A,003H ;Set PC1 NST=1 + OUT (PPICTL),A +START: LD A,082H ;8255 A=OUT B=IN C=OUT + OUT (PPICTL),A + LD A,058H ;PIO A=OUT + OUT (PPIC),A + LD SP,SUMDT ;PIO B=IN + LD A,0F7H + OUT (PPIA),A + LD A,00FH + OUT (PIOCTLA),A ;BST=1 NST=0 OPEN=1 WRITE=1 + LD A,0CFH + OUT (PIOCTLB),A + LD A,0FFH + OUT (PIOCTLB),A + XOR A ;Set Graphics VRAM to default, input to GRPH I, no output. + OUT (0F6H),A + OUT (GRPHCTL),A + INC A + OUT (0F7H),A + LD A,007H + OUT (0F5H),A + LD A,0D3H + OUT (PIOA),A + LD HL,0D000H + LD A,CR +CLEAR: LD (HL),000H ; DISPLAY CLEAR + INC HL + CP H + JR NZ,CLEAR + LD A,0FFH + OUT (PPIA),A + LD A,003H + OUT (0F7H),A + CALL L006E + LD A,002H + OUT (0F7H),A + CALL L006E + LD A,001H + OUT (0F7H),A + CALL L006E + LD A,013H + OUT (PIOA),A + XOR A + LD (DRINO),A + LD (MTFG),A +KEYIN: CALL KEYS1 + BIT 3,A ;C - Cassette. + JR Z,CMT + BIT 0,A ;/ - Boot external rom. + JP Z,EXROMT + JR NKIN ;No selection, so standard startup, try FDC then CMT. + +L006E: LD HL,0C000H + DI + IN A,(PIOA) + SET 7,A + RES 6,A + OUT (PIOA),A + LD DE,0C001H + LD (HL),000H + LD BC,03E7FH +L0082: LDIR + RES 7,A + SET 6,A + OUT (PIOA),A + EI + RET + +KEYS1: LD B,014H ;Preserve A4-A7, set A4 to prevent all strobes low, the select line 5 (0-4). +KEYS: IN A,(PIOA) + AND 0F0H + OR B + OUT (PIOA),A + IN A,(PIOB) ;Read the strobed key. + RET + +NKIN: CALL FDCC + JP Z,FD + JR CMT + +FDCC: LD A,0A5H + LD B,A + OUT (TR),A + CALL DLY80U + IN A,(TR) + CP B + RET + ; + ; ; + ; CMT CONTROL ; + ; ; + ; +CMT: CALL MSTOP + CALL KYEMES + CALL RDINF + JR C,ST1 + CALL LDMSG + LD HL,NAME + LD E,010H + LD C,010H + CALL DISP2 + LD A,(IBUFE) + CP 001H + JR NZ,MISMCH + CALL RDDAT +ST1: PUSH AF + CALL FR + POP AF + JP C,TRYAG + JP NST + +MISMCH: LD HL,MES16 + LD E,00AH + LD C,00FH + CALL DISP + CALL MSTOP + SCF + JR ST1 + ; + ;READ INFORMATION + ; CF=1:ERROR +?RDI: +RDINF: DI + IN A,(PPIC) + SET 5,A + OUT (PPIC),A + LD D,004H + LD BC,0080H + LD HL,IBUFE +RD1: CALL MOTOR + JR C,STPEIR + CALL TMARK + JR C,STPEIR + CALL RTAPE + JR C,STPEIR + BIT 3,D + JR Z,EIRTN +STPEIR: CALL MSTOP +EIRTN: EI + RET + ; + ; + ;READ DATA + ; +?RDD: +RDDAT: DI + LD D,008H + LD BC,(0CF12H) + LD HL,IBADR2 + JR RD1 + ; + ; + ;READ TAPE + ; BC=SIZE + ; DE=LOAD ADDRSS +RTAPE: PUSH DE + PUSH BC + PUSH HL + LD H,002H +RTP2: CALL SPDIN + JR C,TRTN1 ; BREAK + JR Z,RTP2 + LD D,H + LD HL,L0000 + LD (SUMDT),HL + POP HL + POP BC + PUSH BC + PUSH HL +RTP3: CALL RBYTE + JR C,TRTN1 + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JR NZ,RTP3 + LD HL,(SUMDT) + CALL RBYTE + JR C,TRTN1 + LD E,A + CALL RBYTE + JR C,TRTN1 + CP L + JR NZ,RTP5 + LD A,E + CP H + JR Z,TRTN1 +RTP5: DEC D + JR Z,RTP6 + LD H,D + JR RTP2 + +RTP6: CALL BOOTER + SCF +TRTN1: POP HL + POP BC + POP DE + RET + +EDGE: IN A,(PPIB) + CPL + RLCA + RET C ; BREAK + RLCA + JR NC,EDGE ; WAIT ON LOW +L016A: IN A,(PPIB) + CPL + RLCA + RET C ; BREAK + RLCA + JR C,L016A ; WAIT ON HIGH + RET + ; 1 BYTE READ + ; DATA=A + ; SUMDT STORE +RBYTE: PUSH HL + LD HL,00800H ; 8 BITS +RBY1: CALL SPDIN + JR C,RBY3 ; BREAK + JR Z,RBY2 ; BIT=0 + PUSH HL + LD HL,(SUMDT) ;CHECKSUM + INC HL + LD (SUMDT),HL + POP HL + SCF +RBY2: RL L + DEC H + JR NZ,RBY1 + CALL EDGE + LD A,L +RBY3: POP HL + RET + ;TAPE MARK DETECT + ; E=L:INFORMATION + ; E=S:DATA +TMARK: PUSH HL + LD HL,01414H + BIT 3,D + JR NZ,TM0 + ADD HL,HL +TM0: LD (TMCNT),HL +TM1: LD HL,(TMCNT) +TM2: CALL SPDIN + JR C,RBY3 + JR Z,TM1 + DEC H + JR NZ,TM2 +TM3: CALL SPDIN + JR C,RBY3 + JR NZ,TM1 + DEC L + JR NZ,TM3 + CALL EDGE + JR RBY3 + +SPDIN: CALL EDGE ;WAIT ON HIGH + RET C ;BREAK + CALL DLY2 + IN A,(PPIB) ;READ BIT + AND 040H + RET + ; + ; + ;MOTOR ON +MOTOR: PUSH DE + PUSH BC + PUSH HL + IN A,(PPIB) + AND 020H + JR Z,MOTRD + LD HL,MES6 + LD E,00AH + LD C,00EH + CALL DISP + CALL OPEN +MOT1: IN A,(PIOB) + CPL + RLCA + JR C,MOTR + IN A,(PPIB) + AND 020H + JR NZ,MOT1 + CALL KYEMES + CALL DEL1M +MOTRD: CALL PLAY +MOTR: POP HL + POP BC + POP DE + RET + ; + ; + ;MOTOR STOP +MSTOP: LD A,0F7H + OUT (PPIA),A + CALL DEL6 + LD A,0FFH + OUT (PPIA),A + RET + ;EJECT +OPEN: LD A,008H ;Reset PC4 - EJECT activate + OUT (PPICTL),A + CALL DEL6 + LD A,009H + OUT (PPICTL),A ;Set PC4 - Deactivate EJECT + RET + +KYEMES: LD HL,MES3 + LD E,004H + LD C,01CH + CALL DISP + RET + ; + ;PLAY +PLAY: LD A,0FBH + OUT (PPIA),A + CALL DEL6 + LD A,0FFH + OUT (PPIA),A + RET + +FR: LD A,0FEH +FR1: OUT (PPIA),A + CALL DEL6 + LD A,0FFH + OUT (PPIA),A + IN A,(PPIC) + RES 5,A + OUT (PPIC),A + RET + ; + ;TIMING DEL +DM1: PUSH AF +DM1A: XOR A +DM1B: DEC A + JR NZ,DM1B + DEC BC + LD A,B + OR C + JR NZ,DM1A + POP AF + POP BC + RET + +DEL6: PUSH BC + LD BC,RDINF + JR DM1 + +DEL1M: PUSH BC + LD BC,060FH + JR DM1 + ; + ;TAPE DELAY TIMING + ; + ; +DLY2: LD A,031H +DLY2A: DEC A + JP NZ,DLY2A + RET + +LDMSG: LD HL,MES1 + LD E,000H + LD C,00EH + JR DISP + +DISP2: LD A,0D3H + OUT (PIOA),A + JR DISP1 + +BOOTER: LD HL,MES8 + LD E,00AH + LD C,00DH +DISP: LD A,0D3H + OUT (PIOA),A + EXX + LD HL,0D000H + LD A,CR +DISP3: LD (HL),000H + INC HL + CP H + JR NZ,DISP3 + EXX +DISP1: XOR A + LD B,A + LD D,0D0H + LDIR + LD A,013H + OUT (PIOA),A + RET + + ; +MES1: DB "IPL is loading" +MES3: DB "IPL is looking for a program" +MES6: DB "Make ready CMT" +MES8: DB "Loading error" +MES9: DB "Make ready FD" +MES10: DB "Press F or C" +MES11: DB "F:Floppy disk " +MES12: DB "C:Cassette tape" +MES13: DB "Drive No? (1-4)" +MES14: DB "This disk is not master " +MES15: DB "Pressing S key starts the CMT" +MES16: DB "File mode error" + ; +IPLMC: DB 01H + DB "IPLPRO" + + ; + ; + ;FD +FD: LD IX,IBUFE + XOR A + LD (0CF1EH),A + LD (0CF1FH),A + LD IY,SUMDT + LD HL,0100H + LD (IY+002H),L + LD (IY+003H),H + CALL BREAD ;INFORMATION INPUT + LD HL,IBUFE ;MASTER CHECK + LD DE,IPLMC + LD B,006H +MCHECK: LD C,(HL) + LD A,(DE) + CP C + JP NZ,NMASTE + INC HL + INC DE + DJNZ MCHECK + CALL LDMSG + LD HL,0CF07H + LD E,010H + LD C,00AH + CALL DISP2 + LD IX,IBADR2 + LD HL,(0CF14H) + LD (IY+002H),L + LD (IY+003H),H + CALL BREAD + CALL MOFF + JP NST + +NODISK: LD HL,MES9 + LD E,00AH + LD C,00DH + CALL DISP + JP ERR1 + ; + ; READY CHECK + ; +READY: LD A,(MTFG) + RRCA + CALL NC,MTON + LD A,(DRINO) ;DRIVE NO GET + OR 084H + OUT (DM),A ;DRIVE SELECT MOTON + XOR A + CALL DLY60M + LD HL,L0000 +REDY0: DEC HL + LD A,H + OR L + JR Z,NODISK + RET C + RET C + CPL + RLCA + JR C,REDY0 + LD A,(DRINO) + LD C,A + LD HL,CLBF0 + LD B,000H + ADD HL,BC + BIT 0,(HL) + RET NZ + CALL RCLB + SET 0,(HL) + RET + ; + ; MOTOR ON + ; +MTON: LD A,080H + OUT (DM),A + LD B,00AH ;1SEC DELAY +MTD1: LD HL,03C19H +MTD2: DEC HL + LD A,L + OR H + JR NZ,MTD2 + DJNZ MTD1 + LD A,001H + LD (MTFG),A + RET + ; + ; Track SEEK + ; +SEEK: LD A,01BH + CPL + OUT (CR),A + CALL BUSY + CALL DLY60M + IN A,(CR) + CPL + AND 099H + RET + ; + ;MOTOR OFF + ; +MOFF: CALL DLY1M + XOR A + OUT (DM),A + LD (CLBF0),A + LD (CLBF1),A + LD (CLBF2),A + LD (CLBF3),A + LD (MTFG),A + RET + ; + ; RECALIBRATION + ; +RCLB: PUSH HL + LD A,00BH + CPL + OUT (CR),A + CALL BUSY + CALL DLY60M + IN A,(CR) + CPL + AND 085H + XOR 004H + POP HL + RET Z + JP ERR + ; + ; BUSY AND WAIT + ; +BUSY: PUSH DE + PUSH HL + CALL DLY80U + LD E,007H +BUSY2: LD HL,L0000 +BUSY0: DEC HL + LD A,H + OR L + JR Z,BUSY1 + IN A,(CR) + CPL + RRCA + JR C,BUSY0 + POP HL + POP DE + RET + +BUSY1: DEC E + JR NZ,BUSY2 + JP ERR + ; + ; DATA CHECK + ; +CONVRT: LD B,000H + LD DE,0010H + LD HL,(0CF1EH) + XOR A +TRANS: SBC HL,DE + JR C,TRANS1 + INC B + JR TRANS + +TRANS1: ADD HL,DE + LD H,B + INC L + LD (IY+004H),H + LD (IY+005H),L +DCHK: LD A,(DRINO) + CP 004H + JR NC,DTCK1 + LD A,(IY+004H) + CP 046H + JR NC,DTCK1 + LD A,(IY+005H) + OR A + JR Z,DTCK1 + CP 011H + JR NC,DTCK1 + LD A,(IY+002H) + OR (IY+003H) + RET NZ +DTCK1: JP ERR + ; + ; SEQUENTIAL READ + ; +BREAD: DI + CALL CONVRT + LD A,00AH + LD (RETRY),A +READ1: CALL READY + LD D,(IY+003H) + LD A,(IY+002H) + OR A + JR Z,RE0 + INC D +RE0: LD A,(IY+005H) + LD (IY+001H),A + LD A,(IY+004H) + LD (IY+000H),A + PUSH IX + POP HL +RE8: SRL A + CPL + OUT (DR),A + JR NC,RE1 + LD A,001H + JR RE2 + +RE1: LD A,000H +RE2: CPL + OUT (HS),A + CALL SEEK + JR NZ,REE + LD C,DR + LD A,(IY+000H) + SRL A + CPL + OUT (TR),A + LD A,(IY+001H) + CPL + OUT (SCR),A + EXX + LD HL,RE3 + PUSH HL + EXX + LD A,094H + CPL + OUT (CR),A + CALL WAIT +RE6: LD B,000H +RE4: IN A,(CR) + RRCA + RET C + RRCA + JR C,RE4 + INI + JR NZ,RE4 + INC (IY+001H) + LD A,(IY+001H) + CP 011H + JR Z,RETS + DEC D + JR NZ,RE6 + JR RE5 + +RETS: DEC D +RE5: LD A,CR + CPL + OUT (CR),A + CALL BUSY +RE3: IN A,(CR) + CPL + AND 0FFH + JR NZ,REE + EXX + POP HL + EXX + LD A,(IY+001H) + CP 011H + JR NZ,REX + LD A,001H + LD (IY+001H),A + INC (IY+000H) +REX: LD A,D + OR A + JR NZ,RE7 + LD A,080H + OUT (DM),A + RET + +RE7: LD A,(IY+000H) + JR RE8 + +REE: LD A,(RETRY) + DEC A + LD (RETRY),A + JR Z,ERR + CALL RCLB + JP READ1 + ; + ; WAIT AND BUSY OFF + ; +WAIT: PUSH DE + PUSH HL + CALL DLY80U + LD E,008H +WAIT2: LD HL,L0000 +WAIT0: DEC HL + LD A,H + OR L + JR Z,WAIT1 + IN A,(CR) + CPL + RRCA + JR NC,WAIT0 + POP HL + POP DE + RET + +WAIT1: DEC E + JR NZ,WAIT2 + JR ERR + +NMASTE: LD HL,MES14 + LD E,007H + LD C,01BH + CALL DISP + JR ERR1 + ; + ; ; + ; ERRROR OR BREAK ; + ; ; + ; +ERR: CALL BOOTER +ERR1: CALL MOFF + LD SP,SUMDT +TRYAG: CALL FDCC + JR NZ,TRYAG3 + LD HL,MES10 + LD E,05AH + LD C,00CH + CALL DISP2 + LD E,0ABH + LD C,011H + CALL DISP2 + LD E,0D3H + LD C,00FH + CALL DISP2 +TRYAG1: CALL KEYS1 + BIT 3,A + JP Z,CMT + BIT 6,A + JR Z,DNO + JR TRYAG1 + +DNO: LD HL,MES13 + LD E,00AH + LD C,00FH + CALL DISP +DNO10: LD D,012H + CALL DNO0 + JR NC,DNO3 + LD D,018H + CALL DNO0 + JR NC,DNO3 + JR DNO10 + +DNO3: LD A,B + LD (DRINO),A + JP FD + +TRYAG3: LD HL,MES15 + LD E,054H + LD C,01DH + CALL DISP2 +TRYAG4: LD B,006H +TRYAG5: CALL KEYS + BIT 3,A + JP Z,CMT + JR TRYAG5 + +DNO0: IN A,(PIOA) + AND 0F0H + OR D + OUT (PIOA),A + IN A,(PIOB) + LD B,000H + LD C,004H + RRCA +DNO1: RRCA + RET NC + INC B + DEC C + JR NZ,DNO1 + RET + ; + ; TIME DELAY (1M &60M &80U ) + ; +DLY80U: PUSH DE + LD DE,000DH + JP DLYT + +DLY1M: PUSH DE + LD DE,L0082 + JP DLYT + +DLY60M: PUSH DE + LD DE,01A2CH +DLYT: DEC DE + LD A,E + OR D + JR NZ,DLYT + POP DE + RET + ; + ; + ; ; + ; INTRAM EXROM ; + ; ; + ; +EXROMT: LD HL,IBADR2 + LD IX,EROM1 + JR SEROMA + +EROM1: IN A,(0F9H) + CP 000H + JP NZ,NKIN + LD IX,EROM2 +ERMT1: JR SEROMA + +EROM2: IN A,(0F9H) + LD (HL),A + INC HL + LD A,L + OR H + JR NZ,ERMT1 + OUT (0F8H),A + JP NST + +SEROMA: LD A,H + OUT (0F8H),A + LD A,L + OUT (0F9H),A + LD D,004H +SEROMD: DEC D + JR NZ,SEROMD + JP (IX) + + ; Align to rom size. + DS 0800H - 1 - ($ + 0800H - 1) % 0800H, 0FFh diff --git a/tools/dz80 b/tools/dz80 new file mode 100755 index 000000000..b47a24a98 Binary files /dev/null and b/tools/dz80 differ