38 KiB
38 KiB
tzpuFusion
Website: engineers@work | Repository: git.eaw.app/eaw/tzpuFusion
Project Status — The tranZPUterFusion v1.0 PCB has been fully designed and a prototype built, but the project is currently on hold. The board uses fine-pitch BGA packages — the EP4CE75F484I7 FPGA (BGA-484, 23×23mm) and the IS66WVO32M8DBLL PSRAM (BGA-24, 6×4mm pitch) — that proved unreliable to hand-place and reflow with a low-cost reflow oven in a home workshop environment. An additional complication is that several of the key components are not stocked by standard PCB assembly services, making a professionally-assembled batch difficult without dedicated component sourcing. The design is otherwise complete and the intent is to resume the project when a suitable manufacturing route is identified. All KiCad schematics, PCB layout, FPGA RTL, and software source are available in the Gitea repository.
Foreword
The tranZPUterFusion is a fusion of the original tranZPUter hardware concept (Z80 replaced by an FPGA), the
tranZPUter SW concept (Z80 enhanced and aided by an I/O processor) and the tranZPUter SW-700 concept
(Z80 enhanced, I/O processor, FPGA and sound/graphics).
The design addresses issues and shortcomings found in the earlier designs and adds further enhancements:
- 75K/115K Logical Element FPGA with 300-400K internal BRAM
- a reconfigurable hardware array to implement most digital hardware functionality. - 512 Cell CPLD
- to interface the host 5V subsystem to the tranZPUterFusion and encode Z80 bus timing protocols. - ARM Cortex-M4 CPU
- to provide I/O support, SD Drive, Remote connection and maintain compatibility with earlier tranZPUter versions - 64MByte 32bit wide 200MHz SDRAM
- to enhance the ZPU processor and zSoft, provide additional resource to the host during normal and emulation modes. - 3x32MB RGB GRAM
- to allow for all VGA and HD standard resolutions upto 1920x1080 in 1M colours. - 30bit VideoDAC
- to allow for exact framebuffer and colour rendering. - 8bit Contrast DAC
- to allow for colour representation on an internal Sharp Monitor by representing colour as a varying contrast signal. - GRAM can be repurposed if required as FPGA has sufficient BRAM to support standard Sharp graphics modes.
- Sharp Series Emulation - the full suite of Sharp machines emulated in hardware, using the host resources such as keyboard, tape, FD etc.
- ZPU and zSoft OS
- allows the ZPU to act as the host processor, utilising host resources and running zOS. - High Efficiency Voltage Regulators
- the original tranZPUters ran hot, primarily through heat generated by the 4 on-board AM117 regulators dissipating through the board copper fill. These devices address the issue and use less host PSU resource. - Modular host VideoInterface
- the tranZPUterFusion and the tranZPUterFusionX share a common platform. Both are designed as small as possible so that they will fit into all Sharp Series hosts and many other Z80 based systems. The board interfaces to the host via the Z80 socket only.
- in order to fuse the Video and Sound of the host with the enhanced capabilities of the tranZPUterFusion, a standard modular daughter board, customised to each Sharp host, has been developed. The daughter board allows selection of host Video and Sound resources with those of the tranZPUter.
- the daughter boards can be used with either of the tranZPUterFusion boards.
To most retro users, the above won't have meaning or interest as it is primarily for hardware (HDL) and software research and development. What the boards do offer the end user though are:
- Original host specifications
- there might be slight differences in the Z80 functionality but these will be minimal. - Accelerator
- the Z80 can run at 128MHz using fast internal RAM yet maintain cycle accuracy with host hardware. - Emulation
- hardware emulation, ie. recreation of original hardware of the MZ-80K, MZ-80C, MZ-1200, MZ-80A, MZ-80B, MZ-700, MZ-800, MZ-1500, MZ-2000 and MZ-2200 systems. The host will appear as the selected machine and all host hardware will be available to the emulation, ie. tape drive. - Graphics
- all original Sharp MZ graphics modes, regardless of host, are available and can be programmed via Basic etc. Also VGA graphics modes and FPGA GPU devices available. - Sound
- the host will have access to 2xSN76489 sound processors along with original audio capabilities. - Processors
- the Z80 and ZPU processors are tried and tested, the IP cores exist for many other processor families and could quite easily be ported to the tranZPUterFusion, ie. a Sharp MZ-700 host running as a BBC Micro B!
The tranZPUterFusion is under development and these pages will be completed with technical detail in due course.
Hardware
The tranZPUterFusion v1.0 is a compact four-layer PCB measuring 109 × 55 mm, designed to fit within the Z80 DIP-40 socket of all Sharp MZ series machines. The board operates entirely from the 5 V supply present on the Z80 socket and generates its own internal 3.3 V, 2.5 V, and 1.2 V rails using high-efficiency buck converters. All host-facing signals are 5 V tolerant; the CPLD provides the level translation boundary between the host bus and the 3.3 V FPGA/MCU logic.
Two FPGA size options are supported: the EP4CE75F484I7 (75K logic elements, BGA-484) for a baseline configuration, or the pin-compatible EP4CE115F23I7 (115K logic elements) for configurations requiring additional resources. All other components are identical between the two variants.
| Component | Part Number | Package | Function |
|---|---|---|---|
| FPGA | EP4CE75F484I7 / EP4CE115F23I7 | BGA-484 | Main logic fabric — Z80 emulation, video, memory control |
| CPLD | EPM7512AEQFP144 | QFP-144 | 5 V host interface, Z80 bus timing, level translation |
| MCU | NXP MK64FX512 (Kinetis K64F) | LQFP-100 | ARM Cortex-M4 — I/O processor, SD card, USB |
| PSRAM × 4 | IS66WVO32M8DBLL | BGA-24 | 4 × 16 MB = 64 MB system memory (32-bit wide, 200 MHz) |
| FPGA Config Flash | EPCS64 | SOIC-16W | 64 Mbit serial flash for FPGA configuration bitstream |
| Video DAC | ADV7123 | LQFP-48 | 30-bit RGB DAC for VGA/HD video output |
| Audio DAC | TLC5602C | — | 8-bit audio DAC for sound output |
| USB Serial | CH340E | — | USB-to-serial bridge for debug and firmware |
| Buck Converter | TLV62569DBV | SOT-23-5 | High-efficiency 3.3 V / 1.2 V switching regulators |
| Power IC | SY6280 | — | Power sequencing and protection |
| Voltage Ref | REF3040 | SOT-23-3 | 4.096 V precision reference for DAC |
| Analog MUX | TMUX1134 | — | Video/audio signal multiplexing |
| Audio Amp | HXJ8002 | — | Stereo audio amplifier |
| Coin Cell | MS621F | — | RTC battery backup |
The main board schematic is divided into nine KiCad sheets. A compiled PDF (
tzpuFusion_v1_0_Schematics.pdf) is available in the pcb/Fusion/v1.0/ directory.
| Sheet | File | Contents |
|---|---|---|
| Top | tzpuFusion_v1_0 | Top-level block diagram and fiducials |
| FPGA/CPU | tzpuFusion_FPGA_CPU_v1_0 | Cyclone IV FPGA, DDR interface, clock routing |
| Memory | tzpuFusion_FPGA_CPU_Memory_v1_0 | 4× IS66WVO32M8DBLL PSRAM array |
| Video | tzpuFusion_FPGA_Video_v1_0 | ADV7123 video DAC, RGB GRAM, contrast DAC |
| MCU | tzpuFusion_k64fx512_v1_0 | NXP MK64FX512 ARM Cortex-M4, peripherals |
| CPU Interface | tzpuFusion_CPU_Interface_v1_0 | Z80 socket connector, CPLD control interface |
| Level Translator | tzpuFusion_CPU_LevelXlator | 5 V ↔ 3.3 V bus signal conversion |
| Programming | tzpuFusion_CPLDFPGA_Programming_v1_0 | JTAG header, EPCS64 flash, debug connectors |
| Power | tzpuFusion_PowerSupply_v1_0 | Buck converters, power sequencing, rail distribution |
Architecture
The board is organised around three independent processing elements — the FPGA, the ARM MCU, and the CPLD — plus a dedicated video memory subsystem. The CPLD forms the boundary between the 5 V Sharp MZ host bus and the 3.3 V core logic; everything behind it operates at 3.3 V or lower.
┌─────────────────────────────────────────────────────────────────────────────┐
│ Sharp MZ Host (5 V) │
│ Z80 socket — address, data, control, CLK, INT, RESET │
└────────────────────────────┬────────────────────────────────────────────────┘
│ 5 V signals
┌─────────────────▼──────────────────┐
│ CPLD EPM7512AEQFP144 (512 cells) │
│ - 5 V ↔ 3.3 V level translation │
│ - Z80 bus timing protocol encoding │
│ - Host clock synchronisation │
│ - Reset and interrupt routing │
└─────────────────┬──────────────────┘
│ 3.3 V signals
┌───────────────────────────▼─────────────────────────────────────────┐
│ FPGA Cyclone IV EP4CE75F484I7 / EP4CE115F23I7 │
│ │
│ ┌────────────────┐ ┌─────────────────┐ ┌───────────────────────┐ │
│ │ Z80 Interface │ │ Video System │ │ Memory Controller │ │
│ │ - Soft Z80 │ │ - All Sharp MZ │ │ - PSRAM arbiter │ │
│ │ (T80 core) │ │ video modes │ │ - GRAM controller │ │
│ │ - Bus decode │ │ - VGA/HD out │ │ - Cache / banking │ │
│ │ - Mem banking │ │ - Colour GPU │ │ │ │
│ └────────────────┘ └────────┬────────┘ └───────────────────────┘ │
│ │ │
│ ┌────────────────┐ ┌────────▼────────┐ ┌───────────────────────┐ │
│ │ Emulation │ │ ADV7123 DAC │ │ Audio │ │
│ │ - MZ-80K/C │ │ 30-bit RGB │ │ 2× SN76489 (soft) │ │
│ │ - MZ-80A/B │ │ VGA/HD output │ │ TLC5602C DAC │ │
│ │ - MZ-700/800 │ └─────────────────┘ └───────────────────────┘ │
│ │ - MZ-2000 │ │
│ └────────────────┘ │
│ │
│ ┌─────────────────────────────────────────────────────────────────┐ │
│ │ ZPU Evolution CPU (optional configuration) │ │
│ │ - 32-bit RISC stack processor running zSoft / zOS │ │
│ └─────────────────────────────────────────────────────────────────┘ │
└──────────────────────────────────────────────────────────────────────┘
│ │
┌─────────────▼────────────┐ ┌────────────▼───────────────────────┐
│ System Memory │ │ ARM Cortex-M4 NXP MK64FX512 │
│ 4× IS66WVO32M8DBLL │ │ - I/O processor, service IRQs │
│ 64 MB PSRAM, 32-bit │ │ - SD card (FAT32 file system) │
│ wide at 200 MHz │ │ - USB debug / remote connectivity │
└──────────────────────────┘ │ - tranZPUter SW backward compat. │
└────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────┐
│ RGB GRAM (3 × 32 MB, one per colour channel) │
│ Video frame buffers — up to 1920 × 1080 at 1M colours │
└─────────────────────────────────────────────────────────────┘
The Altera MAX7000 EPM7512AEQFP144 (512 macrocells, QFP-144) sits directly between the Sharp MZ host bus and the FPGA. Its primary roles are:
- Level translation
- the Sharp MZ bus operates at 5 V; the CPLD input cells are 5 V tolerant while all outputs toward the FPGA are 3.3 V LVTTL. This makes the CPLD the sole 5 V component on the board aside from the bus buffer resistors. - Z80 bus timing protocol
- the CPLD encodes Z80 bus cycles (MREQ, IORQ, RD, WR, M1, RFSH, WAIT, HALT) into a compact control word that the FPGA can latch synchronously, decoupling the FPGA from the host's Z80 bus setup and hold times. - Clock synchronisation
- the host Z80 clock is received by the CPLD and used as a reference to synchronise bus transactions with the FPGA's internal PLL-derived clocks. - Reset and interrupt routing
- RESET and INT/NMI signals from the host are filtered and re-driven to the FPGA with appropriate synchronisation to prevent metastability.
The Cyclone IV E FPGA is the heart of the board. Depending on the loaded bitstream configuration, it can act as a Z80 bus master (replacing the host's physical Z80), a hardware emulator of any Sharp MZ machine, a multi-CPU platform running the ZPU Evolution processor, or a video controller providing enhanced graphics output. Internal block RAM (300–400 KB depending on device size) holds character generators, video line buffers, and CPU register files. The PSRAM is connected to the FPGA via a 32-bit wide interface operating at up to 200 MHz, providing the main working memory for all CPU and video workloads.
The NXP MK64FX512 (Kinetis K64F, 120 MHz Cortex-M4 with FPU, 512 KB Flash, 192 KB SRAM) provides the board's I/O subsystem. It manages the microSD card using a FAT32 file system, exposes a USB virtual serial port via the CH340E bridge for debug and remote connectivity, and responds to service interrupt requests from the FPGA to load ROM images or perform disk I/O on the FPGA's behalf. This architecture maintains software compatibility with the earlier tranZPUter SW and tranZPUter SW-700 designs, where the K64F served the same role.
The video output chain runs from the FPGA's video controller logic through the ADV7123 30-bit RGB DAC (10 bits per channel) to a VGA/HD connector. Three dedicated 32 MB frame buffer SRAMs (one per colour channel, R, G, B) allow double-buffered rendering at resolutions up to 1920 × 1080 with 1 M simultaneous colours. A separate 8-bit contrast DAC provides a varying-contrast greyscale output for connection to the original Sharp internal monitors, maintaining backward compatibility with machines that use analogue contrast rather than RGB video.
The daughter board connectors allow a host-specific video/audio interface board to intercept and mix the original Sharp video and audio signals with the FPGA output, enabling transparent switching between the host's native display and FPGA-generated video without any permanent modification to the host machine.
FPGA
The Quartus project (
FPGA/v1.0/build/coreMZ.qpf) contains seven pre-defined settings files, each targeting a specific FPGA size and use case. Select the appropriate .qsf as the active configuration before compiling.
| Settings File | FPGA | Description |
|---|---|---|
coreMZ_E115_Z80.qsf |
EP4CE115 | Z80 soft CPU — T80 core as Z80 replacement with full bus interface |
coreMZ_E75_emuMZ.qsf |
EP4CE75 | Full Sharp MZ hardware emulation (MZ-80K through MZ-2200) |
coreMZ_E115_emuMZ.qsf |
EP4CE115 | As above with additional logic resources |
coreMZ_E75_SoftCPU.qsf |
EP4CE75 | Multi-CPU platform (T80 Z80 + ZPU Evolution, selectable) |
coreMZ_E115_SoftCPU.qsf |
EP4CE115 | As above with additional logic resources |
coreMZ_E75.qsf |
EP4CE75 | Base video controller only |
coreMZ_E115.qsf |
EP4CE115 | Base video controller, larger device |
The RTL source is organised into a small set of top-level files and a collection of functional IP cores:
| Module | File | Description |
|---|---|---|
| Z80 Interface | coreMZ_Z80.vhd |
Main Z80 bus interface — bus cycle decode, memory banking, I/O port handling, T80 core integration |
| Package | coreMZ_pkg.vhd |
Board-wide constants: host machine type (HOST_HW), CPU/emulation feature flags (IMPL_*), clock tick calculations, utility functions |
| Utilities | functions.vhd |
Common RTL utilities: log2ceil, IntMax, reverse_vector, clockTicks |
| Soft CPU | hold/coreMZ_SoftCPU.vhd |
Multi-processor top-level integrating T80 Z80 and ZPU Evolution cores, selectable via coreMZ_pkg.vhd flags |
| Emulation | hold/coreMZ_emuMZ.vhd |
Sharp MZ hardware emulation top-level; instantiates machine-specific hardware modules |
| Video Controller | hold/VideoController/VideoController.vhd |
Video generation state machine — timing, scan-line rendering, mode switching |
| Video RAM | hold/VideoController/VideoRAM_DP_3216.vhd |
Dual-port BRAM tile for video line buffers |
| Character ROM | hold/VideoController/ChrGenRAM_DP_3208.vhd |
Character generator BRAM |
| ZPU Core | hold/softZPU/zpu_core_evo_*.vhd |
ZPU Evolution 32-bit RISC stack processor (issue / no-issue variants) |
| ZPU Package | hold/softZPU/zpu_pkg.vhd |
ZPU configuration: cache sizes, BRAM depth, peripheral enable flags |
| MZ-80B Hardware | hold/emuMZ/mz80b_hw.vhd |
MZ-80B specific hardware emulation |
| Keyboard | hold/emuMZ/keymatrix_mz700.vhd |
MZ-700 keyboard matrix scanner |
| Clock Gen | hold/emuMZ/clkgen.vhd |
Host machine clock generation and synchronisation |
| 8254 Timer | hold/emuMZ/i8254/ |
Intel 8254 programmable interval timer emulation |
| Z8420 CTC | hold/emuMZ/z8420/ |
Zilog Z8420 counter/timer circuit emulation |
| T80 Z80 | softT80/ |
T80-based Z80-compatible soft CPU core (up to 128 MHz, cycle accurate) |
The bitstream is compiled with Intel Quartus II 17.1.1 (or any later release that retains Cyclone IV support). The Web/Lite edition is sufficient. Select the target
.qsf configuration and compile:
cd FPGA/v1.0/build # Example: build the MZ emulation configuration on EP4CE75 quartus_map --read_settings_files=on coreMZ -c coreMZ_E75_emuMZ quartus_fit --read_settings_files=on coreMZ -c coreMZ_E75_emuMZ quartus_asm --read_settings_files=on coreMZ -c coreMZ_E75_emuMZ quartus_sta coreMZ -c coreMZ_E75_emuMZ
Or open
coreMZ.qpf in the Quartus GUI, set the active configuration from the Assignment menu, and use Processing → Start Compilation. Compile time is approximately 20–40 minutes depending on configuration and host CPU.
Output files are written to FPGA/v1.0/build/output_files/:
coreMZ.sof— SRAM Object File for direct JTAG programming (volatile, lost on power-off).coreMZ.pof— Programmer Object File for programming the EPCS64 serial flash (persistent, loads automatically at every power-on).
Connect an Altera USB-Blaster (or compatible clone) to the 10-pin JTAG header on the tranZPUterFusion board.
To load directly into the FPGA SRAM (for development/testing — not persistent):
quartus_pgm -c "USB-Blaster" -m JTAG \ -o "p;FPGA/v1.0/build/output_files/coreMZ.sof"
To program the EPCS64 serial flash (persistent across power cycles):
quartus_pgm -c "USB-Blaster" -m JTAG \ -o "p;FPGA/v1.0/build/output_files/coreMZ.pof"
Software
The tranZPUterFusion runs the same Z80 software stack as the tranZPUter SW-700: machine monitor ROMs, the tranZPUter Filing System (TZFS), CP/M, and Nascom BASIC are all assembled from the same source tree. The output binary images are loaded into FPGA block RAM at bitstream compile time, or placed on the SD card for runtime loading by the ARM MCU.
| Component | Source | Description |
|---|---|---|
| Machine Monitor ROMs | software/asm/1z-013a.asm, mz80_1z_013b.asm, mz2000_ipl.asm |
Original Sharp MZ monitor ROMs, reassembled from disassembly |
| MZ-80C Monitor | software/asm/monitor_80c_1z-013a-km.asm |
MZ-80C variant |
| TZFS (Bank 4) | software/asm/tzfs_bank4.asm |
tranZPUter Filing System — file management, SD card interface |
| CP/M CBIOS | software/asm/cbiosII.asm |
CP/M 2.2 custom BIOS for tranZPUter disk interface |
| Nascom BASIC | software/asm/nascombasic.asm |
Nascom BASIC interpreter |
| Board Test | software/asm/sharpmz-test.asm |
Hardware self-test routine |
| zOS | software/zOS/ |
ZPU-based operating system for ZPU Evolution CPU configurations |
The build system uses shell scripts with a Z80 assembler (zmac or compatible). The master script assembles all components in the correct order:
cd software # Build everything ./build.sh # Or build individual components: ./tools/assemble_roms.sh # Monitor ROMs ./tools/assemble_tzfs.sh # tranZPUter Filing System ./tools/assemble_cpm.sh # CP/M CBIOS
Assembled binary images are written to
software/roms/. These are then either compiled into the FPGA bitstream (placed in initialised BRAM via Quartus MIF/HEX files) or placed in the root of the SD card for runtime loading by the K64F MCU.
Daughter Boards
The tranZPUter series was initially developed in the Sharp MZ-80A and was primarily a Z80 replacement. As the concept evolved and the tranZPUter SW-700 was developed for the MZ-700 it became more of an integral component of the machine, offering original and upgraded Video and Audio capabilities by intercepting and routing existing signals.
After significant developments on the tranZPUter SW-700 it became desirable to port it back to the MZ-80A and MZ-2000 but these machines had different CPU orientation and signal requirements, ie. driving internal and external monitor. This requirement led to the concept of daughter boards, where a specific board would be designed and developed for the target host and would plug into the tranZPUter SW-700 card. Ideally I wanted to port the SW-700 to an MZ-800/MZ-1500 and X1 but the size of the card and orientation of the Z80 was a limitation.
During the design of the tranZPUterFusion one of the main requirements was to make the board small and the Z80 orientation changeable so that it could fit many more machines. As the SW-700 also interfaced to the Video and Audio of the machines and each was quite different, it became apparent that the tranZPUterFusion needed to include a concept to allow different video/audio interfaces according to the targeted host. This concept was realised via daughter boards. Two connectors would link the tranZPUterFusion to a daughter board which would be specifically designed for the intended host.
The daughter boards would be responsible for switching and mixing video/audio signals and to drive internal monitors and provide the correct input and output connectors for ease of installation.
Currently three daughter boards have been developed, for the MZ-700, MZ-80A and MZ-2000 and more will follow as the design progresses.
MZ-700 Daughter Board
The MZ-700 daughter board is designed to be inserted into mainboard modulator output and the modulator in turn connected to the daughter board.
The MZ-700 requires switching of the original mainboard video and tranZPUterFusion FPGA video to the existing output connectors. This is accomplished with analogue MUX switches.
The sound of the MZ-700 is sent directly to a speaker and in order to inject tranZPUterFusion sound, the mainboard speaker output is routed to the daughter board, level converted and switched. The FPGA offers stereo sound so this is selectively switched/mixed with the original sound and fed to a Class D amplifier which then drives the internal speaker.
This setup allows for emulated machines, whilst running in the host on the FPGA such as the MZ-800/MZ-1500, to output their sound to the internal speaker. An audio output connector is provided for connection to stereo speakers if desired.
MZ-2000 Daughter Board
The MZ-2000 daughter board is designed to be inserted simultaneously into the mainboard monitor and IPL connectors. The daughter board switches video source to the internal monitor, either the original mainboard video or FPGA video. The video source for the internal monitor is independent to the external monitor source so different images can
be displayed on the internal monitor and external source at the same time.
The external video output can be fed from the original mainboard video or the FPGA video, the external video uses its own framebuffer so can be different to the internal monitor.
The audio is intercepted and switched/mixed prior to being sent to the internal audio amplifier.
The daughter board presents all the original connectors so it is easily installed.
MZ-80A Daughter Board
The MZ-80A daughter board is designed to be inserted into the original Hirose monitor connector with the tape recorder plug being inserted through the gap in the daughter board. The system RESET is routed through the daughter board via 2pin connectors.
The daughter board switches video source to the internal monitor, either the original mainboard video or FPGA video. The video source for the internal monitor is independent to the external monitor source so different images can be displayed on the internal monitor and external source at the same time.
The external video output can be fed from the original mainboard video or the FPGA video, the external video uses its own framebuffer so can be different to the internal monitor.
The audio is intercepted and switched/mixed prior to being sent to the internal audio amplifier.
The daughter board presents all the original connectors so it is easily installed.
Credits
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice. All 3rd party software, to my knowledge and research, is open source and freely useable, if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.
Licenses
This design, hardware and software, is licensed under the GNU Public Licence v3.
The Gnu Public License v3
The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.