diff --git a/CPLD/SW700/tranZPUterSW700.vhd b/CPLD/SW700/tranZPUterSW700.vhd index d2c17b9..5b8d9f0 100644 --- a/CPLD/SW700/tranZPUterSW700.vhd +++ b/CPLD/SW700/tranZPUterSW700.vhd @@ -180,6 +180,8 @@ architecture rtl of cpld512 is signal CS_VIDEO_IOn : std_logic; -- Select to read/write video IO registers according to mode. signal CS_VIDEO_RDn : std_logic; -- Select to read video memory and video IO registers according to mode. signal CS_VIDEO_WRn : std_logic; -- Select to write video memory and video IO registers according to mode. + signal CS_DVRAMn : std_logic; -- Chip select for the Video RAM. + signal CS_DARAMn : std_logic; -- Chip select for the Attribute RAM. signal MEM_MODE_LATCH : std_logic_vector(4 downto 0); -- Register to store the active memory mode. signal MEM_MODE_DATA : std_logic_vector(7 downto 0); -- Scratch signal to form an 8 bit read of the memory mode register. @@ -266,7 +268,7 @@ begin -- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there -- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator. -- - MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPLD_CFGn, CS_CPLD_INFOn, Z80_ADDR, Z80_DATA ) + MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPLD_CFGn, Z80_ADDR, Z80_DATA ) begin if(Z80_RESETn = '0') then @@ -1310,12 +1312,12 @@ begin else 'Z'; -- Bus control logic. - SYS_BUSACKni <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + SYS_BUSACKni <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' else - '0' when DISABLE_BUSn = '0' or (KEY_SUBSTITUTE = '1' and Z80_MREQn = '0') or (Z80_BUSACKn = '0' and CTL_BUSACKn = '0') + '0' when DISABLE_BUSn = '0' or (KEY_SUBSTITUTE = '1' and Z80_MREQn = '0') or (Z80_BUSACKn = '0' and CTL_BUSACKn = '0') else '1'; SYS_BUSACKn <= SYS_BUSACKni; - Z80_BUSRQn <= '0' when SYS_BUSRQn = '0' or CTL_BUSRQn = '0' or MB_BUSRQn = '0' + Z80_BUSRQn <= '0' when SYS_BUSRQn = '0' or CTL_BUSRQn = '0' or MB_BUSRQn = '0' else '1'; -- Register read values. @@ -1323,6 +1325,12 @@ begin MEM_MODE_DATA <= "000" & MEM_MODE_LATCH(4 downto 0); CPLD_INFO_DATA <= std_logic_vector(to_unsigned(CPLD_VERSION, 3)) & '0' & CPLD_HAS_FPGA_VIDEO & std_logic_vector(to_unsigned(CPLD_HOST_HW, 3)); + -- Standard access to VRAM/ARAM. + CS_DVRAMn <= '0' when Z80_MREQn = '0' and Z80_ADDR(13 downto 11) = "010" + else '1'; + CS_DARAMn <= '0' when Z80_MREQn = '0' and Z80_ADDR(13 downto 11) = "011" + else '1'; + -- Select for video based on the memory being accessed, the mode and control signals. -- Standard access to VRAM/ARAM. CS_VIDEOn <= '0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '0' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) < X"E000" @@ -1338,12 +1346,12 @@ begin else '1'; -- Read from memory and IO devices within the FPGA. - CS_VIDEO_RDn <= '0' when (CS_VIDEO_MEMn = '0' or CS_VIDEO_IOn = '0') - else '1'; + CS_VIDEO_RDn <= '0' when (CS_VIDEO_MEMn = '0' or CS_VIDEO_IOn = '0') + else '1'; -- Write to memory and IO devices within the FPGA. Duplicate the transaction to the FPGA for CPLD register writes 0x60:0x6F so that the FPGA can register current settings. - CS_VIDEO_WRn <= '0' when (CS_VIDEO_MEMn = '0' or CS_VIDEO_IOn = '0' or CS_IO_EXXn = '0' or CS_IO_6XXn = '0') - else '1'; + CS_VIDEO_WRn <= '0' when (CS_VIDEO_MEMn = '0' or CS_VIDEO_IOn = '0' or CS_IO_EXXn = '0' or CS_IO_6XXn = '0') + else '1'; -- -- Data Bus Multiplexing, plex the output devices onto the Z80 data bus. @@ -1438,6 +1446,7 @@ begin CS_80B_PIOn <= '0' when CS_IO_EXXn = '0' and Z80_ADDR(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1' else '1'; + -- Set the video wait state generator, 0 = disabled, 1 = enabled. MODE_CPLD_VIDEO_WAIT <= CPLD_CFG_DATA(4); -- Set the mainboard video state, 0 = enabled, 1 = disabled. diff --git a/FPGA/SW700/VideoController700.vhd b/FPGA/SW700/VideoController700.vhd index 71ee252..7ac9e24 100644 --- a/FPGA/SW700/VideoController700.vhd +++ b/FPGA/SW700/VideoController700.vhd @@ -1238,7 +1238,7 @@ begin when others => end case; end if; - + -- Activate/deactivate signals according to pixel position. -- if H_COUNT = H_DSP_START then H_BLANKi <= '0'; end if; @@ -2268,7 +2268,7 @@ begin else GRAM_DO_GII when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '1' -- For MZ80B GRAM II memory read - lower 8K of blue framebuffer. else - V_BLANKi & H_BLANKi & VIDEO_MODE_REG(5 downto 0)when VZ80_RDn = '0' and CS_FB_VMn = '0' + VIDEO_MODE_REG(7 downto 0) when VZ80_RDn = '0' and CS_FB_VMn = '0' else GRAM_MODE_REG when VZ80_RDn = '0' and CS_FB_CTLn = '0' else @@ -2278,7 +2278,7 @@ begin else GRAM_B_FILTER when VZ80_RDn = '0' and CS_FB_BLUEn = '0' else - PAGE_MODE_REG when VZ80_RDn = '0' and CS_FB_PAGEn = '0' + PAGE_MODE_REG(7) & V_BLANKi & H_BLANKi & PAGE_MODE_REG(4 downto 0) when VZ80_RDn = '0' and CS_FB_PAGEn = '0' else CGROM_DO when VZ80_RDn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '1' else @@ -2563,10 +2563,10 @@ begin -- end if; -- end process; -- --- process(SYS_CLK) --- begin --- if rising_edge(SYS_CLK) then --- if MODE_CPLD_MB_VIDEOn = '1' then + process(SYS_CLK) + begin + if rising_edge(SYS_CLK) then + if MODE_CPLD_MB_VIDEOn = '1' then -- if H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') then -- VGA_R(3 downto 0) <= FB_PALETTE_R(3 downto 0); -- VGA_G(3 downto 0) <= FB_PALETTE_G(3 downto 0); @@ -2595,31 +2595,31 @@ begin -- VGA_B_COMPOSITE <= 'Z'; -- end if; -- --- if H_POLARITY(0) = '0' then --- HSYNC_OUTn <= H_SYNCni; --- else --- HSYNC_OUTn <= not H_SYNCni; --- end if; --- --- if V_POLARITY(0) = '0' then --- VSYNC_OUTn <= V_SYNCni; --- else --- VSYNC_OUTn <= not V_SYNCni; --- end if; --- --- elsif MODE_CPLD_MB_VIDEOn = '0' then + if H_POLARITY(0) = '0' then + HSYNC_OUTn <= H_SYNCni; + else + HSYNC_OUTn <= not H_SYNCni; + end if; + + if V_POLARITY(0) = '0' then + VSYNC_OUTn <= V_SYNCni; + else + VSYNC_OUTn <= not V_SYNCni; + end if; + + elsif MODE_CPLD_MB_VIDEOn = '0' then -- VGA_R_COMPOSITE <= V_R; -- VGA_G_COMPOSITE <= V_G; -- VGA_B_COMPOSITE <= V_B; -- VGA_R <= (others => V_R); -- VGA_G <= (others => V_G); -- VGA_B <= (others => V_B); --- HSYNC_OUTn <= V_HSYNCn; -- Horizontal sync (negative) from mainboard. --- VSYNC_OUTn <= V_VSYNCn; -- Vertical sync (negative) from mainboard. --- end if; --- end if; --- --- end process; + HSYNC_OUTn <= V_HSYNCn; -- Horizontal sync (negative) from mainboard. + VSYNC_OUTn <= V_VSYNCn; -- Vertical sync (negative) from mainboard. + end if; + end if; + + end process; -- Set the mainboard video state, 0 = enabled, 1 = disabled. @@ -2646,44 +2646,56 @@ begin else (others => V_R) when MODE_CPLD_MB_VIDEOn = '0' else (others => '0'); - VGA_R_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_R = '1' - else - '0' when MODE_CPLD_MB_VIDEOn = '1' and FB_PALETTE_R(4) = '0' - else 'Z'; VGA_G(3 downto 0) <= FB_PALETTE_G(3 downto 0) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') else (others => V_G) when MODE_CPLD_MB_VIDEOn = '0' else (others => '0'); - VGA_G_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_G = '1' - else - '0' when MODE_CPLD_MB_VIDEOn = '1' and FB_PALETTE_G(4) = '0' - else 'Z'; VGA_B(3 downto 0) <= FB_PALETTE_B(3 downto 0) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') else (others => V_B) when MODE_CPLD_MB_VIDEOn = '0' else (others => '0'); + VGA_R_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_R = '1' + else + FB_PALETTE_R(4) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_MONO = '1' or MODE_VIDEO_MONO80 = '1') + else + '1' when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_COLOUR = '1' or MODE_VIDEO_COLOUR80 = '1') and SR_R_DATA(7) = '1' and PALETTE_REG = X"00" + else + '0' when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_COLOUR = '1' or MODE_VIDEO_COLOUR80 = '1') and FB_PALETTE_R(4) = '0' + else 'Z'; + VGA_G_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_G = '1' + else + FB_PALETTE_G(4) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_MONO = '1' or MODE_VIDEO_MONO80 = '1') + else + '1' when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_COLOUR = '1' or MODE_VIDEO_COLOUR80 = '1') and SR_G_DATA(7) = '1' and PALETTE_REG = X"00" + else + '0' when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_COLOUR = '1' or MODE_VIDEO_COLOUR80 = '1') and FB_PALETTE_G(4) = '0' + else 'Z'; VGA_B_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_B = '1' else - '0' when MODE_CPLD_MB_VIDEOn = '1' and FB_PALETTE_B(4) = '0' + FB_PALETTE_B(4) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_MONO = '1' or MODE_VIDEO_MONO80 = '1') + else + '1' when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_COLOUR = '1' or MODE_VIDEO_COLOUR80 = '1') and SR_B_DATA(7) = '1' and PALETTE_REG = X"00" + else + '0' when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and (MODE_VIDEO_COLOUR = '1' or MODE_VIDEO_COLOUR80 = '1') and FB_PALETTE_B(4) = '0' else 'Z'; - HSYNC_OUTn <= H_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and H_POLARITY(0) = '0' - else - not H_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and H_POLARITY(0) = '1' - else - V_HSYNCn; -- Horizontal sync (negative) from mainboard. - VSYNC_OUTn <= V_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and V_POLARITY(0) = '0' - else - not V_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and V_POLARITY(0) = '1' - else - V_VSYNCn; -- Vertical sync (negative) from mainboard. +-- HSYNC_OUTn <= H_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and H_POLARITY(0) = '0' +-- else +-- not H_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and H_POLARITY(0) = '1' +-- else +-- V_HSYNCn; -- Horizontal sync (negative) from mainboard. +-- VSYNC_OUTn <= V_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and V_POLARITY(0) = '0' +-- else +-- not V_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and V_POLARITY(0) = '1' +-- else +-- V_VSYNCn; -- Vertical sync (negative) from mainboard. -- Composite video signal output. Composite video is formed in external hardware by the combination of VGA R/G/B signals. CSYNC_OUTn <= not V_CSYNC when MODE_CPLD_MB_VIDEOn = '0' else - not (H_SYNCni or V_SYNCni); + not (H_SYNCni xor not V_SYNCni); CSYNC_OUT <= V_CSYNC when MODE_CPLD_MB_VIDEOn = '0' else - H_SYNCni or V_SYNCni; + H_SYNCni xor not V_SYNCni; COLR_OUT <= V_COLR when MODE_CPLD_MB_VIDEOn = '0' -- Composite and RF base frequency from mainboard. else V_COLR; diff --git a/FPGA/SW700/build/output_files/VideoController700.jic b/FPGA/SW700/build/output_files/VideoController700.jic index b4fc9f2..67ed682 100644 Binary files a/FPGA/SW700/build/output_files/VideoController700.jic and b/FPGA/SW700/build/output_files/VideoController700.jic differ diff --git a/software/MZF/CPM223.MZF b/software/MZF/CPM223.MZF index dd3cbbf..7b77a17 100644 Binary files a/software/MZF/CPM223.MZF and b/software/MZF/CPM223.MZF differ diff --git a/software/asm/include/CPM_Definitions.asm b/software/asm/include/CPM_Definitions.asm index a8d258d..b8a1907 100644 --- a/software/asm/include/CPM_Definitions.asm +++ b/software/asm/include/CPM_Definitions.asm @@ -34,8 +34,8 @@ ; Features. ;----------------------------------------------- BUILD_VIDEOMODULE EQU 1 ; Build for the Video Module v2 board (=1) otherwise build for the 80Char Colour Board v1.0 -BUILD_MZ80A EQU 0 ; Build for the Sharp MZ-80A base hardware. -BUILD_MZ700 EQU 1 ; Build for the Sharp MZ-700 base hardware. +BUILD_MZ80A EQU 1 ; Build for the Sharp MZ-80A base hardware. +BUILD_MZ700 EQU 0 ; Build for the Sharp MZ-700 base hardware. ;----------------------------------------------- ; Entry/compilation start points. diff --git a/software/asm/tzfs.asm b/software/asm/tzfs.asm index 757047e..7938a19 100644 --- a/software/asm/tzfs.asm +++ b/software/asm/tzfs.asm @@ -128,7 +128,7 @@ MONITOR: LD A, (SCRNMODE) JR Z, MONITOR1 ; IN A,(CPLDCFG) - OR MODE_VIDEO_FPGA ; Set the tranZPUter CPLD hardware translation to MZ700 mode. + OR MODE_VIDEO_FPGA ; Set the tranZPUter CPLD hardware to enable FPGA video. OUT (CPLDCFG),A ; MONITOR1: LD A, C ; Recall screen mode. @@ -142,7 +142,16 @@ SET40CHAR: IN A,(CPLDINFO) ; Get c AND 007H ; Get the base machine mode, use as the starting mode for the video. LD D, A LD A, C ; Get the VGA mode and add. - AND 0C0H + BIT 2, A + JR Z, SET40_0 + RRC A ; Get the override mode into lower 3 bits. + RRC A + RRC A + AND 007H + LD D, A + LD A, C + ; +SET40_0: AND 0C0H OR D OUT (VMCTRL),A ; Activate. SET40_1: LD A, 0 @@ -156,8 +165,19 @@ SET80CHAR: IN A,(CPLDINFO) ; Get c AND 007H OR MODE_80CHAR ; Set 80 char flag. LD D, A - LD A, C ; Get the VGA mode and add. - AND 0C0H + ; + LD A, C ; Check to see if a mode override has been set. + BIT 2, A + JR Z, SET80_0 + RRC A ; Get the override mode into lower 3 bits. + RRC A + RRC A + AND 007H + OR MODE_80CHAR ; Set 80 char flag. + LD D, A + LD A, C + ; +SET80_0: AND 0C0H ; Get the VGA mode and add. OR D OUT (VMCTRL),A ; Activate. LD A, C ; Indicate we are using the FPGA video hardware. diff --git a/software/asm/tzfs_bank2.asm b/software/asm/tzfs_bank2.asm index 3e53198..dba0ca5 100644 --- a/software/asm/tzfs_bank2.asm +++ b/software/asm/tzfs_bank2.asm @@ -76,11 +76,18 @@ SETVMODE: IN A,(CPLDINFO) ; Get c OUT (VMCTRL),A RLC L ; Shift mode to position for SCRNMODE storage. RLC L + RLC L LD A,(SCRNMODE) ; Repeat for the screen mode variable, used when resetting or changing display settings. - AND 0E3H ; Clear video mode setting. + AND 0C7H ; Clear video mode setting. OR L ; Add in new setting. + SET 2,A ; Set flag to indicate video mode override - ie, dont use base machine mode. SET 1, A ; Ensure flag set so on restart the FPGA video mode is selected. LD (SCRNMODE),A + LD A, 016H ; Clear the screen so we start from a known position. + CALL PRNT + LD A,071H ; Blue background and white characters. + LD HL,ARAM + CALL CLR8 RET SETVMODEOFF:LD A,(DE) CP 'O' @@ -147,6 +154,19 @@ SETFREQ2: CALL SVC_CMD OR A JR NZ,SETFREQERR RET + + ; Simple routine to clear screen or attributes. +CLR8: LD BC,00800H + PUSH DE + LD D,A +CLR8_1: LD (HL),D + INC HL + DEC BC + LD A,B + OR C + JR NZ,CLR8_1 + POP DE + RET ; NOFPGAERR: LD DE,MSGNOFPGA JR BADNUM2 diff --git a/software/roms/CPM223.BIN b/software/roms/CPM223.BIN index eb23477..caf8d0b 100644 Binary files a/software/roms/CPM223.BIN and b/software/roms/CPM223.BIN differ diff --git a/software/roms/tzfs.rom b/software/roms/tzfs.rom index 2b40c86..7e8a107 100644 Binary files a/software/roms/tzfs.rom and b/software/roms/tzfs.rom differ