369 lines
14 KiB
C
Vendored
369 lines
14 KiB
C
Vendored
/* Zeta API - Z/hardware/ISA/RISC-V.h
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______ ______________ ___
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|__ / | ___|___ ___|/ \
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/ /__| __| | | / - \
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/______|_____| |__| /__/ \__\
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Copyright (C) 2006-2024 Manuel Sainz de Baranda y Goñi.
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Released under the terms of the GNU Lesser General Public License v3. */
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#ifndef Z_hardware_ISA_RISC_V_H
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#define Z_hardware_ISA_RISC_V_H
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/* Unprivileged Floating-Point CSRs */
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#define Z_RISC_V_CSR_FFLAGS 0x001
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#define Z_RISC_V_CSR_FRM 0x002
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#define Z_RISC_V_CSR_FCSR 0x003
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/* Unprivileged Counter/Timers */
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#define Z_RISC_V_CSR_CYCLE 0xC00
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#define Z_RISC_V_CSR_TIME 0xC00
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#define Z_RISC_V_CSR_INSTRET 0xC02
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#define Z_RISC_V_CSR_HPMCOUNTER3 0xC03
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#define Z_RISC_V_CSR_HPMCOUNTER4 0xC04
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#define Z_RISC_V_CSR_HPMCOUNTER5 0xC05
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#define Z_RISC_V_CSR_HPMCOUNTER6 0xC06
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#define Z_RISC_V_CSR_HPMCOUNTER7 0xC07
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#define Z_RISC_V_CSR_HPMCOUNTER8 0xC08
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#define Z_RISC_V_CSR_HPMCOUNTER9 0xC09
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#define Z_RISC_V_CSR_HPMCOUNTER10 0xC0A
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#define Z_RISC_V_CSR_HPMCOUNTER11 0xC0B
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#define Z_RISC_V_CSR_HPMCOUNTER12 0xC0C
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#define Z_RISC_V_CSR_HPMCOUNTER13 0xC0D
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#define Z_RISC_V_CSR_HPMCOUNTER14 0xC0E
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#define Z_RISC_V_CSR_HPMCOUNTER15 0xC0F
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#define Z_RISC_V_CSR_HPMCOUNTER16 0xC10
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#define Z_RISC_V_CSR_HPMCOUNTER17 0xC11
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#define Z_RISC_V_CSR_HPMCOUNTER18 0xC12
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#define Z_RISC_V_CSR_HPMCOUNTER19 0xC13
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#define Z_RISC_V_CSR_HPMCOUNTER20 0xC14
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#define Z_RISC_V_CSR_HPMCOUNTER21 0xC15
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#define Z_RISC_V_CSR_HPMCOUNTER22 0xC16
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#define Z_RISC_V_CSR_HPMCOUNTER23 0xC17
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#define Z_RISC_V_CSR_HPMCOUNTER24 0xC18
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#define Z_RISC_V_CSR_HPMCOUNTER25 0xC19
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#define Z_RISC_V_CSR_HPMCOUNTER26 0xC1A
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#define Z_RISC_V_CSR_HPMCOUNTER27 0xC1B
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#define Z_RISC_V_CSR_HPMCOUNTER28 0xC1C
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#define Z_RISC_V_CSR_HPMCOUNTER29 0xC1D
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#define Z_RISC_V_CSR_HPMCOUNTER30 0xC1E
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#define Z_RISC_V_CSR_HPMCOUNTER31 0xC1F
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#define Z_RISC_V_CSR_CYCLEH 0xC80
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#define Z_RISC_V_CSR_TIMEH 0xC81
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#define Z_RISC_V_CSR_INSTRETH 0xC82
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#define Z_RISC_V_CSR_HPMCOUNTER3H 0xC83
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#define Z_RISC_V_CSR_HPMCOUNTER4H 0xC84
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#define Z_RISC_V_CSR_HPMCOUNTER5H 0xC85
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#define Z_RISC_V_CSR_HPMCOUNTER6H 0xC86
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#define Z_RISC_V_CSR_HPMCOUNTER7H 0xC87
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#define Z_RISC_V_CSR_HPMCOUNTER8H 0xC88
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#define Z_RISC_V_CSR_HPMCOUNTER9H 0xC89
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#define Z_RISC_V_CSR_HPMCOUNTER10H 0xC8A
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#define Z_RISC_V_CSR_HPMCOUNTER11H 0xC8B
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#define Z_RISC_V_CSR_HPMCOUNTER12H 0xC8C
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#define Z_RISC_V_CSR_HPMCOUNTER13H 0xC8D
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#define Z_RISC_V_CSR_HPMCOUNTER14H 0xC8E
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#define Z_RISC_V_CSR_HPMCOUNTER15H 0xC8F
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#define Z_RISC_V_CSR_HPMCOUNTER16H 0xC90
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#define Z_RISC_V_CSR_HPMCOUNTER17H 0xC91
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#define Z_RISC_V_CSR_HPMCOUNTER18H 0xC92
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#define Z_RISC_V_CSR_HPMCOUNTER19H 0xC93
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#define Z_RISC_V_CSR_HPMCOUNTER20H 0xC94
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#define Z_RISC_V_CSR_HPMCOUNTER21H 0xC95
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#define Z_RISC_V_CSR_HPMCOUNTER22H 0xC96
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#define Z_RISC_V_CSR_HPMCOUNTER23H 0xC97
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#define Z_RISC_V_CSR_HPMCOUNTER24H 0xC98
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#define Z_RISC_V_CSR_HPMCOUNTER25H 0xC99
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#define Z_RISC_V_CSR_HPMCOUNTER26H 0xC9A
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#define Z_RISC_V_CSR_HPMCOUNTER27H 0xC9B
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#define Z_RISC_V_CSR_HPMCOUNTER28H 0xC9C
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#define Z_RISC_V_CSR_HPMCOUNTER29H 0xC9D
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#define Z_RISC_V_CSR_HPMCOUNTER30H 0xC9E
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#define Z_RISC_V_CSR_HPMCOUNTER31H 0xC9F
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/* Supervisor Trap Setup */
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#define Z_RISC_V_CSR_SSTATUS 0x100
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#define Z_RISC_V_CSR_SIE 0x104
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#define Z_RISC_V_CSR_STVEC 0x105
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#define Z_RISC_V_CSR_SCOUNTEREN 0x106
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/* Supervisor Configuration */
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#define Z_RISC_V_CSR_SENVCFG 0x10A
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/* Supervisor Trap Handling */
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#define Z_RISC_V_CSR_SSCRATCH 0x140
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#define Z_RISC_V_CSR_SEPC 0x141
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#define Z_RISC_V_CSR_SCAUSE 0x142
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#define Z_RISC_V_CSR_STVAL 0x143
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#define Z_RISC_V_CSR_SIP 0x144
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/* Supervisor Protection and Translation */
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#define Z_RISC_V_CSR_SATP 0x180
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/* Debug/Trace Registers */
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#define Z_RISC_V_CSR_SCONTEXT 0x5A8
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/* Hypervisor Trap Setup */
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#define Z_RISC_V_CSR_HSTATUS 0x600
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#define Z_RISC_V_CSR_HEDELEG 0x602
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#define Z_RISC_V_CSR_HIDELEG 0x603
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#define Z_RISC_V_CSR_HIE 0x604
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#define Z_RISC_V_CSR_HCOUNTEREN 0x606
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#define Z_RISC_V_CSR_HGEIE 0x607
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/* Hypervisor Trap Handling */
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#define Z_RISC_V_CSR_HTVAL 0x643
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#define Z_RISC_V_CSR_HIP 0x644
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#define Z_RISC_V_CSR_HVIP 0x645
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#define Z_RISC_V_CSR_HTINST 0x64A
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#define Z_RISC_V_CSR_HGEIP 0xE12
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/* Hypervisor Configuration */
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#define Z_RISC_V_CSR_HENVCFG 0x60A
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#define Z_RISC_V_CSR_HENVCFGH 0x61A
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/* Hypervisor Protection and Translation */
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#define Z_RISC_V_CSR_HGATP 0x680
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/* Debug/Trace Registers */
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#define Z_RISC_V_CSR_hcontext 0x6A8
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/* Hypervisor Counter/Timer Virtualization Registers */
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#define Z_RISC_V_CSR_htimedelta 0x605
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#define Z_RISC_V_CSR_htimedeltah 0x615
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/* Virtual Supervisor Registers */
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#define Z_RISC_V_CSR_VSSTATUS 0x200
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#define Z_RISC_V_CSR_VSIE 0x204
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#define Z_RISC_V_CSR_VSTVEC 0x205
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#define Z_RISC_V_CSR_VSSCRATCH 0x240
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#define Z_RISC_V_CSR_VSEPC 0x241
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#define Z_RISC_V_CSR_VSCAUSE 0x242
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#define Z_RISC_V_CSR_VSTVAL 0x243
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#define Z_RISC_V_CSR_VSIP 0x244
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#define Z_RISC_V_CSR_VSATP 0x280
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/* Machine Information Registers */
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#define Z_RISC_V_CSR_MVENDORID 0xF11
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#define Z_RISC_V_CSR_MARCHID 0xF12
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#define Z_RISC_V_CSR_MIMPID 0xF13
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#define Z_RISC_V_CSR_MHARTID 0xF14
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#define Z_RISC_V_CSR_MCONFIGPTR 0xF15
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/* Machine Trap Setup */
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#define Z_RISC_V_CSR_MSTATUS 0x300
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#define Z_RISC_V_CSR_MISA 0x301
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#define Z_RISC_V_CSR_MEDELEG 0x302
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#define Z_RISC_V_CSR_MIDELEG 0x303
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#define Z_RISC_V_CSR_MIE 0x304
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#define Z_RISC_V_CSR_MTVEC 0x305
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#define Z_RISC_V_CSR_MCOUNTEREN 0x306
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#define Z_RISC_V_CSR_MSTATUSH 0x310
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/* Machine Trap Handling */
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#define Z_RISC_V_CSR_MSCRATCH 0x340
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#define Z_RISC_V_CSR_MEPC 0x341
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#define Z_RISC_V_CSR_MCAUSE 0x342
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#define Z_RISC_V_CSR_MTVAL 0x343
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#define Z_RISC_V_CSR_MIP 0x344
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#define Z_RISC_V_CSR_MTINST 0x34A
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#define Z_RISC_V_CSR_MTVAL2 0x34B
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/* Machine Configuration */
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#define Z_RISC_V_CSR_MENVCFG 0x30A
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#define Z_RISC_V_CSR_MENVCFGH 0x31A
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#define Z_RISC_V_CSR_MSECCFG 0x747
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#define Z_RISC_V_CSR_MSECCFGH 0x757
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/* Machine Memory Protection */
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#define Z_RISC_V_CSR_PMPCFG0 0x3A0
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#define Z_RISC_V_CSR_PMPCFG1 0x3A1
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#define Z_RISC_V_CSR_PMPCFG2 0x3A2
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#define Z_RISC_V_CSR_PMPCFG3 0x3A3
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#define Z_RISC_V_CSR_PMPCFG4 0x3A4
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#define Z_RISC_V_CSR_PMPCFG5 0x3A5
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#define Z_RISC_V_CSR_PMPCFG6 0x3A6
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#define Z_RISC_V_CSR_PMPCFG7 0x3A7
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#define Z_RISC_V_CSR_PMPCFG8 0x3A8
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#define Z_RISC_V_CSR_PMPCFG9 0x3A9
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#define Z_RISC_V_CSR_PMPCFG10 0x3AA
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#define Z_RISC_V_CSR_PMPCFG11 0x3AB
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#define Z_RISC_V_CSR_PMPCFG12 0x3AC
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#define Z_RISC_V_CSR_PMPCFG13 0x3AD
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#define Z_RISC_V_CSR_PMPCFG14 0x3AE
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#define Z_RISC_V_CSR_PMPCFG15 0x3AF
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#define Z_RISC_V_CSR_PMPADDR0 0x3B0
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#define Z_RISC_V_CSR_PMPADDR1 0x3B1
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#define Z_RISC_V_CSR_PMPADDR2 0x3B2
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#define Z_RISC_V_CSR_PMPADDR3 0x3B3
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#define Z_RISC_V_CSR_PMPADDR4 0x3B4
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#define Z_RISC_V_CSR_PMPADDR5 0x3B5
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#define Z_RISC_V_CSR_PMPADDR6 0x3B6
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#define Z_RISC_V_CSR_PMPADDR7 0x3B7
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#define Z_RISC_V_CSR_PMPADDR8 0x3B8
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#define Z_RISC_V_CSR_PMPADDR9 0x3B9
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#define Z_RISC_V_CSR_PMPADDR10 0x3BA
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#define Z_RISC_V_CSR_PMPADDR11 0x3BB
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#define Z_RISC_V_CSR_PMPADDR12 0x3BC
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#define Z_RISC_V_CSR_PMPADDR13 0x3BD
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#define Z_RISC_V_CSR_PMPADDR14 0x3BE
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#define Z_RISC_V_CSR_PMPADDR15 0x3BF
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#define Z_RISC_V_CSR_PMPADDR16 0x3C0
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#define Z_RISC_V_CSR_PMPADDR17 0x3C1
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#define Z_RISC_V_CSR_PMPADDR18 0x3C2
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#define Z_RISC_V_CSR_PMPADDR19 0x3C3
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#define Z_RISC_V_CSR_PMPADDR20 0x3C4
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#define Z_RISC_V_CSR_PMPADDR21 0x3C5
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#define Z_RISC_V_CSR_PMPADDR22 0x3C6
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#define Z_RISC_V_CSR_PMPADDR23 0x3C7
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#define Z_RISC_V_CSR_PMPADDR24 0x3C8
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#define Z_RISC_V_CSR_PMPADDR25 0x3C9
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#define Z_RISC_V_CSR_PMPADDR26 0x3CA
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#define Z_RISC_V_CSR_PMPADDR27 0x3CB
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#define Z_RISC_V_CSR_PMPADDR28 0x3CC
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#define Z_RISC_V_CSR_PMPADDR29 0x3CD
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#define Z_RISC_V_CSR_PMPADDR30 0x3CE
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#define Z_RISC_V_CSR_PMPADDR31 0x3CF
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#define Z_RISC_V_CSR_PMPADDR32 0x3D0
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#define Z_RISC_V_CSR_PMPADDR33 0x3D1
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#define Z_RISC_V_CSR_PMPADDR34 0x3D2
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#define Z_RISC_V_CSR_PMPADDR35 0x3D3
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#define Z_RISC_V_CSR_PMPADDR36 0x3D4
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#define Z_RISC_V_CSR_PMPADDR37 0x3D5
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#define Z_RISC_V_CSR_PMPADDR38 0x3D6
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#define Z_RISC_V_CSR_PMPADDR39 0x3D7
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#define Z_RISC_V_CSR_PMPADDR40 0x3D8
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#define Z_RISC_V_CSR_PMPADDR41 0x3D9
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#define Z_RISC_V_CSR_PMPADDR42 0x3DA
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#define Z_RISC_V_CSR_PMPADDR43 0x3DB
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#define Z_RISC_V_CSR_PMPADDR44 0x3DC
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#define Z_RISC_V_CSR_PMPADDR45 0x3DD
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#define Z_RISC_V_CSR_PMPADDR46 0x3DE
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#define Z_RISC_V_CSR_PMPADDR47 0x3DF
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#define Z_RISC_V_CSR_PMPADDR48 0x3E0
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#define Z_RISC_V_CSR_PMPADDR49 0x3E1
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#define Z_RISC_V_CSR_PMPADDR50 0x3E2
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#define Z_RISC_V_CSR_PMPADDR51 0x3E3
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#define Z_RISC_V_CSR_PMPADDR52 0x3E4
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#define Z_RISC_V_CSR_PMPADDR53 0x3E5
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#define Z_RISC_V_CSR_PMPADDR54 0x3E6
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#define Z_RISC_V_CSR_PMPADDR55 0x3E7
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#define Z_RISC_V_CSR_PMPADDR56 0x3E8
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#define Z_RISC_V_CSR_PMPADDR57 0x3E9
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#define Z_RISC_V_CSR_PMPADDR58 0x3EA
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#define Z_RISC_V_CSR_PMPADDR59 0x3EB
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#define Z_RISC_V_CSR_PMPADDR60 0x3EC
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#define Z_RISC_V_CSR_PMPADDR61 0x3ED
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#define Z_RISC_V_CSR_PMPADDR62 0x3EE
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#define Z_RISC_V_CSR_PMPADDR63 0x3EF
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/* Machine Counter/Timers */
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#define Z_RISC_V_CSR_MCYCLE 0xB00
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#define Z_RISC_V_CSR_MINSTRET 0xB02
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#define Z_RISC_V_CSR_MHPMCOUNTER3 0xB03
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#define Z_RISC_V_CSR_MHPMCOUNTER4 0xB04
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#define Z_RISC_V_CSR_MHPMCOUNTER5 0xB05
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#define Z_RISC_V_CSR_MHPMCOUNTER6 0xB06
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#define Z_RISC_V_CSR_MHPMCOUNTER7 0xB07
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#define Z_RISC_V_CSR_MHPMCOUNTER8 0xB08
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#define Z_RISC_V_CSR_MHPMCOUNTER9 0xB09
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#define Z_RISC_V_CSR_MHPMCOUNTER10 0xB0A
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#define Z_RISC_V_CSR_MHPMCOUNTER11 0xB0B
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#define Z_RISC_V_CSR_MHPMCOUNTER12 0xB0C
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#define Z_RISC_V_CSR_MHPMCOUNTER13 0xB0D
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#define Z_RISC_V_CSR_MHPMCOUNTER14 0xB0E
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#define Z_RISC_V_CSR_MHPMCOUNTER15 0xB0F
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#define Z_RISC_V_CSR_MHPMCOUNTER16 0xB10
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#define Z_RISC_V_CSR_MHPMCOUNTER17 0xB11
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#define Z_RISC_V_CSR_MHPMCOUNTER18 0xB12
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#define Z_RISC_V_CSR_MHPMCOUNTER19 0xB13
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#define Z_RISC_V_CSR_MHPMCOUNTER20 0xB14
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#define Z_RISC_V_CSR_MHPMCOUNTER21 0xB15
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#define Z_RISC_V_CSR_MHPMCOUNTER22 0xB16
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#define Z_RISC_V_CSR_MHPMCOUNTER23 0xB17
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#define Z_RISC_V_CSR_MHPMCOUNTER24 0xB18
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#define Z_RISC_V_CSR_MHPMCOUNTER25 0xB19
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#define Z_RISC_V_CSR_MHPMCOUNTER26 0xB1A
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#define Z_RISC_V_CSR_MHPMCOUNTER27 0xB1B
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#define Z_RISC_V_CSR_MHPMCOUNTER28 0xB1C
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#define Z_RISC_V_CSR_MHPMCOUNTER29 0xB1D
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#define Z_RISC_V_CSR_MHPMCOUNTER30 0xB1E
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#define Z_RISC_V_CSR_MHPMCOUNTER31 0xB1F
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#define Z_RISC_V_CSR_MCYCLEH 0xB80
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#define Z_RISC_V_CSR_MINSTRETH 0xB82
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#define Z_RISC_V_CSR_MHPMCOUNTER3H 0xB83
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#define Z_RISC_V_CSR_MHPMCOUNTER4H 0xB84
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#define Z_RISC_V_CSR_MHPMCOUNTER5H 0xB85
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#define Z_RISC_V_CSR_MHPMCOUNTER6H 0xB86
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#define Z_RISC_V_CSR_MHPMCOUNTER7H 0xB87
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#define Z_RISC_V_CSR_MHPMCOUNTER8H 0xB88
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#define Z_RISC_V_CSR_MHPMCOUNTER9H 0xB89
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#define Z_RISC_V_CSR_MHPMCOUNTER10H 0xB8A
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#define Z_RISC_V_CSR_MHPMCOUNTER11H 0xB8B
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#define Z_RISC_V_CSR_MHPMCOUNTER12H 0xB8C
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#define Z_RISC_V_CSR_MHPMCOUNTER13H 0xB8D
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#define Z_RISC_V_CSR_MHPMCOUNTER14H 0xB8E
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#define Z_RISC_V_CSR_MHPMCOUNTER15H 0xB8F
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#define Z_RISC_V_CSR_MHPMCOUNTER16H 0xB90
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#define Z_RISC_V_CSR_MHPMCOUNTER17H 0xB91
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#define Z_RISC_V_CSR_MHPMCOUNTER18H 0xB92
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#define Z_RISC_V_CSR_MHPMCOUNTER19H 0xB93
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#define Z_RISC_V_CSR_MHPMCOUNTER20H 0xB94
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#define Z_RISC_V_CSR_MHPMCOUNTER21H 0xB95
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#define Z_RISC_V_CSR_MHPMCOUNTER22H 0xB96
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#define Z_RISC_V_CSR_MHPMCOUNTER23H 0xB97
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#define Z_RISC_V_CSR_MHPMCOUNTER24H 0xB98
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#define Z_RISC_V_CSR_MHPMCOUNTER25H 0xB99
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#define Z_RISC_V_CSR_MHPMCOUNTER26H 0xB9A
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#define Z_RISC_V_CSR_MHPMCOUNTER27H 0xB9B
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#define Z_RISC_V_CSR_MHPMCOUNTER28H 0xB9C
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#define Z_RISC_V_CSR_MHPMCOUNTER29H 0xB9D
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#define Z_RISC_V_CSR_MHPMCOUNTER30H 0xB9E
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#define Z_RISC_V_CSR_MHPMCOUNTER31H 0xB9F
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/* Machine Counter Setup */
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#define Z_RISC_V_CSR_MCOUNTINHIBIT 0x320
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#define Z_RISC_V_CSR_MHPMEVENT3 0x323
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#define Z_RISC_V_CSR_MHPMEVENT4 0x324
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#define Z_RISC_V_CSR_MHPMEVENT5 0x325
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#define Z_RISC_V_CSR_MHPMEVENT6 0x326
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#define Z_RISC_V_CSR_MHPMEVENT7 0x327
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#define Z_RISC_V_CSR_MHPMEVENT8 0x328
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#define Z_RISC_V_CSR_MHPMEVENT9 0x329
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#define Z_RISC_V_CSR_MHPMEVENT10 0x32A
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#define Z_RISC_V_CSR_MHPMEVENT11 0x32B
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#define Z_RISC_V_CSR_MHPMEVENT12 0x32C
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#define Z_RISC_V_CSR_MHPMEVENT13 0x32D
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#define Z_RISC_V_CSR_MHPMEVENT14 0x32E
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#define Z_RISC_V_CSR_MHPMEVENT15 0x32F
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#define Z_RISC_V_CSR_MHPMEVENT16 0x320
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#define Z_RISC_V_CSR_MHPMEVENT17 0x321
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#define Z_RISC_V_CSR_MHPMEVENT18 0x332
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#define Z_RISC_V_CSR_MHPMEVENT19 0x333
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#define Z_RISC_V_CSR_MHPMEVENT20 0x334
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#define Z_RISC_V_CSR_MHPMEVENT21 0x335
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#define Z_RISC_V_CSR_MHPMEVENT22 0x336
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#define Z_RISC_V_CSR_MHPMEVENT23 0x337
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#define Z_RISC_V_CSR_MHPMEVENT24 0x338
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#define Z_RISC_V_CSR_MHPMEVENT25 0x339
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#define Z_RISC_V_CSR_MHPMEVENT26 0x33A
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#define Z_RISC_V_CSR_MHPMEVENT27 0x33B
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#define Z_RISC_V_CSR_MHPMEVENT28 0x33C
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#define Z_RISC_V_CSR_MHPMEVENT29 0x33D
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#define Z_RISC_V_CSR_MHPMEVENT30 0x33E
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#define Z_RISC_V_CSR_MHPMEVENT31 0x33F
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/* Debug/Trace Registers (shared with Debug Mode) */
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#define Z_RISC_V_CSR_TSELECT 0x7A0
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#define Z_RISC_V_CSR_TDATA1 0x7A1
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#define Z_RISC_V_CSR_TDATA2 0x7A2
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#define Z_RISC_V_CSR_TDATA3 0x7A3
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#define Z_RISC_V_CSR_MCONTEXT 0x7A8
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/* Debug Mode Registers */
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#define Z_RISC_V_CSR_DCSR 0x7B0
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#define Z_RISC_V_CSR_DPC 0x7B1
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#define Z_RISC_V_CSR_DSCRATCH0 0x7B2
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#define Z_RISC_V_CSR_DSCRATCH1 0x7B3
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#endif /* Z_hardware_ISA_RISC_V_H */
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