Angus Gratton 67ad5852f6 Secure Boot & Flash encryption: Support 3/4 Coding Scheme ...

Includes esptool update to v2.6-beta1

2018-10-24 23:21:17 +00:00

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esp32

Secure Boot & Flash encryption: Support 3/4 Coding Scheme

2018-10-24 23:21:17 +00:00

include/soc

soc: Fix check_long_hold_gpio and move def to soc

2018-06-26 12:47:55 +05:00

test

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

CMakeLists.txt

cmake: make main a component again

2018-09-13 11:13:27 +08:00

component.mk

Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.

2017-09-04 12:05:49 +08:00