Ivan Grokhotkov 450118fdf8 soc/rtc_clk: don’t clear DPORT_CPUPERIOD_SEL when switching to XTAL ...

This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this.

2019-02-28 21:58:03 +08:00

..

esp32

soc/rtc_clk: don’t clear DPORT_CPUPERIOD_SEL when switching to XTAL

2019-02-28 21:58:03 +08:00

include/soc

soc: Fix check_long_hold_gpio and move def to soc

2018-06-26 12:47:55 +05:00

test

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

CMakeLists.txt

cmake: make main a component again

2018-09-13 11:13:27 +08:00

component.mk

Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.

2017-09-04 12:05:49 +08:00