Michael (XIAO Xufeng) ebfda40b7c refactor(spi): move pin information into soc folder

2018-06-14 11:29:15 +08:00

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esp32

refactor(spi): move pin information into soc folder

2018-06-14 11:29:15 +08:00

include/soc

refactor(spi): move pin information into soc folder

2018-06-14 11:29:15 +08:00

test

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

component.mk

Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.

2017-09-04 12:05:49 +08:00