Ivan Grokhotkov 3369f15fa3 soc/rtc: don't power down BIAS_I2C along with APLL if other PLL is used ...

If enable == false, and SOC_CLK_SEL == PLL, the code would would
erroneously set RTC_CNTL_BIAS_I2C_FORCE_PD. This change fixes the logic.

2017-11-20 15:27:16 +08:00

..

esp32

soc/rtc: don't power down BIAS_I2C along with APLL if other PLL is used

2017-11-20 15:27:16 +08:00

include/soc

Add logic to make external RAM usable with malloc()

2017-09-28 17:17:50 +08:00

test

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

component.mk

Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.

2017-09-04 12:05:49 +08:00