e65ed8c959
Sometimes the flash size read from bootloader is not correct. This may forbid SPI Flash driver from reading the the area larger than the size in bootloader header. When the new config option is enabled, the latest configured ESPTOOLPY_FLAHSIZE in the app header will be used to override the value read from bootloader header.
171 lines
7.3 KiB
C
171 lines
7.3 KiB
C
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdbool.h>
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#include <assert.h>
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#include "string.h"
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp32/rom/gpio.h"
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#include "esp32/rom/spi_flash.h"
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#include "esp32/rom/efuse.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_caps.h"
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#include "flash_qio_mode.h"
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#include "bootloader_flash_config.h"
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void bootloader_flash_update_id()
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{
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g_rom_flashchip.device_id = bootloader_read_flash_id();
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}
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void bootloader_flash_update_size(uint32_t size)
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{
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g_rom_flashchip.chip_size = size;
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}
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void IRAM_ATTR bootloader_flash_cs_timing_config()
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{
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SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
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SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
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}
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void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
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{
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uint32_t spi_clk_div = 0;
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_80M:
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spi_clk_div = 1;
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break;
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case ESP_IMAGE_SPI_SPEED_40M:
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spi_clk_div = 2;
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break;
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case ESP_IMAGE_SPI_SPEED_26M:
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spi_clk_div = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_20M:
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spi_clk_div = 4;
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break;
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default:
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break;
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}
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esp_rom_spiflash_config_clk(spi_clk_div, 0);
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esp_rom_spiflash_config_clk(spi_clk_div, 1);
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}
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void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
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{
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uint32_t drv = 2;
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if (pfhdr->spi_speed == ESP_IMAGE_SPI_SPEED_80M) {
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drv = 3;
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}
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_ver = chip_ver & 0x7;
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
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// For ESP32D2WD the SPI pins are already configured
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// flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
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// For ESP32PICOD2 the SPI pins are already configured
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// flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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// For ESP32PICOD4 the SPI pins are already configured
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// flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else {
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
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gpio_matrix_out(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
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gpio_matrix_out(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
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gpio_matrix_out(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
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gpio_matrix_in(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
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gpio_matrix_out(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
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gpio_matrix_in(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
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gpio_matrix_out(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
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gpio_matrix_in(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
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//select pin function gpio
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
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// flash clock signal should come from IO MUX.
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// set drive ability for clock
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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uint32_t flash_id = g_rom_flashchip.device_id;
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if (flash_id == FLASH_ID_GD25LQ32C) {
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// Set drive ability for 1.8v flash in 80Mhz.
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
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}
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}
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}
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}
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void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
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{
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int spi_cache_dummy = 0;
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uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));
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if (modebit & SPI_FASTRD_MODE) {
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if (modebit & SPI_FREAD_QIO) { //SPI mode is QIO
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
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} else if (modebit & SPI_FREAD_DIO) { //SPI mode is DIO
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
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} else if(modebit & (SPI_FREAD_QUAD | SPI_FREAD_DUAL)) { //SPI mode is QOUT or DIO
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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}
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}
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_80M:
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g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
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g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
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break;
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case ESP_IMAGE_SPI_SPEED_40M:
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g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
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g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
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break;
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case ESP_IMAGE_SPI_SPEED_26M:
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case ESP_IMAGE_SPI_SPEED_20M:
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g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
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g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
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break;
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default:
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break;
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}
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
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SPI_USR_DUMMY_CYCLELEN_S);
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} |