Marius Vikhammer c36dd7834f core: fix cases where riscv SP were not 16 byte aligned ...

RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.

2021-02-19 11:26:21 +08:00

..

CMakeLists.txt

cmock: added cmock as component

2020-09-02 16:38:37 +08:00

component.mk

add unit tests to esp-idf

2016-11-22 14:45:50 +08:00

test_locks.c

newlib: add _RETARGETABLE_LOCKING support

2020-12-29 16:18:04 +01:00

test_newlib.c

core: fix cases where riscv SP were not 16 byte aligned

2021-02-19 11:26:21 +08:00

test_setjmp.c

freertos: save/restore PS and EPC1 around window spilling

2019-12-27 11:27:01 +01:00

test_shared_stack_printf.c

core: fix cases where riscv SP were not 16 byte aligned

2021-02-19 11:26:21 +08:00

test_time.c

esp32c3: Apply one-liner/small changes for ESP32-C3

2020-12-01 10:58:50 +11:00