Angus Gratton 654d6ee594 efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field ...

8th bit is not used by hardware.

As reported https://esp32.com/viewtopic.php?f=2&t=7800&p=40895#p40894

2019-04-09 09:59:15 +10:00

..

include/soc

efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field

2019-04-09 09:59:15 +10:00

test

ci: Only run XTAL unit tests assuming board has an XTAL, run less repeats

2018-05-15 15:43:24 +08:00

cpu_util.c

esp_restart: fix possible race while stalling other CPU, enable WDT early

2017-10-26 19:53:53 +08:00

gpio_periph.c

soc: Fix check_long_hold_gpio and move def to soc

2018-06-26 12:47:55 +05:00

i2c_apll.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

i2c_bbpll.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

i2c_rtc_clk.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

rtc_clk.c

soc: define named constants for DPORT_CPUPERIOD_SEL values

2019-02-28 21:58:03 +08:00

rtc_init.c

soc: rtc_vddsdio_get_config() In default configuration, VDD_SDIO LDO is always enabled

2018-05-25 15:14:13 +10:00

rtc_periph.c

Fix errors in rtc_gpio_desc values

2018-07-19 10:27:31 +03:00

rtc_pm.c

soc/rtc: don’t switch frequency in rtc_sleep_init

2018-04-26 18:52:45 +08:00

rtc_sleep.c

sleep: optimize light sleep wakeup latency

2018-04-26 19:36:47 +08:00

rtc_time.c

component/bt: implement bluetooth modem sleep mode, one mode for BLE only and another for dual mode bluetooth

2018-05-19 15:37:26 +08:00

soc_log.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

soc_memory_layout.c

Add logic to make external RAM usable with malloc()

2017-09-28 17:17:50 +08:00

sources.cmake

cmake: make main a component again

2018-09-13 11:13:27 +08:00

spi_periph.c

refactor(spi): move pin information into soc folder

2018-06-14 11:29:15 +08:00