Introduced in 9c23b8e5 and 4f87a62f. To get higher speed, menuconfig
options are added to put ISR and other functions into the IRAM. The
interrupt flag ESP_INTR_FLAG_IRAM is also mistakenly set when the ISR is
put into the IRAM. However callbacks, which are wrote by the user, are
called in the master and slave ISR. The user may not be aware of that
these callbacks are not disabled during flash operations. Any cache miss
during flash operation will cause panic.
Essentially IRAM functions and intrrupt flag ESP_INTR_FLAG_IRAM are
different, the latter means not disabling the ISR during flash
operations. New bus_config flag intr_flags is offered to help set the
interrupt attribute, including priority level, SHARED, IRAM (not
disabled during flash operations). It introduced a small BREAK to
IDFv3.1 (but the same as IDFv3.0) that the user has to manually set IRAM
flag now (therefore he's aware of the IRAM thing) to void the ISR being
disabled during flash operations.
If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
New unity component can be used for testing other applications.
Upstream version of Unity is included as a submodule.
Utilities specific to ESP-IDF unit tests (partitions, leak checking
setup/teardown functions, etc) are kept only in unit-test-app.
Kconfig options are added to allow disabling certain Unity features.
1. call esp_timer_get_time and ref_clock_get in the same order on
start and in the loop
2. disable interrupts when calculating delta between ref_clock
and esp_timer
3. ensure both functions are in cache before calculating the delta
mdns queries did not work properly when send imeadiately after set_hostname, which cuased reinit of pcb and therefore restarted probing, so search packets were blocked until probing finished
closes#2507, closes#2593
1. Fix the bug that disable controller suddenly cause crash when ble is working. (585cfba1)
2. Fix the bug that when disable controller, it will cause wifi cannot RX, TX timeout, buffer lack and etc. (f8546145)
It is an ESP specific FreeRTOS feature that the ISR is always executed
on the core which calls the interrupt register function. In the SPI
driver, the function is always called in the bus initialization
function.
Hence, the ISR will be executed on the core which initialize the driver.
If the core is starved due to higher priority ISRs, or the interrupt is
disabled on the core (spinlock called, etc.), the ISR will not get
executed and SPI transactions will not be handled.
(MINOR CHANGE)
Resolves https://github.com/espressif/esp-idf/issues/2432.
The MISO signal will be delayed if the GPIO matrix is enabled.
However, delay also comes from the slave.
Previous code only considers the former case, and assume the frequency
limitations is only violated when GPIO matrix is used.
Now we are able to calculate the freq limit when extenal MISO delay is
given (feature introduced in 9c6c6ec34ab0641ace89aeb9b1a133eb6fae1a18).
The frequency limit is lower when the external MISO delay is large, and
the limit is likely to be violated even with IOMUX.
Resolves https://github.com/espressif/esp-idf/issues/2690.
1. If L2_TO_L3_RX_BUF_MODE is not selected, we must assign l2_owner explictly before we call pbuf_free.
2. free intr resource in esp_eth_deinit
Closes https://github.com/espressif/esp-idf/issues/2670
