spi: apply gdma allocator to SPI
This commit is contained in:
@@ -72,6 +72,7 @@ typedef struct {
|
||||
typedef struct {
|
||||
spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address
|
||||
spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address
|
||||
bool dma_enabled; ///< Whether the DMA is enabled, do not update after initialization
|
||||
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
@@ -80,8 +81,10 @@ typedef struct {
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
uint32_t tx_dma_chan; ///< TX DMA channel
|
||||
uint32_t rx_dma_chan; ///< RX DMA channel
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
} spi_hal_dma_config_t;
|
||||
} spi_hal_config_t;
|
||||
|
||||
/**
|
||||
* Transaction configuration structure, this should be assigned by driver each time.
|
||||
@@ -104,12 +107,24 @@ typedef struct {
|
||||
* Context that should be maintained by both the driver and the HAL.
|
||||
*/
|
||||
typedef struct {
|
||||
/* These two need to be malloced by the driver first */
|
||||
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
|
||||
/* Configured by driver at initialization, don't touch */
|
||||
spi_dev_t *hw; ///< Beginning address of the peripheral registers.
|
||||
spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM (DMA -> RAM).
|
||||
spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral (RAM -> DMA).
|
||||
bool dma_enabled; ///< Whether the DMA is enabled, do not update after initialization
|
||||
spi_hal_dma_config_t dma_config; ///< DMA configuration
|
||||
uint32_t tx_dma_chan; ///< TX DMA channel
|
||||
uint32_t rx_dma_chan; ///< RX DMA channel
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
|
||||
/* Internal parameters, don't touch */
|
||||
spi_hal_trans_config_t trans_config; ///< Transaction configuration
|
||||
@@ -144,10 +159,11 @@ typedef struct {
|
||||
/**
|
||||
* Init the peripheral and the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
|
||||
* @param hal_config Configuration of the hal defined by the upper layer.
|
||||
*/
|
||||
void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_dma_config_t *hal_dma_config);
|
||||
void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config_t *hal_config);
|
||||
|
||||
/**
|
||||
* Deinit the peripheral (and the context if needed).
|
||||
|
||||
@@ -55,7 +55,9 @@ typedef struct {
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
uint32_t tx_dma_chan; ///< TX DMA channel
|
||||
uint32_t rx_dma_chan; ///< RX DMA channel
|
||||
|
||||
/*
|
||||
* configurations to be filled after ``spi_slave_hal_init``. Updated to
|
||||
|
||||
@@ -70,7 +70,9 @@ typedef struct {
|
||||
uint32_t host_id; ///< Host ID of the spi peripheral
|
||||
spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address
|
||||
spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address
|
||||
uint32_t dma_chan; ///< The dma channel used.
|
||||
bool dma_enabled; ///< DMA enabled or not
|
||||
uint32_t tx_dma_chan; ///< TX DMA channel used.
|
||||
uint32_t rx_dma_chan; ///< RX DMA channel used.
|
||||
bool append_mode; ///< True for DMA append mode, false for segment mode
|
||||
uint32_t spics_io_num; ///< CS GPIO pin for this device
|
||||
uint8_t mode; ///< SPI mode (0-3)
|
||||
@@ -94,7 +96,9 @@ typedef struct {
|
||||
spi_dev_t *dev; ///< Beginning address of the peripheral registers.
|
||||
spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM.
|
||||
spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral.
|
||||
|
||||
bool dma_enabled; ///< DMA enabled or not
|
||||
uint32_t tx_dma_chan; ///< TX DMA channel used.
|
||||
uint32_t rx_dma_chan; ///< RX DMA channel used.
|
||||
bool append_mode; ///< True for DMA append mode, false for segment mode
|
||||
uint32_t dma_desc_num; ///< Number of the available DMA descriptors. Calculated from ``bus_max_transfer_size``.
|
||||
spi_slave_hd_hal_desc_append_t *tx_cur_desc; ///< Current TX DMA descriptor that could be linked (set up).
|
||||
|
||||
Reference in New Issue
Block a user