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psram: add ESP32-D0WD-R2-V3 support

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This commit is contained in:
Cao Sen Miao
2021-11-10 12:50:12 +08:00
parent f104bf1b76
commit ce1ee3d8ae
5 changed files with 25 additions and 14 deletions
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1
components/esp_hw_support/include/esp_chip_info.h
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@@ -34,6 +34,7 @@ typedef enum {
#define CHIP_FEATURE_BLE BIT(4) //!< Chip has Bluetooth LE
#define CHIP_FEATURE_BT BIT(5) //!< Chip has Bluetooth Classic
#define CHIP_FEATURE_IEEE802154 BIT(6) //!< Chip has IEEE 802.15.4
#define CHIP_FEATURE_EMB_PSRAM BIT(7) //!< Chip has embedded psram
/**
* @brief The structure represents information about the chip

3
components/esp_hw_support/port/esp32/chip_info.c
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@@ -34,6 +34,9 @@ void esp_chip_info(esp_chip_info_t* out_info)
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
out_info->features |= CHIP_FEATURE_EMB_FLASH;
}
if(package == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3) {
out_info->features |= CHIP_FEATURE_EMB_PSRAM;
}
}
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX

15
components/esp_hw_support/port/esp32/spiram_psram.c
View File

@@ -111,6 +111,11 @@ typedef enum {
#define D2WD_PSRAM_CLK_IO CONFIG_D2WD_PSRAM_CLK_IO // Default value is 9
#define D2WD_PSRAM_CS_IO CONFIG_D2WD_PSRAM_CS_IO // Default value is 10
// There is no reason to change the pin of an embedded psram.
// So define the number of pin directly, instead of configurable.
#define D0WDR2_V3_PSRAM_CLK_IO 6
#define D0WDR2_V3_PSRAM_CS_IO 16
// For ESP32-PICO chip, the psram share clock with flash. The flash clock pin is fixed, which is IO6.
#define PICO_PSRAM_CLK_IO 6
#define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO // Default value is 10
@@ -842,6 +847,16 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WD");
psram_io.psram_clk_io = D0WD_PSRAM_CLK_IO;
psram_io.psram_cs_io = D0WD_PSRAM_CS_IO;
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3){
ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WDR2-V3");
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
return ESP_FAIL;
}
s_clk_mode = PSRAM_CLK_MODE_NORM;
psram_io.psram_clk_io = D0WDR2_V3_PSRAM_CLK_IO;
psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO;
} else {
ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
abort();