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bootloader: move bootloader flash support to isolate folders

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This commit is contained in:
Cao Sen Miao
2021-11-08 15:10:13 +08:00
parent 3a4db97cec
commit b0decda1e3
40 changed files with 474 additions and 196 deletions
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2
components/app_update/test/test_switch_ota.c
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@@ -21,7 +21,7 @@
#include "unity.h"
#include "bootloader_common.h"
#include "../include_bootloader/bootloader_flash_priv.h"
#include "../include_bootloader/bootloader_flash_private/bootloader_flash_priv.h"
#include "esp_log.h"
#include "esp_ota_ops.h"

13
components/bootloader_support/CMakeLists.txt
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@@ -2,7 +2,7 @@ set(srcs
"src/bootloader_common.c"
"src/bootloader_common_loader.c"
"src/bootloader_clock_init.c"
"src/bootloader_flash.c"
"src/flash_support/bootloader_flash.c"
"src/bootloader_mem.c"
"src/bootloader_random.c"
"src/bootloader_random_${IDF_TARGET}.c"
@@ -11,13 +11,14 @@ set(srcs
"src/flash_encrypt.c"
"src/secure_boot.c"
"src/flash_partitions.c"
"src/flash_qio_mode.c"
"src/bootloader_flash_config_${IDF_TARGET}.c"
"src/flash_support/flash_qio_mode.c"
"src/flash_support/bootloader_flash_config_${IDF_TARGET}.c"
"src/bootloader_efuse_${IDF_TARGET}.c"
)
if(BOOTLOADER_BUILD)
set(include_dirs "include" "include_bootloader")
set(include_dirs "include" "bootloader_flash/include"
"include_bootloader" "include_bootloader/bootloader_flash_private")
set(priv_requires micro-ecc spi_flash efuse)
list(APPEND srcs
"src/bootloader_init.c"
@@ -33,8 +34,8 @@ if(BOOTLOADER_BUILD)
else()
list(APPEND srcs
"src/idf/bootloader_sha.c")
set(include_dirs "include")
set(priv_include_dirs "include_bootloader")
set(include_dirs "include" "bootloader_flash/include")
set(priv_include_dirs "include_bootloader" "include_bootloader/bootloader_flash_private")
# heap is required for `heap_memory_layout.h` header
set(priv_requires spi_flash mbedtls efuse app_update heap)
endif()

0
components/bootloader_support/include/bootloader_flash.h → components/bootloader_support/bootloader_flash/include/bootloader_flash.h
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0
components/bootloader_support/include/bootloader_flash_config.h → components/bootloader_support/bootloader_flash/include/bootloader_flash_config.h
View File

0
components/bootloader_support/include_bootloader/bootloader_flash_priv.h → components/bootloader_support/include_bootloader/bootloader_flash_private/bootloader_flash_priv.h
View File

0
components/bootloader_support/include_bootloader/flash_qio_mode.h → components/bootloader_support/include_bootloader/bootloader_flash_private/flash_qio_mode.h
View File

4
components/bootloader_support/src/bootloader_flash.c → components/bootloader_support/src/flash_support/bootloader_flash.c
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@@ -509,10 +509,6 @@ esp_err_t IRAM_ATTR __attribute__((weak)) bootloader_flash_unlock(void)
return err;
}
/* dummy_len_plus values defined in ROM for SPI flash configuration */
#ifndef g_rom_spiflash_dummy_len_plus // ESP32-C3 uses a macro to access ROM data here
extern uint8_t g_rom_spiflash_dummy_len_plus[];
#endif
IRAM_ATTR static uint32_t bootloader_flash_execute_command_common(
uint8_t command,
uint32_t addr_len, uint32_t address,

4
components/bootloader_support/src/bootloader_flash_config_esp32.c → components/bootloader_support/src/flash_support/bootloader_flash_config_esp32.c
View File

@@ -11,6 +11,7 @@
#include "esp_log.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp32/rom/spi_flash.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
@@ -20,7 +21,7 @@
#include "flash_qio_mode.h"
#include "bootloader_common.h"
#include "bootloader_flash_config.h"
#include "esp_rom_spiflash.h"
void bootloader_flash_update_id(void)
{
@@ -134,7 +135,6 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
}
}
extern uint8_t g_rom_spiflash_dummy_len_plus[];
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_80M:
g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;

2
components/bootloader_support/src/bootloader_flash_config_esp32c3.c → components/bootloader_support/src/flash_support/bootloader_flash_config_esp32c3.c
View File

@@ -10,6 +10,7 @@
#include "esp_err.h"
#include "esp_log.h"
#include "esp32c3/rom/gpio.h"
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
@@ -19,7 +20,6 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "esp_rom_spiflash.h"
#define FLASH_IO_MATRIX_DUMMY_40M 0
#define FLASH_IO_MATRIX_DUMMY_80M 0

2
components/bootloader_support/src/bootloader_flash_config_esp32h2.c → components/bootloader_support/src/flash_support/bootloader_flash_config_esp32h2.c
View File

@@ -10,6 +10,7 @@
#include "esp_err.h"
#include "esp_log.h"
#include "esp32h2/rom/gpio.h"
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
@@ -19,7 +20,6 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "esp_rom_spiflash.h"
#define FLASH_IO_MATRIX_DUMMY_40M 0
#define FLASH_IO_MATRIX_DUMMY_80M 0

2
components/bootloader_support/src/bootloader_flash_config_esp32s2.c → components/bootloader_support/src/flash_support/bootloader_flash_config_esp32s2.c
View File

@@ -9,6 +9,7 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp32s2/rom/spi_flash.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
#include "soc/spi_mem_reg.h"
@@ -16,7 +17,6 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "esp_rom_spiflash.h"
#define FLASH_IO_MATRIX_DUMMY_40M 0
#define FLASH_IO_MATRIX_DUMMY_80M 0

2
components/bootloader_support/src/bootloader_flash_config_esp32s3.c → components/bootloader_support/src/flash_support/bootloader_flash_config_esp32s3.c
View File

@@ -9,6 +9,7 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp32s3/rom/spi_flash.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
#include "soc/spi_mem_reg.h"
@@ -16,7 +17,6 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "esp_rom_spiflash.h"
#define FLASH_IO_MATRIX_DUMMY_40M 0
#define FLASH_IO_MATRIX_DUMMY_80M 0

2
components/bootloader_support/src/bootloader_flash_config_esp8684.c → components/bootloader_support/src/flash_support/bootloader_flash_config_esp8684.c
View File

@@ -10,8 +10,8 @@
#include "esp_err.h"
#include "esp_log.h"
#include "esp8684/rom/gpio.h"
#include "esp8684/rom/spi_flash.h"
#include "esp8684/rom/efuse.h"
#include "esp_rom_spiflash.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"

0
components/bootloader_support/src/flash_qio_mode.c → components/bootloader_support/src/flash_support/flash_qio_mode.c
View File

2
components/efuse/src/esp_efuse_utility.c
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@@ -404,7 +404,7 @@ void esp_efuse_init_virtual_mode_in_ram(void)
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
#include "../include_bootloader/bootloader_flash_priv.h"
#include "../include_bootloader/bootloader_flash_private/bootloader_flash_priv.h"
static uint32_t esp_efuse_flash_offset = 0;
static uint32_t esp_efuse_flash_size = 0;

2
components/esp_hw_support/port/esp32/spiram_psram.c
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@@ -17,6 +17,7 @@
#include "esp_log.h"
#include "esp_efuse.h"
#include "spiram_psram.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/efuse.h"
#include "esp_rom_efuse.h"
@@ -30,7 +31,6 @@
#include "bootloader_common.h"
#include "esp_rom_gpio.h"
#include "bootloader_flash_config.h"
#include "esp_rom_spiflash.h"
#if CONFIG_SPIRAM
#include "soc/rtc.h"

2
components/esp_hw_support/port/esp32s2/spiram_psram.c
View File

@@ -16,6 +16,7 @@
#include "esp_types.h"
#include "esp_log.h"
#include "spiram_psram.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/opi_flash.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/efuse.h"
@@ -32,7 +33,6 @@
#include "driver/spi_common.h"
#include "esp_private/periph_ctrl.h"
#include "bootloader_common.h"
#include "esp_rom_spiflash.h"
#if CONFIG_SPIRAM
#include "soc/rtc.h"

2
components/esp_hw_support/port/esp32s3/opiram_psram.c
View File

@@ -12,6 +12,7 @@
#include "esp_log.h"
#include "spiram_psram.h"
#include "esp32s3/rom/ets_sys.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#include "esp32s3/rom/gpio.h"
#include "esp32s3/rom/cache.h"
@@ -23,7 +24,6 @@
#include "driver/gpio.h"
#include "driver/spi_common.h"
#include "esp_private/periph_ctrl.h"
#include "esp_rom_spiflash.h"
#if CONFIG_SPIRAM_MODE_OCT
#include "soc/rtc.h"

2
components/esp_hw_support/port/esp32s3/spiram_psram.c
View File

@@ -16,6 +16,7 @@
#include "esp_types.h"
#include "esp_log.h"
#include "spiram_psram.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/efuse.h"
@@ -34,7 +35,6 @@
#include "driver/spi_common.h"
#include "esp_private/periph_ctrl.h"
#include "bootloader_common.h"
#include "esp_rom_spiflash.h"
#if CONFIG_SPIRAM_MODE_QUAD
#include "soc/rtc.h"

78
components/esp_rom/include/esp32/rom/spi_flash.h
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@@ -4,15 +4,13 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "sdkconfig.h"
#include "esp_rom_spiflash.h"
#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
#include "soc/spi_reg.h"
@@ -115,20 +113,72 @@ extern "C" {
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
extern uint8_t g_rom_spiflash_dummy_len_plus[];
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @}
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

79
components/esp_rom/include/esp32c3/rom/spi_flash.h
View File

@@ -4,13 +4,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
@@ -70,12 +69,6 @@ extern "C" {
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
@@ -98,8 +91,72 @@ typedef struct {
spi_flash_op_t wait_idle;
} spiflash_legacy_funcs_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

85
components/esp_rom/include/esp32h2/rom/spi_flash.h
View File

@@ -4,13 +4,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
@@ -70,12 +69,6 @@ extern "C" {
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
@@ -83,8 +76,13 @@ typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
typedef struct {
uint8_t pp_addr_bit_len;
uint8_t se_addr_bit_len;
uint8_t be_addr_bit_len;
uint8_t rd_addr_bit_len;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
@@ -96,18 +94,75 @@ typedef struct {
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @}
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

2
components/esp_rom/include/esp32s2/rom/opi_flash.h
View File

@@ -8,7 +8,7 @@
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "esp_rom_spiflash.h"
#include "spi_flash.h"
#ifdef __cplusplus
extern "C" {

77
components/esp_rom/include/esp32s2/rom/spi_flash.h
View File

@@ -4,8 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#ifndef CONFIG_IDF_TARGET_ESP32S2
#error This file should only be included for ESP32-S2 target
@@ -13,9 +12,9 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/spi_mem_reg.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
@@ -106,20 +105,72 @@ extern "C" {
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
extern uint8_t g_rom_spiflash_dummy_len_plus[];
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @}
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

2
components/esp_rom/include/esp32s3/rom/opi_flash.h
View File

@@ -9,7 +9,7 @@
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include "esp_rom_spiflash.h"
#include "spi_flash.h"
#ifdef __cplusplus
extern "C" {

74
components/esp_rom/include/esp32s3/rom/spi_flash.h
View File

@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
@@ -98,13 +99,6 @@ extern "C" {
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef void (*spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (*spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (*spi_flash_erase_t)(uint32_t);
@@ -133,6 +127,72 @@ typedef struct {
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif

85
components/esp_rom/include/esp8684/rom/spi_flash.h
View File

@@ -4,13 +4,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
@@ -70,12 +69,6 @@ extern "C" {
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
@@ -83,8 +76,13 @@ typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
typedef struct {
uint8_t pp_addr_bit_len;
uint8_t se_addr_bit_len;
uint8_t be_addr_bit_len;
uint8_t rd_addr_bit_len;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
@@ -96,10 +94,75 @@ typedef struct {
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

103
components/esp_rom/include/esp_rom_spiflash.h
View File

@@ -7,36 +7,14 @@
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "sdkconfig.h"
#include <stdint.h>
#include <stdbool.h>
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp32h2/rom/spi_flash.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
@@ -69,59 +47,11 @@ typedef struct {
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
@@ -130,7 +60,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
@@ -220,18 +150,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
/**
* @brief Unlock SPI write protect.
* Please do not call this function in SDK.
@@ -460,14 +378,15 @@ typedef struct {
esp_rom_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
} spiflash_legacy_data_t;
} esp_rom_spiflash_legacy_data_t;
/* Flash data defined in ROM*/
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
extern esp_rom_spiflash_chip_t g_rom_flashchip;
extern uint8_t g_rom_spiflash_dummy_len_plus[];
#else
extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
extern esp_rom_spiflash_legacy_data_t *rom_spiflash_legacy_data;
#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
#endif

11
components/esp_rom/patches/esp_rom_spiflash.c
View File

@@ -5,18 +5,21 @@
*/
#include "sdkconfig.h"
#include "esp_rom_spiflash.h"
#include "soc/spi_periph.h"
#include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#endif
#define SPI_IDX 1
extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
#if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
#if CONFIG_IDF_TARGET_ESP32
extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
static inline bool is_issi_chip(const esp_rom_spiflash_chip_t* chip)
{
return (((chip->device_id >> 16)&0xff) == 0x9D);

1
components/fatfs/test_fatfs_host/Makefile.files
View File

@@ -35,6 +35,7 @@ INCLUDE_DIRS := \
esp32/include \
esp_common/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
spi_flash/include \

2
components/spi_flash/esp32s3/spi_flash_oct_flash_init.c
View File

@@ -9,7 +9,7 @@
#include "esp_err.h"
#include "esp_rom_gpio.h"
#include "esp32s3/rom/gpio.h"
#include "esp_rom_spiflash.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#include "esp_private/spi_flash_os.h"
#include "opi_flash_private.h"

2
components/spi_flash/esp32s3/spi_timing_config.h
View File

@@ -7,7 +7,7 @@
#pragma once
#include "esp_flash_partitions.h"
#include "esp_rom_spiflash.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#include "mspi_timing_tuning_configs.h"

1
components/spi_flash/flash_ops.c
View File

@@ -24,6 +24,7 @@
#include "esp_private/esp_clk.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32S3

2
components/spi_flash/include/esp_private/spi_flash_os.h
View File

@@ -19,10 +19,10 @@
*/
#pragma once
#include "esp_rom_spiflash.h"
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_rom_spiflash.h"
#include "esp_err.h"
#include "esp_flash.h"
#include "hal/spi_flash_hal.h"

1
components/spi_flash/sim/Makefile.files
View File

@@ -37,6 +37,7 @@ INCLUDE_DIRS := \
esp32/include \
esp_timer/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
hal/esp32/include \

1
components/spi_flash/sim/stubs/Makefile.files
View File

@@ -31,6 +31,7 @@ INCLUDE_DIRS := \
esp32/include \
esp_timer/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
spi_flash/include \

14
components/spi_flash/test/test_read_write.c
View File

@@ -18,7 +18,19 @@
#include "../cache_utils.h"
#include "soc/timer_periph.h"
#include "esp_heap_caps.h"
#include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#endif
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP8684)
// TODO: SPI_FLASH IDF-4025

1
components/spiffs/test_spiffs_host/Makefile.files
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@@ -35,6 +35,7 @@ INCLUDE_DIRS := \
soc/include \
esp32/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
spi_flash/include \
hal/include \

1
components/wear_levelling/test_wl_host/Makefile.files
View File

@@ -35,6 +35,7 @@ INCLUDE_DIRS := \
soc/include \
esp32/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
spi_flash/include \