esp32: move brownout and cache err int setup

components/esp_system/port/CMakeLists.txt

@@ -1,4 +1,4 @@
-target_include_directories(${COMPONENT_LIB} PRIVATE include .)
+target_include_directories(${COMPONENT_LIB} PRIVATE include . PUBLIC soc)
 
 set(srcs "cpu_start.c" "panic_handler.c" "brownout.c")
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})

components/esp_system/port/arch/riscv/panic_arch.c

@@ -18,15 +18,12 @@
 #include "esp_private/panic_internal.h"
 #include "esp_private/panic_reason.h"
 #include "riscv/rvruntime-frames.h"
+#include "cache_err_int.h"
 
-#if CONFIG_IDF_TARGET_ESP32C3
-#include "esp32c3/cache_err_int.h"
-#endif
 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #include "esp32c3/memprot.h"
 #endif
 
-
 #define DIM(array) (sizeof(array)/sizeof(*array))
 
 /**

components/esp_system/port/arch/xtensa/panic_arch.c

@@ -21,21 +21,19 @@
 #include "esp_private/panic_reason.h"
 #include "soc/soc.h"
 
+#include "cache_err_int.h"
+
 #include "sdkconfig.h"
 
-#if CONFIG_IDF_TARGET_ESP32
-#include "esp32/cache_err_int.h"
-#else
+#if !CONFIG_IDF_TARGET_ESP32
 #include "soc/extmem_reg.h"
 #include "soc/cache_memory.h"
 #include "soc/rtc_cntl_reg.h"
 #if CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/cache_err_int.h"
 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #include "esp32s2/memprot.h"
 #endif
 #elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/cache_err_int.h"
 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #include "esp32s3/memprot.h"
 #endif

components/esp_system/port/cpu_start.c

@@ -23,6 +23,7 @@
 #include "esp_system.h"
 
 #include "esp_efuse.h"
+#include "cache_err_int.h"
 #include "esp_clk_internal.h"
 
 #include "esp_rom_efuse.h"
@@ -33,14 +34,11 @@
 #if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
 #include "esp32/rtc.h"
-#include "esp32/cache_err_int.h"
 #include "esp32/rom/cache.h"
 #include "esp32/rom/rtc.h"
 #include "esp32/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rtc.h"
-#include "esp32s2/brownout.h"
-#include "esp32s2/cache_err_int.h"
 #include "esp32s2/rom/cache.h"
 #include "esp32s2/rom/rtc.h"
 #include "esp32s2/spiram.h"
@@ -48,8 +46,6 @@
 #include "esp32s2/memprot.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rtc.h"
-#include "esp32s3/brownout.h"
-#include "esp32s3/cache_err_int.h"
 #include "esp32s3/rom/cache.h"
 #include "esp32s3/rom/rtc.h"
 #include "esp32s3/spiram.h"
@@ -60,7 +56,6 @@
 #include "soc/system_reg.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rtc.h"
-#include "esp32c3/cache_err_int.h"
 #include "esp32s3/rom/cache.h"
 #include "esp32c3/rom/rtc.h"
 #include "soc/cache_memory.h"

components/esp_system/port/include/brownout.h

@@ -0,0 +1,31 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_BROWNOUT_H
+#define __ESP_BROWNOUT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void esp_brownout_init(void);
+
+void esp_brownout_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/esp_system/port/include/cache_err_int.h

@@ -0,0 +1,45 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief initialize cache invalid access interrupt
+ *
+ * This function enables cache invalid access interrupt source and connects it
+ * to interrupt input number. It is called from the startup code.
+ *
+ * On ESP32, the interrupt input number is ETS_MEMACCESS_ERR_INUM. On other targets
+ * it is ETS_CACHEERR_INUM. See soc/soc.h for more information.
+ */
+void esp_cache_err_int_init(void);
+
+
+/**
+ * @brief get the CPU which caused cache invalid access interrupt. Helper function in
+ * panic handling.
+ * @return
+ *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
+ *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
+ *  - (-1) otherwise
+ */
+int esp_cache_err_get_cpuid(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_system/port/panic_handler.c

@@ -25,21 +25,19 @@
 #include "hal/soc_hal.h"
 #include "hal/cpu_hal.h"
 
+#include "cache_err_int.h"
+
 #include "sdkconfig.h"
 #include "esp_rom_sys.h"
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/dport_access.h"
-#include "esp32/cache_err_int.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/memprot.h"
-#include "esp32s2/cache_err_int.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/memprot.h"
-#include "esp32s3/cache_err_int.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/memprot.h"
-#include "esp32c3/cache_err_int.h"
 #endif
 
 #include "esp_private/panic_internal.h"

components/esp_system/port/soc/esp32/CMakeLists.txt

@@ -1,6 +1,7 @@
 set(srcs "dport_panic_highint_hdl.S"
          "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../arch/xtensa/panic_arch.c"
          "../../arch/xtensa/panic_handler_asm.S"
          "../../arch/xtensa/expression_with_stack.c"

components/esp_system/port/soc/esp32/cache_err_int.c

@@ -0,0 +1,105 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ The cache has an interrupt that can be raised as soon as an access to a cached
+ region (flash, psram) is done without the cache being enabled. We use that here
+ to panic the CPU, which from a debugging perspective is better than grabbing bad
+ data from the bus.
+*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+
+#include "esp_err.h"
+#include "esp_attr.h"
+
+#include "esp_intr_alloc.h"
+#include "soc/dport_reg.h"
+#include "hal/cpu_hal.h"
+
+#include "esp32/dport_access.h"
+#include "esp32/rom/ets_sys.h" // for intr_matrix_set
+
+#include "sdkconfig.h"
+
+void esp_cache_err_int_init(void)
+{
+    uint32_t core_id = cpu_hal_get_core_id();
+    ESP_INTR_DISABLE(ETS_MEMACCESS_ERR_INUM);
+
+    // We do not register a handler for the interrupt because it is interrupt
+    // level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
+    // a call to the panic handler for
+    // this interrupt.
+    intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
+
+    // Enable invalid cache access interrupt when the cache is disabled.
+    // When the interrupt happens, we can not determine the CPU where the
+    // invalid cache access has occurred. We enable the interrupt to catch
+    // invalid access on both CPUs, but the interrupt is connected to the
+    // CPU which happens to call this function.
+    // For this reason, panic handler backtrace will not be correct if the
+    // interrupt is connected to PRO CPU and invalid access happens on the APP
+    // CPU.
+
+    if (core_id == PRO_CPU_NUM) {
+        DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
+            DPORT_CACHE_IA_INT_PRO_OPPOSITE |
+            DPORT_CACHE_IA_INT_PRO_DRAM1 |
+            DPORT_CACHE_IA_INT_PRO_DROM0 |
+            DPORT_CACHE_IA_INT_PRO_IROM0 |
+            DPORT_CACHE_IA_INT_PRO_IRAM0 |
+            DPORT_CACHE_IA_INT_PRO_IRAM1);
+    } else {
+        DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
+            DPORT_CACHE_IA_INT_APP_OPPOSITE |
+            DPORT_CACHE_IA_INT_APP_DRAM1 |
+            DPORT_CACHE_IA_INT_APP_DROM0 |
+            DPORT_CACHE_IA_INT_APP_IROM0 |
+            DPORT_CACHE_IA_INT_APP_IRAM0 |
+            DPORT_CACHE_IA_INT_APP_IRAM1);
+    }
+    ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
+}
+
+int IRAM_ATTR esp_cache_err_get_cpuid(void)
+{
+    const uint32_t pro_mask =
+            DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |
+            DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 |
+            DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 |
+            DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 |
+            DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 |
+            DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE;
+
+    if (DPORT_GET_PERI_REG_MASK(DPORT_PRO_DCACHE_DBUG3_REG, pro_mask)) {
+        return PRO_CPU_NUM;
+    }
+
+    const uint32_t app_mask =
+            DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 |
+            DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 |
+            DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 |
+            DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 |
+            DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 |
+            DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE;
+
+    if (DPORT_GET_PERI_REG_MASK(DPORT_APP_DCACHE_DBUG3_REG, app_mask)) {
+        return APP_CPU_NUM;
+    }
+    return -1;
+}

components/esp_system/port/soc/esp32/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/port/soc/esp32c3/CMakeLists.txt

@@ -1,5 +1,6 @@
 set(srcs "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../async_memcpy_impl_gdma.c"
          "apb_backup_dma.c"
          "../../arch/riscv/expression_with_stack.c"

components/esp_system/port/soc/esp32c3/cache_err_int.c

@@ -0,0 +1,102 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ The cache has an interrupt that can be raised as soon as an access to a cached
+ region (flash) is done without the cache being enabled. We use that here
+ to panic the CPU, which from a debugging perspective is better than grabbing bad
+ data from the bus.
+*/
+#include "esp32c3/rom/ets_sys.h"
+#include "esp_attr.h"
+#include "esp_intr_alloc.h"
+#include "soc/extmem_reg.h"
+#include "soc/periph_defs.h"
+#include "riscv/interrupt.h"
+
+void esp_cache_err_int_init(void)
+{
+    const uint32_t core_id = 0;
+
+    /* Disable cache interrupts if enabled. */
+    ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
+
+    /**
+     *  Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with
+     * them in handler by different types
+     * I) Cache access error
+     *     1. dbus trying to write to icache
+     *     2. dbus authentication fail
+     *     3. cpu access icache while dbus is disabled [1]
+     *     4. ibus authentication fail
+     *     5. ibus trying to write icache
+     *     6. cpu access icache while ibus is disabled
+     * II) Cache illegal error
+     *     1. dbus counter overflow
+     *     2. ibus counter overflow
+     *     3. mmu entry fault
+     *     4. icache preload configurations fault
+     *     5. icache sync configuration fault
+     *
+     * [1]: On ESP32C3 boards, the caches are shared but buses are still
+     * distinct. So, we have an ibus and a dbus sharing the same cache.
+     * This error can occur if the dbus performs a request but the icache
+     * (or simply cache) is disabled.
+     */
+    intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
+    intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
+
+    /* Set the type and priority to cache error interrupts. */
+    esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);
+    esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+
+    /* On the hardware side, stat by clearing all the bits reponsible for
+    * enabling cache access error interrupts.  */
+    SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG,
+                      EXTMEM_CORE0_DBUS_WR_IC_INT_CLR |
+                      EXTMEM_CORE0_DBUS_REJECT_INT_CLR |
+                      EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR |
+                      EXTMEM_CORE0_IBUS_REJECT_INT_CLR |
+                      EXTMEM_CORE0_IBUS_WR_IC_INT_CLR |
+                      EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR);
+
+    /* Enable these interrupts. */
+    SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG,
+                      EXTMEM_CORE0_DBUS_WR_IC_INT_ENA |
+                      EXTMEM_CORE0_DBUS_REJECT_INT_ENA |
+                      EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA |
+                      EXTMEM_CORE0_IBUS_REJECT_INT_ENA |
+                      EXTMEM_CORE0_IBUS_WR_IC_INT_ENA |
+                      EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA);
+
+    /* Same goes for cache illegal error: start by clearing the bits and then
+    * set them back. */
+    SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG,
+                      EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
+                      EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR |
+                      EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR);
+
+    SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG,
+                      EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
+                      EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
+                      EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
+
+    /* Enable the interrupts for cache error. */
+    ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
+}
+
+int IRAM_ATTR esp_cache_err_get_cpuid(void)
+{
+    return 0;
+}

components/esp_system/port/soc/esp32c3/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/port/soc/esp32s2/CMakeLists.txt

@@ -2,6 +2,7 @@ set(srcs "async_memcpy_impl_cp_dma.c"
          "dport_panic_highint_hdl.S"
          "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../arch/xtensa/panic_arch.c"
          "../../arch/xtensa/panic_handler_asm.S"
          "../../arch/xtensa/expression_with_stack.c"

components/esp_system/port/soc/esp32s2/cache_err_int.c

@@ -0,0 +1,86 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ The cache has an interrupt that can be raised as soon as an access to a cached
+ region (flash, psram) is done without the cache being enabled. We use that here
+ to panic the CPU, which from a debugging perspective is better than grabbing bad
+ data from the bus.
+*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+
+#include "esp_err.h"
+#include "esp_attr.h"
+
+#include "esp_intr_alloc.h"
+
+#include "soc/extmem_reg.h"
+#include "soc/dport_reg.h"
+#include "soc/periph_defs.h"
+#include "hal/cpu_hal.h"
+
+#include "esp32s2/dport_access.h"
+#include "esp32s2/rom/ets_sys.h"  // for intr_matrix_set
+
+#include "sdkconfig.h"
+
+void esp_cache_err_int_init(void)
+{
+    uint32_t core_id = cpu_hal_get_core_id();
+    ESP_INTR_DISABLE(ETS_MEMACCESS_ERR_INUM);
+
+    // We do not register a handler for the interrupt because it is interrupt
+    // level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
+    // a call to the panic handler for
+    // this interrupt.
+    intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
+
+    // Enable invalid cache access interrupt when the cache is disabled.
+    // The status bits are cleared first, in case we are restarting after
+    // a cache error has triggered.
+    DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_CLR_REG,
+                            EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
+                            EXTMEM_DCACHE_REJECT_INT_CLR |
+                            EXTMEM_DCACHE_WRITE_FLASH_INT_CLR |
+                            EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR |
+                            EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR |
+                            EXTMEM_ICACHE_REJECT_INT_CLR |
+                            EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR |
+                            EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR);
+    DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_ENA_REG,
+                            EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
+                            EXTMEM_DCACHE_REJECT_INT_ENA |
+                            EXTMEM_DCACHE_WRITE_FLASH_INT_ENA |
+                            EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA |
+                            EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA |
+                            EXTMEM_ICACHE_REJECT_INT_ENA |
+                            EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA |
+                            EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA |
+                            EXTMEM_CACHE_DBG_EN);
+
+    ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
+}
+
+int IRAM_ATTR esp_cache_err_get_cpuid(void)
+{
+    if (REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG) != 0 ||
+        REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) {
+            return PRO_CPU_NUM;
+    }
+    return -1;
+}

components/esp_system/port/soc/esp32s2/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/port/soc/esp32s3/CMakeLists.txt

@@ -1,6 +1,7 @@
 set(srcs "dport_panic_highint_hdl.S"
          "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../async_memcpy_impl_gdma.c"
          "../../arch/xtensa/panic_arch.c"
          "../../arch/xtensa/panic_handler_asm.S"

components/esp_system/port/soc/esp32s3/cache_err_int.c

@@ -0,0 +1,75 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @file cache_err_int.c
+ * @brief The cache has an interrupt that can be raised as soon as an access to a cached
+ *        region (Flash, PSRAM) is done without the cache being enabled.
+ *        We use that here to panic the CPU, which from a debugging perspective,
+ *        is better than grabbing bad data from the bus.
+ */
+
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_attr.h"
+#include "esp_intr_alloc.h"
+#include "soc/soc.h"
+#include "soc/extmem_reg.h"
+#include "soc/periph_defs.h"
+#include "hal/cpu_hal.h"
+#include "esp32s3/dport_access.h"
+#include "esp32s3/rom/ets_sys.h"
+
+void esp_cache_err_int_init(void)
+{
+    uint32_t core_id = cpu_hal_get_core_id();
+    ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
+
+    // We do not register a handler for the interrupt because it is interrupt
+    // level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
+    // a call to the panic handler for this interrupt.
+    intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
+
+    // Enable invalid cache access interrupt when the cache is disabled.
+    // When the interrupt happens, we can not determine the CPU where the
+    // invalid cache access has occurred. We enable the interrupt to catch
+    // invalid access on both CPUs, but the interrupt is connected to the
+    // CPU which happens to call this function.
+    // For this reason, panic handler backtrace will not be correct if the
+    // interrupt is connected to PRO CPU and invalid access happens on the APP CPU.
+
+    SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG,
+                      EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
+                      EXTMEM_DCACHE_WRITE_FLASH_INT_CLR |
+                      EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR |
+                      EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR |
+                      EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR |
+                      EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR);
+    SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG,
+                      EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
+                      EXTMEM_DCACHE_WRITE_FLASH_INT_ENA |
+                      EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA |
+                      EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA |
+                      EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
+                      EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
+
+    ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
+}
+
+int IRAM_ATTR esp_cache_err_get_cpuid(void)
+{
+    // FIXME
+    return -1;
+}

components/esp_system/port/soc/esp32s3/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/sleep_modes.c

@@ -48,6 +48,7 @@
 
 #include "sdkconfig.h"
 #include "esp_rom_uart.h"
+#include "brownout.h"
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/cache.h"
@@ -58,7 +59,6 @@
 #include "esp32s2/clk.h"
 #include "esp32s2/rom/cache.h"
 #include "esp32s2/rom/rtc.h"
-#include "esp32s2/brownout.h"
 #include "soc/extmem_reg.h"
 #include "driver/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32S3

components/esp_system/startup.c

@@ -60,24 +60,22 @@
 #include "esp_private/usb_console.h"
 #include "esp_vfs_cdcacm.h"
 
+#include "brownout.h"
+
 #include "esp_rom_sys.h"
 
 // [refactor-todo] make this file completely target-independent
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/clk.h"
 #include "esp32/spiram.h"
-#include "esp32/brownout.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/clk.h"
 #include "esp32s2/spiram.h"
-#include "esp32s2/brownout.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
 #include "esp32s3/spiram.h"
-#include "esp32s3/brownout.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/clk.h"
-#include "esp32c3/brownout.h"
 #endif
 /***********************************************/