Merge branch 'refactor/remove_redundant_rom_cache_dependency' into 'master'

cache: remove redundant rom cache dependency in bootloader Closes IDF-4523 See merge request espressif/esp-idf!17077
2022-03-12 10:11:39 +08:00
parent ab3d6a802d c1cbd7bbf6
commit 6ed3ffbbf1
70 changed files with 2314 additions and 466 deletions
--- a/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
+++ b/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
@@ -22,6 +22,20 @@ extern "C" {
 #define FLASH_BLOCK_SIZE 	0x10000
 #define MMAP_ALIGNED_MASK 	0x0000FFFF

+//This will be replaced with a kconfig, TODO: IDF-3821
+#define MMU_PAGE_SIZE                   0x10000
+#define MMU_FLASH_MASK                  (~(MMU_PAGE_SIZE - 1))
+/**
+ * MMU mapping must always be in the unit of a MMU_PAGE_SIZE
+ * This macro is a helper for you to get needed page nums to be mapped. e.g.:
+ * Let's say MMU_PAGE_SIZE is 64KB.
+ * - v_start = 0x4200_0004
+ * - size = 4 * 64KB
+ *
+ * You should map from 0x4200_0000, then map 5 pages.
+ */
+#define GET_REQUIRED_MMU_PAGES(size, v_start)    ((size + (v_start - (v_start & MMU_FLASH_MASK)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE)
+
 /* SPI commands (actual on-wire commands not SPI controller bitmasks)
   Suitable for use with the bootloader_execute_flash_command static function.
 */
@@ -135,23 +149,6 @@ esp_err_t bootloader_flash_erase_sector(size_t sector);
 */
 esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size);

-/* Cache MMU block size */
-#define MMU_BLOCK_SIZE    0x10000
-
-/* Cache MMU address mask (MMU tables ignore bits which are zero) */
-#define MMU_FLASH_MASK    (~(MMU_BLOCK_SIZE - 1))
-
-/**
- * @brief Calculate the number of cache pages to map
- * @param size  size of data to map
- * @param vaddr  virtual address where data will be mapped
- * @return number of cache MMU pages required to do the mapping
- */
-static inline uint32_t bootloader_cache_pages_to_map(uint32_t size, uint32_t vaddr)
-{
-    return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / MMU_BLOCK_SIZE;
-}
-
 /**
 * @brief Execute a user command on the flash
 *
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
@@ -42,7 +42,6 @@
 #define ESP_BOOTLOADER_SPIFLASH_QE_GD_SR2        BIT1   // QE position when you write 8 bits(for SR2) at one time.
 #define ESP_BOOTLOADER_SPIFLASH_QE_SR1_2BYTE     BIT9   // QE position when you write 16 bits at one time.

-
 #ifndef BOOTLOADER_BUILD
 /* Normal app version maps to esp_spi_flash.h operations...
 */
@@ -116,23 +115,11 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 /* Bootloader version, uses ROM functions only */
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/cache.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/cache.h"
-#include "soc/cache_memory.h"
-#elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/rom/cache.h"
-#include "soc/cache_memory.h"
-#elif CONFIG_IDF_TARGET_ESP32C3
-#include "esp32c3/rom/cache.h"
-#include "soc/cache_memory.h"
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/cache.h"
-#include "soc/cache_memory.h"
-#elif CONFIG_IDF_TARGET_ESP32C2
-#include "esp32c2/rom/cache.h"
-#include "soc/cache_memory.h"
 #endif
 #include "esp_rom_spiflash.h"
+#include "hal/mmu_hal.h"
+#include "hal/mmu_ll.h"
+#include "hal/cache_hal.h"
 static const char *TAG = "bootloader_flash";

 #if CONFIG_IDF_TARGET_ESP32
@@ -171,60 +158,75 @@ uint32_t bootloader_mmap_get_free_pages(void)
    return MMU_FREE_PAGES;
 }

-const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
+const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
 {
    if (mapped) {
-        ESP_LOGE(TAG, "tried to bootloader_mmap twice");
+        ESP_EARLY_LOGE(TAG, "tried to bootloader_mmap twice");
        return NULL; /* can't map twice */
    }
    if (size > MMU_SIZE) {
-        ESP_LOGE(TAG, "bootloader_mmap excess size %x", size);
+        ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size);
        return NULL;
    }

-    uint32_t src_addr_aligned = src_addr & MMU_FLASH_MASK;
-    uint32_t count = bootloader_cache_pages_to_map(size, src_addr);
+    uint32_t src_paddr_aligned = src_paddr & MMU_FLASH_MASK;
+    //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
+    uint32_t size_after_paddr_aligned = (src_paddr - src_paddr_aligned) + size;
+    /**
+     * @note 1
+     * Will add here a check to make sure the vaddr is on read-only and executable buses, since we use others for psram
+     * Now simply check if it's valid vaddr, didn't check if it's readable, writable or executable.
+     * TODO: IDF-4710
+     */
+    if (mmu_ll_check_valid_ext_vaddr_region(0, MMU_BLOCK0_VADDR, size_after_paddr_aligned) == 0) {
+        ESP_EARLY_LOGE(TAG, "vaddr not valid");
+        return NULL;
+    }
+
+    //-------------stop cache to do the MMU mapping--------------
 #if CONFIG_IDF_TARGET_ESP32
    Cache_Read_Disable(0);
    Cache_Flush(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-    uint32_t autoload = Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-#else // access rodata with DCache
-    uint32_t autoload = Cache_Suspend_DCache();
-    Cache_Invalidate_DCache_All();
-#endif
-    ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x",
-             src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned );
-#if CONFIG_IDF_TARGET_ESP32
-    int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
 #else
-    int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
+    cache_hal_disable(CACHE_TYPE_ALL);
 #endif
-    if (e != 0) {
-        ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
+
+    //---------------Do mapping------------------------
+    ESP_EARLY_LOGD(TAG, "rodata starts from paddr=0x%08x, size=0x%x, will be mapped to vaddr=0x%08x", src_paddr, size, MMU_BLOCK0_VADDR);
 #if CONFIG_IDF_TARGET_ESP32
+    uint32_t count = GET_REQUIRED_MMU_PAGES(size, src_paddr);
+    int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_paddr_aligned, 64, count);
+    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, count * MMU_PAGE_SIZE);
+    if (e != 0) {
+        ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
        Cache_Read_Enable(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-        Cache_Resume_ICache(autoload);
-#else // access rodata with DCache
-        Cache_Resume_DCache(autoload);
-#endif
        return NULL;
    }
+#else
+    /**
+     * This hal won't return error, it assumes the inputs are valid. The related check should be done in `bootloader_mmap()`.
+     * See above comments (note 1) about IDF-4710
+     */
+    uint32_t actual_mapped_len = 0;
+    mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_BLOCK0_VADDR, src_paddr_aligned, size_after_paddr_aligned, &actual_mapped_len);
+    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, actual_mapped_len);
+#endif
+
+    /**
+     * If after mapping, your code stucks, it possibly means that some of the buses are not enabled, check `cache_ll_l1_enable_bus()`
+     * For now, keep this unchanged.
+     */
+
+    //-------------enable cache--------------
 #if CONFIG_IDF_TARGET_ESP32
    Cache_Read_Enable(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-    Cache_Resume_ICache(autoload);
-#else // access rodata with DCache
-    Cache_Resume_DCache(autoload);
+#else
+    cache_hal_enable(CACHE_TYPE_ALL);
 #endif

    mapped = true;

-    return (void *)(MMU_BLOCK0_VADDR + (src_addr - src_addr_aligned));
+    return (void *)(MMU_BLOCK0_VADDR + (src_paddr - src_paddr_aligned));
 }

 void bootloader_munmap(const void *mapping)
@@ -235,15 +237,9 @@ void bootloader_munmap(const void *mapping)
        Cache_Read_Disable(0);
        Cache_Flush(0);
        mmu_init(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-        //TODO, save the autoload value.
-        Cache_Suspend_ICache();
-        Cache_Invalidate_ICache_All();
-        Cache_MMU_Init();
-#else // access rodata with DCache
-        Cache_Suspend_DCache();
-        Cache_Invalidate_DCache_All();
-        Cache_MMU_Init();
+#else
+        cache_hal_disable(CACHE_TYPE_ALL);
+        mmu_hal_init();
 #endif
        mapped = false;
        current_read_mapping = UINT32_MAX;
@@ -269,18 +265,16 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
 #if CONFIG_IDF_TARGET_ESP32
    Cache_Read_Disable(0);
    Cache_Flush(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-    uint32_t autoload = Cache_Suspend_ICache();
-#else // access rodata with DCache
-    uint32_t autoload = Cache_Suspend_DCache();
+#else
+    cache_hal_disable(CACHE_TYPE_ALL);
 #endif
+
    esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
+
 #if CONFIG_IDF_TARGET_ESP32
    Cache_Read_Enable(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-    Cache_Resume_ICache(autoload);
-#else // access rodata with DCache
-    Cache_Resume_DCache(autoload);
+#else
+    cache_hal_enable(CACHE_TYPE_ALL);
 #endif

    return spi_to_esp_err(r);
@@ -294,44 +288,35 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
        uint32_t word_src = src_addr + word * 4;  /* Read this offset from flash */
        uint32_t map_at = word_src & MMU_FLASH_MASK; /* Map this 64KB block from flash */
        uint32_t *map_ptr;
+
+        /* Move the 64KB mmu mapping window to fit map_at */
        if (map_at != current_read_mapping) {
-            /* Move the 64KB mmu mapping window to fit map_at */
+
+            //----------Stop cache for mapping----------------
 #if CONFIG_IDF_TARGET_ESP32
            Cache_Read_Disable(0);
            Cache_Flush(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-            uint32_t autoload = Cache_Suspend_ICache();
-            Cache_Invalidate_ICache_All();
-#else // access rodata with DCache
-            uint32_t autoload = Cache_Suspend_DCache();
-            Cache_Invalidate_DCache_All();
+#else
+            cache_hal_disable(CACHE_TYPE_ALL);
 #endif
-            ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
+
+            //---------------Do mapping------------------------
+            ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
 #if CONFIG_IDF_TARGET_ESP32
+            //Should never fail if we only map a MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
            int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
-#elif CONFIG_IDF_TARGET_ESP32S2
-            int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
-#else // map rodata with DBus
-            int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
+            assert(e == 0);
+#else
+            uint32_t actual_mapped_len = 0;
+            mmu_hal_map_region(0, MMU_TARGET_FLASH0, FLASH_READ_VADDR, map_at, MMU_PAGE_SIZE - 1, &actual_mapped_len);
 #endif
-            if (e != 0) {
-                ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
-#if CONFIG_IDF_TARGET_ESP32
-                Cache_Read_Enable(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-                Cache_Resume_ICache(autoload);
-#else // access rodata with DCache
-                Cache_Resume_DCache(autoload);
-#endif
-                return ESP_FAIL;
-            }
            current_read_mapping = map_at;
+
+            //-------------enable cache-------------------------
 #if CONFIG_IDF_TARGET_ESP32
            Cache_Read_Enable(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-            Cache_Resume_ICache(autoload);
-#else // access rodata with DCache
-            Cache_Resume_DCache(autoload);
+#else
+            cache_hal_enable(CACHE_TYPE_ALL);
 #endif
        }
        map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at));
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -19,56 +19,46 @@
 #include "esp32/rom/cache.h"
 #include "esp32/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/cache.h"
 #include "esp32s2/rom/secure_boot.h"
-#include "soc/extmem_reg.h"
-#include "soc/cache_memory.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/rom/cache.h"
 #include "esp32s3/rom/secure_boot.h"
-#include "soc/extmem_reg.h"
-#include "soc/cache_memory.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
-#include "esp32c3/rom/cache.h"
 #include "esp32c3/rom/efuse.h"
 #include "esp32c3/rom/crc.h"
 #include "esp32c3/rom/uart.h"
 #include "esp32c3/rom/gpio.h"
 #include "esp32c3/rom/secure_boot.h"
-#include "soc/extmem_reg.h"
-#include "soc/cache_memory.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/cache.h"
 #include "esp32h2/rom/efuse.h"
 #include "esp32h2/rom/crc.h"
 #include "esp32h2/rom/uart.h"
 #include "esp32h2/rom/gpio.h"
 #include "esp32h2/rom/secure_boot.h"
-#include "soc/extmem_reg.h"
-#include "soc/cache_memory.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
-#include "esp32c2/rom/cache.h"
 #include "esp32c2/rom/efuse.h"
 #include "esp32c2/rom/crc.h"
 #include "esp32c2/rom/rtc.h"
 #include "esp32c2/rom/uart.h"
 #include "esp32c2/rom/gpio.h"
 #include "esp32c2/rom/secure_boot.h"
-#include "soc/extmem_reg.h"
-#include "soc/cache_memory.h"
+
 #else // CONFIG_IDF_TARGET_*
 #error "Unsupported IDF_TARGET"
 #endif
 #include "esp_rom_spiflash.h"

 #include "soc/soc.h"
-#include "esp_cpu.h"
 #include "soc/rtc.h"
 #include "soc/gpio_periph.h"
 #include "soc/efuse_periph.h"
 #include "soc/rtc_periph.h"
 #include "soc/timer_periph.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_types.h"
+#include "hal/cache_ll.h"
+#include "hal/cache_hal.h"

+#include "esp_cpu.h"
 #include "esp_image_format.h"
 #include "esp_secure_boot.h"
 #include "esp_flash_encrypt.h"
@@ -716,99 +706,74 @@ static void set_cache_and_start_app(
 {
    int rc __attribute__((unused));

-    ESP_LOGD(TAG, "configure drom and irom and start");
+    ESP_EARLY_LOGD(TAG, "configure drom and irom and start");
+    //-----------------------Disable Cache to do the mapping---------
 #if CONFIG_IDF_TARGET_ESP32
    Cache_Read_Disable(0);
    Cache_Flush(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-    uint32_t autoload = Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-#else // access rodata with DCache
-    uint32_t autoload = Cache_Suspend_DCache();
-    Cache_Invalidate_DCache_All();
+#else
+    cache_hal_disable(CACHE_TYPE_ALL);
 #endif

-    /* Clear the MMU entries that are already set up,
-     * so the new app only has the mappings it creates.
-     */
-#if CONFIG_IDF_TARGET_ESP32
-    for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
-        DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
-    }
-#else
-    for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
-        FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
-    }
-#endif
+    mmu_hal_init();
+
+    //-----------------------MAP DROM--------------------------
    uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
    uint32_t drom_addr_aligned = drom_addr & MMU_FLASH_MASK;
-    uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr);
-    ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d",
-             drom_addr_aligned, drom_load_addr_aligned, drom_size, drom_page_count);
+    ESP_EARLY_LOGV(TAG, "rodata starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", drom_addr, drom_load_addr, drom_size);
+    //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
+    drom_size = (drom_load_addr - drom_load_addr_aligned) + drom_size;
 #if CONFIG_IDF_TARGET_ESP32
+    uint32_t drom_page_count = (drom_size + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
    rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
-#else // map rodata with DBUS
-    rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
-#endif
-    ESP_LOGV(TAG, "rc=%d", rc);
-#if CONFIG_IDF_TARGET_ESP32
+    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
    rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
-    ESP_LOGV(TAG, "rc=%d", rc);
+    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
+    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * MMU_PAGE_SIZE);
+#else
+    uint32_t actual_mapped_len = 0;
+    mmu_hal_map_region(0, MMU_TARGET_FLASH0, drom_load_addr_aligned, drom_addr_aligned, drom_size, &actual_mapped_len);
+    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
 #endif
+
+    //-----------------------MAP IROM--------------------------
    uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK;
    uint32_t irom_addr_aligned = irom_addr & MMU_FLASH_MASK;
-    uint32_t irom_page_count = bootloader_cache_pages_to_map(irom_size, irom_load_addr);
-    ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d",
-             irom_addr_aligned, irom_load_addr_aligned, irom_size, irom_page_count);
+    ESP_EARLY_LOGV(TAG, "text starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", irom_addr, irom_load_addr, irom_size);
+    //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
+    irom_size = (irom_load_addr - irom_load_addr_aligned) + irom_size;
 #if CONFIG_IDF_TARGET_ESP32
+    uint32_t irom_page_count = (irom_size + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
    rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
-#else // access text with IBUS
-#if CONFIG_IDF_TARGET_ESP32S2
-    uint32_t iram1_used = 0;
-    if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
-        iram1_used = 1;
-    }
-    if (iram1_used) {
-        rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1);
-        rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
-        REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
-    }
-#endif
-    rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count, 0);
-#endif
-    ESP_LOGV(TAG, "rc=%d", rc);
-#if CONFIG_IDF_TARGET_ESP32
+    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
    rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
    ESP_LOGV(TAG, "rc=%d", rc);
-    DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG,
-                       (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
-                       (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 |
-                       DPORT_PRO_CACHE_MASK_DRAM1 );
-    DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG,
-                       (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) |
-                       (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 |
-                       DPORT_APP_CACHE_MASK_DRAM1 );
-#elif CONFIG_IDF_TARGET_ESP32S2
-    REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0 );
-#elif CONFIG_IDF_TARGET_ESP32S3
-    REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS);
+    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * MMU_PAGE_SIZE);
+#else
+    mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
+    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
+#endif
+
+    //----------------------Enable corresponding buses----------------
+    cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, drom_load_addr_aligned, drom_size);
+    cache_ll_l1_enable_bus(0, bus_mask);
+    bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size);
+    cache_ll_l1_enable_bus(0, bus_mask);
+
 #if !CONFIG_FREERTOS_UNICORE
-    REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
-#endif
-#else // ESP32C3, ESP32H2
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
+    bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size);
+    cache_ll_l1_enable_bus(1, bus_mask);
+    bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size);
+    cache_ll_l1_enable_bus(1, bus_mask);
 #endif
+
+    //----------------------Enable Cache----------------
 #if CONFIG_IDF_TARGET_ESP32
-    Cache_Read_Enable(0);
-#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-    Cache_Resume_ICache(autoload);
-#else // access rodata with DCache
-    Cache_Resume_DCache(autoload);
-#endif
    // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
+    Cache_Read_Enable(0);
+#else
+    cache_hal_enable(CACHE_TYPE_ALL);
+#endif

    ESP_LOGD(TAG, "start: 0x%08x", entry_addr);
    bootloader_atexit();
--- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
+++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
@@ -25,7 +25,6 @@
 #include "soc/io_mux_reg.h"
 #include "soc/system_reg.h"
 #include "esp32c2/rom/efuse.h"
-#include "esp32c2/rom/cache.h"
 #include "esp32c2/rom/ets_sys.h"
 #include "esp32c2/rom/rtc.h"
 #include "bootloader_common.h"
@@ -37,6 +36,9 @@
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
 #include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/mmu_ll.h"

 static const char *TAG = "boot.esp32c2";

@@ -65,16 +67,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
    }
 }

-static void bootloader_reset_mmu(void)
-{
-    Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-    Cache_MMU_Init();
-
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
-}
-
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
 {
    uint32_t size;
@@ -97,10 +89,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
    default:
        size = 2;
    }
-    uint32_t autoload = Cache_Suspend_ICache();
+    cache_hal_disable(CACHE_TYPE_ALL);
    // Set flash chip size
    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
-    Cache_Resume_ICache(autoload);
+    cache_hal_enable(CACHE_TYPE_ALL);
 }

 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@@ -171,10 +163,10 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)

 static void bootloader_print_mmu_page_size(void)
 {
-    int page_mode = MMU_Get_Page_Mode();
-    int size = (page_mode == 0 ? 16 :
-                page_mode == 1 ? 32 :
-                page_mode == 2 ? 64 : 0);
+    mmu_page_size_t page_size = mmu_ll_get_page_size(0);
+    int size = (page_size == MMU_PAGE_16KB ? 16 :
+                page_size == MMU_PAGE_32KB ? 32 :
+                page_size == MMU_PAGE_64KB ? 64 : 0);
    ESP_LOGI(TAG, "MMU Page Size  : %dK", size);
 }

@@ -272,8 +264,10 @@ esp_err_t bootloader_init(void)
    esp_efuse_init_virtual_mode_in_ram();
 #endif
 #endif
-    // reset MMU
-    bootloader_reset_mmu();
+    //init cache hal
+    cache_hal_init();
+    //reset mmu
+    mmu_hal_init();
    // config clock
    bootloader_clock_configure();
    // initialize console, from now on, we can use esp_log
--- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
+++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
@@ -25,7 +25,6 @@
 #include "soc/io_mux_reg.h"
 #include "soc/system_reg.h"
 #include "esp32c3/rom/efuse.h"
-#include "esp32c3/rom/cache.h"
 #include "esp32c3/rom/ets_sys.h"
 #include "bootloader_common.h"
 #include "bootloader_init.h"
@@ -37,6 +36,8 @@
 #include "bootloader_flash_priv.h"
 #include "bootloader_soc.h"
 #include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"

 static const char *TAG = "boot.esp32c3";

@@ -72,16 +73,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
    }
 }

-static void bootloader_reset_mmu(void)
-{
-    Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-    Cache_MMU_Init();
-
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
-}
-
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
 {
    uint32_t size;
@@ -104,10 +95,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
    default:
        size = 2;
    }
-    uint32_t autoload = Cache_Suspend_ICache();
+    cache_hal_disable(CACHE_TYPE_ALL);
    // Set flash chip size
    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
-    Cache_Resume_ICache(autoload);
+    cache_hal_enable(CACHE_TYPE_ALL);
 }

 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@@ -316,8 +307,10 @@ esp_err_t bootloader_init(void)
    esp_efuse_init_virtual_mode_in_ram();
 #endif
 #endif
-    // reset MMU
-    bootloader_reset_mmu();
+    //init cache hal
+    cache_hal_init();
+    //reset mmu
+    mmu_hal_init();
    // config clock
    bootloader_clock_configure();
    // initialize console, from now on, we can use esp_log
--- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
+++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
@@ -25,7 +25,6 @@
 #include "soc/io_mux_reg.h"
 #include "soc/system_reg.h"
 #include "esp32h2/rom/efuse.h"
-#include "esp32h2/rom/cache.h"
 #include "esp32h2/rom/ets_sys.h"
 #include "bootloader_common.h"
 #include "bootloader_init.h"
@@ -36,6 +35,8 @@
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
 #include "bootloader_soc.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"

 static const char *TAG = "boot.esp32h2";

@@ -71,16 +72,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
    }
 }

-static void bootloader_reset_mmu(void)
-{
-    Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-    Cache_MMU_Init();
-
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
-}
-
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
 {
    uint32_t size;
@@ -103,10 +94,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
    default:
        size = 2;
    }
-    uint32_t autoload = Cache_Suspend_ICache();
+    cache_hal_disable(CACHE_TYPE_ALL);
    // Set flash chip size
    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
-    Cache_Resume_ICache(autoload);
+    cache_hal_enable(CACHE_TYPE_ALL);
 }

 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@@ -279,8 +270,10 @@ esp_err_t bootloader_init(void)
    assert(&_data_start <= &_data_end);
    // clear bss section
    bootloader_clear_bss_section();
-    // reset MMU
-    bootloader_reset_mmu();
+    //init cache hal
+    cache_hal_init();   //TODO IDF-4649
+    //reset mmu
+    mmu_hal_init();
    // config clock
    bootloader_clock_configure();
    // initialize console, from now on, we can use esp_log
--- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
+++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
@@ -23,7 +23,6 @@
 #include "esp_rom_efuse.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
-#include "esp32s2/rom/cache.h"

 #include "esp_attr.h"
 #include "esp_log.h"
@@ -36,6 +35,8 @@
 #include "soc/rtc.h"
 #include "soc/spi_periph.h"
 #include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"

 static const char *TAG = "boot.esp32s2";
 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
@@ -70,18 +71,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
    }
 }

-static void bootloader_reset_mmu(void)
-{
-    //ToDo: save the autoload value
-    Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-    Cache_MMU_Init();
-
-    /* normal ROM boot exits with DROM0 cache unmasked,
-    but serial bootloader exits with it masked. */
-    REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
-}
-
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
 {
    uint32_t size;
@@ -113,12 +102,12 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
    default:
        size = 2;
    }
-    uint32_t autoload = Cache_Suspend_ICache();
+    cache_hal_disable(CACHE_TYPE_ALL);
    // Set flash chip size
    esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
    // TODO: set mode
    // TODO: set frequency
-    Cache_Resume_ICache(autoload);
+    cache_hal_enable(CACHE_TYPE_ALL);
 }

 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@@ -315,8 +304,12 @@ esp_err_t bootloader_init(void)
    esp_efuse_init_virtual_mode_in_ram();
 #endif
 #endif
-    // reset MMU
-    bootloader_reset_mmu();
+    // init cache hal
+    cache_hal_init();
+    // reset mmu
+    mmu_hal_init();
+    // Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked.
+    REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
    // config clock
    bootloader_clock_configure();
    // initialize console, from now on, we can use esp_log
--- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
+++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
@@ -24,7 +24,6 @@
 #include "esp_rom_efuse.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
-#include "esp32s3/rom/cache.h"
 #include "esp32s3/rom/rtc.h"

 #include "bootloader_common.h"
@@ -36,6 +35,8 @@
 #include "bootloader_flash_priv.h"
 #include "bootloader_soc.h"
 #include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"


 static const char *TAG = "boot.esp32s3";
@@ -72,18 +73,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
    }
 }

-static void bootloader_reset_mmu(void)
-{
-    Cache_Suspend_DCache();
-    Cache_Invalidate_DCache_All();
-    Cache_MMU_Init();
-
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS);
-#if !CONFIG_FREERTOS_UNICORE
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS);
-#endif
-}
-
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
 {
    uint32_t size;
@@ -115,12 +104,13 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
    default:
        size = 2;
    }
-    uint32_t autoload = Cache_Suspend_DCache();
+
+    cache_hal_disable(CACHE_TYPE_ALL);
    // Set flash chip size
    esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
    // TODO: set mode
    // TODO: set frequency
-    Cache_Resume_DCache(autoload);
+    cache_hal_enable(CACHE_TYPE_ALL);
 }

 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@@ -346,8 +336,10 @@ esp_err_t bootloader_init(void)
    esp_efuse_init_virtual_mode_in_ram();
 #endif
 #endif
-    // reset MMU
-    bootloader_reset_mmu();
+    //init cache hal
+    cache_hal_init();
+    //reset mmu
+    mmu_hal_init();
    // config clock
    bootloader_clock_configure();
    // initialize console, from now on, we can use esp_log