Merge branch 'feature/deep_sleep_wakeup_from_touch' into 'master'
add wakeup from touch sensor, and deep sleep example - add new deep sleep wakeup mode - change documentation to explain incompatibilities between different wakeup mode, add error checks - add new ULP instructions necessary for ULP wakeup scenario - fix issues with I_WR_REG, I_SLEEP, I_END instructions - add deep sleep example, illustrating the use of timer, gpio, touch, and ULP wakeup triggers See merge request !461
This commit is contained in:
Ivan Grokhotkov
@@ -126,6 +126,9 @@ void IRAM_ATTR esp_deep_sleep_start()
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if (s_config.wakeup_triggers & EXT_EVENT1_TRIG_EN) {
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ext1_wakeup_prepare();
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}
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if (s_config.wakeup_triggers & SAR_TRIG_EN) {
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN);
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}
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// TODO: move timer wakeup configuration into a similar function
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// once rtc_sleep is opensourced.
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@@ -163,6 +166,10 @@ void system_deep_sleep(uint64_t) __attribute__((alias("esp_deep_sleep")));
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esp_err_t esp_deep_sleep_enable_ulp_wakeup()
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{
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#ifdef CONFIG_ULP_COPROC_ENABLED
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if(s_config.wakeup_triggers & RTC_EXT_EVENT0_TRIG_EN) {
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ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
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return ESP_ERR_INVALID_STATE;
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}
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s_config.wakeup_triggers |= RTC_SAR_TRIG_EN;
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return ESP_OK;
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#else
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@@ -177,6 +184,26 @@ esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us)
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return ESP_OK;
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}
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esp_err_t esp_deep_sleep_enable_touchpad_wakeup()
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{
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if (s_config.wakeup_triggers & (RTC_EXT_EVENT0_TRIG_EN)) {
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ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
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return ESP_ERR_INVALID_STATE;
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}
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s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN;
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return ESP_OK;
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}
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touch_pad_t esp_deep_sleep_get_touchpad_wakeup_status()
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{
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if (esp_deep_sleep_get_wakeup_cause() != ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD) {
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return TOUCH_PAD_MAX;
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}
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uint32_t touch_mask = REG_GET_FIELD(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_EN);
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assert(touch_mask != 0 && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero");
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return (touch_pad_t) (__builtin_ffs(touch_mask) - 1);
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}
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esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
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{
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if (level < 0 || level > 1) {
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@@ -185,6 +212,10 @@ esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
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if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
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return ESP_ERR_INVALID_ARG;
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}
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if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_SAR_TRIG_EN)) {
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ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
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return ESP_ERR_INVALID_STATE;
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}
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s_config.ext0_rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
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s_config.ext0_trigger_level = level;
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s_config.wakeup_triggers |= RTC_EXT_EVENT0_TRIG_EN;
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@@ -276,8 +307,7 @@ static void ext1_wakeup_prepare()
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uint64_t esp_deep_sleep_get_ext1_wakeup_status()
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{
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int wakeup_reason = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
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if (wakeup_reason != RTC_EXT_EVENT1_TRIG) {
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if (esp_deep_sleep_get_wakeup_cause() != ESP_DEEP_SLEEP_WAKEUP_EXT1) {
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return 0;
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}
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uint32_t status = REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
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@@ -296,6 +326,28 @@ uint64_t esp_deep_sleep_get_ext1_wakeup_status()
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return gpio_mask;
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}
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esp_deep_sleep_wakeup_cause_t esp_deep_sleep_get_wakeup_cause()
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{
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if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET) {
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return ESP_DEEP_SLEEP_WAKEUP_UNDEFINED;
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}
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uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
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if (wakeup_cause & RTC_EXT_EVENT0_TRIG) {
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return ESP_DEEP_SLEEP_WAKEUP_EXT0;
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} else if (wakeup_cause & RTC_EXT_EVENT1_TRIG) {
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return ESP_DEEP_SLEEP_WAKEUP_EXT1;
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} else if (wakeup_cause & RTC_TIMER_EXPIRE) {
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return ESP_DEEP_SLEEP_WAKEUP_TIMER;
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} else if (wakeup_cause & RTC_TOUCH_TRIG) {
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return ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD;
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} else if (wakeup_cause & RTC_SAR_TRIG) {
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return ESP_DEEP_SLEEP_WAKEUP_ULP;
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} else {
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return ESP_DEEP_SLEEP_WAKEUP_UNDEFINED;
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}
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}
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esp_err_t esp_deep_sleep_pd_config(esp_deep_sleep_pd_domain_t domain,
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esp_deep_sleep_pd_option_t option)
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{
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@@ -333,13 +385,15 @@ static uint32_t get_power_down_flags()
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s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
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}
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// RTC_PERIPH is needed for EXT0 wakeup and for ULP.
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// If RTC_PERIPH is auto, and both EXT0 and ULP aren't enabled,
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// power down RTC_PERIPH.
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// RTC_PERIPH is needed for EXT0 wakeup.
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// If RTC_PERIPH is auto, and EXT0 isn't enabled, power down RTC_PERIPH.
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
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if (s_config.wakeup_triggers &
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(RTC_SAR_TRIG_EN | RTC_EXT_EVENT0_TRIG_EN)) {
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if (s_config.wakeup_triggers & RTC_EXT_EVENT0_TRIG_EN) {
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s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
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} else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_SAR_TRIG_EN)) {
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// In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH
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// prevents ULP timer and touch FSMs from working correctly.
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s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
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}
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}
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@@ -17,6 +17,7 @@
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#include <stdint.h>
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#include "esp_err.h"
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#include "driver/gpio.h"
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#include "driver/touch_pad.h"
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#ifdef __cplusplus
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extern "C" {
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@@ -50,12 +51,28 @@ typedef enum {
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ESP_PD_OPTION_AUTO //!< Keep power domain enabled in deep sleep, if it is needed by one of the wakeup options. Otherwise power it down.
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} esp_deep_sleep_pd_option_t;
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/**
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* @brief Deep sleep wakeup cause
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*/
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typedef enum {
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ESP_DEEP_SLEEP_WAKEUP_UNDEFINED, //! Wakeup was not caused by deep sleep
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ESP_DEEP_SLEEP_WAKEUP_EXT0, //! Wakeup caused by external signal using RTC_IO
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ESP_DEEP_SLEEP_WAKEUP_EXT1, //! Wakeup caused by external signal using RTC_CNTL
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ESP_DEEP_SLEEP_WAKEUP_TIMER, //! Wakeup caused by timer
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ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD, //! Wakeup caused by touchpad
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ESP_DEEP_SLEEP_WAKEUP_ULP, //! Wakeup caused by ULP program
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} esp_deep_sleep_wakeup_cause_t;
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/**
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* @brief Enable wakeup by ULP coprocessor
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* @note In revisions 0 and 1 of the ESP32, ULP wakeup source
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* can not be used when RTC_PERIPH power domain is forced
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* to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
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* source is used.
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled.
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* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
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*/
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esp_err_t esp_deep_sleep_enable_ulp_wakeup();
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@@ -68,6 +85,29 @@ esp_err_t esp_deep_sleep_enable_ulp_wakeup();
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*/
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esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us);
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/**
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* @brief Enable wakeup by touch sensor
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*
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* @note In revisions 0 and 1 of the ESP32, touch wakeup source
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* can not be used when RTC_PERIPH power domain is forced
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* to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
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* source is used.
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*
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
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*/
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esp_err_t esp_deep_sleep_enable_touchpad_wakeup();
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/**
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* @brief Get the touch pad which caused wakeup
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*
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* If wakeup was caused by another source, this function will return TOUCH_PAD_MAX;
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*
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* @return touch pad which caused wakeup
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*/
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touch_pad_t esp_deep_sleep_get_touchpad_wakeup_status();
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/**
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* @brief Enable wakeup using a pin
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*
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@@ -81,6 +121,9 @@ esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us);
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* configured in esp_deep_sleep_start, immediately before
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* entering deep sleep.
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*
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* @note In revisions 0 and 1 of the ESP32, ext0 wakeup source
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* can not be used together with touch or ULP wakeup sources.
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*
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* @param gpio_num GPIO number used as wakeup source. Only GPIOs which are have RTC
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* functionality can be used: 0,2,4,12-15,25-27,32-39.
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* @param level input level which will trigger wakeup (0=low, 1=high)
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@@ -88,6 +131,7 @@ esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us);
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* - ESP_OK on success
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* - ESP_ERR_INVALID_ARG if the selected GPIO is not an RTC GPIO,
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* or the mode is invalid
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* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
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*/
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esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level);
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@@ -188,6 +232,15 @@ void esp_deep_sleep(uint64_t time_in_us) __attribute__((noreturn));
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*/
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void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated));
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/**
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* @brief Get the source which caused deep sleep wakeup
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*
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* @return wakeup cause, or ESP_DEEP_SLEEP_WAKEUP_UNDEFINED if reset reason is other than deep sleep reset.
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*/
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esp_deep_sleep_wakeup_cause_t esp_deep_sleep_get_wakeup_cause();
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/**
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* @brief Default stub to run on wake from deep sleep.
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*
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@@ -240,7 +240,7 @@
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#define RTC_CNTL_TIME_VALID_S 30
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/* frequency of RTC slow clock, Hz */
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#define RTC_CTNL_SLOWCLK_FREQ 150000
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#define RTC_CNTL_SLOWCLK_FREQ 150000
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#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10)
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/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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20
components/esp32/test/test_tsens.c
Normal file
20
components/esp32/test/test_tsens.c
Normal file
@@ -0,0 +1,20 @@
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#include <stdio.h>
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#include "unity.h"
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#include "rom/ets_sys.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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TEST_CASE("can control TSENS using registers", "[rtc][ignore]")
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{
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
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CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
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CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
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SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
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SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
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ets_delay_us(100);
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SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
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ets_delay_us(5);
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int res = GET_PERI_REG_BITS2(SENS_SAR_SLAVE_ADDR3_REG, SENS_TSENS_OUT, SENS_TSENS_OUT_S);
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printf("res=%d\n", res);
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}
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@@ -52,7 +52,7 @@ static uint64_t get_rtc_time_us()
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uint64_t low = READ_PERI_REG(RTC_CNTL_TIME0_REG);
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uint64_t high = READ_PERI_REG(RTC_CNTL_TIME1_REG);
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uint64_t ticks = (high << 32) | low;
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return ticks * 100 / (RTC_CTNL_SLOWCLK_FREQ / 10000); // scale RTC_CTNL_SLOWCLK_FREQ to avoid overflow
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return ticks * 100 / (RTC_CNTL_SLOWCLK_FREQ / 10000); // scale RTC_CNTL_SLOWCLK_FREQ to avoid overflow
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}
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#endif // WITH_RTC
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@@ -81,7 +81,7 @@ extern "C" {
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#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */
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#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */
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#define OPCODE_END 9 /*!< Stop executing the program (not implemented yet) */
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#define OPCODE_END 9 /*!< Stop executing the program */
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#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */
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#define SUB_OPCODE_SLEEP 1 /*!< Stop executing the program and run it again after selected interval */
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@@ -222,7 +222,7 @@ typedef union {
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struct {
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uint32_t dreg : 2; /*!< Register where to store temperature measurement result */
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uint32_t wait_delay: 14; /*!< Cycles to wait after measurement is done */
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uint32_t cycles: 12; /*!< Cycles used to perform measurement */
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uint32_t reserved: 12; /*!< Reserved, set to 0 */
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uint32_t opcode: 4; /*!< Opcode (OPCODE_TSENS) */
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} tsens; /*!< Format of TSENS instruction */
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@@ -271,7 +271,12 @@ _Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should
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.cycles = cycles_ } }
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/**
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* Halt the coprocessor
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* Halt the coprocessor.
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*
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* This instruction halts the coprocessor, but keeps ULP timer active.
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* As such, ULP program will be restarted again by timer.
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* To stop the program and prevent the timer from restarting the program,
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* use I_END(0) instruction.
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*/
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#define I_HALT() { .halt = {\
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.unused = 0, \
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@@ -307,7 +312,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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*/
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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.addr = reg & 0xff, \
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.data = val, \
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.low = low_bit, \
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@@ -320,8 +325,8 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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* R0 = reg[high_bit : low_bit]
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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*/
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#define I_RD_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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.addr = reg & 0xff, \
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.unused = 0, \
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.low = low_bit, \
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@@ -329,25 +334,105 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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.opcode = OPCODE_RD_REG } }
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/**
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* End program.
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* Set or clear a bit in the peripheral register.
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*
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* If wake == 1, wake up main CPU.
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* Sets bit (1 << shift) of register reg to value val.
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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*/
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#define I_END(wake) { .end = { \
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.wakeup = wake, \
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#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val)
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/**
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* Wake the SoC from deep sleep.
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*
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* This instruction initiates wake up from deep sleep.
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* Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup
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* triggered by the ULP before going into deep sleep.
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* Note that ULP program will still keep running until the I_HALT
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* instruction, and it will still be restarted by timer at regular
|
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* intervals, even when the SoC is woken up.
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*
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* To stop the ULP program, use I_HALT instruction.
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*
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* To disable the timer which start ULP program, use I_END()
|
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* instruction. I_END instruction clears the
|
||||
* RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG
|
||||
* register, which controls the ULP timer.
|
||||
*/
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||||
#define I_WAKE() { .end = { \
|
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.wakeup = 1, \
|
||||
.unused = 0, \
|
||||
.sub_opcode = SUB_OPCODE_END, \
|
||||
.opcode = OPCODE_END } }
|
||||
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||||
/**
|
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* Stop ULP program timer.
|
||||
*
|
||||
* This is a convenience macro which disables the ULP program timer.
|
||||
* Once this instruction is used, ULP program will not be restarted
|
||||
* anymore until ulp_run function is called.
|
||||
*
|
||||
* ULP program will continue running after this instruction. To stop
|
||||
* the currently running program, use I_HALT().
|
||||
*/
|
||||
#define I_END() \
|
||||
I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
|
||||
/**
|
||||
* Select the time interval used to run ULP program.
|
||||
*
|
||||
* This instructions selects which of the SENS_SLEEP_CYCLES_Sx
|
||||
* registers' value is used by the ULP program timer.
|
||||
* When the ULP program stops at I_HALT instruction, ULP program
|
||||
* timer start counting. When the counter reaches the value of
|
||||
* the selected SENS_SLEEP_CYCLES_Sx register, ULP program
|
||||
* start running again from the start address (passed to the ulp_run
|
||||
* function).
|
||||
* There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5.
|
||||
*
|
||||
* By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP
|
||||
* program timer.
|
||||
*/
|
||||
#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \
|
||||
.cycle_sel = timer_idx, \
|
||||
.unused = 0, \
|
||||
.sub_opcode = SUB_OPCODE_SLEEP, \
|
||||
.opcode = OPCODE_END } }
|
||||
|
||||
/**
|
||||
* Perform temperature sensor measurement and store it into reg_dest.
|
||||
*
|
||||
* Delay can be set between 1 and ((1 << 14) - 1). Higher values give
|
||||
* higher measurement resolution.
|
||||
*/
|
||||
#define I_TSENS(reg_dest, delay) { .tsens = { \
|
||||
.dreg = reg_dest, \
|
||||
.wait_delay = delay, \
|
||||
.reserved = 0, \
|
||||
.opcode = OPCODE_TSENS } }
|
||||
|
||||
/**
|
||||
* Perform ADC measurement and store result in reg_dest.
|
||||
*
|
||||
* adc_idx selects ADC (0 or 1).
|
||||
* pad_idx selects ADC pad (0 - 7).
|
||||
*/
|
||||
#define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\
|
||||
.dreg = reg_dest, \
|
||||
.mux = pad_idx + 1, \
|
||||
.sar_sel = adc_idx, \
|
||||
.unused1 = 0, \
|
||||
.cycles = 0, \
|
||||
.unused2 = 0, \
|
||||
.opcode = OPCODE_ADC } }
|
||||
|
||||
/**
|
||||
* Store value from register reg_val into RTC memory.
|
||||
*
|
||||
* The value is written to an offset calculated by adding value of
|
||||
* reg_addr register and offset_ field (this offset is expressed in 32-bit words).
|
||||
* 32 bits written to RTC memory are built as follows:
|
||||
* - 5 MSBs are zero
|
||||
* - next 11 bits hold the PC of current instruction, expressed in 32-bit words
|
||||
* - next 16 bits hold the actual value to be written
|
||||
* - bits [31:21] hold the PC of current instruction, expressed in 32-bit words
|
||||
* - bits [20:16] = 5'b1
|
||||
* - bits [15:0] are assigned the contents of reg_val
|
||||
*
|
||||
* RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] }
|
||||
*/
|
||||
|
||||
@@ -112,7 +112,9 @@ TEST_CASE("ulp wakeup test", "[ulp][ignore]")
|
||||
I_MOVI(R2, 42),
|
||||
I_MOVI(R3, 15),
|
||||
I_ST(R2, R3, 0),
|
||||
I_END(1)
|
||||
I_WAKE(),
|
||||
I_END(),
|
||||
I_HALT()
|
||||
};
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(0, program, &size);
|
||||
@@ -121,6 +123,100 @@ TEST_CASE("ulp wakeup test", "[ulp][ignore]")
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("ulp can write and read peripheral registers", "[ulp]")
|
||||
{
|
||||
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
|
||||
REG_WRITE(RTC_CNTL_STORE1_REG, 0x89abcdef);
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, 64),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15),
|
||||
I_ST(R0, R1, 0),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11),
|
||||
I_ST(R0, R1, 1),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31),
|
||||
I_ST(R0, R1, 2),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27),
|
||||
I_ST(R0, R1, 3),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef),
|
||||
I_LD(R0, R1, 4),
|
||||
I_ADDI(R0, R0, 1),
|
||||
I_ST(R0, R1, 4),
|
||||
I_END(),
|
||||
I_HALT()
|
||||
};
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
vTaskDelay(100/portTICK_PERIOD_MS);
|
||||
|
||||
TEST_ASSERT_EQUAL_HEX32(0xefcdab89, REG_READ(RTC_CNTL_STORE0_REG));
|
||||
TEST_ASSERT_EQUAL_HEX16(0xcdef, RTC_SLOW_MEM[64] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0xde, RTC_SLOW_MEM[65] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0x89ab, RTC_SLOW_MEM[66] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0x9a, RTC_SLOW_MEM[67] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX32(1 | (15 << 21) | (1 << 16), RTC_SLOW_MEM[68]);
|
||||
}
|
||||
|
||||
TEST_CASE("ULP I_WR_REG instruction test", "[ulp]")
|
||||
{
|
||||
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
|
||||
typedef struct {
|
||||
int low;
|
||||
int width;
|
||||
} wr_reg_test_item_t;
|
||||
|
||||
const wr_reg_test_item_t test_items[] = {
|
||||
{0, 1}, {0, 2}, {0, 3}, {0, 4}, {0, 5}, {0, 6}, {0, 7}, {0, 8},
|
||||
{3, 1}, {3, 2}, {3, 3}, {3, 4}, {3, 5}, {3, 6}, {3, 7}, {3, 8},
|
||||
{15, 1}, {15, 2}, {15, 3}, {15, 4}, {15, 5}, {15, 6}, {15, 7}, {15, 8},
|
||||
{16, 1}, {16, 2}, {16, 3}, {16, 4}, {16, 5}, {16, 6}, {16, 7}, {16, 8},
|
||||
{18, 1}, {18, 2}, {18, 3}, {18, 4}, {18, 5}, {18, 6}, {18, 7}, {18, 8},
|
||||
{24, 1}, {24, 2}, {24, 3}, {24, 4}, {24, 5}, {24, 6}, {24, 7}, {24, 8},
|
||||
};
|
||||
|
||||
const size_t test_items_count =
|
||||
sizeof(test_items)/sizeof(test_items[0]);
|
||||
for (size_t i = 0; i < test_items_count; ++i) {
|
||||
const uint32_t mask = (uint32_t) (((1ULL << test_items[i].width) - 1) << test_items[i].low);
|
||||
const uint32_t not_mask = ~mask;
|
||||
printf("#%2d: low: %2d width: %2d mask: %08x expected: %08x ", i,
|
||||
test_items[i].low, test_items[i].width,
|
||||
mask, not_mask);
|
||||
|
||||
REG_WRITE(RTC_CNTL_STORE0_REG, 0xffffffff);
|
||||
REG_WRITE(RTC_CNTL_STORE1_REG, 0x00000000);
|
||||
const ulp_insn_t program[] = {
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG,
|
||||
test_items[i].low,
|
||||
test_items[i].low + test_items[i].width - 1,
|
||||
0),
|
||||
I_WR_REG(RTC_CNTL_STORE1_REG,
|
||||
test_items[i].low,
|
||||
test_items[i].low + test_items[i].width - 1,
|
||||
0xff & ((1 << test_items[i].width) - 1)),
|
||||
I_END(),
|
||||
I_HALT()
|
||||
};
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(0, program, &size);
|
||||
ulp_run(0);
|
||||
vTaskDelay(10/portTICK_PERIOD_MS);
|
||||
uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);
|
||||
uint32_t set = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
printf("clear: %08x set: %08x\n", clear, set);
|
||||
TEST_ASSERT_EQUAL_HEX32(not_mask, clear);
|
||||
TEST_ASSERT_EQUAL_HEX32(mask, set);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
@@ -149,7 +245,9 @@ TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
|
||||
M_LABEL(5),
|
||||
M_BX(4),
|
||||
M_LABEL(6),
|
||||
I_END(1) // wake up the SoC
|
||||
I_WAKE(), // wake up the SoC
|
||||
I_END(), // stop ULP program timer
|
||||
I_HALT()
|
||||
};
|
||||
const gpio_num_t led_gpios[] = {
|
||||
GPIO_NUM_2,
|
||||
@@ -168,3 +266,198 @@ TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("ulp power consumption in deep sleep", "[ulp]")
|
||||
{
|
||||
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 4 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
ulp_insn_t insn = I_HALT();
|
||||
RTC_SLOW_MEM[0] = *(uint32_t*) &insn;
|
||||
|
||||
REG_WRITE(SENS_ULP_CP_SLEEP_CYC0_REG, 0x8000);
|
||||
|
||||
ulp_run(0);
|
||||
|
||||
esp_deep_sleep_enable_ulp_wakeup();
|
||||
esp_deep_sleep_enable_timer_wakeup(10 * 1000000);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("ulp timer setting", "[ulp]")
|
||||
{
|
||||
/*
|
||||
* Run a simple ULP program which increments the counter, for one second.
|
||||
* Program calls I_HALT each time and gets restarted by the timer.
|
||||
* Compare the expected number of times the program runs with the actual.
|
||||
*/
|
||||
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
|
||||
|
||||
const int offset = 6;
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 0), // load counter
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 0), // save counter
|
||||
I_HALT(),
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size && "data offset needs to be greater or equal to program size");
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
// disable the ULP program timer — we will enable it later
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
|
||||
const uint32_t cycles_to_test[] = {0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000};
|
||||
const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]);
|
||||
for (size_t i = 0; i < tests_count; ++i) {
|
||||
// zero out the counter
|
||||
RTC_SLOW_MEM[offset] = 0;
|
||||
// set the number of slow clock cycles
|
||||
REG_WRITE(SENS_ULP_CP_SLEEP_CYC0_REG, cycles_to_test[i]);
|
||||
// enable the timer and wait for a second
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
vTaskDelay(1000 / portTICK_PERIOD_MS);
|
||||
// get the counter value and stop the timer
|
||||
uint32_t counter = RTC_SLOW_MEM[offset] & 0xffff;
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
// compare the actual and expected numbers of iterations of ULP program
|
||||
float expected_period = (cycles_to_test[i] + 16) / (float) RTC_CNTL_SLOWCLK_FREQ + 5 / 8e6f;
|
||||
float error = 1.0f - counter * expected_period;
|
||||
printf("%u\t%u\t%.01f\t%.04f\n", cycles_to_test[i], counter, 1.0f / expected_period, error);
|
||||
// Should be within 15%
|
||||
TEST_ASSERT_INT_WITHIN(15, 0, (int) error * 100);
|
||||
// Note: currently RTC_CNTL_SLOWCLK_FREQ is ballpark value — we need to determine it
|
||||
// Precisely by running calibration similar to the one done in deep sleep.
|
||||
// This may cause the test to fail on some chips which have the slow clock frequency
|
||||
// way off.
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ulp can use TSENS in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
|
||||
printf("\n\n");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
|
||||
|
||||
// Allow TSENS to be controlled by the ULP
|
||||
SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
|
||||
|
||||
// data start offset
|
||||
size_t offset = 20;
|
||||
// number of samples to collect
|
||||
RTC_SLOW_MEM[offset] = (CONFIG_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
|
||||
// sample counter
|
||||
RTC_SLOW_MEM[offset + 1] = 0;
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 1), // r2 <- counter
|
||||
I_LD(R3, R1, 0), // r3 <- length
|
||||
I_SUBI(R3, R3, 1), // end = length - 1
|
||||
I_SUBR(R3, R3, R2), // r3 = length - counter
|
||||
M_BXF(1), // if overflow goto 1:
|
||||
I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 3),
|
||||
I_TSENS(R0, 16383), // r0 <- tsens
|
||||
I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 0),
|
||||
I_ST(R0, R2, offset + 4),
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 1), // save counter
|
||||
I_HALT(), // enter sleep
|
||||
M_LABEL(1), // done with measurements
|
||||
I_END(), // stop ULP timer
|
||||
I_WAKE(), // initiate wakeup
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size);
|
||||
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
esp_deep_sleep_enable_timer_wakeup(4000000);
|
||||
esp_deep_sleep_enable_ulp_wakeup();
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("can use ADC in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
|
||||
printf("\n\n");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR1_BIT_WIDTH, 3, SENS_SAR1_BIT_WIDTH_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR2_BIT_WIDTH, 3, SENS_SAR2_BIT_WIDTH_S);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_READ_CTRL_REG, SENS_SAR1_SAMPLE_BIT, 0x3, SENS_SAR1_SAMPLE_BIT_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_SAMPLE_BIT, 0x3, SENS_SAR2_SAMPLE_BIT_S);
|
||||
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_MEAS2_START_FORCE);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_MEAS1_START_FORCE);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_AMP, 2, SENS_FORCE_XPD_AMP_S);
|
||||
|
||||
// SAR1 invert result
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DATA_INV);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR2_DATA_INV);
|
||||
|
||||
|
||||
// const int adc = 1;
|
||||
// const int channel = 1;
|
||||
// const int atten = 3;
|
||||
// const int gpio_num = 0;
|
||||
|
||||
const int adc = 0;
|
||||
const int channel = 0;
|
||||
const int atten = 0;
|
||||
const int gpio_num = 36;
|
||||
|
||||
rtc_gpio_init(gpio_num);
|
||||
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_SAR1_EN_PAD_FORCE_M);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_SAR2_EN_PAD_FORCE_M);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_ATTEN1_REG, 3, atten, 2 * channel); //set SAR1 attenuation
|
||||
SET_PERI_REG_BITS(SENS_SAR_ATTEN2_REG, 3, atten, 2 * channel); //set SAR2 attenuation
|
||||
|
||||
// data start offset
|
||||
size_t offset = 20;
|
||||
// number of samples to collect
|
||||
RTC_SLOW_MEM[offset] = (CONFIG_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
|
||||
// sample counter
|
||||
RTC_SLOW_MEM[offset + 1] = 0;
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 1), // r2 <- counter
|
||||
I_LD(R3, R1, 0), // r3 <- length
|
||||
I_SUBI(R3, R3, 1), // end = length - 1
|
||||
I_SUBR(R3, R3, R2), // r3 = length - counter
|
||||
M_BXF(1), // if overflow goto 1:
|
||||
I_ADC(R0, adc, channel), // r0 <- ADC
|
||||
I_ST(R0, R2, offset + 4),
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 1), // save counter
|
||||
I_HALT(),
|
||||
M_LABEL(1), // done with measurements
|
||||
I_END(), // stop ULP program timer
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size);
|
||||
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
esp_deep_sleep_enable_timer_wakeup(4000000);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
|
||||
@@ -265,12 +265,16 @@ esp_err_t ulp_run(uint32_t entry_point)
|
||||
{
|
||||
// disable ULP timer
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
// wait for at least 1 RTC_SLOW_CLK cycle
|
||||
ets_delay_us(10);
|
||||
// set entry point
|
||||
SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_PC_INIT_V, entry_point, SENS_PC_INIT_S);
|
||||
// disable force start
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP_M);
|
||||
// make sure voltage is raised when RTC 8MCLK is enabled
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M);
|
||||
// enable ULP timer
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
return ESP_OK;
|
||||
|
||||
Reference in New Issue
Block a user