Merge branch 'feature/wdt_c3' into 'master'
wdt: Fix RTC_SLOW_CLK for chips, corrects WDT timeout. Closes IDF-2118 and IDF-2332 See merge request espressif/esp-idf!12796
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@@ -136,7 +136,9 @@ Once the program is loaded into RTC memory, the application can start it, callin
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ULP-RISC-V Program Flow
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-----------------------
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The ULP-RISC-V coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_riscv_run` is called. The timer counts the number of RTC_SLOW_CLK ticks (by default, produced by an internal 90 kHz RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register. When starting the ULP, ``RTC_CNTL_ULP_CP_TIMER_1_REG`` will be used to set the number of timer ticks.
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{IDF_TARGET_RTC_CLK_FRE:default="150kHz", esp32s2="90kHz"}
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The ULP-RISC-V coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_riscv_run` is called. The timer counts the number of RTC_SLOW_CLK ticks (by default, produced by an internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register. When starting the ULP, ``RTC_CNTL_ULP_CP_TIMER_1_REG`` will be used to set the number of timer ticks.
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The application can set ULP timer period values (RTC_CNTL_ULP_CP_TIMER_1_REG) using the :cpp:func:`ulp_set_wakeup_period` function.
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@@ -1,7 +1,7 @@
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System Time
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===========
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{IDF_TARGET_RTC_CLK_FRE:default="90kHz", esp32="150kHz"}
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{IDF_TARGET_RTC_CLK_FRE:default="150kHz", esp32s2="90kHz"}
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{IDF_TARGET_HARDWARE_DESIGN_URL:default="`ESP32 Hardware Design Guidelines <https://www.espressif.com/sites/default/files/documentation/esp32_hardware_design_guidelines_en.pdf#page=10>`_", esp32="`ESP32 Hardware Design Guidelines <https://www.espressif.com/sites/default/files/documentation/esp32_hardware_design_guidelines_en.pdf#page=10>`_", esp32s2="`ESP32-S2 Hardware Design Guidelines <https://www.espressif.com/sites/default/files/documentation/esp32-s2_hardware_design_guidelines_en.pdf#page=10>`_"}
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Overview
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