eaw/esp-idf
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

driver(uart):merge branch into v3.0 which fixed three bug related with uart

Browse Source 
1. uart fifo reset
    2. uart pattern interrupt
    3. uart buffered_len error.
This commit is contained in:
kooho
2018-01-24 21:27:12 +08:00
parent 2a55629556
commit 3a6be05945
5 changed files with 395 additions and 130 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
components/driver/include/driver/uart.h
View File

@@ -618,8 +618,10 @@ int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t si
int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait);
/**
* @brief UART ring buffer flush. This will discard all data in the UART RX buffer.
*
* @brief Alias of uart_flush_input.
* UART ring buffer flush. This will discard all data in the UART RX buffer.
* @note Instead of waiting the data sent out, this function will clear UART rx buffer.
* In order to send all the data in tx FIFO, we can use uart_wait_tx_done function.
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return
@@ -629,8 +631,18 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
esp_err_t uart_flush(uart_port_t uart_num);
/**
* @brief UART get RX ring buffer cached data length
* @brief Clear input buffer, discard all the data is in the ring-buffer.
* @note In order to send all the data in tx FIFO, we can use uart_wait_tx_done function.
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return
* - ESP_OK Success
* - ESP_FAIL Parameter error
*/
esp_err_t uart_flush_input(uart_port_t uart_num);
/**
* @brief UART get RX ring buffer cached data length
* @param uart_num UART port number.
* @param size Pointer of size_t to accept cached data length
*
@@ -671,6 +683,39 @@ esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num);
*/
esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle);
/**
* @brief Return the nearest detected pattern position in buffer.
* The positions of the detected pattern are saved in a queue,
* this function will dequeue the first pattern position and move the pointer to next pattern position.
* @note If the RX buffer is full and flow control is not enabled,
* the detected pattern may not be found in the rx buffer due to overflow.
*
* The following APIs will modify the pattern position info:
* uart_flush_input, uart_read_bytes, uart_driver_delete, uart_pop_pattern_pos
* It is the application's responsibility to ensure atomic access to the pattern queue and the rx data buffer
* when using pattern detect feature.
*
* @param uart_num UART port number
* @return
* - (-1) No pattern found for current index or parameter error
* - others the pattern position in rx buffer.
*/
int uart_pattern_pop_pos(uart_port_t uart_num);
/**
* @brief Allocate a new memory with the given length to save record the detected pattern position in rx buffer.
* @param uart_num UART port number
* @param queue_length Max queue length for the detected pattern.
* If the queue length is not large enough, some pattern positions might be lost.
* Set this value to the maximum number of patterns that could be saved in data buffer at the same time.
* @return
* - ESP_ERR_NO_MEM No enough memory
* - ESP_ERR_INVALID_STATE Driver not installed
* - ESP_FAIL Parameter error
* - ESP_OK Success
*/
esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length);
#ifdef __cplusplus
}
#endif

309
components/driver/uart.c
View File

@@ -44,6 +44,8 @@ static const char* UART_TAG = "uart";
#define UART_FULL_THRESH_DEFAULT (120)
#define UART_TOUT_THRESH_DEFAULT (10)
#define UART_TX_IDLE_NUM_DEFAULT (0)
#define UART_PATTERN_DET_QLEN_DEFAULT (10)
#define UART_ENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux)
#define UART_EXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux)
#define UART_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux)
@@ -58,6 +60,13 @@ typedef struct {
} tx_data;
} uart_tx_data_t;
typedef struct {
int wr;
int rd;
int len;
int* data;
} uart_pat_rb_t;
typedef struct {
uart_port_t uart_num; /*!< UART port number*/
int queue_size; /*!< UART event queue size*/
@@ -74,6 +83,8 @@ typedef struct {
uint8_t* rx_head_ptr; /*!< pointer to the head of RX item*/
uint8_t rx_data_buf[UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
uart_pat_rb_t rx_pattern_pos;
//tx parameters
SemaphoreHandle_t tx_fifo_sem; /*!< UART TX FIFO semaphore*/
SemaphoreHandle_t tx_mux; /*!< UART TX mutex*/
@@ -91,8 +102,6 @@ typedef struct {
uint8_t tx_waiting_brk; /*!< Flag to indicate that TX FIFO is ready to send break signal after FIFO is empty, do not push data into TX FIFO right now.*/
} uart_obj_t;
static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
/* DRAM_ATTR is required to avoid UART array placed in flash, due to accessed from ISR */
static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = {&UART0, &UART1, &UART2};
@@ -271,8 +280,11 @@ esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flo
static esp_err_t uart_reset_rx_fifo(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
// Read all data from the FIFO
while (UART[uart_num]->status.rxfifo_cnt) {
//Due to hardware issue, we can not use fifo_rst to reset uart fifo.
//See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
// we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
while(UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.wr_addr != UART[uart_num]->mem_rx_status.rd_addr)) {
READ_PERI_REG(UART_FIFO_REG(uart_num));
}
return ESP_OK;
@@ -305,6 +317,120 @@ esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask)
return ESP_OK;
}
static esp_err_t uart_pattern_link_free(uart_port_t uart_num)
{
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
if (p_uart_obj[uart_num]->rx_pattern_pos.data != NULL) {
int* pdata = p_uart_obj[uart_num]->rx_pattern_pos.data;
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
p_uart_obj[uart_num]->rx_pattern_pos.data = NULL;
p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
free(pdata);
}
return ESP_OK;
}
static esp_err_t uart_pattern_enqueue(uart_port_t uart_num, int pos)
{
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
esp_err_t ret = ESP_OK;
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
int next = p_pos->wr + 1;
if (next >= p_pos->len) {
next = 0;
}
if (next == p_pos->rd) {
ESP_EARLY_LOGW(UART_TAG, "Fail to enqueue pattern position, pattern queue is full.");
ret = ESP_FAIL;
} else {
p_pos->data[p_pos->wr] = pos;
p_pos->wr = next;
ret = ESP_OK;
}
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ret;
}
static esp_err_t uart_pattern_dequeue(uart_port_t uart_num)
{
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
if(p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) {
return ESP_ERR_INVALID_STATE;
} else {
esp_err_t ret = ESP_OK;
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
if (p_pos->rd == p_pos->wr) {
ret = ESP_FAIL;
} else {
p_pos->rd++;
}
if (p_pos->rd >= p_pos->len) {
p_pos->rd = 0;
}
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ret;
}
}
static esp_err_t uart_pattern_queue_update(uart_port_t uart_num, int diff_len)
{
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
int rd = p_pos->rd;
while(rd != p_pos->wr) {
p_pos->data[rd] -= diff_len;
int rd_rec = rd;
rd ++;
if (rd >= p_pos->len) {
rd = 0;
}
if (p_pos->data[rd_rec] < 0) {
p_pos->rd = rd;
}
}
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
int uart_pattern_pop_pos(uart_port_t uart_num)
{
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
int pos = -1;
if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
pos = pat_pos->data[pat_pos->rd];
uart_pattern_dequeue(uart_num);
}
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return pos;
}
esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
int* pdata = (int*) malloc(queue_length * sizeof(int));
if(pdata == NULL) {
return ESP_ERR_NO_MEM;
}
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
int* ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data;
p_uart_obj[uart_num]->rx_pattern_pos.data = pdata;
p_uart_obj[uart_num]->rx_pattern_pos.len = queue_length;
p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
free(ptmp);
return ESP_OK;
}
esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
@@ -531,26 +657,42 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_
return ESP_OK;
}
static int uart_find_pattern_from_last(uint8_t* buf, int length, uint8_t pat_chr, int pat_num)
{
int cnt = 0;
int len = length;
while (len >= 0) {
if (buf[len] == pat_chr) {
cnt++;
} else {
cnt = 0;
}
if (cnt >= pat_num) {
break;
}
len --;
}
return len;
}
//internal isr handler for default driver code.
static void uart_rx_intr_handler_default(void *param)
{
uart_obj_t *p_uart = (uart_obj_t*) param;
uint8_t uart_num = p_uart->uart_num;
uart_dev_t* uart_reg = UART[uart_num];
int rx_fifo_len = uart_reg->status.rxfifo_cnt;
uint8_t buf_idx = 0;
uint32_t uart_intr_status = UART[uart_num]->int_st.val;
int rx_fifo_len = 0;
uart_event_t uart_event;
portBASE_TYPE HPTaskAwoken = 0;
static uint8_t pat_flg = 0;
while(uart_intr_status != 0x0) {
buf_idx = 0;
uart_event.type = UART_EVENT_MAX;
if(uart_intr_status & UART_TXFIFO_EMPTY_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.txfifo_empty = 0;
uart_reg->int_clr.txfifo_empty = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_clear_intr_status(uart_num, UART_TXFIFO_EMPTY_INT_CLR_M);
uart_disable_intr_mask(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M);
if(p_uart->tx_waiting_brk) {
continue;
}
@@ -561,8 +703,7 @@ static void uart_rx_intr_handler_default(void *param)
if(HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR() ;
}
}
else {
} else {
//We don't use TX ring buffer, because the size is zero.
if(p_uart->tx_buf_size == 0) {
continue;
@@ -604,7 +745,7 @@ static void uart_rx_intr_handler_default(void *param)
break;
}
}
if(p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) {
if (p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) {
//To fill the TX FIFO.
int send_len = p_uart->tx_len_cur > tx_fifo_rem ? tx_fifo_rem : p_uart->tx_len_cur;
for(buf_idx = 0; buf_idx < send_len; buf_idx++) {
@@ -613,7 +754,7 @@ static void uart_rx_intr_handler_default(void *param)
p_uart->tx_len_tot -= send_len;
p_uart->tx_len_cur -= send_len;
tx_fifo_rem -= send_len;
if(p_uart->tx_len_cur == 0) {
if (p_uart->tx_len_cur == 0) {
//Return item to ring buffer.
vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
if(HPTaskAwoken == pdTRUE) {
@@ -642,62 +783,96 @@ static void uart_rx_intr_handler_default(void *param)
}
}
}
if(en_tx_flg) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_clr.txfifo_empty = 1;
uart_reg->int_ena.txfifo_empty = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
if (en_tx_flg) {
uart_clear_intr_status(uart_num, UART_TXFIFO_EMPTY_INT_CLR_M);
uart_enable_intr_mask(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M);
}
}
}
else if((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M) || (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M)) {
if(p_uart->rx_buffer_full_flg == false) {
//Get the buffer from the FIFO
rx_fifo_len = uart_reg->status.rxfifo_cnt;
p_uart->rx_stash_len = rx_fifo_len;
else if ((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M)
|| (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M)
|| (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M)
) {
rx_fifo_len = uart_reg->status.rxfifo_cnt;
if(pat_flg == 1) {
uart_intr_status |= UART_AT_CMD_CHAR_DET_INT_ST_M;
pat_flg = 0;
}
if (p_uart->rx_buffer_full_flg == false) {
//We have to read out all data in RX FIFO to clear the interrupt signal
while(buf_idx < rx_fifo_len) {
while (buf_idx < rx_fifo_len) {
p_uart->rx_data_buf[buf_idx++] = uart_reg->fifo.rw_byte;
}
//After Copying the Data From FIFO ,Clear intr_status
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_clr.rxfifo_tout = 1;
uart_reg->int_clr.rxfifo_full = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.size = rx_fifo_len;
uint8_t pat_chr = uart_reg->at_cmd_char.data;
int pat_num = uart_reg->at_cmd_char.char_num;
int pat_idx = -1;
//Get the buffer from the FIFO
if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
uart_clear_intr_status(uart_num, UART_AT_CMD_CHAR_DET_INT_CLR_M);
uart_event.type = UART_PATTERN_DET;
uart_event.size = rx_fifo_len;
pat_idx = uart_find_pattern_from_last(p_uart->rx_data_buf, rx_fifo_len - 1, pat_chr, pat_num);
} else {
//After Copying the Data From FIFO ,Clear intr_status
uart_clear_intr_status(uart_num, UART_RXFIFO_TOUT_INT_CLR_M | UART_RXFIFO_FULL_INT_CLR_M);
uart_event.type = UART_DATA;
uart_event.size = rx_fifo_len;
}
p_uart->rx_stash_len = rx_fifo_len;
//If we fail to push data to ring buffer, we will have to stash the data, and send next time.
//Mainly for applications that uses flow control or small ring buffer.
if(pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.rxfifo_full = 0;
uart_reg->int_ena.rxfifo_tout = 0;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
p_uart->rx_buffer_full_flg = true;
uart_disable_intr_mask(uart_num, UART_RXFIFO_TOUT_INT_ENA_M | UART_RXFIFO_FULL_INT_ENA_M);
if (uart_event.type == UART_PATTERN_DET) {
if (rx_fifo_len < pat_num) {
//some of the characters are read out in last interrupt
uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
} else {
uart_pattern_enqueue(uart_num,
pat_idx <= -1 ?
//can not find the pattern in buffer,
p_uart->rx_buffered_len + p_uart->rx_stash_len :
// find the pattern in buffer
p_uart->rx_buffered_len + pat_idx);
}
if ((p_uart->xQueueUart != NULL) && (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken))) {
ESP_EARLY_LOGW(UART_TAG, "UART event queue full");
}
}
uart_event.type = UART_BUFFER_FULL;
p_uart->rx_buffer_full_flg = true;
} else {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
if (rx_fifo_len < pat_num) {
//some of the characters are read out in last interrupt
uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
} else if(pat_idx >= 0) {
// find pattern in statsh buffer.
uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len + pat_idx);
}
}
p_uart->rx_buffered_len += p_uart->rx_stash_len;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.type = UART_DATA;
}
if(HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR() ;
}
} else {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.rxfifo_full = 0;
uart_reg->int_ena.rxfifo_tout = 0;
uart_reg->int_clr.val = UART_RXFIFO_FULL_INT_CLR_M | UART_RXFIFO_TOUT_INT_CLR_M;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.type = UART_BUFFER_FULL;
uart_disable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA_M | UART_RXFIFO_TOUT_INT_ENA_M);
uart_clear_intr_status(uart_num, UART_RXFIFO_FULL_INT_CLR_M | UART_RXFIFO_TOUT_INT_CLR_M);
if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
uart_reg->int_clr.at_cmd_char_det = 1;
uart_event.type = UART_PATTERN_DET;
uart_event.size = rx_fifo_len;
pat_flg = 1;
}
}
} else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
// When fifo overflows, we reset the fifo.
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
// Read all data from the FIFO
rx_fifo_len = uart_reg->status.rxfifo_cnt;
for (int i = 0; i < rx_fifo_len; i++) {
READ_PERI_REG(UART_FIFO_REG(uart_num));
}
uart_reset_rx_fifo(uart_num);
uart_reg->int_clr.rxfifo_ovf = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.type = UART_FIFO_OVF;
@@ -729,18 +904,14 @@ static void uart_rx_intr_handler_default(void *param)
}
}
} else if(uart_intr_status & UART_TX_BRK_IDLE_DONE_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.tx_brk_idle_done = 0;
uart_reg->int_clr.tx_brk_idle_done = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_disable_intr_mask(uart_num, UART_TX_BRK_IDLE_DONE_INT_ENA_M);
uart_clear_intr_status(uart_num, UART_TX_BRK_IDLE_DONE_INT_CLR_M);
} else if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
uart_reg->int_clr.at_cmd_char_det = 1;
uart_event.type = UART_PATTERN_DET;
} else if(uart_intr_status & UART_TX_DONE_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.tx_done = 0;
uart_reg->int_clr.tx_done = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_disable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M);
uart_clear_intr_status(uart_num, UART_TX_DONE_INT_CLR_M);
xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken);
if(HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR() ;
@@ -751,7 +922,9 @@ static void uart_rx_intr_handler_default(void *param)
}
if(uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) {
xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken);
if (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken)) {
ESP_EARLY_LOGW(UART_TAG, "UART event queue full");
}
if(HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR() ;
}
@@ -858,7 +1031,6 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool
offset += send_size;
uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
}
xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
} else {
while(size) {
//semaphore for tx_fifo available
@@ -921,9 +1093,6 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
p_uart_obj[uart_num]->rx_cur_remain = size;
} else {
xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
p_uart_obj[uart_num]->rx_buffered_len -= copy_len;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return copy_len;
}
}
@@ -933,7 +1102,11 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
len_tmp = p_uart_obj[uart_num]->rx_cur_remain;
}
memcpy(buf + copy_len, p_uart_obj[uart_num]->rx_ptr, len_tmp);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
p_uart_obj[uart_num]->rx_buffered_len -= len_tmp;
uart_pattern_queue_update(uart_num, len_tmp);
p_uart_obj[uart_num]->rx_ptr += len_tmp;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
p_uart_obj[uart_num]->rx_cur_remain -= len_tmp;
copy_len += len_tmp;
length -= len_tmp;
@@ -953,10 +1126,8 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
}
}
}
xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
p_uart_obj[uart_num]->rx_buffered_len -= copy_len;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return copy_len;
}
@@ -968,7 +1139,9 @@ esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size)
return ESP_OK;
}
esp_err_t uart_flush(uart_port_t uart_num)
esp_err_t uart_flush(uart_port_t uart_num) __attribute__((alias("uart_flush_input")));
esp_err_t uart_flush_input(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
@@ -984,6 +1157,7 @@ esp_err_t uart_flush(uart_port_t uart_num)
vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain;
uart_pattern_queue_update(uart_num, p_uart->rx_cur_remain);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
p_uart->rx_ptr = NULL;
p_uart->rx_cur_remain = 0;
@@ -995,6 +1169,7 @@ esp_err_t uart_flush(uart_port_t uart_num)
}
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
p_uart_obj[uart_num]->rx_buffered_len -= size;
uart_pattern_queue_update(uart_num, size);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
vRingbufferReturnItem(p_uart->rx_ring_buf, data);
if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
@@ -1025,7 +1200,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
UART_CHECK((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM set in intr_alloc_flags", ESP_FAIL); /* uart_rx_intr_handler_default is not in IRAM */
if(p_uart_obj[uart_num] == NULL) {
p_uart_obj[uart_num] = (uart_obj_t*) malloc(sizeof(uart_obj_t));
p_uart_obj[uart_num] = (uart_obj_t*) calloc(1, sizeof(uart_obj_t));
if(p_uart_obj[uart_num] == NULL) {
ESP_LOGE(UART_TAG, "UART driver malloc error");
return ESP_FAIL;
@@ -1045,6 +1220,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
p_uart_obj[uart_num]->tx_brk_len = 0;
p_uart_obj[uart_num]->tx_waiting_brk = 0;
p_uart_obj[uart_num]->rx_buffered_len = 0;
uart_pattern_queue_reset(uart_num, UART_PATTERN_DET_QLEN_DEFAULT);
if(uart_queue) {
p_uart_obj[uart_num]->xQueueUart = xQueueCreate(queue_size, sizeof(uart_event_t));
@@ -1104,6 +1280,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
esp_intr_free(p_uart_obj[uart_num]->intr_handle);
uart_disable_rx_intr(uart_num);
uart_disable_tx_intr(uart_num);
uart_pattern_link_free(uart_num);
if(p_uart_obj[uart_num]->tx_fifo_sem) {
vSemaphoreDelete(p_uart_obj[uart_num]->tx_fifo_sem);

15
components/soc/esp32/include/soc/uart_reg.h
View File

@@ -1105,11 +1105,24 @@
#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60)
/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: */
/*description: This register stores the current uart rx mem read address
and rx mem write address */
#define UART_MEM_RX_STATUS 0x00FFFFFF
#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S))
#define UART_MEM_RX_STATUS_V 0xFFFFFF
#define UART_MEM_RX_STATUS_S 0
/* UART_MEM_RX_RD_ADDR : RO ;bitpos:[12:2] ;default: 11'h0 ; */
/*description: This register stores the rx mem read address */
#define UART_MEM_RX_RD_ADDR 0x000007FF
#define UART_MEM_RX_RD_ADDR_M ((UART_MEM_RX_RD_ADDR_V)<<(UART_MEM_RX_RD_ADDR_S))
#define UART_MEM_RX_RD_ADDR_V (0x7FF)
#define UART_MEM_RX_RD_ADDR_S (2)
/* UART_MEM_RX_WR_ADDR : RO ;bitpos:[23:13] ;default: 11'h0 ; */
/*description: This register stores the rx mem write address */
#define UART_MEM_RX_WR_ADDR 0x000007FF
#define UART_MEM_RX_WR_ADDR_M ((UART_MEM_RX_WR_ADDR_V)<<(UART_MEM_RX_WR_ADDR_S))
#define UART_MEM_RX_WR_ADDR_V (0x7FF)
#define UART_MEM_RX_WR_ADDR_S (13)
#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */

10
components/soc/esp32/include/soc/uart_struct.h
View File

@@ -332,8 +332,14 @@ typedef volatile struct {
} mem_tx_status;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
uint32_t status: 24;
uint32_t reserved24: 8;
};
struct {
uint32_t reserved0: 2;
uint32_t rd_addr: 11; /*This register stores the rx mem read address.*/
uint32_t wr_addr: 11; /*This register stores the rx mem write address.*/
uint32_t reserved: 8;
};
uint32_t val;
} mem_rx_status;