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RISCV-ULP: Add DS18B20 1wire RISCV-ULP example

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Marius Vikhammer
2021-06-23 14:54:36 +08:00
parent 67743ac444
commit 386739595f
38 changed files with 369 additions and 25 deletions
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4
tools/ci/mypy_ignore_list.txt
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@@ -144,8 +144,8 @@ examples/system/startup_time/example_test.py
examples/system/sysview_tracing/example_test.py
examples/system/sysview_tracing_heap_log/example_test.py
examples/system/task_watchdog/example_test.py
examples/system/ulp/example_test.py
examples/system/ulp_adc/example_test.py
examples/system/ulp_fsm/ulp/example_test.py
examples/system/ulp_fsm/ulp_adc/example_test.py
examples/system/unit_test/example_test.py
examples/wifi/iperf/iperf_test.py
tools/ble/lib_ble_client.py