RISCV-ULP: Add DS18B20 1wire RISCV-ULP example

This commit is contained in:
Marius Vikhammer
2021-06-23 14:54:36 +08:00
parent 67743ac444
commit 386739595f
38 changed files with 369 additions and 25 deletions

View File

@@ -0,0 +1,24 @@
#
# ULP support additions to component makefile.
#
# 1. ULP_APP_NAME must be unique (if multiple components use ULP)
# Default value, override if necessary:
ULP_APP_NAME ?= ulp_$(COMPONENT_NAME)
#
# 2. Specify all assembly source files here.
# Files should be placed into a separate directory (in this case, ulp/),
# which should not be added to COMPONENT_SRCDIRS.
ULP_S_SOURCES = $(addprefix $(COMPONENT_PATH)/ulp/, \
pulse_cnt.S \
wake_up.S \
)
#
# 3. List all the component object files which include automatically
# generated ULP export file, $(ULP_APP_NAME).h:
ULP_EXP_DEP_OBJECTS := ulp_example_main.o
#
# 4. Include build rules for ULP program
include $(IDF_PATH)/components/ulp/component_ulp_common.mk
#
# End of ULP support additions to component makefile.
#