// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_EXTMEM_REG_H_
#define _SOC_EXTMEM_REG_H_


#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DPORT_PRO_DCACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x000)
/* DPORT_PRO_DCACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_UNLOCK_DONE  (BIT(23))
#define DPORT_PRO_DCACHE_UNLOCK_DONE_M  (BIT(23))
#define DPORT_PRO_DCACHE_UNLOCK_DONE_V  0x1
#define DPORT_PRO_DCACHE_UNLOCK_DONE_S  23
/* DPORT_PRO_DCACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_UNLOCK_ENA  (BIT(22))
#define DPORT_PRO_DCACHE_UNLOCK_ENA_M  (BIT(22))
#define DPORT_PRO_DCACHE_UNLOCK_ENA_V  0x1
#define DPORT_PRO_DCACHE_UNLOCK_ENA_S  22
/* DPORT_PRO_DCACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_DONE  (BIT(21))
#define DPORT_PRO_DCACHE_PRELOAD_DONE_M  (BIT(21))
#define DPORT_PRO_DCACHE_PRELOAD_DONE_V  0x1
#define DPORT_PRO_DCACHE_PRELOAD_DONE_S  21
/* DPORT_PRO_DCACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_ENA  (BIT(20))
#define DPORT_PRO_DCACHE_PRELOAD_ENA_M  (BIT(20))
#define DPORT_PRO_DCACHE_PRELOAD_ENA_V  0x1
#define DPORT_PRO_DCACHE_PRELOAD_ENA_S  20
/* DPORT_PRO_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_DONE  (BIT(19))
#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_M  (BIT(19))
#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_V  0x1
#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_S  19
/* DPORT_PRO_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_ENA  (BIT(18))
#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_M  (BIT(18))
#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_V  0x1
#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_S  18
/* DPORT_PRO_DCACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_LOCK1_EN  (BIT(15))
#define DPORT_PRO_DCACHE_LOCK1_EN_M  (BIT(15))
#define DPORT_PRO_DCACHE_LOCK1_EN_V  0x1
#define DPORT_PRO_DCACHE_LOCK1_EN_S  15
/* DPORT_PRO_DCACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_LOCK0_EN  (BIT(14))
#define DPORT_PRO_DCACHE_LOCK0_EN_M  (BIT(14))
#define DPORT_PRO_DCACHE_LOCK0_EN_V  0x1
#define DPORT_PRO_DCACHE_LOCK0_EN_S  14
/* DPORT_PRO_DCACHE_CLEAN_DONE : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_CLEAN_DONE  (BIT(13))
#define DPORT_PRO_DCACHE_CLEAN_DONE_M  (BIT(13))
#define DPORT_PRO_DCACHE_CLEAN_DONE_V  0x1
#define DPORT_PRO_DCACHE_CLEAN_DONE_S  13
/* DPORT_PRO_DCACHE_CLEAN_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_CLEAN_ENA  (BIT(12))
#define DPORT_PRO_DCACHE_CLEAN_ENA_M  (BIT(12))
#define DPORT_PRO_DCACHE_CLEAN_ENA_V  0x1
#define DPORT_PRO_DCACHE_CLEAN_ENA_S  12
/* DPORT_PRO_DCACHE_FLUSH_DONE : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_FLUSH_DONE  (BIT(11))
#define DPORT_PRO_DCACHE_FLUSH_DONE_M  (BIT(11))
#define DPORT_PRO_DCACHE_FLUSH_DONE_V  0x1
#define DPORT_PRO_DCACHE_FLUSH_DONE_S  11
/* DPORT_PRO_DCACHE_FLUSH_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_FLUSH_ENA  (BIT(10))
#define DPORT_PRO_DCACHE_FLUSH_ENA_M  (BIT(10))
#define DPORT_PRO_DCACHE_FLUSH_ENA_V  0x1
#define DPORT_PRO_DCACHE_FLUSH_ENA_S  10
/* DPORT_PRO_DCACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_INVALIDATE_DONE  (BIT(9))
#define DPORT_PRO_DCACHE_INVALIDATE_DONE_M  (BIT(9))
#define DPORT_PRO_DCACHE_INVALIDATE_DONE_V  0x1
#define DPORT_PRO_DCACHE_INVALIDATE_DONE_S  9
/* DPORT_PRO_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_DCACHE_INVALIDATE_ENA  (BIT(8))
#define DPORT_PRO_DCACHE_INVALIDATE_ENA_M  (BIT(8))
#define DPORT_PRO_DCACHE_INVALIDATE_ENA_V  0x1
#define DPORT_PRO_DCACHE_INVALIDATE_ENA_S  8
/* DPORT_PRO_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE  0x00000003
#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_M  ((DPORT_PRO_DCACHE_BLOCKSIZE_MODE_V)<<(DPORT_PRO_DCACHE_BLOCKSIZE_MODE_S))
#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_V  0x3
#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_S  3
/* DPORT_PRO_DCACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_SETSIZE_MODE  (BIT(2))
#define DPORT_PRO_DCACHE_SETSIZE_MODE_M  (BIT(2))
#define DPORT_PRO_DCACHE_SETSIZE_MODE_V  0x1
#define DPORT_PRO_DCACHE_SETSIZE_MODE_S  2
/* DPORT_PRO_DCACHE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_MODE  (BIT(1))
#define DPORT_PRO_DCACHE_MODE_M  (BIT(1))
#define DPORT_PRO_DCACHE_MODE_V  0x1
#define DPORT_PRO_DCACHE_MODE_S  1
/* DPORT_PRO_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_ENABLE  (BIT(0))
#define DPORT_PRO_DCACHE_ENABLE_M  (BIT(0))
#define DPORT_PRO_DCACHE_ENABLE_V  0x1
#define DPORT_PRO_DCACHE_ENABLE_S  0

#define DPORT_PRO_DCACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x004)
/* DPORT_PRO_DCACHE_MASK_BUS3 : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_DCACHE_MASK_BUS3  (BIT(3))
#define DPORT_PRO_DCACHE_MASK_BUS3_M  (BIT(3))
#define DPORT_PRO_DCACHE_MASK_BUS3_V  0x1
#define DPORT_PRO_DCACHE_MASK_BUS3_S  3
/* DPORT_PRO_DCACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_DCACHE_MASK_BUS2  (BIT(2))
#define DPORT_PRO_DCACHE_MASK_BUS2_M  (BIT(2))
#define DPORT_PRO_DCACHE_MASK_BUS2_V  0x1
#define DPORT_PRO_DCACHE_MASK_BUS2_S  2
/* DPORT_PRO_DCACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_DCACHE_MASK_BUS1  (BIT(1))
#define DPORT_PRO_DCACHE_MASK_BUS1_M  (BIT(1))
#define DPORT_PRO_DCACHE_MASK_BUS1_V  0x1
#define DPORT_PRO_DCACHE_MASK_BUS1_S  1
/* DPORT_PRO_DCACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_DCACHE_MASK_BUS0  (BIT(0))
#define DPORT_PRO_DCACHE_MASK_BUS0_M  (BIT(0))
#define DPORT_PRO_DCACHE_MASK_BUS0_V  0x1
#define DPORT_PRO_DCACHE_MASK_BUS0_S  0
#define DPORT_PRO_DCACHE_MASK_DRAM0 DPORT_PRO_DCACHE_MASK_BUS0
#define DPORT_PRO_DCACHE_MASK_DRAM1 DPORT_PRO_DCACHE_MASK_BUS1
#define DPORT_PRO_DCACHE_MASK_DPORT DPORT_PRO_DCACHE_MASK_BUS2
#define DPORT_PRO_DCACHE_MASK_DROM0 DPORT_PRO_DCACHE_MASK_BUS3

#define DPORT_PRO_DCACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x008)
/* DPORT_PRO_DCACHE_TAG_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_TAG_MEM_PD  (BIT(1))
#define DPORT_PRO_DCACHE_TAG_MEM_PD_M  (BIT(1))
#define DPORT_PRO_DCACHE_TAG_MEM_PD_V  0x1
#define DPORT_PRO_DCACHE_TAG_MEM_PD_S  1
/* DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON  (BIT(0))
#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_V  0x1
#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_S  0

#define DPORT_PRO_DCACHE_LOCK0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x00C)
/* DPORT_PRO_DCACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
/*description: */
#define DPORT_PRO_DCACHE_LOCK0_ADDR  0xFFFFFFFF
#define DPORT_PRO_DCACHE_LOCK0_ADDR_M  ((DPORT_PRO_DCACHE_LOCK0_ADDR_V)<<(DPORT_PRO_DCACHE_LOCK0_ADDR_S))
#define DPORT_PRO_DCACHE_LOCK0_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_DCACHE_LOCK0_ADDR_S  0

#define DPORT_PRO_DCACHE_LOCK0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x010)
/* DPORT_PRO_DCACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define DPORT_PRO_DCACHE_LOCK0_SIZE  0x0000FFFF
#define DPORT_PRO_DCACHE_LOCK0_SIZE_M  ((DPORT_PRO_DCACHE_LOCK0_SIZE_V)<<(DPORT_PRO_DCACHE_LOCK0_SIZE_S))
#define DPORT_PRO_DCACHE_LOCK0_SIZE_V  0xFFFF
#define DPORT_PRO_DCACHE_LOCK0_SIZE_S  0

#define DPORT_PRO_DCACHE_LOCK1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x014)
/* DPORT_PRO_DCACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
/*description: */
#define DPORT_PRO_DCACHE_LOCK1_ADDR  0xFFFFFFFF
#define DPORT_PRO_DCACHE_LOCK1_ADDR_M  ((DPORT_PRO_DCACHE_LOCK1_ADDR_V)<<(DPORT_PRO_DCACHE_LOCK1_ADDR_S))
#define DPORT_PRO_DCACHE_LOCK1_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_DCACHE_LOCK1_ADDR_S  0

#define DPORT_PRO_DCACHE_LOCK1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x018)
/* DPORT_PRO_DCACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define DPORT_PRO_DCACHE_LOCK1_SIZE  0x0000FFFF
#define DPORT_PRO_DCACHE_LOCK1_SIZE_M  ((DPORT_PRO_DCACHE_LOCK1_SIZE_V)<<(DPORT_PRO_DCACHE_LOCK1_SIZE_S))
#define DPORT_PRO_DCACHE_LOCK1_SIZE_V  0xFFFF
#define DPORT_PRO_DCACHE_LOCK1_SIZE_S  0

#define DPORT_PRO_DCACHE_MEM_SYNC0_REG          (DR_REG_EXTMEM_BASE + 0x01C)
/* DPORT_PRO_DCACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_MEMSYNC_ADDR  0xFFFFFFFF
#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_M  ((DPORT_PRO_DCACHE_MEMSYNC_ADDR_V)<<(DPORT_PRO_DCACHE_MEMSYNC_ADDR_S))
#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_S  0

#define DPORT_PRO_DCACHE_MEM_SYNC1_REG          (DR_REG_EXTMEM_BASE + 0x020)
/* DPORT_PRO_DCACHE_MEMSYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h400000 ; */
/*description: */
#define DPORT_PRO_DCACHE_MEMSYNC_SIZE  0x007FFFFF
#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_M  ((DPORT_PRO_DCACHE_MEMSYNC_SIZE_V)<<(DPORT_PRO_DCACHE_MEMSYNC_SIZE_S))
#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_V  0x7FFFFF
#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_S  0

#define DPORT_PRO_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x024)
/* DPORT_PRO_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_ADDR  0xFFFFFFFF
#define DPORT_PRO_DCACHE_PRELOAD_ADDR_M  ((DPORT_PRO_DCACHE_PRELOAD_ADDR_V)<<(DPORT_PRO_DCACHE_PRELOAD_ADDR_S))
#define DPORT_PRO_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_DCACHE_PRELOAD_ADDR_S  0

#define DPORT_PRO_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x028)
/* DPORT_PRO_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_ORDER  (BIT(16))
#define DPORT_PRO_DCACHE_PRELOAD_ORDER_M  (BIT(16))
#define DPORT_PRO_DCACHE_PRELOAD_ORDER_V  0x1
#define DPORT_PRO_DCACHE_PRELOAD_ORDER_S  16
/* DPORT_PRO_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h8000 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_SIZE  0x0000FFFF
#define DPORT_PRO_DCACHE_PRELOAD_SIZE_M  ((DPORT_PRO_DCACHE_PRELOAD_SIZE_V)<<(DPORT_PRO_DCACHE_PRELOAD_SIZE_S))
#define DPORT_PRO_DCACHE_PRELOAD_SIZE_V  0xFFFF
#define DPORT_PRO_DCACHE_PRELOAD_SIZE_S  0

#define DPORT_PRO_DCACHE_AUTOLOAD_CFG_REG          (DR_REG_EXTMEM_BASE + 0x02C)
/* DPORT_PRO_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[21:6] ;default: 16'h1 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE  0x0000FFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SIZE_S))
#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_V  0xFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_S  6
/* DPORT_PRO_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_RQST  0x00000003
#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_M  ((DPORT_PRO_DCACHE_AUTOLOAD_RQST_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_RQST_S))
#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_V  0x3
#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_S  4
/* DPORT_PRO_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER  (BIT(3))
#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_M  (BIT(3))
#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_V  0x1
#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_S  3
/* DPORT_PRO_DCACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_STEP  0x00000003
#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_M  ((DPORT_PRO_DCACHE_AUTOLOAD_STEP_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_STEP_S))
#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_V  0x3
#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_S  1
/* DPORT_PRO_DCACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_MODE  (BIT(0))
#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_M  (BIT(0))
#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_V  0x1
#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_S  0

#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x030)
/* DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S))
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S  0

#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x034)
/* DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE  0x00FFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S))
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S  0

#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x038)
/* DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S))
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S  0

#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x03C)
/* DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
/*description: */
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE  0x00FFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S))
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S  0

#define DPORT_PRO_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x040)
/* DPORT_PRO_ICACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_UNLOCK_DONE  (BIT(23))
#define DPORT_PRO_ICACHE_UNLOCK_DONE_M  (BIT(23))
#define DPORT_PRO_ICACHE_UNLOCK_DONE_V  0x1
#define DPORT_PRO_ICACHE_UNLOCK_DONE_S  23
/* DPORT_PRO_ICACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_UNLOCK_ENA  (BIT(22))
#define DPORT_PRO_ICACHE_UNLOCK_ENA_M  (BIT(22))
#define DPORT_PRO_ICACHE_UNLOCK_ENA_V  0x1
#define DPORT_PRO_ICACHE_UNLOCK_ENA_S  22
/* DPORT_PRO_ICACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_DONE  (BIT(21))
#define DPORT_PRO_ICACHE_PRELOAD_DONE_M  (BIT(21))
#define DPORT_PRO_ICACHE_PRELOAD_DONE_V  0x1
#define DPORT_PRO_ICACHE_PRELOAD_DONE_S  21
/* DPORT_PRO_ICACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_ENA  (BIT(20))
#define DPORT_PRO_ICACHE_PRELOAD_ENA_M  (BIT(20))
#define DPORT_PRO_ICACHE_PRELOAD_ENA_V  0x1
#define DPORT_PRO_ICACHE_PRELOAD_ENA_S  20
/* DPORT_PRO_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_DONE  (BIT(19))
#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_M  (BIT(19))
#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_V  0x1
#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_S  19
/* DPORT_PRO_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_ENA  (BIT(18))
#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_M  (BIT(18))
#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_V  0x1
#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_S  18
/* DPORT_PRO_ICACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_LOCK1_EN  (BIT(15))
#define DPORT_PRO_ICACHE_LOCK1_EN_M  (BIT(15))
#define DPORT_PRO_ICACHE_LOCK1_EN_V  0x1
#define DPORT_PRO_ICACHE_LOCK1_EN_S  15
/* DPORT_PRO_ICACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_LOCK0_EN  (BIT(14))
#define DPORT_PRO_ICACHE_LOCK0_EN_M  (BIT(14))
#define DPORT_PRO_ICACHE_LOCK0_EN_V  0x1
#define DPORT_PRO_ICACHE_LOCK0_EN_S  14
/* DPORT_PRO_ICACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_INVALIDATE_DONE  (BIT(9))
#define DPORT_PRO_ICACHE_INVALIDATE_DONE_M  (BIT(9))
#define DPORT_PRO_ICACHE_INVALIDATE_DONE_V  0x1
#define DPORT_PRO_ICACHE_INVALIDATE_DONE_S  9
/* DPORT_PRO_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_ICACHE_INVALIDATE_ENA  (BIT(8))
#define DPORT_PRO_ICACHE_INVALIDATE_ENA_M  (BIT(8))
#define DPORT_PRO_ICACHE_INVALIDATE_ENA_V  0x1
#define DPORT_PRO_ICACHE_INVALIDATE_ENA_S  8
/* DPORT_PRO_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE  0x00000003
#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_M  ((DPORT_PRO_ICACHE_BLOCKSIZE_MODE_V)<<(DPORT_PRO_ICACHE_BLOCKSIZE_MODE_S))
#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_V  0x3
#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_S  3
/* DPORT_PRO_ICACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_SETSIZE_MODE  (BIT(2))
#define DPORT_PRO_ICACHE_SETSIZE_MODE_M  (BIT(2))
#define DPORT_PRO_ICACHE_SETSIZE_MODE_V  0x1
#define DPORT_PRO_ICACHE_SETSIZE_MODE_S  2
/* DPORT_PRO_ICACHE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_MODE  (BIT(1))
#define DPORT_PRO_ICACHE_MODE_M  (BIT(1))
#define DPORT_PRO_ICACHE_MODE_V  0x1
#define DPORT_PRO_ICACHE_MODE_S  1
/* DPORT_PRO_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_ENABLE  (BIT(0))
#define DPORT_PRO_ICACHE_ENABLE_M  (BIT(0))
#define DPORT_PRO_ICACHE_ENABLE_V  0x1
#define DPORT_PRO_ICACHE_ENABLE_S  0

#define DPORT_PRO_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x044)
/* DPORT_PRO_ICACHE_MASK_BUS3 : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_ICACHE_MASK_BUS3  (BIT(3))
#define DPORT_PRO_ICACHE_MASK_BUS3_M  (BIT(3))
#define DPORT_PRO_ICACHE_MASK_BUS3_V  0x1
#define DPORT_PRO_ICACHE_MASK_BUS3_S  3
/* DPORT_PRO_ICACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_ICACHE_MASK_BUS2  (BIT(2))
#define DPORT_PRO_ICACHE_MASK_BUS2_M  (BIT(2))
#define DPORT_PRO_ICACHE_MASK_BUS2_V  0x1
#define DPORT_PRO_ICACHE_MASK_BUS2_S  2
/* DPORT_PRO_ICACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_ICACHE_MASK_BUS1  (BIT(1))
#define DPORT_PRO_ICACHE_MASK_BUS1_M  (BIT(1))
#define DPORT_PRO_ICACHE_MASK_BUS1_V  0x1
#define DPORT_PRO_ICACHE_MASK_BUS1_S  1
/* DPORT_PRO_ICACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_ICACHE_MASK_BUS0  (BIT(0))
#define DPORT_PRO_ICACHE_MASK_BUS0_M  (BIT(0))
#define DPORT_PRO_ICACHE_MASK_BUS0_V  0x1
#define DPORT_PRO_ICACHE_MASK_BUS0_S  0
#define DPORT_PRO_ICACHE_MASK_IRAM0 DPORT_PRO_ICACHE_MASK_BUS0
#define DPORT_PRO_ICACHE_MASK_IRAM1 DPORT_PRO_ICACHE_MASK_BUS1
#define DPORT_PRO_ICACHE_MASK_IROM0 DPORT_PRO_ICACHE_MASK_BUS2
#define DPORT_PRO_ICACHE_MASK_DROM0 DPORT_PRO_ICACHE_MASK_BUS3

#define DPORT_PRO_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x048)
/* DPORT_PRO_ICACHE_TAG_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_TAG_MEM_PD  (BIT(1))
#define DPORT_PRO_ICACHE_TAG_MEM_PD_M  (BIT(1))
#define DPORT_PRO_ICACHE_TAG_MEM_PD_V  0x1
#define DPORT_PRO_ICACHE_TAG_MEM_PD_S  1
/* DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON  (BIT(0))
#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_V  0x1
#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_S  0

#define DPORT_PRO_ICACHE_LOCK0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x04C)
/* DPORT_PRO_ICACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
/*description: */
#define DPORT_PRO_ICACHE_LOCK0_ADDR  0xFFFFFFFF
#define DPORT_PRO_ICACHE_LOCK0_ADDR_M  ((DPORT_PRO_ICACHE_LOCK0_ADDR_V)<<(DPORT_PRO_ICACHE_LOCK0_ADDR_S))
#define DPORT_PRO_ICACHE_LOCK0_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_ICACHE_LOCK0_ADDR_S  0

#define DPORT_PRO_ICACHE_LOCK0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x050)
/* DPORT_PRO_ICACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define DPORT_PRO_ICACHE_LOCK0_SIZE  0x0000FFFF
#define DPORT_PRO_ICACHE_LOCK0_SIZE_M  ((DPORT_PRO_ICACHE_LOCK0_SIZE_V)<<(DPORT_PRO_ICACHE_LOCK0_SIZE_S))
#define DPORT_PRO_ICACHE_LOCK0_SIZE_V  0xFFFF
#define DPORT_PRO_ICACHE_LOCK0_SIZE_S  0

#define DPORT_PRO_ICACHE_LOCK1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x054)
/* DPORT_PRO_ICACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
/*description: */
#define DPORT_PRO_ICACHE_LOCK1_ADDR  0xFFFFFFFF
#define DPORT_PRO_ICACHE_LOCK1_ADDR_M  ((DPORT_PRO_ICACHE_LOCK1_ADDR_V)<<(DPORT_PRO_ICACHE_LOCK1_ADDR_S))
#define DPORT_PRO_ICACHE_LOCK1_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_ICACHE_LOCK1_ADDR_S  0

#define DPORT_PRO_ICACHE_LOCK1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x058)
/* DPORT_PRO_ICACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define DPORT_PRO_ICACHE_LOCK1_SIZE  0x0000FFFF
#define DPORT_PRO_ICACHE_LOCK1_SIZE_M  ((DPORT_PRO_ICACHE_LOCK1_SIZE_V)<<(DPORT_PRO_ICACHE_LOCK1_SIZE_S))
#define DPORT_PRO_ICACHE_LOCK1_SIZE_V  0xFFFF
#define DPORT_PRO_ICACHE_LOCK1_SIZE_S  0

#define DPORT_PRO_ICACHE_MEM_SYNC0_REG          (DR_REG_EXTMEM_BASE + 0x05C)
/* DPORT_PRO_ICACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_MEMSYNC_ADDR  0xFFFFFFFF
#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_M  ((DPORT_PRO_ICACHE_MEMSYNC_ADDR_V)<<(DPORT_PRO_ICACHE_MEMSYNC_ADDR_S))
#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_S  0

#define DPORT_PRO_ICACHE_MEM_SYNC1_REG          (DR_REG_EXTMEM_BASE + 0x060)
/* DPORT_PRO_ICACHE_MEMSYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h400000 ; */
/*description: */
#define DPORT_PRO_ICACHE_MEMSYNC_SIZE  0x007FFFFF
#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_M  ((DPORT_PRO_ICACHE_MEMSYNC_SIZE_V)<<(DPORT_PRO_ICACHE_MEMSYNC_SIZE_S))
#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_V  0x7FFFFF
#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_S  0

#define DPORT_PRO_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x064)
/* DPORT_PRO_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_ADDR  0xFFFFFFFF
#define DPORT_PRO_ICACHE_PRELOAD_ADDR_M  ((DPORT_PRO_ICACHE_PRELOAD_ADDR_V)<<(DPORT_PRO_ICACHE_PRELOAD_ADDR_S))
#define DPORT_PRO_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_ICACHE_PRELOAD_ADDR_S  0

#define DPORT_PRO_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x068)
/* DPORT_PRO_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_ORDER  (BIT(16))
#define DPORT_PRO_ICACHE_PRELOAD_ORDER_M  (BIT(16))
#define DPORT_PRO_ICACHE_PRELOAD_ORDER_V  0x1
#define DPORT_PRO_ICACHE_PRELOAD_ORDER_S  16
/* DPORT_PRO_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h8000 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_SIZE  0x0000FFFF
#define DPORT_PRO_ICACHE_PRELOAD_SIZE_M  ((DPORT_PRO_ICACHE_PRELOAD_SIZE_V)<<(DPORT_PRO_ICACHE_PRELOAD_SIZE_S))
#define DPORT_PRO_ICACHE_PRELOAD_SIZE_V  0xFFFF
#define DPORT_PRO_ICACHE_PRELOAD_SIZE_S  0

#define DPORT_PRO_ICACHE_AUTOLOAD_CFG_REG          (DR_REG_EXTMEM_BASE + 0x06C)
/* DPORT_PRO_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[21:6] ;default: 16'h1 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE  0x0000FFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SIZE_S))
#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_V  0xFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_S  6
/* DPORT_PRO_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_RQST  0x00000003
#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_M  ((DPORT_PRO_ICACHE_AUTOLOAD_RQST_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_RQST_S))
#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_V  0x3
#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_S  4
/* DPORT_PRO_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER  (BIT(3))
#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_M  (BIT(3))
#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_V  0x1
#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_S  3
/* DPORT_PRO_ICACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_STEP  0x00000003
#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_M  ((DPORT_PRO_ICACHE_AUTOLOAD_STEP_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_STEP_S))
#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_V  0x3
#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_S  1
/* DPORT_PRO_ICACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_MODE  (BIT(0))
#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_M  (BIT(0))
#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_V  0x1
#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_S  0

#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x070)
/* DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S))
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S  0

#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x074)
/* DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE  0x00FFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S))
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S  0

#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x078)
/* DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S))
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S  0

#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x07C)
/* DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
/*description: */
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE  0x00FFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S))
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S  0

#define DPORT_IC_PRELOAD_CNT_REG          (DR_REG_EXTMEM_BASE + 0x080)
/* DPORT_IC_PRELOAD_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IC_PRELOAD_CNT  0xFFFFFFFF
#define DPORT_IC_PRELOAD_CNT_M  ((DPORT_IC_PRELOAD_CNT_V)<<(DPORT_IC_PRELOAD_CNT_S))
#define DPORT_IC_PRELOAD_CNT_V  0xFFFFFFFF
#define DPORT_IC_PRELOAD_CNT_S  0

#define DPORT_IC_PRELOAD_EVICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x084)
/* DPORT_IC_PRELOAD_EVICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IC_PRELOAD_EVICT_CNT  0xFFFFFFFF
#define DPORT_IC_PRELOAD_EVICT_CNT_M  ((DPORT_IC_PRELOAD_EVICT_CNT_V)<<(DPORT_IC_PRELOAD_EVICT_CNT_S))
#define DPORT_IC_PRELOAD_EVICT_CNT_V  0xFFFFFFFF
#define DPORT_IC_PRELOAD_EVICT_CNT_S  0

#define DPORT_IC_PRELOAD_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x088)
/* DPORT_IC_PRELOAD_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IC_PRELOAD_MISS_CNT  0xFFFFFFFF
#define DPORT_IC_PRELOAD_MISS_CNT_M  ((DPORT_IC_PRELOAD_MISS_CNT_V)<<(DPORT_IC_PRELOAD_MISS_CNT_S))
#define DPORT_IC_PRELOAD_MISS_CNT_V  0xFFFFFFFF
#define DPORT_IC_PRELOAD_MISS_CNT_S  0

#define DPORT_IBUS3_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x08C)
/* DPORT_IBUS3_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS3_ABANDON_CNT  0xFFFFFFFF
#define DPORT_IBUS3_ABANDON_CNT_M  ((DPORT_IBUS3_ABANDON_CNT_V)<<(DPORT_IBUS3_ABANDON_CNT_S))
#define DPORT_IBUS3_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_IBUS3_ABANDON_CNT_S  0

#define DPORT_IBUS2_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x090)
/* DPORT_IBUS2_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS2_ABANDON_CNT  0xFFFFFFFF
#define DPORT_IBUS2_ABANDON_CNT_M  ((DPORT_IBUS2_ABANDON_CNT_V)<<(DPORT_IBUS2_ABANDON_CNT_S))
#define DPORT_IBUS2_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_IBUS2_ABANDON_CNT_S  0

#define DPORT_IBUS1_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x094)
/* DPORT_IBUS1_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS1_ABANDON_CNT  0xFFFFFFFF
#define DPORT_IBUS1_ABANDON_CNT_M  ((DPORT_IBUS1_ABANDON_CNT_V)<<(DPORT_IBUS1_ABANDON_CNT_S))
#define DPORT_IBUS1_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_IBUS1_ABANDON_CNT_S  0

#define DPORT_IBUS0_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x098)
/* DPORT_IBUS0_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS0_ABANDON_CNT  0xFFFFFFFF
#define DPORT_IBUS0_ABANDON_CNT_M  ((DPORT_IBUS0_ABANDON_CNT_V)<<(DPORT_IBUS0_ABANDON_CNT_S))
#define DPORT_IBUS0_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_IBUS0_ABANDON_CNT_S  0

#define DPORT_IBUS3_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x09C)
/* DPORT_IBUS3_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS3_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_IBUS3_ACS_MISS_CNT_M  ((DPORT_IBUS3_ACS_MISS_CNT_V)<<(DPORT_IBUS3_ACS_MISS_CNT_S))
#define DPORT_IBUS3_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS3_ACS_MISS_CNT_S  0

#define DPORT_IBUS2_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A0)
/* DPORT_IBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS2_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_IBUS2_ACS_MISS_CNT_M  ((DPORT_IBUS2_ACS_MISS_CNT_V)<<(DPORT_IBUS2_ACS_MISS_CNT_S))
#define DPORT_IBUS2_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS2_ACS_MISS_CNT_S  0

#define DPORT_IBUS1_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A4)
/* DPORT_IBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS1_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_IBUS1_ACS_MISS_CNT_M  ((DPORT_IBUS1_ACS_MISS_CNT_V)<<(DPORT_IBUS1_ACS_MISS_CNT_S))
#define DPORT_IBUS1_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS1_ACS_MISS_CNT_S  0

#define DPORT_IBUS0_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A8)
/* DPORT_IBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS0_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_IBUS0_ACS_MISS_CNT_M  ((DPORT_IBUS0_ACS_MISS_CNT_V)<<(DPORT_IBUS0_ACS_MISS_CNT_S))
#define DPORT_IBUS0_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS0_ACS_MISS_CNT_S  0

#define DPORT_IBUS3_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0AC)
/* DPORT_IBUS3_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS3_ACS_CNT  0xFFFFFFFF
#define DPORT_IBUS3_ACS_CNT_M  ((DPORT_IBUS3_ACS_CNT_V)<<(DPORT_IBUS3_ACS_CNT_S))
#define DPORT_IBUS3_ACS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS3_ACS_CNT_S  0

#define DPORT_IBUS2_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B0)
/* DPORT_IBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS2_ACS_CNT  0xFFFFFFFF
#define DPORT_IBUS2_ACS_CNT_M  ((DPORT_IBUS2_ACS_CNT_V)<<(DPORT_IBUS2_ACS_CNT_S))
#define DPORT_IBUS2_ACS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS2_ACS_CNT_S  0

#define DPORT_IBUS1_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B4)
/* DPORT_IBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS1_ACS_CNT  0xFFFFFFFF
#define DPORT_IBUS1_ACS_CNT_M  ((DPORT_IBUS1_ACS_CNT_V)<<(DPORT_IBUS1_ACS_CNT_S))
#define DPORT_IBUS1_ACS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS1_ACS_CNT_S  0

#define DPORT_IBUS0_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B8)
/* DPORT_IBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_IBUS0_ACS_CNT  0xFFFFFFFF
#define DPORT_IBUS0_ACS_CNT_M  ((DPORT_IBUS0_ACS_CNT_V)<<(DPORT_IBUS0_ACS_CNT_S))
#define DPORT_IBUS0_ACS_CNT_V  0xFFFFFFFF
#define DPORT_IBUS0_ACS_CNT_S  0

#define DPORT_DC_PRELOAD_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0BC)
/* DPORT_DC_PRELOAD_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DC_PRELOAD_CNT  0xFFFFFFFF
#define DPORT_DC_PRELOAD_CNT_M  ((DPORT_DC_PRELOAD_CNT_V)<<(DPORT_DC_PRELOAD_CNT_S))
#define DPORT_DC_PRELOAD_CNT_V  0xFFFFFFFF
#define DPORT_DC_PRELOAD_CNT_S  0

#define DPORT_DC_PRELOAD_EVICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C0)
/* DPORT_DC_PRELOAD_EVICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DC_PRELOAD_EVICT_CNT  0xFFFFFFFF
#define DPORT_DC_PRELOAD_EVICT_CNT_M  ((DPORT_DC_PRELOAD_EVICT_CNT_V)<<(DPORT_DC_PRELOAD_EVICT_CNT_S))
#define DPORT_DC_PRELOAD_EVICT_CNT_V  0xFFFFFFFF
#define DPORT_DC_PRELOAD_EVICT_CNT_S  0

#define DPORT_DC_PRELOAD_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C4)
/* DPORT_DC_PRELOAD_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DC_PRELOAD_MISS_CNT  0xFFFFFFFF
#define DPORT_DC_PRELOAD_MISS_CNT_M  ((DPORT_DC_PRELOAD_MISS_CNT_V)<<(DPORT_DC_PRELOAD_MISS_CNT_S))
#define DPORT_DC_PRELOAD_MISS_CNT_V  0xFFFFFFFF
#define DPORT_DC_PRELOAD_MISS_CNT_S  0

#define DPORT_DBUS3_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C8)
/* DPORT_DBUS3_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS3_ABANDON_CNT  0xFFFFFFFF
#define DPORT_DBUS3_ABANDON_CNT_M  ((DPORT_DBUS3_ABANDON_CNT_V)<<(DPORT_DBUS3_ABANDON_CNT_S))
#define DPORT_DBUS3_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_DBUS3_ABANDON_CNT_S  0

#define DPORT_DBUS2_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0CC)
/* DPORT_DBUS2_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS2_ABANDON_CNT  0xFFFFFFFF
#define DPORT_DBUS2_ABANDON_CNT_M  ((DPORT_DBUS2_ABANDON_CNT_V)<<(DPORT_DBUS2_ABANDON_CNT_S))
#define DPORT_DBUS2_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_DBUS2_ABANDON_CNT_S  0

#define DPORT_DBUS1_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D0)
/* DPORT_DBUS1_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS1_ABANDON_CNT  0xFFFFFFFF
#define DPORT_DBUS1_ABANDON_CNT_M  ((DPORT_DBUS1_ABANDON_CNT_V)<<(DPORT_DBUS1_ABANDON_CNT_S))
#define DPORT_DBUS1_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_DBUS1_ABANDON_CNT_S  0

#define DPORT_DBUS0_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D4)
/* DPORT_DBUS0_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS0_ABANDON_CNT  0xFFFFFFFF
#define DPORT_DBUS0_ABANDON_CNT_M  ((DPORT_DBUS0_ABANDON_CNT_V)<<(DPORT_DBUS0_ABANDON_CNT_S))
#define DPORT_DBUS0_ABANDON_CNT_V  0xFFFFFFFF
#define DPORT_DBUS0_ABANDON_CNT_S  0

#define DPORT_DBUS3_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D8)
/* DPORT_DBUS3_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS3_ACS_WB_CNT  0xFFFFFFFF
#define DPORT_DBUS3_ACS_WB_CNT_M  ((DPORT_DBUS3_ACS_WB_CNT_V)<<(DPORT_DBUS3_ACS_WB_CNT_S))
#define DPORT_DBUS3_ACS_WB_CNT_V  0xFFFFFFFF
#define DPORT_DBUS3_ACS_WB_CNT_S  0

#define DPORT_DBUS2_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0DC)
/* DPORT_DBUS2_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS2_ACS_WB_CNT  0xFFFFFFFF
#define DPORT_DBUS2_ACS_WB_CNT_M  ((DPORT_DBUS2_ACS_WB_CNT_V)<<(DPORT_DBUS2_ACS_WB_CNT_S))
#define DPORT_DBUS2_ACS_WB_CNT_V  0xFFFFFFFF
#define DPORT_DBUS2_ACS_WB_CNT_S  0

#define DPORT_DBUS1_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E0)
/* DPORT_DBUS1_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS1_ACS_WB_CNT  0xFFFFFFFF
#define DPORT_DBUS1_ACS_WB_CNT_M  ((DPORT_DBUS1_ACS_WB_CNT_V)<<(DPORT_DBUS1_ACS_WB_CNT_S))
#define DPORT_DBUS1_ACS_WB_CNT_V  0xFFFFFFFF
#define DPORT_DBUS1_ACS_WB_CNT_S  0

#define DPORT_DBUS0_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E4)
/* DPORT_DBUS0_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS0_ACS_WB_CNT  0xFFFFFFFF
#define DPORT_DBUS0_ACS_WB_CNT_M  ((DPORT_DBUS0_ACS_WB_CNT_V)<<(DPORT_DBUS0_ACS_WB_CNT_S))
#define DPORT_DBUS0_ACS_WB_CNT_V  0xFFFFFFFF
#define DPORT_DBUS0_ACS_WB_CNT_S  0

#define DPORT_DBUS3_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E8)
/* DPORT_DBUS3_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS3_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_DBUS3_ACS_MISS_CNT_M  ((DPORT_DBUS3_ACS_MISS_CNT_V)<<(DPORT_DBUS3_ACS_MISS_CNT_S))
#define DPORT_DBUS3_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS3_ACS_MISS_CNT_S  0

#define DPORT_DBUS2_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0EC)
/* DPORT_DBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS2_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_DBUS2_ACS_MISS_CNT_M  ((DPORT_DBUS2_ACS_MISS_CNT_V)<<(DPORT_DBUS2_ACS_MISS_CNT_S))
#define DPORT_DBUS2_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS2_ACS_MISS_CNT_S  0

#define DPORT_DBUS1_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0F0)
/* DPORT_DBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS1_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_DBUS1_ACS_MISS_CNT_M  ((DPORT_DBUS1_ACS_MISS_CNT_V)<<(DPORT_DBUS1_ACS_MISS_CNT_S))
#define DPORT_DBUS1_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS1_ACS_MISS_CNT_S  0

#define DPORT_DBUS0_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0F4)
/* DPORT_DBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS0_ACS_MISS_CNT  0xFFFFFFFF
#define DPORT_DBUS0_ACS_MISS_CNT_M  ((DPORT_DBUS0_ACS_MISS_CNT_V)<<(DPORT_DBUS0_ACS_MISS_CNT_S))
#define DPORT_DBUS0_ACS_MISS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS0_ACS_MISS_CNT_S  0

#define DPORT_DBUS3_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0F8)
/* DPORT_DBUS3_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS3_ACS_CNT  0xFFFFFFFF
#define DPORT_DBUS3_ACS_CNT_M  ((DPORT_DBUS3_ACS_CNT_V)<<(DPORT_DBUS3_ACS_CNT_S))
#define DPORT_DBUS3_ACS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS3_ACS_CNT_S  0

#define DPORT_DBUS2_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0FC)
/* DPORT_DBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS2_ACS_CNT  0xFFFFFFFF
#define DPORT_DBUS2_ACS_CNT_M  ((DPORT_DBUS2_ACS_CNT_V)<<(DPORT_DBUS2_ACS_CNT_S))
#define DPORT_DBUS2_ACS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS2_ACS_CNT_S  0

#define DPORT_DBUS1_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x100)
/* DPORT_DBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS1_ACS_CNT  0xFFFFFFFF
#define DPORT_DBUS1_ACS_CNT_M  ((DPORT_DBUS1_ACS_CNT_V)<<(DPORT_DBUS1_ACS_CNT_S))
#define DPORT_DBUS1_ACS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS1_ACS_CNT_S  0

#define DPORT_DBUS0_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x104)
/* DPORT_DBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_DBUS0_ACS_CNT  0xFFFFFFFF
#define DPORT_DBUS0_ACS_CNT_M  ((DPORT_DBUS0_ACS_CNT_V)<<(DPORT_DBUS0_ACS_CNT_S))
#define DPORT_DBUS0_ACS_CNT_V  0xFFFFFFFF
#define DPORT_DBUS0_ACS_CNT_S  0

#define DPORT_PRO_CACHE_IA_INT_EN_REG DPORT_CACHE_DBG_INT_ENA_REG
#define DPORT_PRO_CACHE_INT_CLR DPORT_CACHE_DBG_INT_CLR
#define DPORT_PRO_CACHE_DBG_EN DPORT_CACHE_DBG_EN
#define DPORT_CACHE_DBG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x108)
/* DPORT_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define DPORT_MMU_ENTRY_FAULT_INT_ENA  (BIT(13))
#define DPORT_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(13))
#define DPORT_MMU_ENTRY_FAULT_INT_ENA_V  0x1
#define DPORT_MMU_ENTRY_FAULT_INT_ENA_S  13
/* DPORT_DCACHE_REJECT_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define DPORT_DCACHE_REJECT_INT_ENA  (BIT(12))
#define DPORT_DCACHE_REJECT_INT_ENA_M  (BIT(12))
#define DPORT_DCACHE_REJECT_INT_ENA_V  0x1
#define DPORT_DCACHE_REJECT_INT_ENA_S  12
/* DPORT_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define DPORT_DCACHE_WRITE_FLASH_INT_ENA  (BIT(11))
#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_M  (BIT(11))
#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_V  0x1
#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_S  11
/* DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA  (BIT(10))
#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_M  (BIT(10))
#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_V  0x1
#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_S  10
/* DPORT_DC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA  (BIT(9))
#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_M  (BIT(9))
#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_V  0x1
#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_S  9
/* DPORT_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS_CNT_OVF_INT_ENA  (BIT(8))
#define DPORT_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
#define DPORT_DBUS_CNT_OVF_INT_ENA_V  0x1
#define DPORT_DBUS_CNT_OVF_INT_ENA_S  8
/* DPORT_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS_ACS_MSK_IC_INT_ENA  (BIT(7))
#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_M  (BIT(7))
#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_V  0x1
#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_S  7
/* DPORT_ICACHE_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define DPORT_ICACHE_REJECT_INT_ENA  (BIT(6))
#define DPORT_ICACHE_REJECT_INT_ENA_M  (BIT(6))
#define DPORT_ICACHE_REJECT_INT_ENA_V  0x1
#define DPORT_ICACHE_REJECT_INT_ENA_S  6
/* DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA  (BIT(5))
#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_M  (BIT(5))
#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_V  0x1
#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_S  5
/* DPORT_IC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA  (BIT(4))
#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_M  (BIT(4))
#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_V  0x1
#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_S  4
/* DPORT_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS_CNT_OVF_INT_ENA  (BIT(3))
#define DPORT_IBUS_CNT_OVF_INT_ENA_M  (BIT(3))
#define DPORT_IBUS_CNT_OVF_INT_ENA_V  0x1
#define DPORT_IBUS_CNT_OVF_INT_ENA_S  3
/* DPORT_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS_ACS_MSK_IC_INT_ENA  (BIT(2))
#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(2))
#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_S  2
/* DPORT_CACHE_DBG_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_CACHE_DBG_INT_CLR  (BIT(1))
#define DPORT_CACHE_DBG_INT_CLR_M  (BIT(1))
#define DPORT_CACHE_DBG_INT_CLR_V  0x1
#define DPORT_CACHE_DBG_INT_CLR_S  1
/* DPORT_CACHE_DBG_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_CACHE_DBG_EN  (BIT(0))
#define DPORT_CACHE_DBG_EN_M  (BIT(0))
#define DPORT_CACHE_DBG_EN_V  0x1
#define DPORT_CACHE_DBG_EN_S  0

#define DPORT_CACHE_DBG_STATUS0_REG          (DR_REG_EXTMEM_BASE + 0x10C)
/* DPORT_ICACHE_REJECT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_ICACHE_REJECT_ST  (BIT(21))
#define DPORT_ICACHE_REJECT_ST_M  (BIT(21))
#define DPORT_ICACHE_REJECT_ST_V  0x1
#define DPORT_ICACHE_REJECT_ST_S  21
/* DPORT_IC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_IC_PRELOAD_SIZE_FAULT_ST  (BIT(20))
#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_M  (BIT(20))
#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_V  0x1
#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_S  20
/* DPORT_IC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define DPORT_IC_SYNC_SIZE_FAULT_ST  (BIT(19))
#define DPORT_IC_SYNC_SIZE_FAULT_ST_M  (BIT(19))
#define DPORT_IC_SYNC_SIZE_FAULT_ST_V  0x1
#define DPORT_IC_SYNC_SIZE_FAULT_ST_S  19
/* DPORT_IC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define DPORT_IC_PRELOAD_CNT_OVF_ST  (BIT(18))
#define DPORT_IC_PRELOAD_CNT_OVF_ST_M  (BIT(18))
#define DPORT_IC_PRELOAD_CNT_OVF_ST_V  0x1
#define DPORT_IC_PRELOAD_CNT_OVF_ST_S  18
/* DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST  (BIT(17))
#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_M  (BIT(17))
#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_V  0x1
#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_S  17
/* DPORT_IC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST  (BIT(16))
#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_M  (BIT(16))
#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_V  0x1
#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_S  16
/* DPORT_IBUS3_ABANDON_CNT_OVF_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS3_ABANDON_CNT_OVF_ST  (BIT(15))
#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_M  (BIT(15))
#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_S  15
/* DPORT_IBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS2_ABANDON_CNT_OVF_ST  (BIT(14))
#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_M  (BIT(14))
#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_S  14
/* DPORT_IBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS1_ABANDON_CNT_OVF_ST  (BIT(13))
#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_M  (BIT(13))
#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_S  13
/* DPORT_IBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS0_ABANDON_CNT_OVF_ST  (BIT(12))
#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_M  (BIT(12))
#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_S  12
/* DPORT_IBUS3_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST  (BIT(11))
#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_M  (BIT(11))
#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_S  11
/* DPORT_IBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST  (BIT(10))
#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_M  (BIT(10))
#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_S  10
/* DPORT_IBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST  (BIT(9))
#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_M  (BIT(9))
#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_S  9
/* DPORT_IBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST  (BIT(8))
#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_S  8
/* DPORT_IBUS3_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS3_ACS_CNT_OVF_ST  (BIT(7))
#define DPORT_IBUS3_ACS_CNT_OVF_ST_M  (BIT(7))
#define DPORT_IBUS3_ACS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS3_ACS_CNT_OVF_ST_S  7
/* DPORT_IBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS2_ACS_CNT_OVF_ST  (BIT(6))
#define DPORT_IBUS2_ACS_CNT_OVF_ST_M  (BIT(6))
#define DPORT_IBUS2_ACS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS2_ACS_CNT_OVF_ST_S  6
/* DPORT_IBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS1_ACS_CNT_OVF_ST  (BIT(5))
#define DPORT_IBUS1_ACS_CNT_OVF_ST_M  (BIT(5))
#define DPORT_IBUS1_ACS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS1_ACS_CNT_OVF_ST_S  5
/* DPORT_IBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS0_ACS_CNT_OVF_ST  (BIT(4))
#define DPORT_IBUS0_ACS_CNT_OVF_ST_M  (BIT(4))
#define DPORT_IBUS0_ACS_CNT_OVF_ST_V  0x1
#define DPORT_IBUS0_ACS_CNT_OVF_ST_S  4
/* DPORT_IBUS3_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS3_ACS_MSK_ICACHE_ST  (BIT(3))
#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_M  (BIT(3))
#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_V  0x1
#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_S  3
/* DPORT_IBUS2_ACS_MSK_ICACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS2_ACS_MSK_ICACHE_ST  (BIT(2))
#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_M  (BIT(2))
#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_V  0x1
#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_S  2
/* DPORT_IBUS1_ACS_MSK_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS1_ACS_MSK_ICACHE_ST  (BIT(1))
#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_M  (BIT(1))
#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_V  0x1
#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_S  1
/* DPORT_IBUS0_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_IBUS0_ACS_MSK_ICACHE_ST  (BIT(0))
#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_M  (BIT(0))
#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_V  0x1
#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_S  0

#define DPORT_CACHE_DBG_STATUS1_REG          (DR_REG_EXTMEM_BASE + 0x110)
/* DPORT_MMU_ENTRY_FAULT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define DPORT_MMU_ENTRY_FAULT_ST  (BIT(27))
#define DPORT_MMU_ENTRY_FAULT_ST_M  (BIT(27))
#define DPORT_MMU_ENTRY_FAULT_ST_V  0x1
#define DPORT_MMU_ENTRY_FAULT_ST_S  27
/* DPORT_DCACHE_REJECT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
#define DPORT_DCACHE_REJECT_ST  (BIT(26))
#define DPORT_DCACHE_REJECT_ST_M  (BIT(26))
#define DPORT_DCACHE_REJECT_ST_V  0x1
#define DPORT_DCACHE_REJECT_ST_S  26
/* DPORT_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
/*description: */
#define DPORT_DCACHE_WRITE_FLASH_ST  (BIT(25))
#define DPORT_DCACHE_WRITE_FLASH_ST_M  (BIT(25))
#define DPORT_DCACHE_WRITE_FLASH_ST_V  0x1
#define DPORT_DCACHE_WRITE_FLASH_ST_S  25
/* DPORT_DC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
/*description: */
#define DPORT_DC_PRELOAD_SIZE_FAULT_ST  (BIT(24))
#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_M  (BIT(24))
#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_V  0x1
#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_S  24
/* DPORT_DC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define DPORT_DC_SYNC_SIZE_FAULT_ST  (BIT(23))
#define DPORT_DC_SYNC_SIZE_FAULT_ST_M  (BIT(23))
#define DPORT_DC_SYNC_SIZE_FAULT_ST_V  0x1
#define DPORT_DC_SYNC_SIZE_FAULT_ST_S  23
/* DPORT_DC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define DPORT_DC_PRELOAD_CNT_OVF_ST  (BIT(22))
#define DPORT_DC_PRELOAD_CNT_OVF_ST_M  (BIT(22))
#define DPORT_DC_PRELOAD_CNT_OVF_ST_V  0x1
#define DPORT_DC_PRELOAD_CNT_OVF_ST_S  22
/* DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST  (BIT(21))
#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_M  (BIT(21))
#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_V  0x1
#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_S  21
/* DPORT_DC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST  (BIT(20))
#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_M  (BIT(20))
#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_V  0x1
#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_S  20
/* DPORT_DBUS3_ABANDON_CNT_OVF_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS3_ABANDON_CNT_OVF_ST  (BIT(19))
#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_M  (BIT(19))
#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_S  19
/* DPORT_DBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS2_ABANDON_CNT_OVF_ST  (BIT(18))
#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_M  (BIT(18))
#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_S  18
/* DPORT_DBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS1_ABANDON_CNT_OVF_ST  (BIT(17))
#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_M  (BIT(17))
#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_S  17
/* DPORT_DBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS0_ABANDON_CNT_OVF_ST  (BIT(16))
#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_M  (BIT(16))
#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_V  0x1
#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_S  16
/* DPORT_DBUS3_ACS_WB_CNT_OVF_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST  (BIT(15))
#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_M  (BIT(15))
#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_V  0x1
#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_S  15
/* DPORT_DBUS2_ACS_WB_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST  (BIT(14))
#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_M  (BIT(14))
#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_V  0x1
#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_S  14
/* DPORT_DBUS1_ACS_WB_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST  (BIT(13))
#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_M  (BIT(13))
#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_V  0x1
#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_S  13
/* DPORT_DBUS0_ACS_WB_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST  (BIT(12))
#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_M  (BIT(12))
#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_V  0x1
#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_S  12
/* DPORT_DBUS3_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST  (BIT(11))
#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_M  (BIT(11))
#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_S  11
/* DPORT_DBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST  (BIT(10))
#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_M  (BIT(10))
#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_S  10
/* DPORT_DBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST  (BIT(9))
#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_M  (BIT(9))
#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_S  9
/* DPORT_DBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST  (BIT(8))
#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_S  8
/* DPORT_DBUS3_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS3_ACS_CNT_OVF_ST  (BIT(7))
#define DPORT_DBUS3_ACS_CNT_OVF_ST_M  (BIT(7))
#define DPORT_DBUS3_ACS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS3_ACS_CNT_OVF_ST_S  7
/* DPORT_DBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS2_ACS_CNT_OVF_ST  (BIT(6))
#define DPORT_DBUS2_ACS_CNT_OVF_ST_M  (BIT(6))
#define DPORT_DBUS2_ACS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS2_ACS_CNT_OVF_ST_S  6
/* DPORT_DBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS1_ACS_CNT_OVF_ST  (BIT(5))
#define DPORT_DBUS1_ACS_CNT_OVF_ST_M  (BIT(5))
#define DPORT_DBUS1_ACS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS1_ACS_CNT_OVF_ST_S  5
/* DPORT_DBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS0_ACS_CNT_OVF_ST  (BIT(4))
#define DPORT_DBUS0_ACS_CNT_OVF_ST_M  (BIT(4))
#define DPORT_DBUS0_ACS_CNT_OVF_ST_V  0x1
#define DPORT_DBUS0_ACS_CNT_OVF_ST_S  4
/* DPORT_DBUS3_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS3_ACS_MSK_DCACHE_ST  (BIT(3))
#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_M  (BIT(3))
#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_V  0x1
#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_S  3
/* DPORT_DBUS2_ACS_MSK_DCACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS2_ACS_MSK_DCACHE_ST  (BIT(2))
#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_M  (BIT(2))
#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_V  0x1
#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_S  2
/* DPORT_DBUS1_ACS_MSK_DCACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS1_ACS_MSK_DCACHE_ST  (BIT(1))
#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_M  (BIT(1))
#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_V  0x1
#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_S  1
/* DPORT_DBUS0_ACS_MSK_DCACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_DBUS0_ACS_MSK_DCACHE_ST  (BIT(0))
#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_M  (BIT(0))
#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_V  0x1
#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_S  0

#define DPORT_PRO_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x114)
/* DPORT_PRO_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_ACS_CNT_CLR  (BIT(1))
#define DPORT_PRO_ICACHE_ACS_CNT_CLR_M  (BIT(1))
#define DPORT_PRO_ICACHE_ACS_CNT_CLR_V  0x1
#define DPORT_PRO_ICACHE_ACS_CNT_CLR_S  1
/* DPORT_PRO_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_ACS_CNT_CLR  (BIT(0))
#define DPORT_PRO_DCACHE_ACS_CNT_CLR_M  (BIT(0))
#define DPORT_PRO_DCACHE_ACS_CNT_CLR_V  0x1
#define DPORT_PRO_DCACHE_ACS_CNT_CLR_S  0

#define DPORT_PRO_DCACHE_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x118)
/* DPORT_PRO_DCACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_CPU_ATTR  0x00000007
#define DPORT_PRO_DCACHE_CPU_ATTR_M  ((DPORT_PRO_DCACHE_CPU_ATTR_V)<<(DPORT_PRO_DCACHE_CPU_ATTR_S))
#define DPORT_PRO_DCACHE_CPU_ATTR_V  0x7
#define DPORT_PRO_DCACHE_CPU_ATTR_S  3
/* DPORT_PRO_DCACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_TAG_ATTR  0x00000007
#define DPORT_PRO_DCACHE_TAG_ATTR_M  ((DPORT_PRO_DCACHE_TAG_ATTR_V)<<(DPORT_PRO_DCACHE_TAG_ATTR_S))
#define DPORT_PRO_DCACHE_TAG_ATTR_V  0x7
#define DPORT_PRO_DCACHE_TAG_ATTR_S  0

#define DPORT_PRO_DCACHE_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x11C)
/* DPORT_PRO_DCACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_DCACHE_CPU_VADDR  0xFFFFFFFF
#define DPORT_PRO_DCACHE_CPU_VADDR_M  ((DPORT_PRO_DCACHE_CPU_VADDR_V)<<(DPORT_PRO_DCACHE_CPU_VADDR_S))
#define DPORT_PRO_DCACHE_CPU_VADDR_V  0xFFFFFFFF
#define DPORT_PRO_DCACHE_CPU_VADDR_S  0

#define DPORT_PRO_ICACHE_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x120)
/* DPORT_PRO_ICACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_CPU_ATTR  0x00000007
#define DPORT_PRO_ICACHE_CPU_ATTR_M  ((DPORT_PRO_ICACHE_CPU_ATTR_V)<<(DPORT_PRO_ICACHE_CPU_ATTR_S))
#define DPORT_PRO_ICACHE_CPU_ATTR_V  0x7
#define DPORT_PRO_ICACHE_CPU_ATTR_S  3
/* DPORT_PRO_ICACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_TAG_ATTR  0x00000007
#define DPORT_PRO_ICACHE_TAG_ATTR_M  ((DPORT_PRO_ICACHE_TAG_ATTR_V)<<(DPORT_PRO_ICACHE_TAG_ATTR_S))
#define DPORT_PRO_ICACHE_TAG_ATTR_V  0x7
#define DPORT_PRO_ICACHE_TAG_ATTR_S  0

#define DPORT_PRO_ICACHE_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x124)
/* DPORT_PRO_ICACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_ICACHE_CPU_VADDR  0xFFFFFFFF
#define DPORT_PRO_ICACHE_CPU_VADDR_M  ((DPORT_PRO_ICACHE_CPU_VADDR_V)<<(DPORT_PRO_ICACHE_CPU_VADDR_S))
#define DPORT_PRO_ICACHE_CPU_VADDR_V  0xFFFFFFFF
#define DPORT_PRO_ICACHE_CPU_VADDR_S  0

#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x128)
/* DPORT_PRO_CACHE_MMU_ERROR_CONTENT : RO ;bitpos:[16:0] ;default: 17'h0 ; */
/*description: */
#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT  0x0001FFFF
#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_M  ((DPORT_PRO_CACHE_MMU_ERROR_CONTENT_V)<<(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_S))
#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_V  0x1FFFF
#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_S  0

#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x12C)
/* DPORT_PRO_CACHE_MMU_ERROR_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_CACHE_MMU_ERROR_VADDR  0xFFFFFFFF
#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_M  ((DPORT_PRO_CACHE_MMU_ERROR_VADDR_V)<<(DPORT_PRO_CACHE_MMU_ERROR_VADDR_S))
#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_V  0xFFFFFFFF
#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_S  0

#define DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x130)
/* DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND  (BIT(1))
#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_M  (BIT(1))
#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_V  0x1
#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_S  1
/* DPORT_PRO_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND  (BIT(0))
#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_V  0x1
#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_S  0

#define DPORT_PRO_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x134)
/* DPORT_PRO_CACHE_MMU_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_CACHE_MMU_MEM_PD  (BIT(1))
#define DPORT_PRO_CACHE_MMU_MEM_PD_M  (BIT(1))
#define DPORT_PRO_CACHE_MMU_MEM_PD_V  0x1
#define DPORT_PRO_CACHE_MMU_MEM_PD_S  1
/* DPORT_PRO_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON  (BIT(0))
#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_V  0x1
#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_S  0

#define DPORT_PRO_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x138)
/* DPORT_PRO_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */
/*description: */
#define DPORT_PRO_DCACHE_STATE  0x00000FFF
#define DPORT_PRO_DCACHE_STATE_M  ((DPORT_PRO_DCACHE_STATE_V)<<(DPORT_PRO_DCACHE_STATE_S))
#define DPORT_PRO_DCACHE_STATE_V  0xFFF
#define DPORT_PRO_DCACHE_STATE_S  12
/* DPORT_PRO_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */
/*description: */
#define DPORT_PRO_ICACHE_STATE  0x00000FFF
#define DPORT_PRO_ICACHE_STATE_M  ((DPORT_PRO_ICACHE_STATE_V)<<(DPORT_PRO_ICACHE_STATE_S))
#define DPORT_PRO_ICACHE_STATE_V  0xFFF
#define DPORT_PRO_ICACHE_STATE_S  0

#define DPORT_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x13C)
/* DPORT_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_RECORD_DISABLE_G0CB_DECRYPT  (BIT(1))
#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_S  1
/* DPORT_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_RECORD_DISABLE_DB_ENCRYPT  (BIT(0))
#define DPORT_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
#define DPORT_RECORD_DISABLE_DB_ENCRYPT_V  0x1
#define DPORT_RECORD_DISABLE_DB_ENCRYPT_S  0

#define DPORT_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x140)
/* DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT  (BIT(2))
#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_M  (BIT(2))
#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V  0x1
#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S  2
/* DPORT_CLK_FORCE_ON_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT  (BIT(1))
#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_M  (BIT(1))
#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_V  0x1
#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_S  1
/* DPORT_CLK_FORCE_ON_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_CLK_FORCE_ON_DB_ENCRYPT  (BIT(0))
#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_M  (BIT(0))
#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_V  0x1
#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_S  0

#define DPORT_CACHE_BRIDGE_ARBITER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x144)
/* DPORT_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_ALLOC_WB_HOLD_ARBITER  (BIT(0))
#define DPORT_ALLOC_WB_HOLD_ARBITER_M  (BIT(0))
#define DPORT_ALLOC_WB_HOLD_ARBITER_V  0x1
#define DPORT_ALLOC_WB_HOLD_ARBITER_S  0

#define DPORT_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x148)
/* DPORT_PRO_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR  (BIT(5))
#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_M  (BIT(5))
#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_V  0x1
#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_S  5
/* DPORT_PRO_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA  (BIT(4))
#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_M  (BIT(4))
#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_V  0x1
#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_S  4
/* DPORT_PRO_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_INT_ST  (BIT(3))
#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_M  (BIT(3))
#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_V  0x1
#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_S  3
/* DPORT_PRO_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR  (BIT(2))
#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_V  0x1
#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_S  2
/* DPORT_PRO_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA  (BIT(1))
#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_V  0x1
#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_S  1
/* DPORT_PRO_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_INT_ST  (BIT(0))
#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_V  0x1
#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_S  0

#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x14C)
/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define EXTMEM_CLK_EN  (BIT(0))
#define EXTMEM_CLK_EN_M  (BIT(0))
#define EXTMEM_CLK_EN_V  0x1
#define EXTMEM_CLK_EN_S  0

#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810250 ; */
/*description: */
#define EXTMEM_DATE  0x0FFFFFFF
#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
#define EXTMEM_DATE_V  0xFFFFFFF
#define EXTMEM_DATE_S  0

#ifdef __cplusplus
}
#endif



#endif /*_SOC_EXTMEM_REG_H_ */


