1253 lines
76 KiB
VHDL
1253 lines
76 KiB
VHDL
-- ZPU
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--
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-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
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-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com
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--
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-- The FreeBSD license
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- The views and conclusions contained in the software and documentation
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-- are those of the authors and should not be interpreted as representing
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-- official policies, either expressed or implied, of the ZPU Project.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.zpu_pkg.all;
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-- mem_writeEnable - set to '1' for a single cycle to send off a write request.
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-- mem_write is valid only while mem_writeEnable='1'.
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-- mem_readEnable - set to '1' for a single cycle to send off a read request.
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--
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-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
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-- Set to '0' when mem_read is valid after a read request.
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-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
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-- is '1'.
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-- mem_addr - address for read/write request
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-- mem_read - read data. Valid only on the cycle after mem_busy='0' after
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-- mem_readEnable='1' for a single cycle.
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-- mem_write - data to write
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-- mem_writeMask - set to '1' for those bits that are to be written to memory upon
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-- write request
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-- break - set to '1' when CPU hits break instruction
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-- interrupt - set to '1' until interrupts are cleared by CPU.
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entity zpu_core_medium is
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generic (
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CLK_FREQ : integer := 100000000; -- Frequency of the input clock.
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STACK_ADDR : integer := 0 -- Initial stack address on CPU start.
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);
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port (
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clk : in std_logic;
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areset : in std_logic;
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enable : in std_logic;
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in_mem_busy : in std_logic;
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mem_read : in std_logic_vector(WORD_32BIT_RANGE);
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mem_write : out std_logic_vector(WORD_32BIT_RANGE);
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out_mem_addr : out std_logic_vector(ADDR_BIT_RANGE);
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out_mem_writeEnable : out std_logic;
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out_mem_bEnable : out std_logic; -- Enable byte write
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out_mem_hEnable : out std_logic; -- Enable halfword write
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out_mem_readEnable : out std_logic;
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mem_writeMask : out std_logic_vector(WORD_4BYTE_RANGE);
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-- Set to one to jump to interrupt vector
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-- The ZPU will communicate with the hardware that caused the
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-- interrupt via memory mapped IO or the interrupt flag can
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-- be cleared automatically
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interrupt_request : in std_logic;
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interrupt_ack : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine.
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interrupt_done : out std_logic; -- Interrupt service routine completed/done.
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break : out std_logic;
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debug_txd : out std_logic -- Debug serial output.
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);
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end zpu_core_medium;
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architecture behave of zpu_core_medium is
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type InsnType is
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(
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State_Add, -- 00
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State_AddSP, -- 01
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State_AddTop, -- 02
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State_Alshift, -- 03
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State_And, -- 04
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State_Break, -- 05
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State_Call, -- 06
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State_Callpcrel, -- 07
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-- State_Div,
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State_Dup, -- 08
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State_DupStackB, -- 09
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State_Emulate, -- 0a
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State_Eq, -- 0b
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State_Flip, -- 0c
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State_Im, -- 0d
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State_Lessthan, -- 0e
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State_Lessthanorequal, -- 0f
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State_Load, -- 10
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State_Loadb, -- 11
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State_Loadh, -- 12
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State_LoadSP, -- 13
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-- State_Mod,
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State_Mult, -- 14
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State_Neq, -- 15
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State_Neqbranch, -- 16
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State_Nop, -- 17
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State_Not, -- 18
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State_Or, -- 19
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State_Pop, -- 1a
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State_PopDown, -- 1b
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State_PopPC, -- 1c
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State_PopPCRel, -- 1d
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State_PopSP, -- 1e
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-- State_PushPC,
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State_PushSP, -- 1f
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State_Pushspadd, -- 20
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State_Shift, -- 21
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State_Store, -- 22
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State_Storeb, -- 23
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State_Storeh, -- 24
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State_StoreSP, -- 25
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State_Sub, -- 26
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State_Ulessthan, -- 27
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State_Ulessthanorequal, -- 28
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State_Xor, -- 29
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State_InsnFetch
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);
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type StateType is
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(
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State_Load2,
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State_Popped,
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State_LoadSP2,
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State_LoadSP3,
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State_AddSP2,
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State_Fetch,
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State_Execute,
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State_Decode,
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State_Decode2,
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State_Resync,
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State_StoreSP2,
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State_Resync2,
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State_Resync3,
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State_Loadb2,
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State_Storeb2,
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State_Mult2,
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State_Mult3,
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State_Mult5,
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State_Mult4,
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State_BinaryOpResult2,
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State_BinaryOpResult,
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State_Idle,
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State_Interrupt,
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State_Debug
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);
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--
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type DebugType is
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(
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Debug_Start,
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Debug_DumpFifo,
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Debug_DumpFifo_1,
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Debug_End
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);
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signal pc : unsigned(ADDR_BIT_RANGE);
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signal sp : unsigned(ADDR_32BIT_RANGE);
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signal interrupt_suspended_addr : unsigned(ADDR_BIT_RANGE);
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signal incSp : unsigned(ADDR_32BIT_RANGE);
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signal incIncSp : unsigned(ADDR_32BIT_RANGE);
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signal decSp : unsigned(ADDR_32BIT_RANGE);
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signal stackA : unsigned(WORD_32BIT_RANGE);
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signal binaryOpResult : unsigned(WORD_32BIT_RANGE);
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signal binaryOpResult2 : unsigned(WORD_32BIT_RANGE);
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signal multResult2 : unsigned(WORD_32BIT_RANGE);
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signal multResult3 : unsigned(WORD_32BIT_RANGE);
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signal multResult : unsigned(WORD_32BIT_RANGE);
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signal multA : unsigned(WORD_32BIT_RANGE);
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signal multB : unsigned(WORD_32BIT_RANGE);
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signal stackB : unsigned(WORD_32BIT_RANGE);
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signal idim_flag : std_logic;
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signal busy : std_logic;
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signal mem_writeEnable : std_logic;
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signal mem_readEnable : std_logic;
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signal mem_addr : std_logic_vector(ADDR_32BIT_RANGE);
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signal mem_delayAddr : std_logic_vector(ADDR_32BIT_RANGE);
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signal mem_delayReadEnable : std_logic;
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signal inInterrupt : std_logic;
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signal decodeWord : std_logic_vector(WORD_32BIT_RANGE);
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signal state : StateType;
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signal debugState : DebugType;
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signal debugCnt : integer;
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signal debugRec : zpu_dbg_t;
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signal debugLoad : std_logic;
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signal debugReady : std_logic;
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signal insn : InsnType;
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type InsnArray is array(0 to wordBytes-1) of InsnType;
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signal decodedOpcode : InsnArray;
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type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
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signal opcode : OpcodeArray;
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signal begin_inst : std_logic;
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signal trace_opcode : std_logic_vector(7 downto 0);
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signal trace_pc : std_logic_vector(ADDR_BIT_RANGE);
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signal trace_sp : std_logic_vector(ADDR_32BIT_RANGE);
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signal trace_topOfStack : std_logic_vector(WORD_32BIT_RANGE);
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signal trace_topOfStackB : std_logic_vector(WORD_32BIT_RANGE);
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signal clkDivider : std_logic;
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begin
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-- traceFileGenerate:
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-- if Generate_Trace generate
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-- trace_file: trace port map (
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-- clk => clk,
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-- begin_inst => begin_inst,
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-- pc => trace_pc,
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-- opcode => trace_opcode,
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-- sp => trace_sp,
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-- memA => trace_topOfStack,
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-- memB => trace_topOfStackB,
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-- busy => busy,
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-- intsp => (others => 'U')
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-- );
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-- end generate;
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-- Not yet implemented.
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out_mem_bEnable <= '0'; -- Enable byte write
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out_mem_hEnable <= '0'; -- Enable halfword write
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-- the memory subsystem will tell us one cycle later whether or
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-- not it is busy
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out_mem_writeEnable <= mem_writeEnable;
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out_mem_readEnable <= mem_readEnable;
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out_mem_addr(ADDR_32BIT_RANGE) <= mem_addr;
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out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
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incSp <= sp + 1;
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incIncSp <= sp + 2;
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decSp <= sp - 1;
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multiPipe: process(clk, areset)
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variable tMultResult : unsigned(wordSize*2-1 downto 0);
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begin
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if areset = '1' then
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tMultResult := (others => '0');
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elsif (clk'event and clk = '1') then
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-- we must multiply unconditionally to get pipelined multiplication
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tMultResult := multA * multB;
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multResult3 <= multResult2;
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multResult2 <= multResult;
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multResult <= tMultResult(wordSize-1 downto 0);
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end if;
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end process;
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opcodeControl: process(clk, areset)
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variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
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variable spOffset : unsigned(4 downto 0);
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variable tSpOffset : unsigned(4 downto 0);
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variable nextPC : unsigned(ADDR_BIT_RANGE);
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variable tNextState : InsnType;
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variable tDecodedOpcode : InsnArray;
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variable tCPURun : std_logic;
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-- variable tMultResult : unsigned(wordSize*2-1 downto 0);
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begin
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if areset = '1' then
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state <= State_Idle;
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break <= '0';
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tCPURun := '1';
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sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE);
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pc <= (others => '0');
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idim_flag <= '0';
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begin_inst <= '0';
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inInterrupt <= '0';
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mem_writeEnable <= '0';
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mem_readEnable <= '0';
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multA <= (others => '0');
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multB <= (others => '0');
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mem_writeMask <= (others => '1');
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interrupt_ack <= '0';
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interrupt_done <= '0';
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clkDivider <= '0';
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if DEBUG_CPU = true then
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debugRec <= ZPU_DBG_T_INIT;
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debugCnt <= 0;
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debugLoad <= '0';
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end if;
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elsif (clk'event and clk = '1') then
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-- we must multiply unconditionally to get pipelined multiplication
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-- tMultResult := multA * multB;
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-- multResult3 <= multResult2;
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-- multResult2 <= multResult;
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-- multResult <= tMultResult(wordSize-1 downto 0);
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binaryOpResult2 <= binaryOpResult; -- pipeline a bit.
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multA <= (others => DontCareValue);
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multB <= (others => DontCareValue);
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-- mem_addr <= (others => DontCareValue);
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mem_readEnable <='0';
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mem_writeEnable <='0';
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-- mem_write <= (others => DontCareValue);
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if DEBUG_CPU = true then
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debugLoad <= '0';
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end if;
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if (mem_writeEnable = '1') and (mem_readEnable = '1') then
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report "read/write collision" severity failure;
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end if;
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-- At the moment, the main state machine wont run at full (100MHz) speed, only 1/2 speed, hence the divider.
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-- Once the delay causing it to fail is removed, freq reduced or re-engineered, remove this divider.
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clkDivider <= '1';
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if clkDivider = '1' then
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clkDivider <= '0';
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if DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1') then
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tCPURun := '1';
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end if;
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else
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tCPURun := '0';
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end if;
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spOffset(4) := not opcode(to_integer(pc(byteBits-1 downto 0)))(4);
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spOffset(3 downto 0) := unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0));
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nextPC := pc + 1;
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-- prepare trace snapshot
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trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0)));
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trace_pc <= std_logic_vector(pc);
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trace_sp <= std_logic_vector(sp);
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trace_topOfStack <= std_logic_vector(stackA);
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trace_topOfStackB <= std_logic_vector(stackB);
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begin_inst <= '0';
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-- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the
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-- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design.
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--
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interrupt_ack <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only.
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interrupt_done <= '0'; -- Reset interrupt done if set, width is 1 clock only.
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if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interrupt_suspended_addr(ADDR_BIT_RANGE) then
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inInterrupt <= '0'; -- no longer in an interrupt
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interrupt_done <= '1'; -- Interrupt service routine complete.
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end if;
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-- If the cpu can run, continue with next state.
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--
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if tCPURun = '1' then
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case state is
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when State_Idle =>
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if enable = '1' then
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state <= State_Resync;
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end if;
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-- Initial state of ZPU, fetch top of stack + first instruction
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when State_Resync =>
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if in_mem_busy = '0' then
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mem_addr <= std_logic_vector(sp);
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mem_readEnable <= '1';
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state <= State_Resync2;
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end if;
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when State_Resync2 =>
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if in_mem_busy = '0' then
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stackA <= unsigned(mem_read);
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mem_addr <= std_logic_vector(incSp);
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mem_readEnable <= '1';
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state <= State_Resync3;
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-- If debug enabled, write out state during resync.
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--if DEBUG_CPU = true then
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-- debugRec.FMT_DATA_PRTMODE <= "00";
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-- debugRec.FMT_PRE_SPACE <= '0';
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-- debugRec.FMT_POST_SPACE <= '0';
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-- debugRec.FMT_PRE_CR <= '1';
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-- debugRec.FMT_POST_CRLF <= '1';
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-- debugRec.FMT_SPLIT_DATA <= "00";
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-- debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(5, 3));
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-- debugRec.WRITE_DATA <= '1';
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-- debugRec.WRITE_OPCODE <= '0';
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-- debugRec.WRITE_DECODED_OPCODE <= '0';
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-- debugRec.WRITE_PC <= '1';
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-- debugRec.WRITE_SP <= '1';
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-- debugRec.WRITE_STACK_TOS <= '1';
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-- debugRec.WRITE_STACK_NOS <= '1';
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-- debugRec.DATA <= X"524553594E430000";
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-- debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc);
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-- debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp);
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-- debugRec.STACK_TOS <= std_logic_vector(stackA);
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-- debugRec.STACK_NOS <= std_logic_vector(stackB);
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-- debugLoad <= '1';
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--end if;
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end if;
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when State_Resync3 =>
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if in_mem_busy = '0' then
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stackB <= unsigned(mem_read);
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mem_addr <= std_logic_vector(pc(ADDR_32BIT_RANGE));
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mem_readEnable <= '1';
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state <= State_Decode;
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end if;
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when State_Decode =>
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if in_mem_busy = '0' then
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decodeWord <= mem_read;
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state <= State_Decode2;
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-- Do not recurse into ISR while interrupt line is active
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if interrupt_request = '1' and inInterrupt = '0' and idim_flag = '0' then
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-- We got an interrupt, execute interrupt instead of next instruction
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inInterrupt <= '1';
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interrupt_ack <= '1'; -- Acknowledge interrupt.
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interrupt_suspended_addr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted.
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sp <= decSp;
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mem_writeEnable <= '1';
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mem_addr <= std_logic_vector(incSp);
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mem_write <= std_logic_vector(stackB);
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stackA <= (others => DontCareValue);
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stackA(ADDR_BIT_RANGE) <= pc;
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stackB <= stackA;
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pc <= to_unsigned(32, maxAddrBit);
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state <= State_Interrupt;
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end if;
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end if;
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when State_Interrupt =>
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if in_mem_busy = '0' then
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mem_addr <= std_logic_vector(pc(ADDR_32BIT_RANGE));
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mem_readEnable <= '1';
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state <= State_Decode;
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report "ZPU jumped to interrupt!" severity note;
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end if;
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when State_Decode2 =>
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-- decode 4 instructions in parallel
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for i in 0 to wordBytes-1 loop
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tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
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tSpOffset(4) := not tOpcode(4);
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tSpOffset(3 downto 0) :=unsigned(tOpcode(3 downto 0));
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opcode(i) <= tOpcode;
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if (tOpcode(7 downto 7) = OpCode_Im) then
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tNextState := State_Im;
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elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
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if tSpOffset = 0 then
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tNextState := State_Pop;
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elsif tSpOffset = 1 then
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tNextState := State_PopDown;
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else
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tNextState := State_StoreSP;
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end if;
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elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
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if tSpOffset = 0 then
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tNextState := State_Dup;
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elsif tSpOffset = 1 then
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tNextState := State_DupStackB;
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else
|
|
tNextState := State_LoadSP;
|
|
end if;
|
|
elsif (tOpcode(7 downto 5) = OpCode_Emulate) then
|
|
tNextState := State_Emulate;
|
|
if tOpcode(5 downto 0) = OpCode_Neqbranch then
|
|
tNextState := State_Neqbranch;
|
|
elsif tOpcode(5 downto 0) = OpCode_Eq then
|
|
tNextState := State_Eq;
|
|
elsif tOpcode(5 downto 0) = OpCode_Lessthan then
|
|
tNextState := State_Lessthan;
|
|
elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then
|
|
tNextState := State_Lessthanorequal; --
|
|
elsif tOpcode(5 downto 0) = OpCode_Ulessthan then
|
|
tNextState := State_Ulessthan;
|
|
elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then
|
|
tNextState := State_Ulessthanorequal; --
|
|
elsif tOpcode(5 downto 0) = OpCode_Loadb then
|
|
tNextState := State_Loadb;
|
|
elsif tOpcode(5 downto 0) = OpCode_Loadh then
|
|
-- Emulated
|
|
elsif tOpcode(5 downto 0) = OpCode_Mult then
|
|
tNextState := State_Mult;
|
|
elsif tOpcode(5 downto 0) = OpCode_Storeb then
|
|
tNextState := State_Storeb;
|
|
elsif tOpcode(5 downto 0) = OpCode_Storeh then
|
|
-- Emulated
|
|
elsif tOpcode(5 downto 0) = OpCode_Pushspadd then
|
|
tNextState := State_Pushspadd;
|
|
elsif tOpcode(5 downto 0) = OpCode_Callpcrel then
|
|
tNextState := State_Callpcrel;
|
|
elsif tOpcode(5 downto 0) = OpCode_Call then
|
|
tNextState := State_Call; --
|
|
elsif tOpcode(5 downto 0) = OpCode_Sub then
|
|
tNextState := State_Sub;
|
|
elsif tOpcode(5 downto 0) = OpCode_PopPCRel then
|
|
tNextState := State_PopPCRel; --
|
|
elsif tOpcode(5 downto 0) = OpCode_Lshiftright then
|
|
-- Emulated
|
|
elsif tOpcode(5 downto 0) = OpCode_Ashiftleft then
|
|
-- Emulated
|
|
elsif tOpcode(5 downto 0) = OpCode_Ashiftright then
|
|
-- Emulated
|
|
end if;
|
|
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
|
|
if tSpOffset = 0 then
|
|
tNextState := State_Shift;
|
|
elsif tSpOffset = 1 then
|
|
tNextState := State_AddTop;
|
|
else
|
|
tNextState := State_AddSP;
|
|
end if;
|
|
else
|
|
case tOpcode(3 downto 0) is
|
|
when OpCode_Nop => tNextState := State_Nop;
|
|
when OpCode_PushSP => tNextState := State_PushSP;
|
|
when OpCode_PopPC => tNextState := State_PopPC;
|
|
when OpCode_Add => tNextState := State_Add;
|
|
when OpCode_Or => tNextState := State_Or;
|
|
when OpCode_And => tNextState := State_And;
|
|
when OpCode_Load => tNextState := State_Load;
|
|
when OpCode_Not => tNextState := State_Not;
|
|
when OpCode_Flip => tNextState := State_Flip;
|
|
when OpCode_Store => tNextState := State_Store;
|
|
when OpCode_PopSP => tNextState := State_PopSP;
|
|
when others => tNextState := State_Break;
|
|
|
|
end case;
|
|
end if;
|
|
tDecodedOpcode(i) := tNextState;
|
|
|
|
end loop;
|
|
|
|
insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0)));
|
|
|
|
-- once we wrap, we need to fetch
|
|
tDecodedOpcode(0) := State_InsnFetch;
|
|
|
|
decodedOpcode <= tDecodedOpcode;
|
|
--state <= State_Execute;
|
|
if DEBUG_CPU = true then
|
|
state <= State_Execute;
|
|
debugState <= Debug_Start;
|
|
else
|
|
state <= State_Execute;
|
|
end if;
|
|
|
|
when State_Debug =>
|
|
case debugState is
|
|
when Debug_Start =>
|
|
|
|
-- Write out the primary data.
|
|
if DEBUG_CPU = true then
|
|
debugRec.FMT_DATA_PRTMODE <= "00";
|
|
debugRec.FMT_PRE_SPACE <= '0';
|
|
debugRec.FMT_POST_SPACE <= '0';
|
|
debugRec.FMT_PRE_CR <= '1';
|
|
debugRec.FMT_POST_CRLF <= '0';
|
|
debugRec.FMT_SPLIT_DATA <= "00";
|
|
debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.WRITE_DATA <= '0';
|
|
debugRec.WRITE_DATA2 <= '0';
|
|
debugRec.WRITE_DATA3 <= '0';
|
|
debugRec.WRITE_DATA4 <= '0';
|
|
debugRec.WRITE_OPCODE <= '0';
|
|
debugRec.WRITE_DECODED_OPCODE <= '0';
|
|
debugRec.WRITE_PC <= '1';
|
|
debugRec.WRITE_SP <= '1';
|
|
debugRec.WRITE_STACK_TOS <= '1';
|
|
debugRec.WRITE_STACK_NOS <= '1';
|
|
debugRec.DATA(63 downto 0) <= (others => '0');
|
|
debugRec.DATA2(63 downto 0) <= (others => '0');
|
|
debugRec.DATA3(63 downto 0) <= (others => '0');
|
|
debugRec.DATA4(63 downto 0) <= (others => '0');
|
|
debugRec.OPCODE <= (others => '0');
|
|
debugRec.DECODED_OPCODE <= (others => '0');
|
|
debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc);
|
|
debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp);
|
|
debugRec.STACK_TOS <= std_logic_vector(stackA);
|
|
debugRec.STACK_NOS <= std_logic_vector(stackB);
|
|
debugLoad <= '1';
|
|
debugCnt <= 0;
|
|
debugState <= Debug_DumpFifo;
|
|
end if;
|
|
|
|
when Debug_DumpFifo =>
|
|
-- Write out the opcode.
|
|
if DEBUG_CPU = true then
|
|
debugRec.FMT_DATA_PRTMODE <= "00";
|
|
debugRec.FMT_PRE_SPACE <= '0';
|
|
debugRec.FMT_POST_SPACE <= '1';
|
|
debugRec.FMT_PRE_CR <= '0';
|
|
if debugCnt = 3 then
|
|
debugRec.FMT_POST_CRLF <= '1';
|
|
else
|
|
debugRec.FMT_POST_CRLF <= '0';
|
|
end if;
|
|
debugRec.FMT_SPLIT_DATA <= "00";
|
|
debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.WRITE_DATA <= '0';
|
|
debugRec.WRITE_DATA2 <= '0';
|
|
debugRec.WRITE_DATA3 <= '0';
|
|
debugRec.WRITE_DATA4 <= '0';
|
|
debugRec.WRITE_OPCODE <= '1';
|
|
debugRec.WRITE_DECODED_OPCODE <= '1';
|
|
debugRec.WRITE_PC <= '0';
|
|
debugRec.WRITE_SP <= '0';
|
|
debugRec.WRITE_STACK_TOS <= '0';
|
|
debugRec.WRITE_STACK_NOS <= '0';
|
|
debugRec.DATA(63 downto 0) <= (others => '0');
|
|
debugRec.DATA2(63 downto 0) <= (others => '0');
|
|
debugRec.DATA3(63 downto 0) <= (others => '0');
|
|
debugRec.DATA4(63 downto 0) <= (others => '0');
|
|
debugRec.OPCODE <= opcode(debugCnt);
|
|
debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(tDecodedOpcode(debugCnt)), 6));
|
|
debugRec.PC(ADDR_BIT_RANGE) <= (others => '0');
|
|
debugRec.SP(ADDR_32BIT_RANGE) <= (others => '0');
|
|
debugRec.STACK_TOS <= (others => '0');
|
|
debugRec.STACK_NOS <= (others => '0');
|
|
debugLoad <= '1';
|
|
debugCnt <= 0;
|
|
debugState <= Debug_DumpFifo_1;
|
|
end if;
|
|
|
|
when Debug_DumpFifo_1 =>
|
|
-- Move onto next opcode in Fifo.
|
|
debugCnt <= debugCnt + 1;
|
|
if debugCnt = 3 then
|
|
debugState <= Debug_End;
|
|
else
|
|
debugState <= Debug_DumpFifo;
|
|
end if;
|
|
|
|
when Debug_End =>
|
|
state <= State_Execute;
|
|
end case;
|
|
|
|
-- Each instruction must:
|
|
--
|
|
-- 1. set idim_flag
|
|
-- 2. increase pc if applicable
|
|
-- 3. set next state if appliable
|
|
-- 4. do it's operation
|
|
|
|
when State_Execute =>
|
|
|
|
-- Debug code, if enabled, writes out the current instruction.
|
|
if DEBUG_CPU = true and insn /= State_InsnFetch and pc >= X"9000" then
|
|
|
|
debugRec.FMT_DATA_PRTMODE <= "00";
|
|
debugRec.FMT_PRE_SPACE <= '0';
|
|
debugRec.FMT_POST_SPACE <= '0';
|
|
debugRec.FMT_PRE_CR <= '1';
|
|
debugRec.FMT_POST_CRLF <= '1';
|
|
debugRec.FMT_SPLIT_DATA <= "00";
|
|
debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.WRITE_DATA <= '0';
|
|
debugRec.WRITE_DATA2 <= '0';
|
|
debugRec.WRITE_DATA3 <= '0';
|
|
debugRec.WRITE_DATA4 <= '0';
|
|
debugRec.WRITE_OPCODE <= '1';
|
|
debugRec.WRITE_DECODED_OPCODE <= '1';
|
|
debugRec.WRITE_PC <= '1';
|
|
debugRec.WRITE_SP <= '1';
|
|
debugRec.WRITE_STACK_TOS <= '1';
|
|
debugRec.WRITE_STACK_NOS <= '1';
|
|
debugRec.DATA(63 downto 0) <= (others => '0');
|
|
debugRec.DATA2(63 downto 0) <= (others => '0');
|
|
debugRec.DATA3(63 downto 0) <= (others => '0');
|
|
debugRec.DATA4(63 downto 0) <= (others => '0');
|
|
debugRec.OPCODE <= opcode(to_integer(pc(byteBits-1 downto 0)));
|
|
debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(insn), 6));
|
|
debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc);
|
|
debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp);
|
|
debugRec.STACK_TOS <= std_logic_vector(stackA);
|
|
debugRec.STACK_NOS <= std_logic_vector(stackB);
|
|
debugLoad <= '1';
|
|
end if;
|
|
|
|
insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0)));
|
|
|
|
case insn is
|
|
when State_InsnFetch =>
|
|
state <= State_Fetch;
|
|
when State_Im =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '1';
|
|
pc <= pc + 1;
|
|
|
|
if idim_flag = '1' then
|
|
stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
|
|
stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
|
|
else
|
|
mem_writeEnable <= '1';
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_write <= std_logic_vector(stackB);
|
|
stackB <= stackA;
|
|
sp <= decSp;
|
|
for i in wordSize-1 downto 7 loop
|
|
stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6);
|
|
end loop;
|
|
stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
|
|
end if;
|
|
end if;
|
|
when State_StoreSP =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
state <= State_StoreSP2;
|
|
|
|
mem_writeEnable <= '1';
|
|
mem_addr <= std_logic_vector(sp+spOffset);
|
|
mem_write <= std_logic_vector(stackA);
|
|
stackA <= stackB;
|
|
sp <= incSp;
|
|
end if;
|
|
|
|
when State_LoadSP =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
state <= State_LoadSP2;
|
|
|
|
sp <= decSp;
|
|
mem_writeEnable <= '1';
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_write <= std_logic_vector(stackB);
|
|
end if;
|
|
when State_Emulate =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
sp <= decSp;
|
|
mem_writeEnable <= '1';
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_write <= std_logic_vector(stackB);
|
|
stackA <= (others => DontCareValue);
|
|
stackA(ADDR_BIT_RANGE) <= pc + 1;
|
|
stackB <= stackA;
|
|
|
|
-- The emulate address is:
|
|
-- 98 7654 3210
|
|
-- 0000 00aa aaa0 0000
|
|
pc <= (others => '0');
|
|
pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0));
|
|
state <= State_Fetch;
|
|
end if;
|
|
when State_Callpcrel =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
stackA <= (others => DontCareValue);
|
|
stackA(ADDR_BIT_RANGE) <= pc + 1;
|
|
|
|
pc <= pc + stackA(ADDR_BIT_RANGE);
|
|
state <= State_Fetch;
|
|
end if;
|
|
when State_Call =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
stackA <= (others => DontCareValue);
|
|
stackA(ADDR_BIT_RANGE) <= pc + 1;
|
|
pc <= stackA(ADDR_BIT_RANGE);
|
|
state <= State_Fetch;
|
|
end if;
|
|
when State_AddSP =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
state <= State_AddSP2;
|
|
|
|
mem_readEnable <= '1';
|
|
mem_addr <= std_logic_vector(sp+spOffset);
|
|
end if;
|
|
when State_PushSP =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
sp <= decSp;
|
|
stackA <= (others => '0');
|
|
stackA(ADDR_32BIT_RANGE) <= sp;
|
|
stackB <= stackA;
|
|
mem_writeEnable <= '1';
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_write <= std_logic_vector(stackB);
|
|
end if;
|
|
when State_PopPC =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= stackA(ADDR_BIT_RANGE);
|
|
sp <= incSp;
|
|
|
|
mem_writeEnable <= '1';
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_write <= std_logic_vector(stackB);
|
|
state <= State_Resync;
|
|
end if;
|
|
when State_PopPCRel =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= stackA(ADDR_BIT_RANGE) + pc;
|
|
sp <= incSp;
|
|
|
|
mem_writeEnable <= '1';
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_write <= std_logic_vector(stackB);
|
|
state <= State_Resync;
|
|
end if;
|
|
when State_Add =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
stackA <= stackA + stackB;
|
|
|
|
mem_readEnable <= '1';
|
|
mem_addr <= std_logic_vector(incIncSp);
|
|
sp <= incSp;
|
|
state <= State_Popped;
|
|
end if;
|
|
when State_Sub =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
binaryOpResult <= stackB - stackA;
|
|
state <= State_BinaryOpResult;
|
|
end if;
|
|
when State_Pop =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
mem_addr <= std_logic_vector(incIncSp);
|
|
mem_readEnable <= '1';
|
|
sp <= incSp;
|
|
stackA <= stackB;
|
|
state <= State_Popped;
|
|
end if;
|
|
when State_PopDown =>
|
|
if in_mem_busy = '0' then
|
|
-- PopDown leaves top of stack unchanged
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
mem_addr <= std_logic_vector(incIncSp);
|
|
mem_readEnable <= '1';
|
|
sp <= incSp;
|
|
state <= State_Popped;
|
|
end if;
|
|
when State_Or =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
stackA <= stackA or stackB;
|
|
mem_readEnable <= '1';
|
|
mem_addr <= std_logic_vector(incIncSp);
|
|
sp <= incSp;
|
|
state <= State_Popped;
|
|
end if;
|
|
when State_And =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
|
|
stackA <= stackA and stackB;
|
|
mem_readEnable <= '1';
|
|
mem_addr <= std_logic_vector(incIncSp);
|
|
sp <= incSp;
|
|
state <= State_Popped;
|
|
end if;
|
|
when State_Eq =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
|
|
binaryOpResult <= (others => '0');
|
|
if (stackA = stackB) then
|
|
binaryOpResult(0) <= '1';
|
|
end if;
|
|
state <= State_BinaryOpResult;
|
|
end if;
|
|
when State_Ulessthan =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
|
|
binaryOpResult <= (others => '0');
|
|
if (stackA<stackB) then
|
|
binaryOpResult(0) <= '1';
|
|
end if;
|
|
state <= State_BinaryOpResult;
|
|
end if;
|
|
when State_Ulessthanorequal =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
|
|
binaryOpResult <= (others => '0');
|
|
if (stackA<=stackB) then
|
|
binaryOpResult(0) <= '1';
|
|
end if;
|
|
state <= State_BinaryOpResult;
|
|
end if;
|
|
when State_Lessthan =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
|
|
binaryOpResult <= (others => '0');
|
|
if (signed(stackA)<signed(stackB)) then
|
|
binaryOpResult(0) <= '1';
|
|
end if;
|
|
state <= State_BinaryOpResult;
|
|
end if;
|
|
when State_Lessthanorequal =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
|
|
binaryOpResult <= (others => '0');
|
|
if (signed(stackA)<=signed(stackB)) then
|
|
binaryOpResult(0) <= '1';
|
|
end if;
|
|
state <= State_BinaryOpResult;
|
|
end if;
|
|
when State_Load =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
state <= State_Load2;
|
|
|
|
mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE));
|
|
mem_readEnable <= '1';
|
|
end if;
|
|
|
|
when State_Dup =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
sp <= decSp;
|
|
stackB <= stackA;
|
|
mem_write <= std_logic_vector(stackB);
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_writeEnable <= '1';
|
|
end if;
|
|
when State_DupStackB =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
sp <= decSp;
|
|
stackA <= stackB;
|
|
stackB <= stackA;
|
|
mem_write <= std_logic_vector(stackB);
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_writeEnable <= '1';
|
|
end if;
|
|
when State_Store =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE));
|
|
mem_write <= std_logic_vector(stackB);
|
|
mem_writeEnable <= '1';
|
|
sp <= incIncSp;
|
|
state <= State_Resync;
|
|
end if;
|
|
when State_PopSP =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
mem_write <= std_logic_vector(stackB);
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_writeEnable <= '1';
|
|
sp <= stackA(ADDR_32BIT_RANGE);
|
|
state <= State_Resync;
|
|
end if;
|
|
when State_Nop =>
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
when State_Not =>
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
stackA <= not stackA;
|
|
when State_Flip =>
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
for i in 0 to wordSize-1 loop
|
|
stackA(i) <= stackA(wordSize-1-i);
|
|
end loop;
|
|
when State_AddTop =>
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
stackA <= stackA + stackB;
|
|
when State_Shift =>
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
|
|
stackA(0) <= '0';
|
|
when State_Pushspadd =>
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
pc <= pc + 1;
|
|
|
|
stackA <= (others => '0');
|
|
stackA(ADDR_32BIT_RANGE) <= stackA((maxAddrBit-1)-minAddrBit downto 0)+sp;
|
|
when State_Neqbranch =>
|
|
-- branches are almost always taken as they form loops
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
sp <= incIncSp;
|
|
if (stackB/=0) then
|
|
pc <= stackA(ADDR_BIT_RANGE) + pc;
|
|
else
|
|
pc <= pc + 1;
|
|
end if;
|
|
-- need to fetch stack again.
|
|
state <= State_Resync;
|
|
when State_Mult =>
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
|
|
multA <= stackA;
|
|
multB <= stackB;
|
|
state <= State_Mult2;
|
|
when State_Break =>
|
|
report "Break instruction encountered" severity failure;
|
|
break <= '1';
|
|
when State_Loadb =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
state <= State_Loadb2;
|
|
|
|
mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE));
|
|
mem_readEnable <= '1';
|
|
end if;
|
|
when State_Storeb =>
|
|
if in_mem_busy = '0' then
|
|
begin_inst <= '1';
|
|
idim_flag <= '0';
|
|
state <= State_Storeb2;
|
|
|
|
mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE));
|
|
mem_readEnable <= '1';
|
|
end if;
|
|
|
|
when others =>
|
|
sp <= (others => DontCareValue);
|
|
report "Illegal instruction" severity failure;
|
|
break <= '1';
|
|
end case;
|
|
|
|
|
|
when State_StoreSP2 =>
|
|
if in_mem_busy = '0' then
|
|
mem_addr <= std_logic_vector(incSp);
|
|
mem_readEnable <= '1';
|
|
state <= State_Popped;
|
|
end if;
|
|
when State_LoadSP2 =>
|
|
if in_mem_busy = '0' then
|
|
state <= State_LoadSP3;
|
|
mem_readEnable <= '1';
|
|
mem_addr <= std_logic_vector(sp+spOffset+1);
|
|
end if;
|
|
when State_LoadSP3 =>
|
|
if in_mem_busy = '0' then
|
|
pc <= pc + 1;
|
|
state <= State_Execute;
|
|
stackB <= stackA;
|
|
stackA <= unsigned(mem_read);
|
|
end if;
|
|
when State_AddSP2 =>
|
|
if in_mem_busy = '0' then
|
|
pc <= pc + 1;
|
|
state <= State_Execute;
|
|
stackA <= stackA + unsigned(mem_read);
|
|
end if;
|
|
when State_Load2 =>
|
|
if in_mem_busy = '0' then
|
|
stackA <= unsigned(mem_read);
|
|
pc <= pc + 1;
|
|
state <= State_Execute;
|
|
end if;
|
|
when State_Loadb2 =>
|
|
if in_mem_busy = '0' then
|
|
stackA <= (others => '0');
|
|
stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8));
|
|
pc <= pc + 1;
|
|
state <= State_Execute;
|
|
end if;
|
|
when State_Storeb2 =>
|
|
if in_mem_busy = '0' then
|
|
mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE));
|
|
mem_write <= mem_read;
|
|
mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0));
|
|
mem_writeEnable <= '1';
|
|
pc <= pc + 1;
|
|
sp <= incIncSp;
|
|
state <= State_Resync;
|
|
end if;
|
|
when State_Fetch =>
|
|
if in_mem_busy = '0' then
|
|
mem_addr <= std_logic_vector(pc(ADDR_32BIT_RANGE));
|
|
mem_readEnable <= '1';
|
|
state <= State_Decode;
|
|
|
|
-- If debug enabled, write out state during fetch.
|
|
if DEBUG_CPU = true and pc >= X"9000" then
|
|
debugRec.FMT_DATA_PRTMODE <= "00";
|
|
debugRec.FMT_PRE_SPACE <= '0';
|
|
debugRec.FMT_POST_SPACE <= '0';
|
|
debugRec.FMT_PRE_CR <= '1';
|
|
debugRec.FMT_POST_CRLF <= '1';
|
|
debugRec.FMT_SPLIT_DATA <= "00";
|
|
debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(4, 3));
|
|
debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3));
|
|
debugRec.WRITE_DATA <= '1';
|
|
debugRec.WRITE_DATA2 <= '0';
|
|
debugRec.WRITE_DATA3 <= '0';
|
|
debugRec.WRITE_DATA4 <= '0';
|
|
debugRec.WRITE_OPCODE <= '0';
|
|
debugRec.WRITE_DECODED_OPCODE <= '0';
|
|
debugRec.WRITE_PC <= '1';
|
|
debugRec.WRITE_SP <= '1';
|
|
debugRec.WRITE_STACK_TOS <= '1';
|
|
debugRec.WRITE_STACK_NOS <= '1';
|
|
debugRec.DATA(63 downto 0) <= X"4645544348000000";
|
|
debugRec.DATA2(63 downto 0) <= (others => '0');
|
|
debugRec.DATA3(63 downto 0) <= (others => '0');
|
|
debugRec.DATA4(63 downto 0) <= (others => '0');
|
|
debugRec.OPCODE <= (others => '0');
|
|
debugRec.DECODED_OPCODE <= (others => '0');
|
|
debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc);
|
|
debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp);
|
|
debugRec.STACK_TOS <= std_logic_vector(stackA);
|
|
debugRec.STACK_NOS <= std_logic_vector(stackB);
|
|
debugLoad <= '1';
|
|
end if;
|
|
end if;
|
|
when State_Mult2 =>
|
|
state <= State_Mult3;
|
|
when State_Mult3 =>
|
|
state <= State_Mult4;
|
|
when State_Mult4 =>
|
|
state <= State_Mult5;
|
|
when State_Mult5 =>
|
|
if in_mem_busy = '0' then
|
|
stackA <= multResult3;
|
|
mem_readEnable <= '1';
|
|
mem_addr <= std_logic_vector(incIncSp);
|
|
sp <= incSp;
|
|
state <= State_Popped;
|
|
end if;
|
|
when State_BinaryOpResult =>
|
|
state <= State_BinaryOpResult2;
|
|
when State_BinaryOpResult2 =>
|
|
mem_readEnable <= '1';
|
|
mem_addr <= std_logic_vector(incIncSp);
|
|
sp <= incSp;
|
|
stackA <= binaryOpResult2;
|
|
state <= State_Popped;
|
|
when State_Popped =>
|
|
if in_mem_busy = '0' then
|
|
pc <= pc + 1;
|
|
stackB <= unsigned(mem_read);
|
|
state <= State_Execute;
|
|
end if;
|
|
when others =>
|
|
sp <= (others => DontCareValue);
|
|
report "Illegal state" severity failure;
|
|
break <= '1';
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
-- Debugger output processor.
|
|
-- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port.
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
-- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU)
|
|
-- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can
|
|
-- shift 10 bits.
|
|
DEBUG : if DEBUG_CPU = true generate
|
|
DEBUGUART: entity work.zpu_uart_debug
|
|
generic map (
|
|
CLK_FREQ => CLK_FREQ -- Frequency of master clock.
|
|
)
|
|
port map (
|
|
-- CPU Interface
|
|
CLK => clk, -- master clock
|
|
RESET => areset, -- high active sync reset
|
|
DEBUG_DATA => debugRec, -- write data
|
|
CS => debugLoad, -- Chip Select.
|
|
READY => debugReady, -- Debug processor ready for next command.
|
|
|
|
-- Serial data
|
|
TXD => debug_txd
|
|
);
|
|
end generate;
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
-- End of debugger output processor.
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
end behave;
|