136 lines
6.5 KiB
Tcl
136 lines
6.5 KiB
Tcl
## Generated SDC file "E115_zpu.out.sdc"
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## Copyright (C) 2017 Intel Corporation. All rights reserved.
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## Your use of Intel Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Intel Program License
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## Subscription Agreement, the Intel Quartus Prime License Agreement,
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## the Intel FPGA IP License Agreement, or other applicable license
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## agreement, including, without limitation, that your use is for
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## the sole purpose of programming logic devices manufactured by
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## Intel and sold by Intel or its authorized distributors. Please
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## refer to the applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus Prime"
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## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
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## DATE "Sat Jun 22 23:32:00 2019"
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##
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## DEVICE "EP4CE115F23I7"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {clk_12} -period 83.333 -waveform { 0.000 0.500 } [get_ports {CLOCK_12M}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk0}]
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#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 50 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
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#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
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#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
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#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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# Delays for async signals - not necessary, but might as well avoid
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# having unconstrained ports in the design
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#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
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#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
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#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -from [get_keepers {USER_BTN*}]
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#set_false_path -from [get_keepers {SW*}]
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#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
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#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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