449 lines
20 KiB
VHDL
449 lines
20 KiB
VHDL
-- 32bit Word Addressed BRAM module for the ZPU Evo implementation.
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--
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-- This memory is used for the stack cache. It has 64bit wide read/
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-- write for the CPU side which represents TOS/NOS and 32bit wide
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-- read/write for the interface between the MXP and the external memory.
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--
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-- Copyright 2018-2021 - Philip Smart for the ZPU Evo implementation.
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--
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-- The FreeBSD license
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- The views and conclusions contained in the software and documentation
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-- are those of the authors and should not be interpreted as representing
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-- official policies, either expressed or implied, of the ZPU Project.
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library ieee;
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library pkgs;
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library work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.zpu_pkg.all;
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use work.zpu_soc_pkg.all;
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entity evo_STcache is
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generic
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(
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addrbits : integer := 16
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);
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port
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(
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clk : in std_logic;
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memAAddr : in std_logic_vector(addrbits-1 downto 2);
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memAWriteTOSEnable : in std_logic;
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memAWriteNOSEnable : in std_logic;
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memAWrite : in std_logic_vector(WORD_64BIT_RANGE);
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memARead : out std_logic_vector(WORD_64BIT_RANGE);
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memBAddr : in std_logic_vector(addrbits-1 downto 0);
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memBWriteEnable : in std_logic;
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memBWriteByte : in std_logic;
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memBWriteHalfWord : in std_logic;
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memBWrite : in std_logic_vector(WORD_32BIT_RANGE);
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memBRead : out std_logic_vector(WORD_32BIT_RANGE)
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);
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end evo_STcache;
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architecture arch of evo_STcache is
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type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0);
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shared variable RAMTOS0 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMTOS1 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMTOS2 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMTOS3 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMTOS4 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMTOS5 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMTOS6 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMTOS7 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS0 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS1 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS2 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS3 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS4 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS5 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS6 : ramArray :=
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(
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others => X"00"
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);
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shared variable RAMNOS7 : ramArray :=
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(
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others => X"00"
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);
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signal TOSreadA : std_logic_vector(WORD_32BIT_RANGE); -- Buffer for reading a 64bit TOS word.
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signal NOSreadA : std_logic_vector(WORD_32BIT_RANGE); -- Buffer for reading a 64bit NOS word.
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signal TOSreadB : std_logic_vector(WORD_32BIT_RANGE); -- Buffer for reading a 32bit TOS word.
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signal NOSreadB : std_logic_vector(WORD_32BIT_RANGE); -- Buffer for reading a 32bit NOS word.
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signal RAMTOS_A_ADDR : unsigned(addrbits-1 downto 2); -- Address on Port A to read/write TOS from.
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signal RAMNOS_A_ADDR : unsigned(addrbits-1 downto 2); -- Address on Port B to read/write NOS from.
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signal RAMTOS0_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMTOS1_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMTOS2_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMTOS3_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMNOS0_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMNOS1_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMNOS2_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMNOS3_B_DATA : std_logic_vector(WORD_8BIT_RANGE); -- Buffer for selecting correct part of a 32bit word to be written in bytes.
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signal RAMTOS_A_WREN : std_logic; -- Write Enable for the TOS word on the A Port.
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signal RAMNOS_A_WREN : std_logic; -- Write Enable for the NOS word on the A Port.
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signal RAMTOS0_B_WREN : std_logic; -- Write Enable for one byte of the TOS word on the B Port.
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signal RAMTOS1_B_WREN : std_logic; -- Write Enable for one byte of the TOS word on the B Port.
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signal RAMTOS2_B_WREN : std_logic; -- Write Enable for one byte of the TOS word on the B Port.
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signal RAMTOS3_B_WREN : std_logic; -- Write Enable for one byte of the TOS word on the B Port.
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signal RAMNOS0_B_WREN : std_logic; -- Write Enable for one byte of the NOS word on the B Port.
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signal RAMNOS1_B_WREN : std_logic; -- Write Enable for one byte of the NOS word on the B Port.
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signal RAMNOS2_B_WREN : std_logic; -- Write Enable for one byte of the NOS word on the B Port.
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signal RAMNOS3_B_WREN : std_logic; -- Write Enable for one byte of the NOS word on the B Port.
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begin
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-- Signal processing. memARead is 64bit so combine the two arrays according to the LSB, memBRead is 32 bit so mux the correct word.
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-- memAWrite is 64bit so write the given long word direct for even addresses or across 2 addresses if address is odd, memBWrite is 32bit so select the correct word to write.
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memARead <= NOSreadA & TOSreadA;
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memBRead <= TOSreadB when memBAddr(2) = '1'
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else
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NOSreadB;
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RAMTOS_A_WREN <= '1' when memAWriteTOSEnable = '1' and memAAddr(2) = '0'
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else
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'1' when memAWriteNOSEnable = '1' and memAAddr(2) = '1'
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else '0';
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RAMNOS_A_WREN <= '1' when memAWriteNOSEnable = '1' and memAAddr(2) = '0'
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else
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'1' when memAWriteNOSEnable = '1' and memAAddr(2) = '1'
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else '0';
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RAMTOS_A_ADDR <= unsigned(memAAddr(addrbits-1 downto 2)) when memAAddr(2) = '0'
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else
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unsigned(memAAddr(addrbits-1 downto 2))-1;
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RAMNOS_A_ADDR <= unsigned(memAAddr(addrbits-1 downto 2));
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RAMTOS0_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '0') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "011") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "01"))
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else '0';
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RAMTOS1_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '0') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "010") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "01"))
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else '0';
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RAMTOS2_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '0') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "001") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "00"))
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else '0';
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RAMTOS3_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '0') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "000") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "00"))
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else '0';
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RAMNOS0_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '1') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "111") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "11"))
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else '0';
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RAMNOS1_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '1') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "110") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "11"))
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else '0';
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RAMNOS2_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '1') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "101") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "10"))
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else '0';
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RAMNOS3_B_WREN <= '1' when memBWriteEnable = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0' and memBAddr(2) = '1') or (memBWriteByte = '1' and memBAddr(2 downto 0) = "100") or (memBWriteHalfWord = '1' and memBAddr(2 downto 1) = "10"))
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else '0';
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RAMTOS0_B_DATA <= memBWrite(7 downto 0) when memBAddr(2) = '0'
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else (others => '0');
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RAMTOS1_B_DATA <= memBWrite(15 downto 8) when memBAddr(2) = '0' and ((memBWriteByte = '0' and memBWriteHalfWord = '0') or memBWriteHalfWord = '1')
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else
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memBWrite(7 downto 0);
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RAMTOS2_B_DATA <= memBWrite(23 downto 16) when memBAddr(2) = '0' and ((memBWriteByte = '0' and memBWriteHalfWord = '0'))
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else
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memBWrite(7 downto 0);
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RAMTOS3_B_DATA <= memBWrite(31 downto 24) when memBAddr(2) = '0' and ((memBWriteByte = '0' and memBWriteHalfWord = '0'))
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else
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memBWrite(15 downto 8) when memBAddr(2) = '0' and (memBWriteHalfWord = '1')
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else
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memBWrite(7 downto 0);
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RAMNOS0_B_DATA <= memBWrite(7 downto 0) when memBAddr(2) = '1'
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else (others => '0');
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RAMNOS1_B_DATA <= memBWrite(15 downto 8) when memBAddr(2) = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0') or memBWriteHalfWord = '1')
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else
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memBWrite(7 downto 0);
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RAMNOS2_B_DATA <= memBWrite(23 downto 16) when memBAddr(2) = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0'))
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else
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memBWrite(7 downto 0);
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RAMNOS3_B_DATA <= memBWrite(31 downto 24) when memBAddr(2) = '1' and ((memBWriteByte = '0' and memBWriteHalfWord = '0'))
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else
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memBWrite(15 downto 8) when memBAddr(2) = '1' and (memBWriteHalfWord = '1')
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else
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memBWrite(7 downto 0);
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----------------------------------------
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-- Port A - 64bit wide.
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-- Word addressable.
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----------------------------------------
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-- RAM Port A - TOS - bits 7 to 0 (7 downto 0 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS_A_WREN = '1' then
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RAMTOS0(to_integer(RAMTOS_A_ADDR)) := memAWrite(7 downto 0);
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TOSreadA(7 downto 0) <= memAWrite(7 downto 0);
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else
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TOSreadA(7 downto 0) <= RAMTOS0(to_integer(RAMTOS_A_ADDR));
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end if;
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end if;
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end process;
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-- RAM Port A - TOS - bits 15 to 8 (15 downto 8 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS_A_WREN = '1' then
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RAMTOS1(to_integer(RAMTOS_A_ADDR)) := memAWrite(15 downto 8);
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TOSreadA(15 downto 8) <= memAWrite(15 downto 8);
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else
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TOSreadA(15 downto 8) <= RAMTOS1(to_integer(RAMTOS_A_ADDR));
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end if;
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end if;
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end process;
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-- RAM Port A - TOS - bits 23 to 16 (23 downto 16 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS_A_WREN = '1' then
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RAMTOS2(to_integer(RAMTOS_A_ADDR)) := memAWrite(23 downto 16);
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TOSreadA(23 downto 16) <= memAWrite(23 downto 16);
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else
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TOSreadA(23 downto 16) <= RAMTOS2(to_integer(RAMTOS_A_ADDR));
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end if;
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end if;
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end process;
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-- RAM Port A - TOS - bits 31 to 24 (31 downto 24 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS_A_WREN = '1' then
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RAMTOS3(to_integer(RAMTOS_A_ADDR)) := memAWrite(31 downto 24);
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TOSreadA(31 downto 24) <= memAWrite(31 downto 24);
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else
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TOSreadA(31 downto 24) <= RAMTOS3(to_integer(RAMTOS_A_ADDR));
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end if;
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end if;
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end process;
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-- RAM Port A - NOS - bits 7 to 0 (39 downto 32 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMNOS_A_WREN = '1' then
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RAMNOS0(to_integer(RAMNOS_A_ADDR)) := memAWrite(39 downto 32);
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NOSreadA(7 downto 0) <= memAWrite(39 downto 32);
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else
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NOSreadA(7 downto 0) <= RAMNOS0(to_integer(RAMNOS_A_ADDR));
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end if;
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end if;
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end process;
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-- RAM Port A - NOS - bits 15 to 8 (47 downto 40 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMNOS_A_WREN = '1' then
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RAMNOS1(to_integer(RAMNOS_A_ADDR)) := memAWrite(47 downto 40);
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NOSreadA(15 downto 8) <= memAWrite(47 downto 40);
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else
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NOSreadA(15 downto 8) <= RAMNOS1(to_integer(RAMNOS_A_ADDR));
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end if;
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end if;
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end process;
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-- RAM Port A - NOS - bits 23 to 16 (55 downto 48 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMNOS_A_WREN = '1' then
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RAMNOS2(to_integer(RAMNOS_A_ADDR)) := memAWrite(55 downto 48);
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NOSreadA(23 downto 16) <= memAWrite(55 downto 48);
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else
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NOSreadA(23 downto 16) <= RAMNOS2(to_integer(RAMNOS_A_ADDR));
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end if;
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end if;
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end process;
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-- RAM Port A - NOS - bits 31 to 24 (63 downto 56 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMNOS_A_WREN = '1' then
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RAMNOS3(to_integer(RAMNOS_A_ADDR)) := memAWrite(63 downto 56);
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NOSreadA(31 downto 24) <= memAWrite(63 downto 56);
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else
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NOSreadA(31 downto 24) <= RAMNOS3(to_integer(RAMNOS_A_ADDR));
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end if;
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end if;
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end process;
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----------------------------------------
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-- Port B - 32bit wide.
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-- Byte addressable.
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----------------------------------------
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-- RAM Port B - TOS - bits 7 downto 0 (7 downto 0 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS0_B_WREN = '1' then
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RAMTOS0(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMTOS0_B_DATA;
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TOSreadB(7 downto 0) <= RAMTOS0_B_DATA;
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else
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TOSreadB(7 downto 0) <= RAMTOS0(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
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end if;
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end if;
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end process;
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-- RAM Port B - TOS - bits 15 downto 8 (15 downto 8 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS1_B_WREN = '1' then
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RAMTOS1(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMTOS1_B_DATA;
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TOSreadB(15 downto 8) <= RAMTOS1_B_DATA;
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else
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TOSreadB(15 downto 8) <= RAMTOS1(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
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end if;
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end if;
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end process;
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-- RAM Port B - TOS - bits 23 downto 16 (23 downto 16 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS2_B_WREN = '1' then
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RAMTOS2(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMTOS2_B_DATA;
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TOSreadB(23 downto 16) <= RAMTOS2_B_DATA;
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else
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TOSreadB(23 downto 16) <= RAMTOS2(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
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end if;
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end if;
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end process;
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-- RAM Port B - TOS - bits 31 downto 24 (31 downto 24 in 64bit word).
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process(clk)
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begin
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if rising_edge(clk) then
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if RAMTOS3_B_WREN = '1' then
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RAMTOS3(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMTOS3_B_DATA;
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TOSreadB(31 downto 24) <= RAMTOS3_B_DATA;
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else
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TOSreadB(31 downto 24) <= RAMTOS3(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- RAM Port B - NOS - bits 7 downto 0 (39 downto 32 in 64bit word).
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if RAMNOS0_B_WREN = '1' then
|
|
RAMNOS0(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMNOS0_B_DATA;
|
|
NOSreadB(7 downto 0) <= RAMNOS0_B_DATA;
|
|
else
|
|
NOSreadB(7 downto 0) <= RAMNOS0(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- RAM Port B - NOS - bits 15 downto 8 (47 downto 40 in 64bit word).
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if RAMNOS1_B_WREN = '1' then
|
|
RAMNOS1(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMNOS1_B_DATA;
|
|
NOSreadB(15 downto 8) <= RAMNOS1_B_DATA;
|
|
else
|
|
NOSreadB(15 downto 8) <= RAMNOS1(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- RAM Port B - NOS - bits 23 downto 16 (55 downto 48 in 64bit word).
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if RAMNOS2_B_WREN = '1' then
|
|
RAMNOS2(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMNOS2_B_DATA;
|
|
NOSreadB(23 downto 16) <= RAMNOS2_B_DATA;
|
|
else
|
|
NOSreadB(23 downto 16) <= RAMNOS2(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- RAM Port B - NOS - bits 31 downto 24 (63 downto 56 in 64bit word).
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if RAMNOS3_B_WREN = '1' then
|
|
RAMNOS3(to_integer(unsigned(memBAddr(addrbits-1 downto 3)))) := RAMNOS3_B_DATA;
|
|
NOSreadB(31 downto 24) <= RAMNOS3_B_DATA;
|
|
else
|
|
NOSreadB(31 downto 24) <= RAMNOS3(to_integer(unsigned(memBAddr(addrbits-1 downto 3))));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end arch;
|