176 lines
9.1 KiB
Plaintext
176 lines
9.1 KiB
Plaintext
# Copyright (C) 1991-2005 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# ledwater_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
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#set_global_assignment -name VERILOG_FILE ledwater.v
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set_global_assignment -name CDF_FILE E115.cdf
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# Pin & Location Assignments
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# ==========================
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# Analysis & Synthesis Assignments
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# ================================
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name TOP_LEVEL_ENTITY E115_zpu
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# Fitter Assignments
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# ==================
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set_global_assignment -name DEVICE EP4CE115F23I7
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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# Assembler Assignments
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# =====================
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
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set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
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set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
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#============================================================
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# UART
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#============================================================
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set_location_assignment PIN_A7 -to UART_RX_0
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set_location_assignment PIN_B7 -to UART_TX_0
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set_location_assignment PIN_C6 -to UART_RX_1
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set_location_assignment PIN_D7 -to UART_TX_1
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
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#============================================================
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# CLOCK
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#============================================================
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set_location_assignment PIN_AB11 -to CLOCK_50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
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#set_location_assignment PIN_AB11 -to clk_25M
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#============================================================
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# LED
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#============================================================
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
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set_location_assignment PIN_A5 -to LED[0]
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set_location_assignment PIN_B5 -to LED[1]
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set_location_assignment PIN_C4 -to LED[2]
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set_location_assignment PIN_C3 -to LED[3]
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#============================================================
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# Modules and Files
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#============================================================
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set_global_assignment -name VHDL_FILE ../E115_zpu_Toplevel.vhd
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set_global_assignment -name QIP_FILE Clock_25to100.qip
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set_global_assignment -name SDC_FILE E115_zpu_constraints.sdc
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set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
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set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
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#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd
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set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
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#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd
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set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
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set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
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#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd
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#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
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#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
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set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
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set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
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set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
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#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd
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#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd
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#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd
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#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd
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set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
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set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
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#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd
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#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd
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set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
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set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
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set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
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set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
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set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
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set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
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set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
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set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
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set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
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set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
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set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
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set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
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set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
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set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd
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set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd
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set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
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#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v
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#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd
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#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd
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#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd
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#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v
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#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd
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#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd
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#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd
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#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd
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#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd
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#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd
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#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd
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#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd
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#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd
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#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |