diff --git a/build/CYC1000_zpu_Toplevel.vhd b/build/CYC1000_zpu_Toplevel.vhd index 1b13f2d..dcd7da1 100644 --- a/build/CYC1000_zpu_Toplevel.vhd +++ b/build/CYC1000_zpu_Toplevel.vhd @@ -154,7 +154,21 @@ port map SDRAM_WE_n => SDRAM_WE, -- write enable SDRAM_RAS_n => SDRAM_RAS, -- row address select SDRAM_CAS_n => SDRAM_CAS, -- columns address select - SDRAM_READY => open -- sd ready. + SDRAM_READY => open, -- sd ready. + + -- DDR2 DRAM - doesnt exist on the QMV. + DDR2_ADDR => open, -- 14 bit multiplexed address bus + DDR2_DQ => open, -- 64 bit bidirectional data bus + DDR2_DQS => open, -- 8 bit bidirectional data bus + DDR2_DQM => open, -- eight byte masks + DDR2_ODT => open, -- 14 bit multiplexed address bus + DDR2_BA => open, -- 8 banks + DDR2_CS => open, -- 2 chip selects. + DDR2_WE => open, -- write enable + DDR2_RAS => open, -- row address select + DDR2_CAS => open, -- columns address select + DDR2_CKE => open, -- 2 clock enable. + DDR2_CLK => open -- 2 clocks. ); diff --git a/build/Clock_50to100.vhd b/build/Clock_50to100.vhd index 54b5e08..c7c51d6 100644 --- a/build/Clock_50to100.vhd +++ b/build/Clock_50to100.vhd @@ -152,8 +152,8 @@ BEGIN clk0_phase_shift => "0", clk1_divide_by => 1, clk1_duty_cycle => 50, - clk1_multiply_by => 4, - clk1_phase_shift => "0", + clk1_multiply_by => 3, + clk1_phase_shift => "00", compensate_clock => "CLK0", gate_lock_signal => "NO", inclk0_input_frequency => 20000, diff --git a/build/DE0_nano_zpu_Toplevel.vhd b/build/DE0_nano_zpu_Toplevel.vhd index 6bcb46b..02d59b5 100644 --- a/build/DE0_nano_zpu_Toplevel.vhd +++ b/build/DE0_nano_zpu_Toplevel.vhd @@ -155,7 +155,21 @@ port map SDRAM_WE_n => open, --SDRAM_WE, -- write enable SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select - SDRAM_READY => open + SDRAM_READY => open, + + -- DDR2 DRAM - doesnt exist on the QMV. + DDR2_ADDR => open, -- 14 bit multiplexed address bus + DDR2_DQ => open, -- 64 bit bidirectional data bus + DDR2_DQS => open, -- 8 bit bidirectional data bus + DDR2_DQM => open, -- eight byte masks + DDR2_ODT => open, -- 14 bit multiplexed address bus + DDR2_BA => open, -- 8 banks + DDR2_CS => open, -- 2 chip selects. + DDR2_WE => open, -- write enable + DDR2_RAS => open, -- row address select + DDR2_CAS => open, -- columns address select + DDR2_CKE => open, -- 2 clock enable. + DDR2_CLK => open -- 2 clocks. ); diff --git a/build/DE10_nano.qpf b/build/DE10_nano.qpf deleted file mode 100644 index d023e2d..0000000 --- a/build/DE10_nano.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition -# Date created = 10:11:34 June 13, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "17.1" -DATE = "10:11:34 June 13, 2019" - -# Revisions - -PROJECT_REVISION = "DE10_nano" diff --git a/build/DE10_nano.qsf b/build/DE10_nano.qsf deleted file mode 100644 index 369c01c..0000000 --- a/build/DE10_nano.qsf +++ /dev/null @@ -1,44 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition -# Date created = 10:11:34 June 13, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# DE10_nano_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE AUTO -set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:11:34 JUNE 13, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" \ No newline at end of file diff --git a/build/DE10_nano_zpu.qsf b/build/DE10_nano_zpu.qsf index 19ef6b3..f9714c4 100644 --- a/build/DE10_nano_zpu.qsf +++ b/build/DE10_nano_zpu.qsf @@ -490,4 +490,5 @@ set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/build/DE10_nano_zpu_Toplevel.vhd b/build/DE10_nano_zpu_Toplevel.vhd index a04e550..7b67fa5 100644 --- a/build/DE10_nano_zpu_Toplevel.vhd +++ b/build/DE10_nano_zpu_Toplevel.vhd @@ -153,7 +153,21 @@ port map SDRAM_WE_n => open, --SDRAM_WE, -- write enable SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select - SDRAM_READY => open + SDRAM_READY => open, + + -- DDR2 DRAM - doesnt exist on the QMV. + DDR2_ADDR => open, -- 14 bit multiplexed address bus + DDR2_DQ => open, -- 64 bit bidirectional data bus + DDR2_DQS => open, -- 8 bit bidirectional data bus + DDR2_DQM => open, -- eight byte masks + DDR2_ODT => open, -- 14 bit multiplexed address bus + DDR2_BA => open, -- 8 banks + DDR2_CS => open, -- 2 chip selects. + DDR2_WE => open, -- write enable + DDR2_RAS => open, -- row address select + DDR2_CAS => open, -- columns address select + DDR2_CKE => open, -- 2 clock enable. + DDR2_CLK => open -- 2 clocks. ); diff --git a/build/E115_zpu.qsf b/build/E115_zpu.qsf index 2e19942..b75006b 100644 --- a/build/E115_zpu.qsf +++ b/build/E115_zpu.qsf @@ -120,6 +120,120 @@ set_location_assignment PIN_B5 -to LED[1] set_location_assignment PIN_C4 -to LED[2] set_location_assignment PIN_C3 -to LED[3] +#============================================================ +# DDR2 DRAM +#============================================================ +set_location_assignment PIN_AA20 -to DDR2_ADDR[13] +set_location_assignment PIN_V8 -to DDR2_ADDR[12] +set_location_assignment PIN_AB6 -to DDR2_ADDR[11] +set_location_assignment PIN_K22 -to DDR2_ADDR[10] +set_location_assignment PIN_W10 -to DDR2_ADDR[9] +set_location_assignment PIN_T19 -to DDR2_ADDR[8] +set_location_assignment PIN_Y14 -to DDR2_ADDR[7] +set_location_assignment PIN_W14 -to DDR2_ADDR[6] +set_location_assignment PIN_T20 -to DDR2_ADDR[5] +set_location_assignment PIN_Y15 -to DDR2_ADDR[4] +set_location_assignment PIN_L22 -to DDR2_ADDR[3] +set_location_assignment PIN_Y17 -to DDR2_ADDR[2] +set_location_assignment PIN_L21 -to DDR2_ADDR[1] +set_location_assignment PIN_AB10 -to DDR2_ADDR[0] +set_location_assignment PIN_Y6 -to DDR2_BA[2] +set_location_assignment PIN_AB17 -to DDR2_BA[1] +set_location_assignment PIN_K21 -to DDR2_BA[0] +set_location_assignment PIN_J18 -to DDR2_CAS +set_location_assignment PIN_Y4 -to DDR2_CKE[0] +set_location_assignment PIN_AB5 -to DDR2_CKE[1] +set_location_assignment PIN_AA19 -to DDR2_CS[0] +set_location_assignment PIN_E21 -to DDR2_CS[1] + +set_location_assignment PIN_F20 -to DDR2_DM[7] +set_location_assignment PIN_F22 -to DDR2_DM[6] +set_location_assignment PIN_P22 -to DDR2_DM[5] +set_location_assignment PIN_V22 -to DDR2_DM[4] +set_location_assignment PIN_W15 -to DDR2_DM[3] +set_location_assignment PIN_AA14 -to DDR2_DM[2] +set_location_assignment PIN_AA8 -to DDR2_DM[1] +set_location_assignment PIN_AA5 -to DDR2_DM[0] + +set_location_assignment PIN_B21 -to DDR2_DQ[63] +set_location_assignment PIN_B22 -to DDR2_DQ[62] +set_location_assignment PIN_C21 -to DDR2_DQ[61] +set_location_assignment PIN_C22 -to DDR2_DQ[60] +set_location_assignment PIN_D22 -to DDR2_DQ[59] +set_location_assignment PIN_F19 -to DDR2_DQ[58] +set_location_assignment PIN_F17 -to DDR2_DQ[57] +set_location_assignment PIN_G18 -to DDR2_DQ[56] +set_location_assignment PIN_E22 -to DDR2_DQ[55] +set_location_assignment PIN_F21 -to DDR2_DQ[54] +set_location_assignment PIN_H21 -to DDR2_DQ[53] +set_location_assignment PIN_H22 -to DDR2_DQ[52] +set_location_assignment PIN_H19 -to DDR2_DQ[51] +set_location_assignment PIN_H20 -to DDR2_DQ[50] +set_location_assignment PIN_K18 -to DDR2_DQ[49] +set_location_assignment PIN_J21 -to DDR2_DQ[48] +set_location_assignment PIN_M22 -to DDR2_DQ[47] +set_location_assignment PIN_M21 -to DDR2_DQ[46] +set_location_assignment PIN_R22 -to DDR2_DQ[45] +set_location_assignment PIN_R21 -to DDR2_DQ[44] +set_location_assignment PIN_M20 -to DDR2_DQ[43] +set_location_assignment PIN_N20 -to DDR2_DQ[42] +set_location_assignment PIN_P21 -to DDR2_DQ[41] +set_location_assignment PIN_R19 -to DDR2_DQ[40] +set_location_assignment PIN_U22 -to DDR2_DQ[39] +set_location_assignment PIN_U21 -to DDR2_DQ[38] +set_location_assignment PIN_V21 -to DDR2_DQ[37] +set_location_assignment PIN_W22 -to DDR2_DQ[36] +set_location_assignment PIN_R20 -to DDR2_DQ[35] +set_location_assignment PIN_U20 -to DDR2_DQ[34] +set_location_assignment PIN_Y22 -to DDR2_DQ[33] +set_location_assignment PIN_AA21 -to DDR2_DQ[32] +set_location_assignment PIN_AB20 -to DDR2_DQ[31] +set_location_assignment PIN_AB18 -to DDR2_DQ[30] +set_location_assignment PIN_AA16 -to DDR2_DQ[29] +set_location_assignment PIN_AB16 -to DDR2_DQ[28] +set_location_assignment PIN_W17 -to DDR2_DQ[27] +set_location_assignment PIN_V15 -to DDR2_DQ[26] +set_location_assignment PIN_T15 -to DDR2_DQ[25] +set_location_assignment PIN_V14 -to DDR2_DQ[24] +set_location_assignment PIN_AA15 -to DDR2_DQ[23] +set_location_assignment PIN_AB15 -to DDR2_DQ[22] +set_location_assignment PIN_AB14 -to DDR2_DQ[21] +set_location_assignment PIN_AA13 -to DDR2_DQ[20] +set_location_assignment PIN_W13 -to DDR2_DQ[19] +set_location_assignment PIN_U12 -to DDR2_DQ[18] +set_location_assignment PIN_AB13 -to DDR2_DQ[17] +set_location_assignment PIN_AA10 -to DDR2_DQ[16] +set_location_assignment PIN_AA9 -to DDR2_DQ[15] +set_location_assignment PIN_AB8 -to DDR2_DQ[14] +set_location_assignment PIN_AB7 -to DDR2_DQ[13] +set_location_assignment PIN_AA7 -to DDR2_DQ[12] +set_location_assignment PIN_V11 -to DDR2_DQ[11] +set_location_assignment PIN_Y10 -to DDR2_DQ[10] +set_location_assignment PIN_U10 -to DDR2_DQ[9] +set_location_assignment PIN_Y8 -to DDR2_DQ[8] +set_location_assignment PIN_W8 -to DDR2_DQ[7] +set_location_assignment PIN_V5 -to DDR2_DQ[6] +set_location_assignment PIN_AA4 -to DDR2_DQ[5] +set_location_assignment PIN_Y3 -to DDR2_DQ[4] +set_location_assignment PIN_U9 -to DDR2_DQ[3] +set_location_assignment PIN_W7 -to DDR2_DQ[2] +set_location_assignment PIN_Y7 -to DDR2_DQ[1] +set_location_assignment PIN_W6 -to DDR2_DQ[0] + +set_location_assignment PIN_C20 -to DDR2_DQS[7] +set_location_assignment PIN_J22 -to DDR2_DQS[6] +set_location_assignment PIN_N18 -to DDR2_DQS[5] +set_location_assignment PIN_W20 -to DDR2_DQS[4] +set_location_assignment PIN_V13 -to DDR2_DQS[3] +set_location_assignment PIN_Y13 -to DDR2_DQS[2] +set_location_assignment PIN_AB9 -to DDR2_DQS[1] +set_location_assignment PIN_V10 -to DDR2_DQS[0] + +set_location_assignment PIN_AB19 -to DDR2_ODT[0] +set_location_assignment PIN_D21 -to DDR2_ODT[1] +set_location_assignment PIN_AA17 -to DDR2_RAS +set_location_assignment PIN_J20 -to DDR2_WE + #============================================================ # Modules and Files #============================================================ @@ -164,4 +278,10 @@ set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3 + +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/build/E115_zpu_Toplevel.vhd b/build/E115_zpu_Toplevel.vhd index f958502..9a452a5 100644 --- a/build/E115_zpu_Toplevel.vhd +++ b/build/E115_zpu_Toplevel.vhd @@ -33,18 +33,21 @@ entity E115_zpu is UART_RX_0 : in std_logic; UART_TX_0 : out std_logic; UART_RX_1 : in std_logic; - UART_TX_1 : out std_logic + UART_TX_1 : out std_logic; --- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz --- SDRAM_CKE : out std_logic; -- clock enable. --- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus --- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus --- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks --- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks --- SDRAM_CS : out std_logic; -- a single chip select --- SDRAM_WE : out std_logic; -- write enable --- SDRAM_RAS : out std_logic; -- row address select --- SDRAM_CAS : out std_logic -- columns address select + -- DDR2 DRAM + DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus + DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus + DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus + DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks + DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus + DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks + DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects. + DDR2_WE : out std_logic; -- write enable + DDR2_RAS : out std_logic; -- row address select + DDR2_CAS : out std_logic; -- columns address select + DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable. + DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks. ); END entity; @@ -142,7 +145,7 @@ port map IOCTL_DOUT => open, -- Data to be written into FPGA. IOCTL_DIN => (others => '0'), -- Data to be read into HPS. - -- SDRAM signals + -- SDRAM signals which do not exist on the E115 SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz SDRAM_CKE => open, --SDRAM_CKE, -- clock enable. SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus @@ -153,7 +156,21 @@ port map SDRAM_WE_n => open, --SDRAM_WE, -- write enable SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select - SDRAM_READY => open -- sd ready. + SDRAM_READY => open, -- sd ready. + + -- DDR2 DRAM + DDR2_ADDR => DDR2_ADDR, -- 14 bit multiplexed address bus + DDR2_DQ => DDR2_DQ, -- 64 bit bidirectional data bus + DDR2_DQS => DDR2_DQS, -- 8 bit bidirectional data bus + DDR2_DQM => DDR2_DQM, -- eight byte masks + DDR2_ODT => DDR2_ODT, -- 14 bit multiplexed address bus + DDR2_BA => DDR2_BA, -- 8 banks + DDR2_CS => DDR2_CS, -- 2 chip selects. + DDR2_WE => DDR2_WE, -- write enable + DDR2_RAS => DDR2_RAS, -- row address select + DDR2_CAS => DDR2_CAS, -- columns address select + DDR2_CKE => DDR2_CKE, -- 2 clock enable. + DDR2_CLK => DDR2_CLK -- 2 clocks. ); diff --git a/build/E115_zpu_assignment_defaults.qdf b/build/E115_zpu_assignment_defaults.qdf index 003e95f..9844afc 100644 --- a/build/E115_zpu_assignment_defaults.qdf +++ b/build/E115_zpu_assignment_defaults.qdf @@ -367,7 +367,7 @@ set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as re set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" set_global_assignment -name ENABLE_CONFIGURATION_PINS On set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off -set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_NCE_PIN On set_global_assignment -name ENABLE_BOOT_SEL_PIN On set_global_assignment -name CRC_ERROR_CHECKING Off set_global_assignment -name INTERNAL_SCRUBBING Off diff --git a/build/QMV_zpu.qsf b/build/QMV_zpu.qsf index 72353ed..0372366 100644 --- a/build/QMV_zpu.qsf +++ b/build/QMV_zpu.qsf @@ -342,8 +342,8 @@ set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd -#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/sdram.qip -set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/sdram.vhd +set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/sdram.qip +#set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/sdram.vhd set_global_assignment -name VHDL_FILE ../devices/WishBone/SRAM/sram.vhd set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" @@ -359,4 +359,7 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati + + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/build/QMV_zpu_Toplevel.vhd b/build/QMV_zpu_Toplevel.vhd index dc8b262..2ec50d8 100644 --- a/build/QMV_zpu_Toplevel.vhd +++ b/build/QMV_zpu_Toplevel.vhd @@ -79,6 +79,7 @@ LEDR <= '0'; mypll : entity work.Clock_50to100 port map ( + areset => not KEY, inclk0 => CLOCK_50, c0 => sysclk, c1 => memclk, @@ -153,7 +154,22 @@ port map SDRAM_WE_n => SDRAM_WE, -- write enable SDRAM_RAS_n => SDRAM_RAS, -- row address select SDRAM_CAS_n => SDRAM_CAS, -- columns address select - SDRAM_READY => open -- sd ready. + SDRAM_READY => open, -- sd ready. + + -- DDR2 DRAM - doesnt exist on the QMV. + DDR2_ADDR => open, -- 14 bit multiplexed address bus + DDR2_DQ => open, -- 64 bit bidirectional data bus + DDR2_DQS => open, -- 8 bit bidirectional data bus + DDR2_DQM => open, -- eight byte masks + DDR2_ODT => open, -- 14 bit multiplexed address bus + DDR2_BA => open, -- 8 banks + DDR2_CS => open, -- 2 chip selects. + DDR2_WE => open, -- write enable + DDR2_RAS => open, -- row address select + DDR2_CAS => open, -- columns address select + DDR2_CKE => open, -- 2 clock enable. + DDR2_CLK => open -- 2 clocks. + ); diff --git a/build/QMV_zpu_constraints.sdc b/build/QMV_zpu_constraints.sdc index c5b13d6..915872d 100644 --- a/build/QMV_zpu_constraints.sdc +++ b/build/QMV_zpu_constraints.sdc @@ -29,7 +29,6 @@ #************************************************************** # Time Information #************************************************************** - set_time_format -unit ns -decimal_places 3 @@ -37,7 +36,6 @@ set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** - create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}] @@ -47,9 +45,9 @@ create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports #create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -multiply_by 2 -divide_by 1 -master_clock {clk_50} [get_nets {mypll|altpll_component|_clk0}] #create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -multiply_by 4 -divide_by 1 -master_clock {clk_50} [get_nets {mypll|altpll_component|_clk1}] -create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 16 -divide_by 2 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]}] +create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 12 -divide_by 2 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]}] create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] +#create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] #************************************************************** # Set Clock Latency @@ -61,31 +59,15 @@ create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll2 # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -#derive_clock_uncertainty +derive_clock_uncertainty +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060 +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060 #************************************************************** @@ -115,7 +97,7 @@ set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_genera #************************************************************** set_false_path -from [get_keepers {KEY*}] -set_false_path -from [get_keepers {SW*}] +#set_false_path -from [get_keepers {SW*}] #************************************************************** diff --git a/devices/WishBone/SDRAM/sdram.qip b/devices/WishBone/SDRAM/sdram.qip new file mode 100644 index 0000000..a0e34f0 --- /dev/null +++ b/devices/WishBone/SDRAM/sdram.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ] diff --git a/devices/WishBone/SDRAM/sdram.sdc b/devices/WishBone/SDRAM/sdram.sdc new file mode 100644 index 0000000..73d4248 --- /dev/null +++ b/devices/WishBone/SDRAM/sdram.sdc @@ -0,0 +1,19 @@ +derive_pll_clocks + +#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -source [get_pins -compatibility_mode {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \ + -name SDRAM_CLK [get_ports {SDRAM_CLK}] + +derive_clock_uncertainty + +# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) +set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] +set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] + +# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ + -to [get_clocks {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \ + -setup 2 + +set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] +set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] diff --git a/zpu_soc.vhd b/zpu_soc.vhd index bcbef3d..d452fa7 100644 --- a/zpu_soc.vhd +++ b/zpu_soc.vhd @@ -104,7 +104,21 @@ entity zpu_soc is SDRAM_WE_n : out std_logic; -- write enable SDRAM_RAS_n : out std_logic; -- row address select SDRAM_CAS_n : out std_logic; -- columns address select - SDRAM_READY : out std_logic -- sd ready. + SDRAM_READY : out std_logic; -- sd ready. + + -- DDR2 DRAM + DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus + DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus + DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus + DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks + DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus + DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks + DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects. + DDR2_WE : out std_logic; -- write enable + DDR2_RAS : out std_logic; -- row address select + DDR2_CAS : out std_logic; -- columns address select + DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable. + DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks. ); end entity;