# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ledwater_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58  SEPTEMBER 01, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
#set_global_assignment -name VERILOG_FILE ledwater.v
set_global_assignment -name CDF_FILE E115.cdf

# Pin & Location Assignments
# ==========================

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY ReVerSE_U16

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP4CE22E22C7
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

# Assembler Assignments
# =====================

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH


#============================================================
# UART
#============================================================
set_location_assignment PIN_72 -to UART_RX_0
set_location_assignment PIN_71 -to UART_TX_0
#set_location_assignment PIN_C6 -to UART_RX_1
#set_location_assignment PIN_D7 -to UART_TX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1

#============================================================
# SD CARD
#============================================================
#set_location_assignment PIN_C8 -to SDCARD_MISO[0]
#set_location_assignment PIN_C7 -to SDCARD_MOSI[0]
#set_location_assignment PIN_B8 -to SDCARD_CLK[0]
#set_location_assignment PIN_A8 -to SDCARD_CS[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]

#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_25 -to REVERSEU16_CLOCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to REVERSEU16_CLOCK
#set_location_assignment PIN_AB11 -to clk_25M

#============================================================
# LED
#============================================================
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
#set_location_assignment PIN_A5 -to LED[0]
#set_location_assignment PIN_B5 -to LED[1]
#set_location_assignment PIN_C4 -to LED[2]
#set_location_assignment PIN_C3 -to LED[3]


set_location_assignment PIN_32 -to reset_button
set_location_assignment PIN_98 -to SDRAM_ADDR[0]
set_location_assignment PIN_86 -to SDRAM_ADDR[1]
set_location_assignment PIN_87 -to SDRAM_ADDR[2]
set_location_assignment PIN_105 -to SDRAM_ADDR[3]
set_location_assignment PIN_76 -to SDRAM_ADDR[4]
set_location_assignment PIN_77 -to SDRAM_ADDR[5]
set_location_assignment PIN_80 -to SDRAM_ADDR[6]
set_location_assignment PIN_83 -to SDRAM_ADDR[7]
set_location_assignment PIN_85 -to SDRAM_ADDR[8]
set_location_assignment PIN_67 -to SDRAM_ADDR[9]
set_location_assignment PIN_99 -to SDRAM_ADDR[10]
set_location_assignment PIN_69 -to SDRAM_ADDR[11]
set_location_assignment PIN_68 -to SDRAM_ADDR[12]
set_location_assignment PIN_101 -to SDRAM_BA[0]
set_location_assignment PIN_100 -to SDRAM_BA[1]
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_119 -to SDRAM_DQM[0]
set_location_assignment PIN_66 -to SDRAM_DQM[1]
set_location_assignment PIN_142 -to SDRAM_DQ[0]
set_location_assignment PIN_141 -to SDRAM_DQ[1]
set_location_assignment PIN_137 -to SDRAM_DQ[2]
set_location_assignment PIN_136 -to SDRAM_DQ[3]
set_location_assignment PIN_135 -to SDRAM_DQ[4]
set_location_assignment PIN_125 -to SDRAM_DQ[5]
set_location_assignment PIN_121 -to SDRAM_DQ[6]
set_location_assignment PIN_120 -to SDRAM_DQ[7]
set_location_assignment PIN_65 -to SDRAM_DQ[8]
set_location_assignment PIN_64 -to SDRAM_DQ[9]
set_location_assignment PIN_60 -to SDRAM_DQ[10]
set_location_assignment PIN_46 -to SDRAM_DQ[11]
set_location_assignment PIN_44 -to SDRAM_DQ[12]
set_location_assignment PIN_59 -to SDRAM_DQ[13]
set_location_assignment PIN_42 -to SDRAM_DQ[14]
set_location_assignment PIN_58 -to SDRAM_DQ[15]
set_location_assignment PIN_106 -to SDRAM_nCAS
set_location_assignment PIN_103 -to SDRAM_nRAS
set_location_assignment PIN_104 -to SDRAM_nWE

#============================================================
# Modules and Files
#============================================================

set_global_assignment -name VHDL_FILE ../ReVerSE_U16_Toplevel.vhd
set_global_assignment -name QIP_FILE Clock_25to100.qip
set_global_assignment -name SDC_FILE ReVerSE_U16_constraints.sdc
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/sdram.qip
#set_global_assignment -name VHDL_FILE ../devices/sysbus/SDRAM/sdram.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3

set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
