345 lines
16 KiB
NASM
345 lines
16 KiB
NASM
;--------------------------------------------------------------------------------------------------------
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;-
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;- Name: tzfs_bank4.asm
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;- Created: July 2019
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;- Author(s): Philip Smart
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;- Description: Sharp MZ series tzfs (tranZPUter Filing System).
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;- Bank 4 - F000:FFFF -
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;-
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;- This assembly language program is a branch from the original RFS written for the
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;- MZ80A_RFS upgrade board. It is adapted to work within the similar yet different
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;- environment of the tranZPUter SW which has a large RAM capacity (512K) and an
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;- I/O processor in the K64F/ZPU.
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;-
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;- Credits:
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;- Copyright: (c) 2018-2020 Philip Smart <philip.smart@net2net.org>
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;-
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;- History: May 2020 - Branch taken from RFS v2.0 and adapted for the tranZPUter SW.
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;- Dec 2020 - Updates to accommodate v1.3 of the tranZPUter SW-700 board where soft
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;- CPU's now become possible.
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;-
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;--------------------------------------------------------------------------------------------------------
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;- This source file is free software: you can redistribute it and-or modify
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;- it under the terms of the GNU General Public License as published
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;- by the Free Software Foundation, either version 3 of the License, or
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;- (at your option) any later version.
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;-
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;- This source file is distributed in the hope that it will be useful,
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;- but WITHOUT ANY WARRANTY; without even the implied warranty of
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;- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;- GNU General Public License for more details.
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;-
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;- You should have received a copy of the GNU General Public License
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;- along with this program. If not, see <http://www.gnu.org/licenses/>.
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;--------------------------------------------------------------------------------------------------------
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;============================================================
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;
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; TZFS BANK 4 - TZFS commands
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;
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;============================================================
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ORG BANKRAMADDR
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;-------------------------------------------------------------------------------
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; START OF ADDITIONAL TZFS COMMANDS
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;-------------------------------------------------------------------------------
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; Method to set the video mode.
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; Param: 0 - Enable FPGA and set to MZ-80K mode.
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; 1 - Enable FPGA and set to MZ-80C mode.
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; 2 - Enable FPGA and set to MZ-1200 mode.
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; 3 - Enable FPGA and set to MZ-80A mode (base mode on MZ-80A hardware).
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; 4 - Enable FPGA and set to MZ-700 mode (base mode on MZ-700 hardware).
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; 5 - Enable FPGA and set to MZ-1500 mode.
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; 6 - Enable FPGA and set to MZ-800 mode.
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; 7 - Enable FPGA and set to MZ-80B mode.
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; 8 - Enable FPGA and set to MZ-2000 mode.
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; 9 - Enable FPGA and set to MZ-2200 mode.
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; 10 - Enable FPGA and set to MZ-2500 mode.
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; O - Turn off FPGA Video, turn on mainboard video.
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SETVMODE: IN A,(CPLDINFO) ; Get configuration of hardware.
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BIT 3,A
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JP Z,NOFPGAERR ; No hardware so cannot change mode.
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PUSH DE ; Preserve DE in case no number given.
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POP BC
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CALL ConvertStringToNumber ; Convert the input into 0 (disable) or frequency in KHz.
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JR NZ,SETVMODEOFF
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LD A,H
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CP 0
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JP NZ,BADNUMERR ; Check that the given mode is in range 0 - 7.
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LD A,L
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CP 10
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JP NC,BADNUMERR
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;
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SETVMODE0: IN A,(CPLDCFG)
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OR MODE_VIDEO_FPGA ; Set the tranZPUter CPLD hardware to enable the FPGA video mode.
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OUT (CPLDCFG),A
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;
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IN A,(VMCTRL) ; Get current setting.
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AND 0F0H ; Clear old mode setting.
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OR L ; Add in new setting.
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OUT (VMCTRL),A
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RLC L ; Shift mode to position for SCRNMODE storage.
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RLC L
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RLC L
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RLC L
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LD A,(SCRNMODE) ; Repeat for the screen mode variable, used when resetting or changing display settings.
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AND 007H ; Clear video mode setting.
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OR L ; Add in new setting.
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SET 2, A ; Set flag to indicate video mode override - ie, dont use base machine mode.
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SETVMODECLR:SET 1, A ; Ensure flag set so on restart the FPGA video mode is selected.
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LD (SCRNMODE),A
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LD A, 016H ; Clear the screen so we start from a known position.
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CALL PRNT
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LD A,071H ; Blue background and white characters.
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LD HL,ARAM
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CALL CLR8
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RET
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SETVMODEOFF:LD A,(DE)
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CP 'O'
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JR Z,SETVMODE1
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CP 'o'
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JP NZ,BADNUMERR
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SETVMODE1: LD A,(SCRNMODE) ; Disable flag to enable FPGA on restart.
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RES 1,A
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LD (SCRNMODE),A
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IN A,(CPLDCFG)
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AND ~MODE_VIDEO_FPGA ; Set the tranZPUter CPLD hardware to disable the FPGA video mode.
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OUT (CPLDCFG),A
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RET
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; Method to set the VGA output mode of the external display.
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SETVGAMODE: IN A,(CPLDINFO) ; Get configuration of hardware.
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BIT 3,A
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JP Z,NOFPGAERR ; No hardware so cannot change mode.
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CALL ConvertStringToNumber ; Convert the input into 0-3, 0 = off, 1 = 640x480, 2=1024x768, 3=800x600.
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JP NZ,BADNUMERR
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LD A,H
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CP 0
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JP NZ,BADNUMERR ; Check that the given mode is in range 0 - 15.
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LD A,L
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CP 15
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JP NC,BADNUMERR
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;
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;RRC L
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;RRC L ; Value to top 2 bits ready to be applied to VGA mode register.
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;
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SETVGAMODE1:IN A,(CPLDCFG)
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OR MODE_VIDEO_FPGA ; Set the tranZPUter CPLD hardware to enable the FPGA video mode.
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OUT (CPLDCFG),A
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;
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LD A, L ; Add in new setting.
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OUT (VMVGAMODE),A
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LD (SCRNMODE2), A
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JP SETVMODECLR
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; Method to set the VGA border colour on the external display.
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SETVBORDER: IN A,(CPLDINFO) ; Get configuration of hardware.
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BIT 3,A
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JP Z,NOFPGAERR ; No hardware so cannot change mode.
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CALL ConvertStringToNumber ; Convert the input into 0 - 7, bit 2 = Red, 1 = Green, 0 = Blue.
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JP NZ,BADNUMERR
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LD A,H
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CP 0
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JP NZ,BADNUMERR ; Check that the given mode is in range 0 - 7.
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LD A,L
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CP 7
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JP NC,BADNUMERR
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;
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IN A,(CPLDCFG)
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OR MODE_VIDEO_FPGA ; Set the tranZPUter CPLD hardware to enable the FPGA video mode.
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OUT (CPLDCFG),A
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;
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LD A,L
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OUT (VMVGATTR),A
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RET
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; Method to enable/disable the alternate CPU frequency and change it's values.
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;
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SETFREQ: CALL ConvertStringToNumber ; Convert the input into 0 (disable) or frequency in KHz.
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JP NZ,BADNUMERR
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LD (TZSVC_CPU_FREQ),HL ; Set the required frequency in the service structure.
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LD A,H
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CP L
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JR NZ,SETFREQ1
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LD A, TZSVC_CMD_CPU_BASEFREQ ; Switch to the base frequency.
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JR SETFREQ2
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SETFREQ1: LD A, TZSVC_CMD_CPU_ALTFREQ ; Switch to the alternate frequency.
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SETFREQ2: CALL SVC_CMD
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OR A
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JP NZ,SETFREQERR
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LD A,H
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CP L
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RET Z ; If we are disabling the alternate cpu frequency (ie. = 0) exit.
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LD A, TZSVC_CMD_CPU_CHGFREQ ; Switch to the base frequency.
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CALL SVC_CMD
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OR A
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JP NZ,SETFREQERR
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RET
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; Method to configure the hardware to use the T80 CPU instantiated in the FPGA.
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;
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SETT80: IN A,(CPUINFO)
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LD C,A
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AND CPUMODE_IS_SOFT_MASK
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CP CPUMODE_IS_SOFT_AVAIL
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JP NZ,SOFTCPUERR
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LD A,C
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AND CPUMODE_IS_T80
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JP Z,NOT80ERR
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;LD L,VMMODE_VGA_640x480 ; Enable VGA mode for a better display.
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;CALL SETVGAMODE1
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LD A, TZSVC_CMD_CPU_SETT80 ; We need to ask the K64F to switch to the T80 as it may involve loading of ROMS.
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CALL SVC_CMD
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OR A
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JP NZ,SETT80ERR
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RET
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; Method to configure the hardware to use the original Z80 CPU installed on the tranZPUter board.
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;
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SETZ80: IN A,(CPUINFO)
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AND CPUMODE_IS_SOFT_MASK
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CP CPUMODE_IS_SOFT_AVAIL
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JP NZ,SOFTCPUERR
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CALL SETVMODE1 ; Turn off VGA mode, return to default MZ video.
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LD A, TZSVC_CMD_CPU_SETZ80
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CALL SVC_CMD
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OR A
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JP NZ,SETZ80ERR
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RET
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; Method to configure the hardware to use the ZPU Evolution CPU instantiated in the FPGA.
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;
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SETZPUEVO: IN A,(CPUINFO)
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LD C,A
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AND CPUMODE_IS_SOFT_MASK
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CP CPUMODE_IS_SOFT_AVAIL
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JP NZ,SOFTCPUERR
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LD A,C
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AND CPUMODE_IS_ZPU_EVO
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JP Z,NOZPUERR
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LD L,VMMODE_VGA_640x480 ; Enable VGA mode for a better display.
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CALL SETVGAMODE1
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LD A, TZSVC_CMD_CPU_SETZPUEVO ; We need to ask the K64F to switch to the ZPU Evo as it may involve loading of ROMS.
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CALL SVC_CMD
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OR A
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JP NZ,SETZPUERR
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HALT ; ZPU will take over so stop the Z80 from further processing.
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;----------------------------------------------
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; Hardware Emulation Mode Activation Routines.
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;----------------------------------------------
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SETMZ80K: LD D, TZSVC_CMD_EMU_SETMZ80K ; We need to ask the K64F to switch to the Sharp MZ80K emulation as it involves loading ROMS.
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JR SETEMUMZ
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SETMZ80C: LD D, TZSVC_CMD_EMU_SETMZ80C
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JR SETEMUMZ
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SETMZ1200: LD D, TZSVC_CMD_EMU_SETMZ1200
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JR SETEMUMZ
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SETMZ80A: LD D, TZSVC_CMD_EMU_SETMZ80A
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JR SETEMUMZ
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SETMZ700: LD D, TZSVC_CMD_EMU_SETMZ700
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JR SETEMUMZ
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SETMZ1500: LD D, TZSVC_CMD_EMU_SETMZ1500
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JR SETEMUMZ
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SETMZ800: LD D, TZSVC_CMD_EMU_SETMZ800
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JR SETEMUMZ
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SETMZ80B: LD D, TZSVC_CMD_EMU_SETMZ80B
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JR SETEMUMZ
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SETMZ2000: LD D, TZSVC_CMD_EMU_SETMZ2000
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JR SETEMUMZ
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SETMZ2200: LD D, TZSVC_CMD_EMU_SETMZ2200
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JR SETEMUMZ
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SETMZ2500: LD D, TZSVC_CMD_EMU_SETMZ2500
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JR SETEMUMZ
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;
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; General function to determine if the emulator MZ hardware is present and activate it. Activation requires making a request to the
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; I/O processor as it needs to load up the correct BIOS etc prior to activating the emulation.
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;
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SETEMUMZ: IN A,(CPUINFO) ; Verify that the FPGA has emuMZ capabilities.
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LD C,A
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AND CPUMODE_IS_SOFT_MASK
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CP CPUMODE_IS_SOFT_AVAIL
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JR NZ,SOFTCPUERR
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LD A,C
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AND CPUMODE_IS_EMU_MZ
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JR Z,NOEMUERR
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LD L,VMMODE_VGA_640x480 ; Enable VGA mode for a better display.
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CALL SETVGAMODE1
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;
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PUSH DE ; Setup the initial video mode based on the required emulation.
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LD A,D
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SUB TZSVC_CMD_EMU_SETMZ80K
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LD L,A
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LD H,0
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CALL SETVMODE0
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POP DE
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;
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LD A, D ; Load up the required emulation mode.
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CALL SVC_CMD
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OR A
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JR NZ,SETT80ERR
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HALT
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; Simple routine to clear screen or attributes.
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CLR8: LD BC,00800H
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PUSH DE
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LD D,A
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CLR8_1: LD (HL),D
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INC HL
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DEC BC
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LD A,B
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OR C
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JR NZ,CLR8_1
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POP DE
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RET
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;
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; Message addresses are in Bank2.
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;
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NOFPGAERR: LD DE,MSGNOFPGA
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JR BADNUM2
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SETFREQERR: LD DE,MSGFREQERR
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JR BADNUM2
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SETT80ERR: LD DE,MSGT80ERR
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JR BADNUM2
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SETZ80ERR: LD DE,MSGZ80ERR
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JR BADNUM2
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SETZPUERR: LD DE,MSGZPUERR
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JR BADNUM2
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SOFTCPUERR: LD DE,MSGNOSOFTCPU
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JR BADNUM2
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NOT80ERR: LD DE,MSGNOT80CPU
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JR BADNUM2
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NOZPUERR: LD DE,MSGNOZPUCPU
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JR BADNUM2
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NOEMUERR: LD DE,MSGNOEMU
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JR BADNUM2
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BADNUMERR: LD DE,MSGBADNUM
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BADNUM2: CALL ?PRINTMSG
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RET
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;-------------------------------------------------------------------------------
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; END OF ADDITIONAL TZFS COMMANDS
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;-------------------------------------------------------------------------------
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; The FDC controller uses it's busy/wait signal as a ROM address line input, this
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; causes a jump in the code dependent on the signal status. It gets around the 2MHz Z80 not being quick
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; enough to process the signal by polling.
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ALIGN_NOPS FDCJMP1
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ORG FDCJMP1
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FDCJMPL4: JP (IX)
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; The FDC controller uses it's busy/wait signal as a ROM address line input, this
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; causes a jump in the code dependent on the signal status. It gets around the 2MHz Z80 not being quick
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; enough to process the signal by polling.
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ALIGN_NOPS FDCJMP2
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ORG FDCJMP2
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FDCJMPH4: JP (IY)
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; Ensure we fill the entire 4K by padding with FF's.
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;
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ALIGN_NOPS 10000H
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