b32c9615e4
Proposal to restructure all the files and folders to keep things organized and similar to other cores.
196 lines
8.4 KiB
VHDL
196 lines
8.4 KiB
VHDL
--
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-- sysctrl.vhd
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--
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-- SHARP MZ-80B/2000 series compatible logic, system control module
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-- for Altera DE0
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--
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-- Nibbles Lab. 2014
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity sysctrl is
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port(
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RST_n : in std_logic; -- Reset
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CLK : in std_logic; -- System Clock
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-- Push Button
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BUTTON : in std_logic_vector(2 downto 0); -- Pushbutton[2:0]
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-- Switch
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SW : in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
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-- PS/2 Keyboard Data
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KBEN : in std_logic; -- PS/2 Keyboard Data Valid
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KBDT : in std_logic_vector(7 downto 0); -- PS/2 Keyboard Data
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-- Interrupt
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INTL : out std_logic; -- Interrupt Signal Output
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I_CMT : in std_logic; -- from CMT
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I_FDD : in std_logic; -- from FD unit
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-- Others
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URST_n : out std_logic; -- Universal Reset
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ARST_n : out std_logic; -- All Reset
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ZRST : out std_logic; -- Z80 Reset
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CLK50 : in std_logic; -- 50MkHz
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SCLK : in std_logic; -- 31.25kHz
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ZBREQ : out std_logic; -- Z80 Bus Request
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ZBACK : in std_logic; -- Z80 Bus Acknowridge
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BST_n : in std_logic; -- BOOT start request from Z80
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BOOTM : out std_logic; -- BOOT mode
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F_BTN : out std_logic -- Function Button
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-- HPS Interface
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IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
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IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
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IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
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IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
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IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
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IOCTL_DOUT : in std_logic_vector(15 downto 0) -- HPS Data to be written into FPGA.
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IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
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IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
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);
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end sysctrl;
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architecture rtl of sysctrl is
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--
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-- Reset & Filters
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--
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signal URSTi : std_logic; -- Universal Reset
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signal BUF : std_logic_vector(7 downto 0) := "00000000";
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signal CNT5 : std_logic_vector(4 downto 0);
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signal SR_BTN : std_logic_vector(7 downto 0);
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signal ZR_BTN : std_logic_vector(7 downto 0);
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signal F_BTNi : std_logic;
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--
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-- Interrupt
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--
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signal IRQ_KB : std_logic;
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signal IE_KB : std_logic;
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signal IKBBUF : std_logic_vector(2 downto 0);
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signal IRQ_FB : std_logic;
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signal IE_FB : std_logic;
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signal IFBBUF : std_logic_vector(2 downto 0);
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signal IRQ_CT : std_logic;
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signal IE_CT : std_logic;
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signal ICTBUF : std_logic_vector(2 downto 0);
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signal IRQ_FD : std_logic;
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signal IE_FD : std_logic;
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signal IFDBUF : std_logic_vector(2 downto 0);
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--
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-- Control for Z80
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--
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signal ZRSTi : std_logic;
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signal BOOTMi : std_logic := '1';
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begin
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--
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-- Avalon Bus
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--
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process( RST_n, CLK ) begin
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if RST_n='0' then
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IRQ_KB <= '0';
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IRQ_FB <= '0';
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IRQ_CT <= '0';
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IRQ_FD <= '0';
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IKBBUF <= (others=>'0');
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IFBBUF <= (others=>'0');
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ICTBUF <= (others=>'0');
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IFDBUF <= (others=>'0');
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IE_KB <= '0';
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IE_FB <= '0';
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IE_CT <= '0';
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IE_FD <= '0';
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ZBREQ <= '1';
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BOOTMi <= '1';
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ZRSTi <= '0';
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elsif CLK'event and CLK='1' then
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-- Edge Sense
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IKBBUF<=IKBBUF(1 downto 0)&(KBEN and ((not ZBACK) or BOOTMi));
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if IKBBUF(2 downto 1)="01" then
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IRQ_KB <= IE_KB;
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end if;
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IFBBUF <= IFBBUF(1 downto 0)&F_BTNi;
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if IFBBUF(2 downto 1)="01" then
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IRQ_FB <= IE_FB;
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end if;
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ICTBUF <= ICTBUF(1 downto 0)&I_CMT;
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if ICTBUF(2 downto 1)="01" then
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IRQ_CT <= IE_CT;
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end if;
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IFDBUF <= IFDBUF(1 downto 0)&I_FDD;
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if IFDBUF(2 downto 1)="01" then
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IRQ_FD <= IE_FD;
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end if;
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-- Register
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if IOCTL_RD='1' and IOCTL_WR='1' then
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if IOCTL_ADDR=X"0005" then -- MZ_SYS_IREQ
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IRQ_KB <= IRQ_KB and (not IOCTL_DOUT(0)); -- I_KBD 0x01
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IRQ_FB <= IRQ_FB and (not IOCTL_DOUT(1)); -- I_FBTN 0x02
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IRQ_CT <= IRQ_CT and (not IOCTL_DOUT(2)); -- I_CMT 0x04
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IRQ_FD <= IRQ_FD and (not IOCTL_DOUT(3)); -- I_FDD 0x08
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end if;
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if IOCTL_ADDR=X"0006" then -- MZ_SYS_IENB
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IE_KB <= IOCTL_DOUT(0); -- I_KBD 0x01
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IE_FB <= IOCTL_DOUT(1); -- I_FBTN 0x02
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IE_CT <= IOCTL_DOUT(2); -- I_CMT 0x04
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IE_FD <= IOCTL_DOUT(3); -- I_FDD 0x08
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end if;
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if IOCTL_ADDR=X"0007" then -- MZ_SYS_CTRL (Control for Z80)
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ZBREQ <= IOCTL_DOUT(0);
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ZRSTi <= IOCTL_DOUT(1);
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BOOTMi <= IOCTL_DOUT(2);
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end if;
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end if;
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end if;
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end process;
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IOCTL_DIN <= "00000"&BUTTON when IOCTL_RD='1' and IOCTL_ADDR=X"0000" else -- MZ_SYS_BUTTON
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SW(7 downto 0) when IOCTL_RD='1' and IOCTL_ADDR=X"0002" else -- MZ_SYS_SW70
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"000000"&SW(9)&SW(8) when IOCTL_RD='1' and IOCTL_ADDR=X"0003" else -- MZ_SYS_SW98
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KBDT when IOCTL_RD='1' and IOCTL_ADDR=X"0004" else -- MZ_SYS_KBDT
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"0000"&IRQ_FD&IRQ_CT&IRQ_FB&IRQ_KB when IOCTL_RD='1' and IOCTL_ADDR=X"0005" else -- MZ_SYS_IREQ
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"0000"&IE_FD&IE_CT&IE_FB&IE_KB when IOCTL_RD='1' and IOCTL_ADDR=X"0006" else -- MZ_SYS_IENB
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"000000"&(not BST_n)&ZBACK when IOCTL_RD='1' and IOCTL_ADDR=X"0007" else -- MZ_SYS_STATUS
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"00000000";
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INTL <= IRQ_KB or IRQ_FB or IRQ_CT or IRQ_FD;
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--
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-- Filter and Asynchronous Reset with automatic
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--
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URST_n <= URSTi;
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process( CLK50 ) begin
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if( CLK50'event and CLK50='1' ) then
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if BUF=X"80" then
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URSTi <= '1';
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else
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BUF <= BUF+'1';
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URSTi <= '0';
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end if;
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end if;
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end process;
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process( URSTi, SCLK ) begin
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if URSTi='0' then
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CNT5 <= (others=>'0');
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SR_BTN <= (others=>'1');
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ZR_BTN <= (others=>'1');
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elsif SCLK'event and SCLK='1' then
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if CNT5="11111" then
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SR_BTN <= SR_BTN(6 downto 0)&(BUTTON(1) or (not BUTTON(0))); -- only BUTTON1
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ZR_BTN <= ZR_BTN(6 downto 0)&((not BUTTON(1)) or BUTTON(0)); -- only BUTTON0
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CNT5 <= (others=>'0');
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else
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CNT5<=CNT5+'1';
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end if;
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end if;
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end process;
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F_BTNi <= '1' when SR_BTN="00000000" else '0';
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F_BTN <= F_BTNi;
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ARST_n <= URSTi ;
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ZRST <= '0' when (ZR_BTN="00000000" and ZBACK='1') or ZRSTi='0' or URSTi='0' else '1';
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BOOTM <= BOOTMi;
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end rtl;
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