b32c9615e4
Proposal to restructure all the files and folders to keep things organized and similar to other cores.
215 lines
8.2 KiB
VHDL
215 lines
8.2 KiB
VHDL
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--
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-- Name: i8254.vhd
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-- Created: November 2018
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-- Author(s): Philip Smart
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-- Description: Sharp MZ series i8254 Timer
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-- This module emulates the Intel i8254 Programmable Interval Timer.
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--
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-- Credits:
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-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
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--
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-- History: November 2018 - Initial write.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity i8254 is
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Port (
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RST : in std_logic;
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CLK : in std_logic;
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ENA : in std_logic;
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A : in std_logic_vector(1 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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CS_n : in std_logic;
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WR_n : in std_logic;
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RD_n : in std_logic;
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--
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CLK0 : in std_logic;
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GATE0 : in std_logic;
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OUT0 : out std_logic;
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CLK1 : in std_logic;
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GATE1 : in std_logic;
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OUT1 : out std_logic;
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CLK2 : in std_logic;
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GATE2 : in std_logic;
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OUT2 : out std_logic
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);
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end i8254;
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architecture Behavioral of i8254 is
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signal WREN : std_logic;
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signal RDEN : std_logic;
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signal WRCTRLEN : std_logic;
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signal WR0 : std_logic;
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signal WR1 : std_logic;
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signal WR2 : std_logic;
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signal RD0 : std_logic;
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signal RD1 : std_logic;
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signal RD2 : std_logic;
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signal DO0 : std_logic_vector(7 downto 0);
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signal DO1 : std_logic_vector(7 downto 0);
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signal DO2 : std_logic_vector(7 downto 0);
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signal LDO0 : std_logic_vector(7 downto 0);
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signal LDO1 : std_logic_vector(7 downto 0);
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signal LDO2 : std_logic_vector(7 downto 0);
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signal READDATA_NEXT : std_logic_vector(7 downto 0);
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signal CTRLM0 : std_logic;
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signal CTRLM1 : std_logic;
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signal CTRLM2 : std_logic;
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signal LATCNT0 : std_logic;
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signal LATCNT1 : std_logic;
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signal LATCNT2 : std_logic;
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signal LATSTS0 : std_logic;
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signal LATSTS1 : std_logic;
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signal LATSTS2 : std_logic;
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component i8254_counter
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Port (
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CLK : in std_logic;
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RESET : in std_logic;
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--
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DATA_IN : in std_logic_vector(7 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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WRITE : in std_logic;
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READ : in std_logic;
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CTRL_MODE_EN : in std_logic;
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LATCH_COUNT_EN : in std_logic;
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LATCH_STATUS_EN : in std_logic;
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--
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CTR_CLK : in std_logic;
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CTR_GATE : in std_logic;
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CTR_OUT : out std_logic
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);
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end component;
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begin
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-- Create signals to select a given register for read or write.
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--
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WREN <= '1' when ENA = '1' and CS_n = '0' and WR_n = '0'
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else '0';
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RDEN <= '1' when ENA = '1' and CS_n = '0' and RD_n = '0'
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else '0';
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WRCTRLEN <= '1' when WREN = '1' and A = "11"
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else '0';
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WR0 <= '1' when WREN = '1' and A = "00"
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else '0';
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WR1 <= '1' when WREN = '1' and A = "01"
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else '0';
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WR2 <= '1' when WREN = '1' and A = "10"
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else '0';
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RD0 <= '1' when RDEN = '1' and A = "00"
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else '0';
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RD1 <= '1' when RDEN = '1' and A = "01"
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else '0';
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RD2 <= '1' when RDEN = '1' and A = "10"
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else '0';
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-- Create signals to enable setting of a command, a count value or latching status per counter.
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--
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CTRLM0 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "00" and DI(5 downto 4) /= "00"
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else '0';
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CTRLM1 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "01" and DI(5 downto 4) /= "00"
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else '0';
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CTRLM2 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "10" and DI(5 downto 4) /= "00"
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else '0';
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LATCNT0 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "00" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(1) = '1'))
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else '0';
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LATCNT1 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "01" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(2) = '1'))
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else '0';
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LATCNT2 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "10" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(3) = '1'))
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else '0';
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LATSTS0 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(1) = '1'
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else '0';
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LATSTS1 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(2) = '1'
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else '0';
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LATSTS2 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(3) = '1'
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else '0';
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-- Assign the counter whose address is active. Not permissible to read back control register.
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--
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DO <= DO0 when A = "00"
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else
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DO1 when A = "01"
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else
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DO2 when A = "10"
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else
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(others => '0');
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-- Instantiate the 3 counters within the 8254.
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--
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CTR0 : i8254_counter port map (
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CLK => CLK,
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RESET => RST,
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--
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DATA_IN => DI,
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DATA_OUT => DO0,
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WRITE => WR0,
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READ => RD0,
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CTRL_MODE_EN => CTRLM0,
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LATCH_COUNT_EN => LATCNT0,
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LATCH_STATUS_EN => LATSTS0,
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--
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CTR_CLK => CLK0,
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CTR_GATE => GATE0,
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CTR_OUT => OUT0
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);
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CTR1 : i8254_counter port map (
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CLK => CLK,
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RESET => RST,
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--
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DATA_IN => DI,
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DATA_OUT => DO1,
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WRITE => WR1,
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READ => RD1,
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CTRL_MODE_EN => CTRLM1,
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LATCH_COUNT_EN => LATCNT1,
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LATCH_STATUS_EN => LATSTS1,
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--
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CTR_CLK => CLK1,
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CTR_GATE => GATE1,
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CTR_OUT => OUT1
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);
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CTR2 : i8254_counter port map (
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CLK => CLK,
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RESET => RST,
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--
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DATA_IN => DI,
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DATA_OUT => DO2,
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WRITE => WR2,
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READ => RD2,
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CTRL_MODE_EN => CTRLM2,
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LATCH_COUNT_EN => LATCNT2,
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LATCH_STATUS_EN => LATSTS2,
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--
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CTR_CLK => CLK2,
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CTR_GATE => GATE2,
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CTR_OUT => OUT2
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);
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end Behavioral;
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