b32c9615e4
Proposal to restructure all the files and folders to keep things organized and similar to other cores.
126 lines
3.5 KiB
VHDL
126 lines
3.5 KiB
VHDL
--
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-- Interrupt.vhd
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--
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-- Z80 Daisy-Chain Interrupt Logic for FPGA
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--
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-- Nibbles Lab. 2013-2014
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity Interrupt is
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Port (
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-- System Signal
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RESET : in std_logic;
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-- CPU Signals
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DI : in std_logic_vector(7 downto 0);
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IORQ_n : in std_logic; -- same as Z80
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RD_n : in std_logic; -- same as Z80
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M1_n : in std_logic; -- same as Z80
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IEI : in std_logic; -- same as Z80
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IEO : out std_logic; -- same as Z80
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INTO_n : out std_logic;
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-- Control Signals
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VECTEN : out std_logic;
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INTI : in std_logic;
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INTEN : in std_logic
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);
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end Interrupt;
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architecture Behavioral of Interrupt is
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-----------------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------------
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signal IREQ : std_logic;
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signal IRES : std_logic;
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signal INTR : std_logic;
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signal IAUTH : std_logic;
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signal AUTHRES : std_logic;
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signal IED1 : std_logic;
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signal IED2 : std_logic;
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signal ICB : std_logic;
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signal I4D : std_logic;
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signal FETCH : std_logic;
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signal INTA : std_logic;
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signal IENB : std_logic;
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signal iINT : std_logic;
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signal iIEO : std_logic;
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begin
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--
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-- External signals
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--
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INTO_n <= iINT;
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IEO <= iIEO;
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--
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-- Internal signals
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--
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iINT <= '0' when IEI='1' and IREQ='1' and IAUTH='0' else '1';
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iIEO <= not (((not IED1) and IREQ) or IAUTH or (not IEI));
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INTA <= ((not M1_n) and (not IORQ_n) and IEI);
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AUTHRES <= RESET or (IEI and IED2 and I4D);
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FETCH <= M1_n or RD_n;
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IRES <= RESET or INTA;
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INTR <= M1_n and (INTI and INTEN);
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VECTEN <= '1' when INTA='1' and IEI='1' and IAUTH='1' else '0';
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--
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-- Keep Interrupt Request
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--
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process( IRES, INTR ) begin
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if IRES='1' then
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IREQ <= '0';
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elsif INTR'event and INTR='1' then
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IREQ <= '1';
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end if;
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end process;
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--
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-- Interrupt Authentication
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--
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process( AUTHRES, INTA ) begin
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if AUTHRES='1' then
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IAUTH <= '0';
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elsif INTA'event and INTA='1' then
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IAUTH <= IREQ;
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end if;
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end process;
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--
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-- Fetch 'RETI'
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--
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process( RESET, FETCH ) begin
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if RESET='1' then
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IED1 <= '0';
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IED2 <= '0';
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ICB <= '0';
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I4D <= '0';
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elsif FETCH'event and FETCH='1' then
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IED2 <= IED1;
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if DI=X"ED" and ICB='0' then
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IED1 <= '1';
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else
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IED1 <= '0';
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end if;
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if DI=X"CB" then
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ICB <= '1';
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else
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ICB <= '0';
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end if;
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if DI=X"4D" then
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I4D <= IEI;
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else
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I4D <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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