b32c9615e4
Proposal to restructure all the files and folders to keep things organized and similar to other cores.
66 lines
2.3 KiB
VHDL
66 lines
2.3 KiB
VHDL
---------------------------------------------------------------------------------------------------------
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--
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-- Name: functions.vhd
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-- Created: October 2018
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-- Author(s): Philip Smart
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-- Description: Collection of re-usable functions for the SharpMZ Project.
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--
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-- Credits:
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-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
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--
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-- History: October 2018 - Initial module written.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library IEEE;
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library pkgs;
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use IEEE.STD_LOGIC_1164.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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package functions_pkg is
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-- Function to reverse the order of the bits in a standard logic vector.
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-- ie. 1010 becomes 0101
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function reverse_vector(slv:std_logic_vector) return std_logic_vector;
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-- Function to convert an integer (0 or 1) into std_logic.
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--
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function to_std_logic(i : in integer) return std_logic;
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end functions_pkg;
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package body functions_pkg is
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function reverse_vector(slv:std_logic_vector) return std_logic_vector is
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variable target : std_logic_vector(slv'high downto slv'low);
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begin
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for idx in slv'high downto slv'low loop
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target(idx) := slv(slv'low + (slv'high-idx));
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end loop;
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return target;
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end reverse_vector;
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function to_std_logic(i : in integer) return std_logic is
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begin
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if i = 0 then
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return '0';
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end if;
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return '1';
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end function;
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end functions_pkg;
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