diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..d4ae7f2 --- /dev/null +++ b/.gitignore @@ -0,0 +1,40 @@ +db +greybox_tmp +incremental_db +output_files +simulation +hc_output +scaler +hps_isw_handoff +vip +*_sim +.qsys_edit +PLLJ_PLLSPE_INFO.txt +*.bak +*.orig +*.rej +*.qdf +*.rpt +*.smsg +*.summary +*.done +*.jdi +*.pin +*.sof +*.qws +*.ppf +*.ddb +build_id.v +c5_pin_model_dump.txt +*.sopcinfo +*.csv +*.f +*.cmp +*.sip +*.spd +*.bsf +*~ +*.xml +*_netlist +*.cdf +**/.DS_Store \ No newline at end of file diff --git a/build_id.v b/build_id.v index c8e54ad..68929f3 100644 --- a/build_id.v +++ b/build_id.v @@ -1,2 +1 @@ -`define BUILD_DATE "200430" -`define BUILD_TIME "002036" +`define BUILD_DATE "210709" \ No newline at end of file diff --git a/common/clkgen.vhd b/common/clkgen.vhd index ae7eeef..c47cf98 100644 --- a/common/clkgen.vhd +++ b/common/clkgen.vhd @@ -106,6 +106,7 @@ signal PLLLOCKED2 : std_logic; signal PLLLOCKED3 : std_logic; signal CK448Mi : std_logic; -- 448MHz signal CK112Mi : std_logic; -- 112MHz +signal CKMasteri : std_logic; -- master clock -- change to allow us to run the clock slower, improve timing signal CK64Mi : std_logic; -- 64MHz signal CK56M750i : std_logic; -- 56MHz signal CK32Mi : std_logic; -- 32MHz @@ -243,6 +244,9 @@ begin locked => PLLLOCKED3 -- PLL locked. ); + + CKMasteri <= CK56M750i; + -- -- Clock Generator - Basic divide circuit for higher end frequencies. -- @@ -546,7 +550,7 @@ begin -- Process the clocks according to the user selections and assign. -- - process (RST, PLLLOCKED1, PLLLOCKED2, PLLLOCKED3, CK112Mi) + process (RST, PLLLOCKED1, PLLLOCKED2, PLLLOCKED3, CKMasteri) begin if RST = '1' or PLLLOCKED1 = '0' or PLLLOCKED2 = '0' or PLLLOCKED3 = '0' then CKENCPUi <= '0'; @@ -558,7 +562,7 @@ begin CKVIDEOi <= '0'; PEREDGE <= "00"; - elsif rising_edge(CK112Mi) then + elsif rising_edge(CKMasteri) then -- Once the rising edge of the CPU clock is detected, enable the CPU Clock Enable signal -- which is used to enable the master clock onto the logic. @@ -781,7 +785,7 @@ begin -- Assign necessary clocks and enables. -- - CLKBUS(CKMASTER) <= CK112Mi; + CLKBUS(CKMASTER) <= CKMasteri; CLKBUS(CKSOUND) <= CKSOUNDi; -- Sound base clock, 50/50 duty cycle. CLKBUS(CKRTC) <= CKRTCi; -- RTC base clock, 50/50 duty cycle. CLKBUS(CKENVIDEO) <= CKENVIDEOi; -- Enable signal for video base clock. diff --git a/common/submodules/pll_pll_0.qip b/common/submodules/pll_pll_0.qip new file mode 100644 index 0000000..d3272ad --- /dev/null +++ b/common/submodules/pll_pll_0.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_0*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_0*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_0*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_0*|altera_pll:altera_pll_i*|*" diff --git a/common/submodules/pll_pll_0.v b/common/submodules/pll_pll_0.v new file mode 100644 index 0000000..87bc175 --- /dev/null +++ b/common/submodules/pll_pll_0.v @@ -0,0 +1,108 @@ +`timescale 1ns/10ps +module pll_pll_0( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'outclk3' + output wire outclk_3, + + // interface 'outclk4' + output wire outclk_4, + + // interface 'outclk5' + output wire outclk_5, + + // interface 'outclk6' + output wire outclk_6, + + // interface 'outclk7' + output wire outclk_7, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("normal"), + .number_of_clocks(8), + .output_clock_frequency0("255.999872 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("109.714257 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("63.999981 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("31.999989 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("15.999994 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("7.999996 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("3.999998 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("1.999999 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_7, outclk_6, outclk_5, outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/common/submodules/pll_pll_1.qip b/common/submodules/pll_pll_1.qip new file mode 100644 index 0000000..a5ee3a6 --- /dev/null +++ b/common/submodules/pll_pll_1.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_1*|altera_pll:altera_pll_i*|*" + +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_1*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_1*|altera_pll:altera_pll_i*|*" diff --git a/common/submodules/pll_pll_1.v b/common/submodules/pll_pll_1.v new file mode 100644 index 0000000..e01e8ad --- /dev/null +++ b/common/submodules/pll_pll_1.v @@ -0,0 +1,99 @@ +`timescale 1ns/10ps +module pll_pll_1( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'outclk3' + output wire outclk_3, + + // interface 'outclk4' + output wire outclk_4, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("false"), + .reference_clock_frequency("256.0 MHz"), + .operation_mode("normal"), + .number_of_clocks(5), + .output_clock_frequency0("56.748768 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("28.374384 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("14.187192 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("7.093596 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("3.546798 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/common/submodules/pll_pll_2.qip b/common/submodules/pll_pll_2.qip new file mode 100644 index 0000000..21d10bf --- /dev/null +++ b/common/submodules/pll_pll_2.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_2*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_2*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_2*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_2*|altera_pll:altera_pll_i*|*" diff --git a/common/submodules/pll_pll_2.v b/common/submodules/pll_pll_2.v new file mode 100644 index 0000000..222ccad --- /dev/null +++ b/common/submodules/pll_pll_2.v @@ -0,0 +1,96 @@ +`timescale 1ns/10ps +module pll_pll_2( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'outclk3' + output wire outclk_3, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("256.0 MHz"), + .operation_mode("normal"), + .number_of_clocks(4), + .output_clock_frequency0("31.099998 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("25.176188 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("17.821346 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("8.860892 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_3, outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/emu.sv b/emu.sv index 02530d3..c17458f 100644 --- a/emu.sv +++ b/emu.sv @@ -30,98 +30,189 @@ module emu ( - //Master input clocks - input CLK_50M, + //Master input clock + input CLK_50M, - //Async reset from top-level module. - //Can be used as initial reset. - input RESET, + //Async reset from top-level module. + //Can be used as initial reset. + input RESET, - //Must be passed to hps_io module - inout [44:0] HPS_BUS, + //Must be passed to hps_io module + inout [45:0] HPS_BUS, - //Base video clock. Usually equals to CLK_SYS. - output CLK_VIDEO, + //Base video clock. Usually equals to CLK_SYS. + output CLK_VIDEO, - //Multiple resolutions are supported using different CE_PIXEL rates. - //Must be based on CLK_VIDEO - output CE_PIXEL, + //Multiple resolutions are supported using different CE_PIXEL rates. + //Must be based on CLK_VIDEO + output CE_PIXEL, - //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - output [7:0] VIDEO_ARX, - output [7:0] VIDEO_ARY, + //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. + //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. + output [12:0] VIDEO_ARX, + output [12:0] VIDEO_ARY, - // These video signals are defined in sys_top.v, via the video_mixer we output the video from the emulator onto these - // signals, which then get passed as follows: - // emu -> video_mixer -> vga_osd -> vga_out - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, // = ~(VBlank | HBlank) + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, + output VGA_HS, + output VGA_VS, + output VGA_DE, // = ~(VBlank | HBlank) + output VGA_F1, + output [1:0] VGA_SL, + output VGA_SCALER, // Force VGA scaler - output LED_USER, // 1 - ON, 0 - OFF. + input [11:0] HDMI_WIDTH, + input [11:0] HDMI_HEIGHT, + output HDMI_FREEZE, - // b[1]: 0 - LED status is system status OR'd with b[0] - // 1 - LED status is controled solely by b[0] - // hint: supply 2'b00 to let the system control the LED. - output [1:0] LED_POWER, - output [1:0] LED_DISK, - output [7:0] LED_MB, +`ifdef MISTER_FB + // Use framebuffer in DDRAM (USE_FB=1 in qsf) + // FB_FORMAT: + // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp + // [3] : 0=16bits 565 1=16bits 1555 + // [4] : 0=RGB 1=BGR (for 16/24/32 modes) + // + // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) + output FB_EN, + output [4:0] FB_FORMAT, + output [11:0] FB_WIDTH, + output [11:0] FB_HEIGHT, + output [31:0] FB_BASE, + output [13:0] FB_STRIDE, + input FB_VBL, + input FB_LL, + output FB_FORCE_BLANK, - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - output AUDIO_S, // 1 - signed audio samples, 0 - unsigned - output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) -// input TAPE_IN, +`ifdef MISTER_FB_PALETTE + // Palette control for 8bit modes. + // Ignored for other video modes. + output FB_PAL_CLK, + output [7:0] FB_PAL_ADDR, + output [23:0] FB_PAL_DOUT, + input [23:0] FB_PAL_DIN, + output FB_PAL_WR, +`endif +`endif - // SD-SPI - output SD_SCK, - output SD_MOSI, - input SD_MISO, - output SD_CS, - input SD_CD, + output LED_USER, // 1 - ON, 0 - OFF. - //High latency DDR3 RAM interface - //Use for non-critical time purposes - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, + // b[1]: 0 - LED status is system status OR'd with b[0] + // 1 - LED status is controled solely by b[0] + // hint: supply 2'b00 to let the system control the LED. + output [1:0] LED_POWER, + output [1:0] LED_DISK, - //SDRAM interface with lower latency -// ,output SDRAM_CLK, -// output SDRAM_CKE, -// output [12:0] SDRAM_A, -// output [1:0] SDRAM_BA, -// inout [15:0] SDRAM_DQ, -// output SDRAM_DQML, -// output SDRAM_DQMH, -// output SDRAM_nCS, -// output SDRAM_nCAS, -// output SDRAM_nRAS, -// output SDRAM_nWE - input UART_RX, - output UART_TX + // I/O board button press simulation (active high) + // b[1]: user button + // b[0]: osd button + output [1:0] BUTTONS, + + input CLK_AUDIO, // 24.576 MHz + output [15:0] AUDIO_L, + output [15:0] AUDIO_R, + output AUDIO_S, // 1 - signed audio samples, 0 - unsigned + output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) + + //ADC + inout [3:0] ADC_BUS, + + //SD-SPI + output SD_SCK, + output SD_MOSI, + input SD_MISO, + output SD_CS, + input SD_CD, + + //High latency DDR3 RAM interface + //Use for non-critical time purposes + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + + //SDRAM interface with lower latency + output SDRAM_CLK, + output SDRAM_CKE, + output [12:0] SDRAM_A, + output [1:0] SDRAM_BA, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nCS, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nWE, + +`ifdef MISTER_DUAL_SDRAM + //Secondary SDRAM + //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 + input SDRAM2_EN, + output SDRAM2_CLK, + output [12:0] SDRAM2_A, + output [1:0] SDRAM2_BA, + inout [15:0] SDRAM2_DQ, + output SDRAM2_nCS, + output SDRAM2_nCAS, + output SDRAM2_nRAS, + output SDRAM2_nWE, +`endif + + input UART_CTS, + output UART_RTS, + input UART_RXD, + output UART_TXD, + output UART_DTR, + input UART_DSR, + + // Open-drain User port. + // 0 - D+/RX + // 1 - D-/TX + // 2..6 - USR2..USR6 + // Set USER_OUT to 1 to read from USER_IN. + input [6:0] USER_IN, + output [6:0] USER_OUT, + + input OSD_STATUS ); -//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; -assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0; +///////// Default values for ports not used in this core ///////// + +assign ADC_BUS = 'Z; +assign USER_OUT = '1; +assign {UART_RTS, UART_TXD, UART_DTR} = 0; +assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; +assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; +assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0; + +assign VGA_SL = 0; +assign VGA_F1 = 0; +assign VGA_SCALER = 0; +assign HDMI_FREEZE = 0; + + +assign LED_DISK = 0; +assign LED_POWER = 0; +assign BUTTONS = 0; + assign LED_USER = ioctl_download; assign LED_DISK = 0; assign LED_POWER = 0; -assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4; -assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3; +wire [1:0] ar = status[9:8]; + +assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1); +assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0; + + + wire [2:0] scale = status[4:2]; @@ -132,13 +223,16 @@ localparam CONF_STR = { "SHARP MZ SERIES;;", "J,Fire;", - "V,v1.02.",`BUILD_DATE + "V,v",`BUILD_DATE }; ///////////////// CLOCKS //////////////////////// wire clk_sys; + + + ///////////////// HPS /////////////////////////// wire [31:0] status; @@ -158,6 +252,8 @@ wire [15:0] ioctl_din; wire forced_scandoubler; hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io + +//hps_io #(.CONF_STR(CONF_STR)) hps_io ( .clk_sys(clk_sys), .HPS_BUS(HPS_BUS), @@ -251,6 +347,7 @@ bridge sharp_mz // Clocks output by the emulator. .clkvid(clk_video_in), + //.cepix(cepix), // Reset .cold_reset(reset), @@ -297,10 +394,11 @@ bridge sharp_mz // If ce_pix is same as pixel clock, uncomment below and remove CE_PIXEL from .ce_pix_out below. // //assign CE_PIXEL=1; -//assign CLK_VIDEO = clk_sys; -assign CLK_VIDEO = clk_video_in; +assign CLK_VIDEO = clk_sys; +//assign CLK_VIDEO = clk_video_in; assign CE_PIXEL = clk_video_in; + assign VGA_R = R_emu; assign VGA_G = G_emu; assign VGA_B = B_emu; diff --git a/files.qip b/files.qip new file mode 100644 index 0000000..3cdda53 --- /dev/null +++ b/files.qip @@ -0,0 +1,70 @@ +set_global_assignment -name VHDL_FILE jtag_uart_0.vhd +set_global_assignment -name SYSTEMVERILOG_FILE emu.sv +set_global_assignment -name VHDL_FILE common/config_pkg.vhd +set_global_assignment -name VHDL_FILE bridge.vhd +set_global_assignment -name VHDL_FILE sharpmz.vhd + +#============================================================ +# Latest T80 CPU +#============================================================ +set_global_assignment -name VHDL_FILE common/T80/T80.vhd +set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE common/T80/T80a.vhd +set_global_assignment -name VHDL_FILE common/T80/T80se.vhd +set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd + +#============================================================ +# i8253 Programmable Interval Timer +#============================================================ +set_global_assignment -name VHDL_FILE common/i8254/i8254_counter.vhd +set_global_assignment -name VHDL_FILE common/i8254/i8254.vhd + +#============================================================ +# i8255 Programmable Peripheral Interface +#============================================================ +set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd +#set_global_assignment -name VHDL_FILE mz80b/i8255/i8255.vhd + +#============================================================ +# MZ80C specific modules. +#============================================================ +set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd + +#============================================================ +# MZ80B specific modules. +#============================================================ +#set_global_assignment -name VHDL_FILE mz80b/mz80b_dummy.vhd +set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd + + + +#============================================================ +# PLL +#============================================================ +set_global_assignment -name QIP_FILE common/pll.qip +set_global_assignment -name VHDL_FILE common/clkgen.vhd +#set_global_assignment -name QIP_FILE common/pll_1.qip +#set_global_assignment -name QIP_FILE common/pll_2.qip +#set_global_assignment -name QIP_FILE common/pll_4.qip + +#============================================================ +# Common modules +#============================================================ +set_global_assignment -name VHDL_FILE common/dprom.vhd +set_global_assignment -name VHDL_FILE common/clk_div.vhd +set_global_assignment -name VHDL_FILE common/mctrl.vhd +set_global_assignment -name VHDL_FILE common/dpram.vhd +set_global_assignment -name VHDL_FILE common/keymatrix.vhd +set_global_assignment -name VHDL_FILE common/video.vhd +set_global_assignment -name VHDL_FILE common/cmt.vhd +set_global_assignment -name VHDL_FILE common/z8420/z8420.vhd +set_global_assignment -name VHDL_FILE common/z8420/Interrupt.vhd + +#============================================================ +# Functions +#============================================================ +set_global_assignment -name VHDL_FILE common/functions.vhd diff --git a/jtag.cdf b/jtag.cdf index f94d545..56ad529 100644 --- a/jtag.cdf +++ b/jtag.cdf @@ -5,7 +5,7 @@ JedecChain; P ActionCode(Ign) Device PartName(SOCVHPS) MfrSpec(OpMask(0)); P ActionCode(Cfg) - Device PartName(5CSEBA6U23I7) Path("output_files/") File("sharpmz-lite.sof") MfrSpec(OpMask(1)); + Device PartName(5CSEBA6U23I7) Path("output_files/") File("sharpmz.sof") MfrSpec(OpMask(1)); ChainEnd; AlteraBegin; diff --git a/sharpmz-lite-div_assignment_defaults.qdf b/sharpmz-lite-div_assignment_defaults.qdf deleted file mode 100644 index 92b284a..0000000 --- a/sharpmz-lite-div_assignment_defaults.qdf +++ /dev/null @@ -1,807 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition -# Date created = 17:23:05 October 20, 2018 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. 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FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On -set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off -set_global_assignment -name REVISION_TYPE Base -family "Arria V" -set_global_assignment -name REVISION_TYPE Base -family "Stratix V" -set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" -set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name 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IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 -set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off -set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On -set_global_assignment -name PRPOF_ID Off -set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off -set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On -set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" -set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" -set_global_assignment -name USE_CONF_DONE AUTO -set_global_assignment -name USE_PWRMGT_SCL AUTO -set_global_assignment -name USE_PWRMGT_SDA AUTO -set_global_assignment -name USE_PWRMGT_ALERT AUTO -set_global_assignment -name USE_INIT_DONE AUTO -set_global_assignment -name USE_CVP_CONFDONE AUTO -set_global_assignment -name USE_SEU_ERROR AUTO -set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On -set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name ENABLE_CONFIGURATION_PINS On -set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off -set_global_assignment -name ENABLE_NCE_PIN Off -set_global_assignment -name ENABLE_BOOT_SEL_PIN On -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF -set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto -set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto -set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name RESERVE_PR_PINS Off -set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off -set_global_assignment -name PR_PINS_OPEN_DRAIN Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name UNUSED_TSD_PINS_GND Off -set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off -set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" -set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 -set_global_assignment -name SEU_FIT_REPORT Off -set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE On -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 -set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" -set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off -set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off -set_global_assignment -name POR_SCHEME "Instant ON" -set_global_assignment -name EN_USER_IO_WEAK_PULLUP On -set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On -set_global_assignment -name POF_VERIFY_PROTECT Off -set_global_assignment -name ENABLE_SPI_MODE_CHECK Off -set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On -set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 -set_global_assignment -name GENERATE_PMSF_FILES On -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name HPS_EARLY_IO_RELEASE Off -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name POWER_HPS_ENABLE Off -set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 -set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off -set_global_assignment -name IGNORE_PARTITIONS Off -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? -set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? -set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? -set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? -set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? -set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? -set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/sharpmz-lite-pll.sdc b/sharpmz-lite-pll.sdc deleted file mode 100644 index 127326e..0000000 --- a/sharpmz-lite-pll.sdc +++ /dev/null @@ -1,459 +0,0 @@ -## Generated SDC file "sharpmz-lite-pll.out.sdc" - -## Copyright (C) 2017 Intel Corporation. All rights reserved. -## Your use of Intel Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Intel Program License -## Subscription Agreement, the Intel Quartus Prime License Agreement, -## the Intel MegaCore Function License Agreement, or other -## applicable license agreement, including, without limitation, -## that your use is for the sole purpose of programming logic -## devices manufactured by Intel and sold by Intel or its -## authorized distributors. Please refer to the applicable -## agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus Prime" -## VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition" - -## DATE "Tue Oct 09 16:54:46 2018" - -## -## DEVICE "5CSEBA6U23I7" -## - - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}] -create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}] -create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}] -create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}] - - -#************************************************************** -# Create Generated Clock -#************************************************************** - -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 5243 -divide_by 512 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 16 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 64 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 256 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 32 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 128 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 8 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 1135 -divide_by 256 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 5 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 64 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 32 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 160 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 80 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 40 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 20 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 10 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170 -set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170 -set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.170 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.170 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230 -set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.170 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.170 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230 -set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200 -set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -#************************************************************** - - - -#************************************************************** -# Set False Path -#************************************************************** - -set_false_path -from [get_ports {KEY*}] -set_false_path -from [get_ports {BTN_*}] -set_false_path -to [get_ports {LED_*}] -set_false_path -to [get_ports {VGA_*}] -set_false_path -to [get_ports {AUDIO_SPDIF}] -set_false_path -to [get_ports {AUDIO_L}] -set_false_path -to [get_ports {AUDIO_R}] - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - -# Decouple different clock groups (to simplify routing) -# -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -# -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \ -set_clock_groups -asynchronous \ - -group [get_clocks { *|h2f_user0_clk}] \ - -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}] - diff --git a/sharpmz-lite-pll_assignment_defaults.qdf b/sharpmz-lite-pll_assignment_defaults.qdf deleted file mode 100644 index d210acb..0000000 --- a/sharpmz-lite-pll_assignment_defaults.qdf +++ /dev/null @@ -1,807 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition -# Date created = 17:23:11 October 20, 2018 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. This file was generated -# automatically by the Quartus Prime software and is used -# to preserve global assignments across Quartus Prime versions. -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off -set_global_assignment -name IP_COMPONENT_INTERNAL Off -set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On -set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off -set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off -set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db -set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off -set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off -set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off -set_global_assignment -name HC_OUTPUT_DIR hc_output -set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off -set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On -set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off -set_global_assignment -name REVISION_TYPE Base -family "Arria V" -set_global_assignment -name REVISION_TYPE Base -family "Stratix V" -set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" -set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name 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Lut -set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name ALLOW_XOR_GATE_USAGE On -set_global_assignment -name AUTO_LCELL_INSERTION On -set_global_assignment -name CARRY_CHAIN_LENGTH 48 -set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 -set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 -set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off -set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On -set_global_assignment -name PRPOF_ID Off -set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off -set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On -set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" -set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" -set_global_assignment -name USE_CONF_DONE AUTO -set_global_assignment -name USE_PWRMGT_SCL AUTO -set_global_assignment -name USE_PWRMGT_SDA AUTO -set_global_assignment -name USE_PWRMGT_ALERT AUTO -set_global_assignment -name USE_INIT_DONE AUTO -set_global_assignment -name USE_CVP_CONFDONE AUTO -set_global_assignment -name USE_SEU_ERROR AUTO -set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On -set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name ENABLE_CONFIGURATION_PINS On -set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off -set_global_assignment -name ENABLE_NCE_PIN Off -set_global_assignment -name ENABLE_BOOT_SEL_PIN On -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF -set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto -set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto -set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name RESERVE_PR_PINS Off -set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off -set_global_assignment -name PR_PINS_OPEN_DRAIN Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name UNUSED_TSD_PINS_GND Off -set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off -set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" -set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 -set_global_assignment -name SEU_FIT_REPORT Off -set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE On -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 -set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" -set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off -set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off -set_global_assignment -name POR_SCHEME "Instant ON" -set_global_assignment -name EN_USER_IO_WEAK_PULLUP On -set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On -set_global_assignment -name POF_VERIFY_PROTECT Off -set_global_assignment -name ENABLE_SPI_MODE_CHECK Off -set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On -set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 -set_global_assignment -name GENERATE_PMSF_FILES On -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name HPS_EARLY_IO_RELEASE Off -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name POWER_HPS_ENABLE Off -set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 -set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off -set_global_assignment -name IGNORE_PARTITIONS Off -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? -set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? -set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? -set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? -set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? -set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? -set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/sharpmz-lite.qsf b/sharpmz-lite.qsf deleted file mode 100644 index 0c98c50..0000000 --- a/sharpmz-lite.qsf +++ /dev/null @@ -1,536 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition -# Date created = 01:53:32 April 20, 2017 -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name VERILOG_MACRO "LITE=1" - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name TOP_LEVEL_ENTITY sys_top -#set_global_assignment -name TOP_LEVEL_ENTITY emu -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 - -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE OFF -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name OPTIMIZATION_MODE "HIGH POWER EFFORT" -set_global_assignment -name SEED 1 -#set_global_assignment -name SDC_FILE sharpmz.sdc -set_global_assignment -name SDC_FILE "sharpmz-lite.sdc" - -#============================================================ -# ADC -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO -#set_location_assignment PIN_U9 -to ADC_CONVST -#set_location_assignment PIN_V10 -to ADC_SCK -#set_location_assignment PIN_AC4 -to ADC_SDI -#set_location_assignment PIN_AD4 -to ADC_SDO - -#============================================================ -# ARDUINO -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] -#set_location_assignment PIN_AG9 -to ARDUINO_IO[3] -#set_location_assignment PIN_U14 -to ARDUINO_IO[4] -#set_location_assignment PIN_U13 -to ARDUINO_IO[5] -#set_location_assignment PIN_AG8 -to ARDUINO_IO[6] -#set_location_assignment PIN_AH8 -to ARDUINO_IO[7] -#set_location_assignment PIN_AF17 -to ARDUINO_IO[8] -#set_location_assignment PIN_AE15 -to ARDUINO_IO[9] -#set_location_assignment PIN_AF15 -to ARDUINO_IO[10] -#set_location_assignment PIN_AG16 -to ARDUINO_IO[11] -#set_location_assignment PIN_AH11 -to ARDUINO_IO[12] -#set_location_assignment PIN_AH12 -to ARDUINO_IO[13] -#set_location_assignment PIN_AH9 -to ARDUINO_IO[14] -#set_location_assignment PIN_AG11 -to ARDUINO_IO[15] - -#============================================================ -# SDIO -#============================================================ -set_location_assignment PIN_AF25 -to SDIO_DAT[0] -set_location_assignment PIN_AF23 -to SDIO_DAT[1] -set_location_assignment PIN_AD26 -to SDIO_DAT[2] -set_location_assignment PIN_AF28 -to SDIO_DAT[3] -set_location_assignment PIN_AF27 -to SDIO_CMD -set_location_assignment PIN_AH26 -to SDIO_CLK -set_location_assignment PIN_AH7 -to SDIO_CD -# -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* -# -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD - -#============================================================ -# VGA -#============================================================ -set_location_assignment PIN_AE17 -to VGA_R[0] -set_location_assignment PIN_AE20 -to VGA_R[1] -set_location_assignment PIN_AF20 -to VGA_R[2] -set_location_assignment PIN_AH18 -to VGA_R[3] -set_location_assignment PIN_AH19 -to VGA_R[4] -set_location_assignment PIN_AF21 -to VGA_R[5] - -set_location_assignment PIN_AE19 -to VGA_G[0] -set_location_assignment PIN_AG15 -to VGA_G[1] -set_location_assignment PIN_AF18 -to VGA_G[2] -set_location_assignment PIN_AG18 -to VGA_G[3] -set_location_assignment PIN_AG19 -to VGA_G[4] -set_location_assignment PIN_AG20 -to VGA_G[5] - -set_location_assignment PIN_AG21 -to VGA_B[0] -set_location_assignment PIN_AA20 -to VGA_B[1] -set_location_assignment PIN_AE22 -to VGA_B[2] -set_location_assignment PIN_AF22 -to VGA_B[3] -set_location_assignment PIN_AH23 -to VGA_B[4] -set_location_assignment PIN_AH21 -to VGA_B[5] - -set_location_assignment PIN_AH22 -to VGA_HS -set_location_assignment PIN_AG24 -to VGA_VS - -set_location_assignment PIN_AH27 -to VGA_EN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* - -#============================================================ -# AUDIO -#============================================================ -set_location_assignment PIN_AC24 -to AUDIO_L -set_location_assignment PIN_AE25 -to AUDIO_R -set_location_assignment PIN_AG26 -to AUDIO_SPDIF -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* - -#============================================================ -# SDRAM -#============================================================ -#set_location_assignment PIN_Y11 -to SDRAM_A[0] -#set_location_assignment PIN_AA26 -to SDRAM_A[1] -#set_location_assignment PIN_AA13 -to SDRAM_A[2] -#set_location_assignment PIN_AA11 -to SDRAM_A[3] -#set_location_assignment PIN_W11 -to SDRAM_A[4] -#set_location_assignment PIN_Y19 -to SDRAM_A[5] -#set_location_assignment PIN_AB23 -to SDRAM_A[6] -#set_location_assignment PIN_AC23 -to SDRAM_A[7] -#set_location_assignment PIN_AC22 -to SDRAM_A[8] -#set_location_assignment PIN_C12 -to SDRAM_A[9] -#set_location_assignment PIN_AB26 -to SDRAM_A[10] -#set_location_assignment PIN_AD17 -to SDRAM_A[11] -#set_location_assignment PIN_D12 -to SDRAM_A[12] -#set_location_assignment PIN_Y17 -to SDRAM_BA[0] -#set_location_assignment PIN_AB25 -to SDRAM_BA[1] - -#set_location_assignment PIN_E8 -to SDRAM_DQ[0] -#set_location_assignment PIN_V12 -to SDRAM_DQ[1] -#set_location_assignment PIN_D11 -to SDRAM_DQ[2] -#set_location_assignment PIN_W12 -to SDRAM_DQ[3] -#set_location_assignment PIN_AH13 -to SDRAM_DQ[4] -#set_location_assignment PIN_D8 -to SDRAM_DQ[5] -#set_location_assignment PIN_AH14 -to SDRAM_DQ[6] -#set_location_assignment PIN_AF7 -to SDRAM_DQ[7] -#set_location_assignment PIN_AE24 -to SDRAM_DQ[8] -#set_location_assignment PIN_AD23 -to SDRAM_DQ[9] -#set_location_assignment PIN_AE6 -to SDRAM_DQ[10] -#set_location_assignment PIN_AE23 -to SDRAM_DQ[11] -#set_location_assignment PIN_AG14 -to SDRAM_DQ[12] -#set_location_assignment PIN_AD5 -to SDRAM_DQ[13] -#set_location_assignment PIN_AF4 -to SDRAM_DQ[14] -#set_location_assignment PIN_AH3 -to SDRAM_DQ[15] -#set_location_assignment PIN_AG13 -to SDRAM_DQML -#set_location_assignment PIN_AF13 -to SDRAM_DQMH - -#set_location_assignment PIN_AD20 -to SDRAM_CLK -#set_location_assignment PIN_AG10 -to SDRAM_CKE - -#set_location_assignment PIN_AA19 -to SDRAM_nWE -#set_location_assignment PIN_AA18 -to SDRAM_nCAS -#set_location_assignment PIN_Y18 -to SDRAM_nCS -#set_location_assignment PIN_W14 -to SDRAM_nRAS - -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* -#set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -#set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* - -#============================================================ -# I/O -#============================================================ -set_location_assignment PIN_Y15 -to LED_USER -set_location_assignment PIN_AA15 -to LED_HDD -set_location_assignment PIN_AG28 -to LED_POWER - -set_location_assignment PIN_AH24 -to BTN_USER -set_location_assignment PIN_AG25 -to BTN_OSD -set_location_assignment PIN_AG23 -to BTN_RESET - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* - -#============================================================ -# CLOCK -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 -set_location_assignment PIN_V11 -to FPGA_CLK1_50 -set_location_assignment PIN_Y13 -to FPGA_CLK2_50 -set_location_assignment PIN_E11 -to FPGA_CLK3_50 - -#============================================================ -# HDMI -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS -#set_location_assignment PIN_U10 -to HDMI_I2C_SCL -#set_location_assignment PIN_AA4 -to HDMI_I2C_SDA -#set_location_assignment PIN_T13 -to HDMI_I2S -#set_location_assignment PIN_T11 -to HDMI_LRCLK -#set_location_assignment PIN_U11 -to HDMI_MCLK -#set_location_assignment PIN_T12 -to HDMI_SCLK -#set_location_assignment PIN_AG5 -to HDMI_TX_CLK -#set_location_assignment PIN_AD19 -to HDMI_TX_DE -#set_location_assignment PIN_AD12 -to HDMI_TX_D[0] -#set_location_assignment PIN_AE12 -to HDMI_TX_D[1] -#set_location_assignment PIN_W8 -to HDMI_TX_D[2] -#set_location_assignment PIN_Y8 -to HDMI_TX_D[3] -#set_location_assignment PIN_AD11 -to HDMI_TX_D[4] -#set_location_assignment PIN_AD10 -to HDMI_TX_D[5] -#set_location_assignment PIN_AE11 -to HDMI_TX_D[6] -#set_location_assignment PIN_Y5 -to HDMI_TX_D[7] -#set_location_assignment PIN_AF10 -to HDMI_TX_D[8] -#set_location_assignment PIN_Y4 -to HDMI_TX_D[9] -#set_location_assignment PIN_AE9 -to HDMI_TX_D[10] -#set_location_assignment PIN_AB4 -to HDMI_TX_D[11] -#set_location_assignment PIN_AE7 -to HDMI_TX_D[12] -#set_location_assignment PIN_AF6 -to HDMI_TX_D[13] -#set_location_assignment PIN_AF8 -to HDMI_TX_D[14] -#set_location_assignment PIN_AF5 -to HDMI_TX_D[15] -#set_location_assignment PIN_AE4 -to HDMI_TX_D[16] -#set_location_assignment PIN_AH2 -to HDMI_TX_D[17] -#set_location_assignment PIN_AH4 -to HDMI_TX_D[18] -#set_location_assignment PIN_AH5 -to HDMI_TX_D[19] -#set_location_assignment PIN_AH6 -to HDMI_TX_D[20] -#set_location_assignment PIN_AG6 -to HDMI_TX_D[21] -#set_location_assignment PIN_AF9 -to HDMI_TX_D[22] -#set_location_assignment PIN_AE8 -to HDMI_TX_D[23] -#set_location_assignment PIN_T8 -to HDMI_TX_HS -#set_location_assignment PIN_AF11 -to HDMI_TX_INT -#set_location_assignment PIN_V13 -to HDMI_TX_VS - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_location_assignment PIN_AH17 -to KEY[0] -set_location_assignment PIN_AH16 -to KEY[1] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] -set_location_assignment PIN_W15 -to LED[0] -set_location_assignment PIN_AA24 -to LED[1] -set_location_assignment PIN_V16 -to LED[2] -set_location_assignment PIN_V15 -to LED[3] -set_location_assignment PIN_AF26 -to LED[4] -set_location_assignment PIN_AE26 -to LED[5] -set_location_assignment PIN_Y16 -to LED[6] -set_location_assignment PIN_AA23 -to LED[7] - -#============================================================ -# SW -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -#set_location_assignment PIN_Y24 -to SW[0] -#set_location_assignment PIN_W24 -to SW[1] -#set_location_assignment PIN_W21 -to SW[2] -#set_location_assignment PIN_W20 -to SW[3] - -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" - -set_global_assignment -name CDF_FILE jtag.cdf -set_global_assignment -name QIP_FILE sys/sys.qip -set_global_assignment -name VHDL_FILE jtag_uart_0.vhd -set_global_assignment -name SYSTEMVERILOG_FILE emu.sv -set_global_assignment -name VHDL_FILE common/config_pkg.vhd -set_global_assignment -name VHDL_FILE bridge.vhd -set_global_assignment -name VHDL_FILE sharpmz.vhd - -#============================================================ -# Latest T80 CPU -#============================================================ -set_global_assignment -name VHDL_FILE common/T80/T80.vhd -set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE common/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE common/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE common/T80/T80a.vhd -set_global_assignment -name VHDL_FILE common/T80/T80se.vhd -set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd - -#============================================================ -# i8253 Programmable Interval Timer -#============================================================ -set_global_assignment -name VHDL_FILE common/i8254/i8254_counter.vhd -set_global_assignment -name VHDL_FILE common/i8254/i8254.vhd - -#============================================================ -# i8255 Programmable Peripheral Interface -#============================================================ -set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd -#set_global_assignment -name VHDL_FILE mz80b/i8255/i8255.vhd - -#============================================================ -# MZ80C specific modules. -#============================================================ -set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd - -#============================================================ -# MZ80B specific modules. -#============================================================ -#set_global_assignment -name VHDL_FILE mz80b/mz80b_dummy.vhd -set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd - -#============================================================ -# NEO430 -#============================================================ -#set_global_assignment -name VHDL_FILE neo430/neo430.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_addr_gen.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_alu.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_application_image.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_boot_rom.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_bootloader_image.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_cfu.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_control.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_cpu.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_crc.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_dmem.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_gpio.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_imem.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_muldiv.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_package.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_pwm.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_reg_file.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_sysconfig.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_timer.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_top.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_uart.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_spi.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_twi.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_wb_interface.vhd -#set_global_assignment -name VHDL_FILE neo430/neo430_wdt.vhd -#============================================================ -# STORM -#============================================================ -#set_global_assignment -name VHDL_FILE storm/STORM_SoC.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/ALU.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/BARREL_SHIFTER.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/BUS_UNIT.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/CACHE.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/CORE.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/CORE_PKG.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/FLOW_CTRL.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/LOAD_STORE_UNIT.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/MC_SYS.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/MS_UNIT.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/MULTIPLY_UNIT.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/OPCODE_DECODER.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/OPERAND_UNIT.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/REG_FILE.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/STORM_TOP.vhd -#set_global_assignment -name VHDL_FILE storm/CPU/WB_UNIT.vhd -#set_global_assignment -name VHDL_FILE storm/components/boot_rom/rtl/BOOT_ROM_FILE.vhd -#set_global_assignment -name VHDL_FILE storm/components/seven_segment_controller/rtl/SEVEN_SEG_CTRL.vhd -#set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2_wb.vhd -#set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2.vhd -#set_global_assignment -name VHDL_FILE storm/components/reset_protector/rtl/RST_PROTECT.vhd -#set_global_assignment -name VHDL_FILE storm/components/timer/rtl/TIMER.vhd -#set_global_assignment -name VHDL_FILE storm/components/io_controller/rtl/GP_IO_CTRL.vhd -#set_global_assignment -name VHDL_FILE storm/components/vector_interrupt_controller/rtl/VIC.vhd -#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/MINI_UART.vhd -#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Txunit.vhd -#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Rxunit.vhd -#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/utils.vhd -#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_top.vhd -#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_byte_ctrl.vhd -#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_bit_ctrl.vhd -#set_global_assignment -name VHDL_FILE storm/components/pwm_controller/rtl/PWM_CTRL.vhd -#set_global_assignment -name VHDL_FILE storm/components/sram_memory/rtl/MEMORY.vhd -#set_global_assignment -name VHDL_FILE storm/components/ioctl/rtl/ioctl.vhd -#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_top.v -#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_defines.v -#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_clgen.v -#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_shift.v -#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/timescale.v - -#============================================================ -# PLL -#============================================================ -set_global_assignment -name QIP_FILE common/pll.qip -set_global_assignment -name VHDL_FILE common/clkgen.vhd -#set_global_assignment -name QIP_FILE common/pll_1.qip -#set_global_assignment -name QIP_FILE common/pll_2.qip -#set_global_assignment -name QIP_FILE common/pll_4.qip - -#============================================================ -# Common modules -#============================================================ -set_global_assignment -name VHDL_FILE common/dprom.vhd -set_global_assignment -name VHDL_FILE common/clk_div.vhd -set_global_assignment -name VHDL_FILE common/mctrl.vhd -set_global_assignment -name VHDL_FILE common/dpram.vhd -set_global_assignment -name VHDL_FILE common/keymatrix.vhd -set_global_assignment -name VHDL_FILE common/video.vhd -set_global_assignment -name VHDL_FILE common/cmt.vhd -set_global_assignment -name VHDL_FILE common/z8420/z8420.vhd -set_global_assignment -name VHDL_FILE common/z8420/Interrupt.vhd - -#============================================================ -# Functions -#============================================================ -set_global_assignment -name VHDL_FILE common/functions.vhd - -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON -set_global_assignment -name ALLOW_REGISTER_RETIMING ON - - -set_location_assignment PIN_AA13 -to UART_TX -set_location_assignment PIN_AA11 -to UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX -# -#set_location_assignment PIN_AF25 -to SPI_MISO -#set_location_assignment PIN_AF28 -to SPI_CS[0] -#set_location_assignment PIN_AF27 -to SPI_MOSI -#set_location_assignment PIN_AH26 -to SPI_SCLK - -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MISO -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_CS[0] -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MOSI -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_SCLK - -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CS[0] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCLK -#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SPI_MISO - - - - - - - - - -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/sharpmz-lite.qws b/sharpmz-lite.qws deleted file mode 100644 index 185237e..0000000 Binary files a/sharpmz-lite.qws and /dev/null differ diff --git a/sharpmz-lite.rbf b/sharpmz-lite.rbf deleted file mode 100644 index 7f3691a..0000000 Binary files a/sharpmz-lite.rbf and /dev/null differ diff --git a/sharpmz-lite.sdc b/sharpmz-lite.sdc deleted file mode 100644 index d000cc8..0000000 --- a/sharpmz-lite.sdc +++ /dev/null @@ -1,206 +0,0 @@ -## Generated SDC file "sharpmz-lite-div.out.sdc" - -## Copyright (C) 2017 Intel Corporation. All rights reserved. -## Your use of Intel Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Intel Program License -## Subscription Agreement, the Intel Quartus Prime License Agreement, -## the Intel MegaCore Function License Agreement, or other -## applicable license agreement, including, without limitation, -## that your use is for the sole purpose of programming logic -## devices manufactured by Intel and sold by Intel or its -## authorized distributors. Please refer to the applicable -## agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus Prime" -## VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition" - -## DATE "Wed Oct 31 10:26:38 2018" - -## -## DEVICE "5CSEBA6U23I7" -## - - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}] -create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}] -create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}] -create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}] - - -#************************************************************** -# Create Generated Clock -#************************************************************** - -derive_pll_clocks -create_base_clocks -use_tan_name - -# create_generated_clock -name -source -divide_by -duty_cycle 50.00 -# a name assigned to the generate clock to be used in TQ analysis -# the reference to your master clock -# in your case this is the lpm_counter port where you pick the generated clock from -# create_generated_clock -name divclk_16mhz -divide_by 2 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[0]} -#set all_enabled_registers ] -#set clock_enable_divide_by_n 4 -#set_multicycle_path -setup $clock_enable_divide_by_n -from $all_enabled_registers -to $all_enabled_registers -#set_multicycle_path -hold -from $all_enabled_registers -to $all_enabled_registers - -#create_generated_clock -name {CK96M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 192 -divide_by 100 \ -# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -#create_generated_clock -name {CK64M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 128 -divide_by 100 \ -# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] -#create_generated_clock -name {CK32M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 64 -divide_by 100 \ -# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] -#create_generated_clock -name {CK16M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 32 -divide_by 100 \ -# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] -#create_generated_clock -name {CK8M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 16 -divide_by 100 \ -# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] -#create_generated_clock -name {CK4M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 8 -divide_by 100 \ -# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[5]}] -#create_generated_clock -name {CK2M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 4 -divide_by 100 \ -# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[6]}] -# -#create_generated_clock -name {CK56M75} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 591146 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -#create_generated_clock -name {CK28M375} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 295573 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] -#create_generated_clock -name {CK14M1875} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 147786 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] -#create_generated_clock -name {CK7M09375} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 73893 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] -#create_generated_clock -name {CK3M546875} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 36947 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] -# -#create_generated_clock -name {CK85M86} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 894375 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -#create_generated_clock -name {CK65M} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 67708 -divide_by 100000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] -#create_generated_clock -name {CK25M175} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 26224 -divide_by 100000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] -#create_generated_clock -name {CK17M734475} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 184734 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] -#create_generated_clock -name {CK8M867237} \ -# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ -# -duty_cycle 50/1 -multiply_by 92367 -divide_by 1000000 \ -# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] -# - -# {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -#create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 8 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -#create_generated_clock -name {clk_2M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -duty_cycle 50/1 -multiply_by 1 -divide_by 224 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_registers {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK2Mi}] -#create_generated_clock -name {clk_15611} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -duty_cycle 50/1 -multiply_by 1 -divide_by 28698 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_registers {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK15611i}] - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -derive_clock_uncertainty - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -#************************************************************** - -#set_clock_groups -asynchronous -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] -group [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -group [get_clocks { }] - -#************************************************************** -# Set False Path -#************************************************************** - -set_false_path -from [get_ports {KEY*}] -set_false_path -from [get_ports {BTN_*}] -set_false_path -to [get_ports {LED_*}] -set_false_path -to [get_ports {VGA_*}] -set_false_path -to [get_ports {AUDIO_SPDIF}] -set_false_path -to [get_ports {AUDIO_L}] -set_false_path -to [get_ports {AUDIO_R}] - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/sharpmz-lite.srf b/sharpmz-lite.srf deleted file mode 100644 index 96a7c6e..0000000 --- a/sharpmz-lite.srf +++ /dev/null @@ -1,17 +0,0 @@ -{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(15): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(14): Argument is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(32): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(594): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/sharpmz-lite_assignment_defaults.qdf b/sharpmz-lite_assignment_defaults.qdf deleted file mode 100644 index 3420a0f..0000000 --- a/sharpmz-lite_assignment_defaults.qdf +++ /dev/null @@ -1,808 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition -# Date created = 18:06:35 June 18, 2018 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. This file was generated -# automatically by the Quartus Prime software and is used -# to preserve global assignments across Quartus Prime versions. -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off -set_global_assignment -name IP_COMPONENT_INTERNAL Off -set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On -set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off -set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off -set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db -set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off -set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off -set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off -set_global_assignment -name HC_OUTPUT_DIR hc_output -set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off -set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On -set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off -set_global_assignment -name REVISION_TYPE Base -family "Arria V" -set_global_assignment -name REVISION_TYPE Base -family "Stratix V" -set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" -set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name DO_COMBINED_ANALYSIS Off -set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off -set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off -set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off -set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off -set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On -set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" -set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" -set_global_assignment -name OPTIMIZATION_MODE Balanced -set_global_assignment -name ALLOW_REGISTER_MERGING On -set_global_assignment -name ALLOW_REGISTER_DUPLICATION On -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V" -set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V" -set_global_assignment -name MUX_RESTRUCTURE Auto -set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off -set_global_assignment -name ENABLE_IP_DEBUG Off -set_global_assignment -name SAVE_DISK_SPACE On -set_global_assignment -name OCP_HW_EVAL -value ENABLE -set_global_assignment -name DEVICE_FILTER_PACKAGE Any -set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name TRUE_WYSIWYG_FLOW Off -set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off -set_global_assignment -name STATE_MACHINE_PROCESSING Auto -set_global_assignment -name SAFE_STATE_MACHINE Off -set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On -set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On -set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off -set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 -set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 -set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On -set_global_assignment -name PARALLEL_SYNTHESIS On -set_global_assignment -name DSP_BLOCK_BALANCING Auto -set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" -set_global_assignment -name NOT_GATE_PUSH_BACK On -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off -set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On -set_global_assignment -name IGNORE_CARRY_BUFFERS Off -set_global_assignment -name IGNORE_CASCADE_BUFFERS Off -set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_LCELL_BUFFERS Off -set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO -set_global_assignment -name IGNORE_SOFT_BUFFERS On -set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off -set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off -set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On -set_global_assignment -name AUTO_GLOBAL_OE_MAX On -set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off -set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut -set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name ALLOW_XOR_GATE_USAGE On -set_global_assignment -name AUTO_LCELL_INSERTION On -set_global_assignment -name CARRY_CHAIN_LENGTH 48 -set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 -set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 -set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off -set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On -set_global_assignment -name PRPOF_ID Off -set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off -set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On -set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" -set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" -set_global_assignment -name USE_CONF_DONE AUTO -set_global_assignment -name USE_PWRMGT_SCL AUTO -set_global_assignment -name USE_PWRMGT_SDA AUTO -set_global_assignment -name USE_PWRMGT_ALERT AUTO -set_global_assignment -name USE_INIT_DONE AUTO -set_global_assignment -name USE_CVP_CONFDONE AUTO -set_global_assignment -name USE_SEU_ERROR AUTO -set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On -set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name ENABLE_CONFIGURATION_PINS On -set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off -set_global_assignment -name ENABLE_NCE_PIN Off -set_global_assignment -name ENABLE_BOOT_SEL_PIN On -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF -set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto -set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto -set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name RESERVE_PR_PINS Off -set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off -set_global_assignment -name PR_PINS_OPEN_DRAIN Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name UNUSED_TSD_PINS_GND Off -set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off -set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" -set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 -set_global_assignment -name SEU_FIT_REPORT Off -set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE On -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 -set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" -set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off -set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off -set_global_assignment -name POR_SCHEME "Instant ON" -set_global_assignment -name EN_USER_IO_WEAK_PULLUP On -set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On -set_global_assignment -name POF_VERIFY_PROTECT Off -set_global_assignment -name ENABLE_SPI_MODE_CHECK Off -set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On -set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 -set_global_assignment -name GENERATE_PMSF_FILES On -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name HPS_EARLY_IO_RELEASE Off -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name POWER_HPS_ENABLE Off -set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 -set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off -set_global_assignment -name IGNORE_PARTITIONS Off -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? -set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? -set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? -set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? -set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? -set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? -set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/sharpmz.qpf b/sharpmz.qpf index ef7dcca..82fdcd2 100644 --- a/sharpmz.qpf +++ b/sharpmz.qpf @@ -1,31 +1,2 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition -# Date created = 15:03:54 April 29, 2020 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "17.1" -DATE = "15:03:54 April 29, 2020" - -# Revisions - -PROJECT_REVISION = "sharpmz-lite" +QUARTUS_VERSION = "17.0" PROJECT_REVISION = "sharpmz" diff --git a/sharpmz.qsf b/sharpmz.qsf index 27edd4a..c682eee 100644 --- a/sharpmz.qsf +++ b/sharpmz.qsf @@ -1,358 +1,66 @@ -# -------------------------------------------------------------------------- # +# -------------------------------------------------------------------------- # -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. +# MiSTer project # -# -------------------------------------------------------------------------- # +# WARNING WARNING WARNING: +# Do not add files to project in Quartus IDE! It will mess this file! +# Add the files manually to files.qip file. # -# Quartus Prime -# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition -# Date created = 01:53:32 April 20, 2017 -# -# -------------------------------------------------------------------------- # +# -------------------------------------------------------------------------- -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSEBA6U23I7 set_global_assignment -name TOP_LEVEL_ENTITY sys_top -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" -set_global_assignment -name SEED 1 +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition" -#============================================================ -# ADC -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO -set_location_assignment PIN_U9 -to ADC_CONVST -set_location_assignment PIN_V10 -to ADC_SCK -set_location_assignment PIN_AC4 -to ADC_SDI -set_location_assignment PIN_AD4 -to ADC_SDO +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON +set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MUX_RESTRUCTURE ON +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM +set_global_assignment -name SEED 1 -#============================================================ -# ARDUINO -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] -set_location_assignment PIN_AG9 -to ARDUINO_IO[3] -set_location_assignment PIN_U14 -to ARDUINO_IO[4] -set_location_assignment PIN_U13 -to ARDUINO_IO[5] -set_location_assignment PIN_AG8 -to ARDUINO_IO[6] -set_location_assignment PIN_AH8 -to ARDUINO_IO[7] -set_location_assignment PIN_AF17 -to ARDUINO_IO[8] -set_location_assignment PIN_AE15 -to ARDUINO_IO[9] -set_location_assignment PIN_AF15 -to ARDUINO_IO[10] -set_location_assignment PIN_AG16 -to ARDUINO_IO[11] -set_location_assignment PIN_AH11 -to ARDUINO_IO[12] -set_location_assignment PIN_AH12 -to ARDUINO_IO[13] -set_location_assignment PIN_AH9 -to ARDUINO_IO[14] -set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1" -#============================================================ -# SDIO -#============================================================ -set_location_assignment PIN_AF25 -to SDIO_DAT[0] -set_location_assignment PIN_AF23 -to SDIO_DAT[1] -set_location_assignment PIN_AD26 -to SDIO_DAT[2] -set_location_assignment PIN_AF28 -to SDIO_DAT[3] -set_location_assignment PIN_AF27 -to SDIO_CMD -set_location_assignment PIN_AH26 -to SDIO_CLK -set_location_assignment PIN_AH7 -to SDIO_CD +#enable it only if 8bit indexed mode is used in core +#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* +#set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1" -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD +#do not enable DEBUG_NOHDMI in release! +#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1" -#============================================================ -# VGA -#============================================================ -set_location_assignment PIN_AE17 -to VGA_R[0] -set_location_assignment PIN_AE20 -to VGA_R[1] -set_location_assignment PIN_AF20 -to VGA_R[2] -set_location_assignment PIN_AH18 -to VGA_R[3] -set_location_assignment PIN_AH19 -to VGA_R[4] -set_location_assignment PIN_AF21 -to VGA_R[5] - -set_location_assignment PIN_AE19 -to VGA_G[0] -set_location_assignment PIN_AG15 -to VGA_G[1] -set_location_assignment PIN_AF18 -to VGA_G[2] -set_location_assignment PIN_AG18 -to VGA_G[3] -set_location_assignment PIN_AG19 -to VGA_G[4] -set_location_assignment PIN_AG20 -to VGA_G[5] - -set_location_assignment PIN_AG21 -to VGA_B[0] -set_location_assignment PIN_AA20 -to VGA_B[1] -set_location_assignment PIN_AE22 -to VGA_B[2] -set_location_assignment PIN_AF22 -to VGA_B[3] -set_location_assignment PIN_AH23 -to VGA_B[4] -set_location_assignment PIN_AH21 -to VGA_B[5] - -set_location_assignment PIN_AH22 -to VGA_HS -set_location_assignment PIN_AG24 -to VGA_VS - -set_location_assignment PIN_AH27 -to VGA_EN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* - -#============================================================ -# AUDIO -#============================================================ -set_location_assignment PIN_AC24 -to AUDIO_L -set_location_assignment PIN_AE25 -to AUDIO_R -set_location_assignment PIN_AG26 -to AUDIO_SPDIF -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* - -#============================================================ -# SDRAM -#============================================================ -set_location_assignment PIN_Y11 -to SDRAM_A[0] -set_location_assignment PIN_AA26 -to SDRAM_A[1] -set_location_assignment PIN_AA13 -to SDRAM_A[2] -set_location_assignment PIN_AA11 -to SDRAM_A[3] -set_location_assignment PIN_W11 -to SDRAM_A[4] -set_location_assignment PIN_Y19 -to SDRAM_A[5] -set_location_assignment PIN_AB23 -to SDRAM_A[6] -set_location_assignment PIN_AC23 -to SDRAM_A[7] -set_location_assignment PIN_AC22 -to SDRAM_A[8] -set_location_assignment PIN_C12 -to SDRAM_A[9] -set_location_assignment PIN_AB26 -to SDRAM_A[10] -set_location_assignment PIN_AD17 -to SDRAM_A[11] -set_location_assignment PIN_D12 -to SDRAM_A[12] -set_location_assignment PIN_Y17 -to SDRAM_BA[0] -set_location_assignment PIN_AB25 -to SDRAM_BA[1] - -set_location_assignment PIN_E8 -to SDRAM_DQ[0] -set_location_assignment PIN_V12 -to SDRAM_DQ[1] -set_location_assignment PIN_D11 -to SDRAM_DQ[2] -set_location_assignment PIN_W12 -to SDRAM_DQ[3] -set_location_assignment PIN_AH13 -to SDRAM_DQ[4] -set_location_assignment PIN_D8 -to SDRAM_DQ[5] -set_location_assignment PIN_AH14 -to SDRAM_DQ[6] -set_location_assignment PIN_AF7 -to SDRAM_DQ[7] -set_location_assignment PIN_AE24 -to SDRAM_DQ[8] -set_location_assignment PIN_AD23 -to SDRAM_DQ[9] -set_location_assignment PIN_AE6 -to SDRAM_DQ[10] -set_location_assignment PIN_AE23 -to SDRAM_DQ[11] -set_location_assignment PIN_AG14 -to SDRAM_DQ[12] -set_location_assignment PIN_AD5 -to SDRAM_DQ[13] -set_location_assignment PIN_AF4 -to SDRAM_DQ[14] -set_location_assignment PIN_AH3 -to SDRAM_DQ[15] -set_location_assignment PIN_AG13 -to SDRAM_DQML -set_location_assignment PIN_AF13 -to SDRAM_DQMH - -set_location_assignment PIN_AD20 -to SDRAM_CLK -set_location_assignment PIN_AG10 -to SDRAM_CKE - -set_location_assignment PIN_AA19 -to SDRAM_nWE -set_location_assignment PIN_AA18 -to SDRAM_nCAS -set_location_assignment PIN_Y18 -to SDRAM_nCS -set_location_assignment PIN_W14 -to SDRAM_nRAS - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* - -#============================================================ -# I/O -#============================================================ -set_location_assignment PIN_Y15 -to LED_USER -set_location_assignment PIN_AA15 -to LED_HDD -set_location_assignment PIN_AG28 -to LED_POWER - -set_location_assignment PIN_AH24 -to BTN_USER -set_location_assignment PIN_AG25 -to BTN_OSD -set_location_assignment PIN_AG23 -to BTN_RESET - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* - -#============================================================ -# CLOCK -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 -set_location_assignment PIN_V11 -to FPGA_CLK1_50 -set_location_assignment PIN_Y13 -to FPGA_CLK2_50 -set_location_assignment PIN_E11 -to FPGA_CLK3_50 - -#============================================================ -# HDMI -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS -set_location_assignment PIN_U10 -to HDMI_I2C_SCL -set_location_assignment PIN_AA4 -to HDMI_I2C_SDA -set_location_assignment PIN_T13 -to HDMI_I2S -set_location_assignment PIN_T11 -to HDMI_LRCLK -set_location_assignment PIN_U11 -to HDMI_MCLK -set_location_assignment PIN_T12 -to HDMI_SCLK -set_location_assignment PIN_AG5 -to HDMI_TX_CLK -set_location_assignment PIN_AD19 -to HDMI_TX_DE -set_location_assignment PIN_AD12 -to HDMI_TX_D[0] -set_location_assignment PIN_AE12 -to HDMI_TX_D[1] -set_location_assignment PIN_W8 -to HDMI_TX_D[2] -set_location_assignment PIN_Y8 -to HDMI_TX_D[3] -set_location_assignment PIN_AD11 -to HDMI_TX_D[4] -set_location_assignment PIN_AD10 -to HDMI_TX_D[5] -set_location_assignment PIN_AE11 -to HDMI_TX_D[6] -set_location_assignment PIN_Y5 -to HDMI_TX_D[7] -set_location_assignment PIN_AF10 -to HDMI_TX_D[8] -set_location_assignment PIN_Y4 -to HDMI_TX_D[9] -set_location_assignment PIN_AE9 -to HDMI_TX_D[10] -set_location_assignment PIN_AB4 -to HDMI_TX_D[11] -set_location_assignment PIN_AE7 -to HDMI_TX_D[12] -set_location_assignment PIN_AF6 -to HDMI_TX_D[13] -set_location_assignment PIN_AF8 -to HDMI_TX_D[14] -set_location_assignment PIN_AF5 -to HDMI_TX_D[15] -set_location_assignment PIN_AE4 -to HDMI_TX_D[16] -set_location_assignment PIN_AH2 -to HDMI_TX_D[17] -set_location_assignment PIN_AH4 -to HDMI_TX_D[18] -set_location_assignment PIN_AH5 -to HDMI_TX_D[19] -set_location_assignment PIN_AH6 -to HDMI_TX_D[20] -set_location_assignment PIN_AG6 -to HDMI_TX_D[21] -set_location_assignment PIN_AF9 -to HDMI_TX_D[22] -set_location_assignment PIN_AE8 -to HDMI_TX_D[23] -set_location_assignment PIN_T8 -to HDMI_TX_HS -set_location_assignment PIN_AF11 -to HDMI_TX_INT -set_location_assignment PIN_V13 -to HDMI_TX_VS - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_location_assignment PIN_AH17 -to KEY[0] -set_location_assignment PIN_AH16 -to KEY[1] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] -set_location_assignment PIN_W15 -to LED[0] -set_location_assignment PIN_AA24 -to LED[1] -set_location_assignment PIN_V16 -to LED[2] -set_location_assignment PIN_V15 -to LED[3] -set_location_assignment PIN_AF26 -to LED[4] -set_location_assignment PIN_AE26 -to LED[5] -set_location_assignment PIN_Y16 -to LED[6] -set_location_assignment PIN_AA23 -to LED[7] - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -set_location_assignment PIN_Y24 -to SW[0] -set_location_assignment PIN_W24 -to SW[1] -set_location_assignment PIN_W21 -to SW[2] -set_location_assignment PIN_W20 -to SW[3] - -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" - -set_global_assignment -name CDF_FILE jtag.cdf -set_global_assignment -name QIP_FILE sys/sys.qip -set_global_assignment -name QSYS_FILE sys/vip.qsys - +source sys/sys.tcl +source sys/sys_analog.tcl +source files.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/sharpmz.vhd b/sharpmz.vhd index f0d3b24..e81f37a 100644 --- a/sharpmz.vhd +++ b/sharpmz.vhd @@ -1089,7 +1089,7 @@ begin -- Clocks. -- CLKSYS <= CLKBUS(CKMASTER); -- HPS clock. - CLKVID <= CLKBUS(CKVIDEO); -- Video pixel clock output. + CLKVID <= CLKBUS(CKENVIDEO);--CKVIDEO); -- Video pixel clock output. CLKIOP <= CLKBUS(CKIOP); -- IO Processor Clock. -- Multiplexer -> Signals to enabled hardware. diff --git a/sharpmz_assignment_defaults.qdf b/sharpmz_assignment_defaults.qdf deleted file mode 100644 index c9c4c19..0000000 --- a/sharpmz_assignment_defaults.qdf +++ /dev/null @@ -1,807 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition -# Date created = 18:26:55 June 18, 2018 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. This file was generated -# automatically by the Quartus Prime software and is used -# to preserve global assignments across Quartus Prime versions. -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off -set_global_assignment -name IP_COMPONENT_INTERNAL Off -set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On -set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off -set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off -set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db -set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off -set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off -set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off -set_global_assignment -name HC_OUTPUT_DIR hc_output -set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off -set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On -set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off -set_global_assignment -name REVISION_TYPE Base -family "Arria V" -set_global_assignment -name REVISION_TYPE Base -family "Stratix V" -set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" -set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name DO_COMBINED_ANALYSIS Off -set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off -set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off -set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off -set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off -set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On -set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" -set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" -set_global_assignment -name OPTIMIZATION_MODE Balanced -set_global_assignment -name ALLOW_REGISTER_MERGING On -set_global_assignment -name ALLOW_REGISTER_DUPLICATION On -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V" -set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V" -set_global_assignment -name MUX_RESTRUCTURE Auto -set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off -set_global_assignment -name ENABLE_IP_DEBUG Off -set_global_assignment -name SAVE_DISK_SPACE On -set_global_assignment -name OCP_HW_EVAL Enable -set_global_assignment -name DEVICE_FILTER_PACKAGE Any -set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name TRUE_WYSIWYG_FLOW Off -set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off -set_global_assignment -name STATE_MACHINE_PROCESSING Auto -set_global_assignment -name SAFE_STATE_MACHINE Off -set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On -set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On -set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off -set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 -set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 -set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On -set_global_assignment -name PARALLEL_SYNTHESIS On -set_global_assignment -name DSP_BLOCK_BALANCING Auto -set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" -set_global_assignment -name NOT_GATE_PUSH_BACK On -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off -set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On -set_global_assignment -name IGNORE_CARRY_BUFFERS Off -set_global_assignment -name IGNORE_CASCADE_BUFFERS Off -set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_LCELL_BUFFERS Off -set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO -set_global_assignment -name IGNORE_SOFT_BUFFERS On -set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off -set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off -set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On -set_global_assignment -name AUTO_GLOBAL_OE_MAX On -set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off -set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut -set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name ALLOW_XOR_GATE_USAGE On -set_global_assignment -name AUTO_LCELL_INSERTION On -set_global_assignment -name CARRY_CHAIN_LENGTH 48 -set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 -set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 -set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off -set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On -set_global_assignment -name PRPOF_ID Off -set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off -set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On -set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" -set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" -set_global_assignment -name USE_CONF_DONE AUTO -set_global_assignment -name USE_PWRMGT_SCL AUTO -set_global_assignment -name USE_PWRMGT_SDA AUTO -set_global_assignment -name USE_PWRMGT_ALERT AUTO -set_global_assignment -name USE_INIT_DONE AUTO -set_global_assignment -name USE_CVP_CONFDONE AUTO -set_global_assignment -name USE_SEU_ERROR AUTO -set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On -set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name ENABLE_CONFIGURATION_PINS On -set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off -set_global_assignment -name ENABLE_NCE_PIN Off -set_global_assignment -name ENABLE_BOOT_SEL_PIN On -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF -set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto -set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto -set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name RESERVE_PR_PINS Off -set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off -set_global_assignment -name PR_PINS_OPEN_DRAIN Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name UNUSED_TSD_PINS_GND Off -set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off -set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" -set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 -set_global_assignment -name SEU_FIT_REPORT Off -set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE On -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 -set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" -set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off -set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off -set_global_assignment -name POR_SCHEME "Instant ON" -set_global_assignment -name EN_USER_IO_WEAK_PULLUP On -set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On -set_global_assignment -name POF_VERIFY_PROTECT Off -set_global_assignment -name ENABLE_SPI_MODE_CHECK Off -set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On -set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 -set_global_assignment -name GENERATE_PMSF_FILES On -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name HPS_EARLY_IO_RELEASE Off -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name POWER_HPS_ENABLE Off -set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 -set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off -set_global_assignment -name IGNORE_PARTITIONS Off -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? -set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment 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--git a/sys/alsa.sv b/sys/alsa.sv new file mode 100644 index 0000000..9034389 --- /dev/null +++ b/sys/alsa.sv @@ -0,0 +1,157 @@ +//============================================================================ +// +// ALSA sound support for MiSTer +// (c)2019,2020 Alexey Melnikov +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +module alsa +#( + parameter CLK_RATE = 24576000 +) +( + input reset, + input clk, + + output reg [31:3] ram_address, + input [63:0] ram_data, + output reg ram_req = 0, + input ram_ready, + + input spi_ss, + input spi_sck, + input spi_mosi, + output spi_miso, + + output reg [15:0] pcm_l, + output reg [15:0] pcm_r +); + +reg [60:0] buf_info; +reg [6:0] spicnt = 0; +always @(posedge spi_sck, posedge spi_ss) begin + reg [95:0] spi_data; + + if(spi_ss) spicnt <= 0; + else begin + spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi; + if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]}; + spicnt <= spicnt + 1'd1; + end +end + +assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}]; + +reg [31:0] spi_out = 0; +always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00}; + + +reg [31:3] buf_addr; +reg [18:3] buf_len; +reg [18:3] buf_wptr = 0; + +always @(posedge clk) begin + reg [60:0] data1,data2; + + data1 <= buf_info; + data2 <= data1; + if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2; +end + +reg [2:0] hurryup = 0; +reg [18:3] buf_rptr = 0; + +always @(posedge clk) begin + reg [18:3] len = 0; + reg [1:0] ready = 0; + reg [63:0] readdata; + reg got_first = 0; + reg [7:0] ce_cnt = 0; + reg [1:0] state = 0; + + if(reset) begin + ready <= 0; + ce_cnt <= 0; + state <= 0; + got_first <= 0; + len <= 0; + end + else begin + + //ramp up + if(len[18:14] && (hurryup < 1)) hurryup <= 1; + if(len[18:16] && (hurryup < 2)) hurryup <= 2; + if(len[18:17] && (hurryup < 4)) hurryup <= 4; + + //ramp down + if(!len[18:15] && (hurryup > 2)) hurryup <= 2; + if(!len[18:13] && (hurryup > 1)) hurryup <= 1; + if(!len[18:10]) hurryup <= 0; + + if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1; + + case(state) + 0: if(!ce_sample) begin + if(ready) begin + if(ce_cnt) begin + {readdata[31:0],pcm_r,pcm_l} <= readdata; + ready <= ready - 1'd1; + ce_cnt <= ce_cnt - 1'd1; + end + end + else if(buf_rptr != buf_wptr) begin + if(~got_first) begin + buf_rptr <= buf_wptr; + got_first <= 1; + end + else begin + ram_address <= buf_addr + buf_rptr; + ram_req <= ~ram_req; + buf_rptr <= buf_rptr + 1'd1; + len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr); + state <= 1; + end + end + else begin + len <= 0; + ce_cnt <= 0; + hurryup <= 0; + end + end + 1: if(ram_ready) begin + ready <= 2; + readdata <= ram_data; + if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len; + state <= 0; + end + endcase + end +end + +reg ce_sample; +always @(posedge clk) begin + reg [31:0] acc = 0; + + ce_sample <= 0; + acc <= acc + 48000 + {hurryup,6'd0}; + if(acc >= CLK_RATE) begin + acc <= acc - CLK_RATE; + ce_sample <= 1; + end +end + +endmodule diff --git a/sys/arcade_video.v b/sys/arcade_video.v new file mode 100644 index 0000000..e47a150 --- /dev/null +++ b/sys/arcade_video.v @@ -0,0 +1,302 @@ +//============================================================================ +// +// Copyright (C) 2017-2020 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +////////////////////////////////////////////////////////// +// DW: +// 6 : 2R 2G 2B +// 8 : 3R 3G 2B +// 9 : 3R 3G 3B +// 12 : 4R 4G 4B +// 24 : 8R 8G 8B + +module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1) +( + input clk_video, + input ce_pix, + + input[DW-1:0] RGB_in, + input HBlank, + input VBlank, + input HSync, + input VSync, + + output CLK_VIDEO, + output CE_PIXEL, + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, + output VGA_HS, + output VGA_VS, + output VGA_DE, + output [1:0] VGA_SL, + + input [2:0] fx, + input forced_scandoubler, + inout [21:0] gamma_bus +); + +assign CLK_VIDEO = clk_video; + +wire hs_fix,vs_fix; +sync_fix sync_v(CLK_VIDEO, HSync, hs_fix); +sync_fix sync_h(CLK_VIDEO, VSync, vs_fix); + +reg [DW-1:0] RGB_fix; + +reg CE,HS,VS,HBL,VBL; +always @(posedge CLK_VIDEO) begin + reg old_ce; + old_ce <= ce_pix; + CE <= 0; + if(~old_ce & ce_pix) begin + CE <= 1; + HS <= hs_fix; + if(~HS & hs_fix) VS <= vs_fix; + + RGB_fix <= RGB_in; + HBL <= HBlank; + if(HBL & ~HBlank) VBL <= VBlank; + end +end + +wire [7:0] R,G,B; + +generate + if(DW == 6) begin + assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]}; + assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]}; + assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; + end + else if(DW == 8) begin + assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]}; + assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]}; + assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; + end + else if(DW == 9) begin + assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]}; + assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]}; + assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]}; + end + else if(DW == 12) begin + assign R = {RGB_fix[11:8],RGB_fix[11:8]}; + assign G = {RGB_fix[7:4],RGB_fix[7:4]}; + assign B = {RGB_fix[3:0],RGB_fix[3:0]}; + end + else begin // 24 + assign R = RGB_fix[23:16]; + assign G = RGB_fix[15:8]; + assign B = RGB_fix[7:0]; + end +endgenerate + +assign VGA_SL = sl[1:0]; +wire [2:0] sl = fx ? fx - 1'd1 : 3'd0; +wire scandoubler = fx || forced_scandoubler; + +video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer +( + .CLK_VIDEO(CLK_VIDEO), + .ce_pix(CE), + .CE_PIXEL(CE_PIXEL), + + .scandoubler(scandoubler), + .hq2x(fx==1), + .gamma_bus(gamma_bus), + + .R((DW!=24) ? R[7:4] : R), + .G((DW!=24) ? G[7:4] : G), + .B((DW!=24) ? B[7:4] : B), + + .HSync (HS), + .VSync (VS), + .HBlank(HBL), + .VBlank(VBL), + + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .VGA_DE(VGA_DE) +); + +endmodule + +//============================================================================ +// +// Screen +90/-90 deg. rotation +// Copyright (C) 2020 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +module screen_rotate +( + input CLK_VIDEO, + input CE_PIXEL, + + input [7:0] VGA_R, + input [7:0] VGA_G, + input [7:0] VGA_B, + input VGA_HS, + input VGA_VS, + input VGA_DE, + + input rotate_ccw, + input no_rotate, + + output FB_EN, + output [4:0] FB_FORMAT, + output [11:0] FB_WIDTH, + output [11:0] FB_HEIGHT, + output [31:0] FB_BASE, + output [13:0] FB_STRIDE, + input FB_VBL, + input FB_LL, + + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + output DDRAM_RD +); + +parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB + +assign DDRAM_CLK = CLK_VIDEO; +assign DDRAM_BURSTCNT = 1; +assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]}; +assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F; +assign DDRAM_DIN = {ram_data,ram_data}; +assign DDRAM_WE = ram_wr; +assign DDRAM_RD = 0; + +assign FB_EN = fb_en[2]; +assign FB_FORMAT = 5'b00110; +assign FB_BASE = {MEM_BASE,o_fb,23'd0}; +assign FB_WIDTH = vsz; +assign FB_HEIGHT = hsz; +assign FB_STRIDE = stride; + +function [1:0] buf_next; + input [1:0] a,b; + begin + buf_next = 1; + if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2; + if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0; + end +endfunction + +reg [1:0] i_fb,o_fb; +always @(posedge CLK_VIDEO) begin + reg old_vbl,old_vs; + old_vbl <= FB_VBL; + old_vs <= VGA_VS; + + if(FB_LL) begin + if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]}; + if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]}; + end + else begin + if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb); + if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb); + end +end + +initial begin + fb_en = 0; +end + +reg [2:0] fb_en = 0; +reg [11:0] hsz = 320, vsz = 240; +reg [11:0] bwidth; +reg [22:0] bufsize; +always @(posedge CLK_VIDEO) begin + reg [11:0] hcnt = 0, vcnt = 0; + reg old_vs, old_de; + + if(CE_PIXEL) begin + old_vs <= VGA_VS; + old_de <= VGA_DE; + + hcnt <= hcnt + 1'd1; + if(~old_de & VGA_DE) begin + hcnt <= 1; + vcnt <= vcnt + 1'd1; + end + if(old_de & ~VGA_DE) hsz <= hcnt; + if(~old_vs & VGA_VS) begin + vsz <= vcnt; + bwidth <= vcnt + 2'd3; + vcnt <= 0; + fb_en <= {fb_en[1:0], ~no_rotate}; + end + if(old_vs & ~VGA_VS) bufsize <= hsz * stride; + end +end + +wire [13:0] stride = {bwidth[11:2], 4'd0}; + +reg [22:0] ram_addr, next_addr; +reg [31:0] ram_data; +reg ram_wr; +always @(posedge CLK_VIDEO) begin + reg [13:0] hcnt = 0; + reg old_vs, old_de; + + ram_wr <= 0; + if(CE_PIXEL) begin + old_vs <= VGA_VS; + old_de <= VGA_DE; + + if(~old_vs & VGA_VS) begin + next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00}; + hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00}; + end + if(VGA_DE) begin + ram_wr <= 1; + ram_data <= {VGA_B,VGA_G,VGA_R}; + ram_addr <= next_addr; + next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride); + end + if(old_de & ~VGA_DE) begin + next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt; + hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4); + end + end +end + +endmodule diff --git a/sys/ascal.vhd b/sys/ascal.vhd new file mode 100644 index 0000000..188d280 --- /dev/null +++ b/sys/ascal.vhd @@ -0,0 +1,2564 @@ +-------------------------------------------------------------------------------- +-- AVALON SCALER +-------------------------------------------------------------------------------- +-- TEMLIB 2018 - 2020 +-------------------------------------------------------------------------------- +-- This code can be freely distributed and used for any purpose, but, if you +-- find any bug, or want to suggest an enhancement, you ought to send a mail +-- to info@temlib.org. +-------------------------------------------------------------------------------- + +-- Features +-- - Arbitrary output video format +-- - Autodetect input image size or fixed window +-- - Progressive and interlaced input +-- - Interpolation +-- Upscaling : Nearest, Bilinear, Sharp Bilinear, Bicubic, Polyphase +-- Downscaling : Nearest, Bilinear +-- - Avalon bus interface with 128 or 64 bits DATA +-- - Optional triple buffering +-- - Support for external low lag syntonization + +-------------------------------------------- +-- Downscaling +-- - Horizontal and vertical up-/down-scaling are independant. +-- - Downscaling, H and/or V, supports only nearest-neighbour and bilinear +-- filtering. +-- - For interlaced video, when the vertical size is lower than a deinterlaced +-- frame size (2x half-frame), the scaler processes only half-frames +-- and upscales (when the output size is between 1x an 2x) or downscales (size +-- below 1x) them. + +-------------------------------------------- +-- 5 clock domains +-- i_xxx : Input video +-- o_xxx : Output video +-- avl_xxx : Avalon memory bus +-- poly_xxx : Polyphase filters memory +-- pal_xxx : Framebuffer mode 8bpp palette. + +-------------------------------------------- +-- O_FB_FORMAT : Framebuffer format +-- [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp +-- [3] : 0=16bits 565 1=16bits 1555 +-- [4] : 0=RGB 1=BGR (for 16/24/32 modes) +-- [5] : TBD + +-------------------------------------------- +-- Image header. When HEADER = TRUE +-- Header Address = RAMBASE +-- Image Address = RAMBASE + HEADER_SIZE + +-- Header (Bytes. Big Endian.) +-- 0 : Type = 1 +-- 1 : Pixel format +-- 0 : 16 bits/pixel, RGB : RRRRRGGGGGGBBBBB +-- 1 : 24 bits/pixel, RGB +-- 2 : 32 bits/pixel, RGB0 + +-- 3:2 : Header size : Offset to start of picture (= N_BURST). 12 bits +-- 5:4 : Attributes +-- b0 ; Interlaced +-- b1 : Field number +-- b2 : Horizontal downscaled +-- b3 : Vertical downscaled +-- b4 : Triple buffered +-- b7-5 : Frame counter +-- 7:6 : Image width. Pixels. 12 bits +-- 9:8 : Image height. Pixels. 12 bits +-- 11:10 : Line length. Bytes. +-- 13:12 : Output width. Pixels. 12 bits +-- 15:14 : Output height. Pixels. 12 bits +-------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +-- MODE[2:0] +-- 000 : Nearest +-- 001 : Bilinear +-- 010 : Sharp Bilinear +-- 011 : Bicubic +-- 100 : Polyphase +-- 101 : TBD +-- 110 : TBD +-- 111 : TBD + +-- MODE[3] +-- 0 : Direct. Single framebuffer. +-- 1 : Triple buffering + +-- MODE[4] : TBD + +-- MASK : Enable / Disable selected interpoler +-- 0:Nearest 1:Bilinear 2:SharpBilinear 3:Bicubic 4:Polyphase +-- RAMBASE : RAM base address for framebuffer +-- RAMSIZE : RAM allocated for one framebuffer (needs x3 if triple-buffering) +-- Must be a power of two +-- INTER : True=Autodetect interlaced video False=Force progressive scan +-- HEADER : True=Add image properties header +-- PALETTE : Enable palette for framebuffer 8bpp mode +-- PALETTE2 : Enable palette for framebuffer 8bpp mode supplied by core +-- DOWNSCALE : True=Support downscaling False=Downscaling disabled +-- BYTESWAP : Little/Big endian byte swap +-- FRAC : Fractional bits, subpixel resolution +-- OHRES : Max. output horizontal resolution. Must be a power of two. +-- (Used for sizing line buffers) +-- IHRES : Max. input horizontal resolution. Must be a power of two. +-- (Used for sizing line buffers) +-- N_DW : Avalon data bus width. 64 or 128 bits +-- N_AW : Avalon address bus width +-- N_BURST : Burst size in bytes. Power of two. + +ENTITY ascal IS + GENERIC ( + MASK : unsigned(7 DOWNTO 0) :=x"FF"; + RAMBASE : unsigned(31 DOWNTO 0); + RAMSIZE : unsigned(31 DOWNTO 0) := x"0080_0000"; -- =8MB + INTER : boolean := true; + HEADER : boolean := true; + DOWNSCALE : boolean := true; + BYTESWAP : boolean := true; + PALETTE : boolean := true; + PALETTE2 : boolean := true; + FRAC : natural RANGE 4 TO 6 :=4; + OHRES : natural RANGE 1 TO 4096 :=2048; + IHRES : natural RANGE 1 TO 2048 :=2048; + N_DW : natural RANGE 64 TO 128 := 128; + N_AW : natural RANGE 8 TO 32 := 32; + N_BURST : natural := 256 -- 256 bytes per burst + ); + PORT ( + ------------------------------------ + -- Input video + i_r : IN unsigned(7 DOWNTO 0); + i_g : IN unsigned(7 DOWNTO 0); + i_b : IN unsigned(7 DOWNTO 0); + i_hs : IN std_logic; -- H sync + i_vs : IN std_logic; -- V sync + i_fl : IN std_logic; -- Interlaced field + i_de : IN std_logic; -- Display Enable + i_ce : IN std_logic; -- Clock Enable + i_clk : IN std_logic; -- Input clock + + ------------------------------------ + -- Output video + o_r : OUT unsigned(7 DOWNTO 0); + o_g : OUT unsigned(7 DOWNTO 0); + o_b : OUT unsigned(7 DOWNTO 0); + o_hs : OUT std_logic; -- H sync + o_vs : OUT std_logic; -- V sync + o_de : OUT std_logic; -- Display Enable + o_vbl : OUT std_logic; -- V blank + o_ce : IN std_logic; -- Clock Enable + o_clk : IN std_logic; -- Output clock + + -- Border colour R G B + o_border : IN unsigned(23 DOWNTO 0) := x"000000"; + + ------------------------------------ + -- Framebuffer mode + o_fb_ena : IN std_logic :='0'; -- Enable Framebuffer Mode + o_fb_hsize : IN natural RANGE 0 TO 4095 :=0; + o_fb_vsize : IN natural RANGE 0 TO 4095 :=0; + o_fb_format : IN unsigned(5 DOWNTO 0) :="000100"; + o_fb_base : IN unsigned(31 DOWNTO 0) :=x"0000_0000"; + o_fb_stride : IN unsigned(13 DOWNTO 0) :=(OTHERS =>'0'); + + -- Framebuffer palette in 8bpp mode + pal1_clk : IN std_logic :='0'; + pal1_dw : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0 + pal1_dr : OUT unsigned(47 DOWNTO 0) :=x"000000000000"; + pal1_a : IN unsigned(6 DOWNTO 0) :="0000000"; -- Colour index/2 + pal1_wr : IN std_logic :='0'; + + pal_n : IN std_logic :='0'; + + pal2_clk : IN std_logic :='0'; + pal2_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B + pal2_dr : OUT unsigned(23 DOWNTO 0) :=x"000000"; + pal2_a : IN unsigned(7 DOWNTO 0) :="00000000"; -- Colour index + pal2_wr : IN std_logic :='0'; + + ------------------------------------ + -- Low lag PLL tuning + o_lltune : OUT unsigned(15 DOWNTO 0); + + ------------------------------------ + -- Input video parameters + iauto : IN std_logic :='1'; -- 1=Autodetect image size 0=Choose window + himin : IN natural RANGE 0 TO 4095 :=0; -- MIN < MAX, MIN >=0, MAX < DISP + himax : IN natural RANGE 0 TO 4095 :=0; + vimin : IN natural RANGE 0 TO 4095 :=0; + vimax : IN natural RANGE 0 TO 4095 :=0; + + -- Detected input image size + i_hdmax : OUT natural RANGE 0 TO 4095; + i_vdmax : OUT natural RANGE 0 TO 4095; + + -- Output video parameters + run : IN std_logic :='1'; -- 1=Enable output image. 0=No image + freeze : IN std_logic :='0'; -- 1=Disable framebuffer writes + mode : IN unsigned(4 DOWNTO 0); + -- SYNC |_________________________/"""""""""\_______| + -- DE |""""""""""""""""""\________________________| + -- RGB | <#IMAGE#> ^HDISP | + -- ^HMIN ^HMAX ^HSSTART ^HSEND ^HTOTAL + htotal : IN natural RANGE 0 TO 4095; + hsstart : IN natural RANGE 0 TO 4095; + hsend : IN natural RANGE 0 TO 4095; + hdisp : IN natural RANGE 0 TO 4095; + hmin : IN natural RANGE 0 TO 4095; + hmax : IN natural RANGE 0 TO 4095; -- 0 <= hmin < hmax < hdisp + vtotal : IN natural RANGE 0 TO 4095; + vsstart : IN natural RANGE 0 TO 4095; + vsend : IN natural RANGE 0 TO 4095; + vdisp : IN natural RANGE 0 TO 4095; + vmin : IN natural RANGE 0 TO 4095; + vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp + + -- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp + format : IN unsigned(1 DOWNTO 0) :="01"; + + ------------------------------------ + -- Polyphase filter coefficients + -- Order : + -- [Horizontal] [Vertical] + -- [0]...[2**FRAC-1] + -- [-1][0][1][2] + poly_clk : IN std_logic; + poly_dw : IN unsigned(8 DOWNTO 0); + poly_a : IN unsigned(FRAC+2 DOWNTO 0); + poly_wr : IN std_logic; + + ------------------------------------ + -- Avalon + avl_clk : IN std_logic; -- Avalon clock + avl_waitrequest : IN std_logic; + avl_readdata : IN std_logic_vector(N_DW-1 DOWNTO 0); + avl_readdatavalid : IN std_logic; + avl_burstcount : OUT std_logic_vector(7 DOWNTO 0); + avl_writedata : OUT std_logic_vector(N_DW-1 DOWNTO 0); + avl_address : OUT std_logic_vector(N_AW-1 DOWNTO 0); + avl_write : OUT std_logic; + avl_read : OUT std_logic; + avl_byteenable : OUT std_logic_vector(N_DW/8-1 DOWNTO 0); + + ------------------------------------ + reset_na : IN std_logic + ); + +BEGIN + ASSERT N_DW=64 OR N_DW=128 REPORT "DW" SEVERITY failure; + +END ENTITY ascal; + +--############################################################################## + +ARCHITECTURE rtl OF ascal IS + + CONSTANT MASK_NEAREST : natural :=0; + CONSTANT MASK_BILINEAR : natural :=1; + CONSTANT MASK_SHARP_BILINEAR : natural :=2; + CONSTANT MASK_BICUBIC : natural :=3; + CONSTANT MASK_POLY : natural :=4; + + ---------------------------------------------------------- + FUNCTION ilog2 (CONSTANT v : natural) RETURN natural IS + VARIABLE r : natural := 1; + VARIABLE n : natural := 0; + BEGIN + WHILE v>r LOOP + n:=n+1; + r:=r*2; + END LOOP; + RETURN n; + END FUNCTION ilog2; + FUNCTION to_std_logic (a : boolean) RETURN std_logic IS + BEGIN + IF a THEN RETURN '1'; + ELSE RETURN '0'; + END IF; + END FUNCTION to_std_logic; + + ---------------------------------------------------------- + CONSTANT NB_BURST : natural :=ilog2(N_BURST); + CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits + CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length + + ---------------------------------------------------------- + TYPE arr_dw IS ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0); + + TYPE type_pix IS RECORD + r,g,b : unsigned(7 DOWNTO 0); -- 0.8 + END RECORD; + TYPE arr_pix IS ARRAY (natural RANGE <>) OF type_pix; + ATTRIBUTE ramstyle : string; + + SUBTYPE uint12 IS natural RANGE 0 TO 4095; + SUBTYPE uint13 IS natural RANGE 0 TO 8191; + + TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0); + TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0); + TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0); + TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255; + TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12; + + ---------------------------------------------------------- + -- Input image + SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic; + SIGNAL i_ppix : type_pix; + SIGNAL i_freeze : std_logic; + SIGNAL i_count : unsigned(2 DOWNTO 0); + SIGNAL i_hsize,i_hmin,i_hmax,i_hcpt : uint12; + SIGNAL i_hrsize,i_vrsize : uint12; + SIGNAL i_himax,i_vimax : uint12; + SIGNAL i_vsize,i_vmaxmin,i_vmin,i_vmax,i_vcpt : uint12; + SIGNAL i_iauto : std_logic; + SIGNAL i_mode : unsigned(4 DOWNTO 0); + SIGNAL i_format : unsigned(1 DOWNTO 0); + SIGNAL i_ven,i_sof : std_logic; + SIGNAL i_wr : std_logic; + SIGNAL i_divstart,i_divrun : std_logic; + SIGNAL i_de_pre,i_vs_pre,i_fl_pre : std_logic; + SIGNAL i_de_delay : natural RANGE 0 TO 31; + SIGNAL i_intercnt : natural RANGE 0 TO 3; + SIGNAL i_inter,i_half,i_flm : std_logic; + SIGNAL i_write,i_wreq,i_alt,i_line,i_wline,i_wline_mem : std_logic; + SIGNAL i_walt,i_walt_mem,i_wreq_mem : std_logic; + SIGNAL i_wdelay : natural RANGE 0 TO 7; + SIGNAL i_push,i_pushend,i_pushend2 : std_logic; + SIGNAL i_eol : std_logic; + SIGNAL i_pushhead,i_pushhead2,i_pushhead3 : std_logic; + SIGNAL i_hburst,i_hbcpt : natural RANGE 0 TO 31; + SIGNAL i_shift : unsigned(0 TO 119) := (OTHERS =>'0'); + SIGNAL i_head : unsigned(127 DOWNTO 0); + SIGNAL i_acpt : natural RANGE 0 TO 15; + SIGNAL i_dpram : arr_dw(0 TO BLEN*2-1); + ATTRIBUTE ramstyle OF i_dpram : SIGNAL IS "no_rw_check"; + SIGNAL i_endframe0,i_endframe1,i_vss : std_logic; + SIGNAL i_wad : natural RANGE 0 TO BLEN*2-1; + SIGNAL i_dw : unsigned(N_DW-1 DOWNTO 0); + SIGNAL i_adrs,i_adrsi,i_wadrs,i_wadrs_mem : unsigned(31 DOWNTO 0); + SIGNAL i_reset_na : std_logic; + SIGNAL i_hnp,i_vnp : std_logic; + SIGNAL i_mem : arr_pix(0 TO IHRES-1); -- Downscale line buffer + ATTRIBUTE ramstyle OF i_mem : SIGNAL IS "no_rw_check"; + SIGNAL i_ohsize,i_ovsize : uint12; + SIGNAL i_vdivi : unsigned(12 DOWNTO 0); + SIGNAL i_vdivr : unsigned(24 DOWNTO 0); + SIGNAL i_div : unsigned(16 DOWNTO 0); + SIGNAL i_dir : unsigned(11 DOWNTO 0); + SIGNAL i_h_frac,i_v_frac : unsigned(11 DOWNTO 0); + SIGNAL i_hacc,i_vacc : uint13; + SIGNAL i_hdown,i_vdown : std_logic; + SIGNAL i_divcpt : natural RANGE 0 TO 36; + SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRES-1; + SIGNAL i_lwr,i_bil : std_logic; + SIGNAL i_ldw,i_ldrm : type_pix; + SIGNAL i_hpixp,i_hpix0,i_hpix1,i_hpix2,i_hpix3,i_hpix4 : type_pix; + SIGNAL i_hpix,i_pix : type_pix; + SIGNAL i_hnp1,i_hnp2,i_hnp3,i_hnp4 : std_logic; + SIGNAL i_ven1,i_ven2,i_ven3,i_ven4,i_ven5,i_ven6 : std_logic; + + ---------------------------------------------------------- + -- Avalon + TYPE type_avl_state IS (sIDLE,sWRITE,sREAD); + SIGNAL avl_state : type_avl_state; + SIGNAL avl_write_i,avl_write_sync,avl_write_sync2 : std_logic; + SIGNAL avl_read_i,avl_read_sync,avl_read_sync2 : std_logic; + SIGNAL avl_read_pulse,avl_write_pulse : std_logic; + SIGNAL avl_read_sr,avl_write_sr,avl_read_clr,avl_write_clr : std_logic; + SIGNAL avl_rad,avl_rad_c,avl_wad : natural RANGE 0 TO 2*BLEN-1; + SIGNAL avl_walt,avl_wline,avl_rline : std_logic; + SIGNAL avl_dw,avl_dr : unsigned(N_DW-1 DOWNTO 0); + SIGNAL avl_wr : std_logic; + SIGNAL avl_readdataack,avl_readack : std_logic; + SIGNAL avl_radrs,avl_wadrs : unsigned(31 DOWNTO 0); + SIGNAL avl_i_offset0,avl_o_offset0 : unsigned(31 DOWNTO 0); + SIGNAL avl_i_offset1,avl_o_offset1 : unsigned(31 DOWNTO 0); + SIGNAL avl_reset_na : std_logic; + SIGNAL avl_o_vs_sync,avl_o_vs : std_logic; + SIGNAL avl_fb_ena : std_logic; + + FUNCTION buf_next(a,b : natural RANGE 0 TO 2; freeze : std_logic := '0') RETURN natural IS + BEGIN + IF (freeze='1') THEN RETURN a; END IF; + IF (a=0 AND b=1) OR (a=1 AND b=0) THEN RETURN 2; END IF; + IF (a=1 AND b=2) OR (a=2 AND b=1) THEN RETURN 0; END IF; + RETURN 1; + END FUNCTION; + FUNCTION buf_offset(b : natural RANGE 0 TO 2; + base : unsigned(31 DOWNTO 0); + size : unsigned(31 DOWNTO 0)) RETURN unsigned IS + BEGIN + IF b=1 THEN RETURN base+size; END IF; + IF b=2 THEN RETURN base+(size(30 DOWNTO 0) & '0'); END IF; + RETURN base; + END FUNCTION; + + ---------------------------------------------------------- + -- Output + SIGNAL o_run : std_logic; + SIGNAL o_freeze : std_logic; + SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0); + SIGNAL o_format : unsigned(5 DOWNTO 0); + SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0); + SIGNAL o_fb_pal_dr2 : unsigned(23 DOWNTO 0); + SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0); + SIGNAL pal_idx: unsigned(7 DOWNTO 0); + SIGNAL pal_idx_lsb: std_logic; + SIGNAL pal1_mem : arr_uv48(0 TO 127); + SIGNAL pal2_mem : arr_uv24(0 TO 255); + ATTRIBUTE ramstyle of pal1_mem : signal is "no_rw_check"; + ATTRIBUTE ramstyle of pal2_mem : signal is "no_rw_check"; + SIGNAL o_htotal,o_hsstart,o_hsend : uint12; + SIGNAL o_hmin,o_hmax,o_hdisp : uint12; + SIGNAL o_hsize,o_vsize : uint12; + SIGNAL o_vtotal,o_vsstart,o_vsend : uint12; + SIGNAL o_vmin,o_vmax,o_vdisp : uint12; + SIGNAL o_divcpt : natural RANGE 0 TO 36; + SIGNAL o_iendframe0,o_iendframe02,o_iendframe1,o_iendframe12 : std_logic; + SIGNAL o_bufup0,o_bufup1,o_inter : std_logic; + SIGNAL o_ibuf0,o_ibuf1,o_obuf0,o_obuf1 : natural RANGE 0 TO 2; + TYPE enum_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD); + SIGNAL o_state : enum_o_state; + TYPE enum_o_copy IS (sWAIT,sSHIFT,sCOPY); + SIGNAL o_copy : enum_o_copy; + SIGNAL o_pshift : natural RANGE 0 TO 15; + SIGNAL o_readack,o_readack_sync,o_readack_sync2 : std_logic; + SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic; + SIGNAL o_copyv : unsigned(0 TO 8); + SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address + SIGNAL o_adrs_pre : natural RANGE 0 TO 2**24-1; + SIGNAL o_stride : unsigned(13 DOWNTO 0); + SIGNAL o_adrsa,o_adrsb,o_rline : std_logic; + SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1; + SIGNAL o_adturn : std_logic; + SIGNAL o_dr : unsigned(N_DW-1 DOWNTO 0); + SIGNAL o_shift : unsigned(0 TO N_DW+15); + SIGNAL o_sh,o_sh1,o_sh2,o_sh3,o_sh4 : std_logic; + SIGNAL o_reset_na : std_logic; + SIGNAL o_dpram : arr_dw(0 TO BLEN*2-1); + ATTRIBUTE ramstyle OF o_dpram : SIGNAL IS "no_rw_check"; + SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRES-1); + ATTRIBUTE ramstyle OF o_line0 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_line1 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_line2 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_line3 : SIGNAL IS "no_rw_check"; + SIGNAL o_wadl,o_radl : natural RANGE 0 TO OHRES-1; + SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix; + SIGNAL o_wr : unsigned(3 DOWNTO 0); + SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3 : uint12; + SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12; + SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767; + + SIGNAL o_vfrac,o_hfrac,o_hfrac1,o_hfrac2,o_hfrac3,o_hfrac4 : unsigned(11 DOWNTO 0); + SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1; + SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 5); + SIGNAL o_hsp,o_vss : std_logic; + SIGNAL o_read,o_read_pre : std_logic; + SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2; + SIGNAL o_hburst,o_hbcpt : natural RANGE 0 TO 31; + SIGNAL o_fload : natural RANGE 0 TO 3; + SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO + SIGNAL o_dshi : natural RANGE 0 TO 3; + SIGNAL o_first,o_last,o_last1,o_last2 : std_logic; + SIGNAL o_lastt1,o_lastt2,o_lastt3,o_lastt4 : std_logic; + SIGNAL o_alt,o_altx : unsigned(3 DOWNTO 0); + SIGNAL o_hdown,o_vdown : std_logic; + SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2); + TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15; + SIGNAL o_off : arr_uint4(0 TO 2); + SIGNAL o_bibu : std_logic :='0'; + SIGNAL o_dcptv : arr_uint12(1 TO 8); + SIGNAL o_dcpt : uint12; + SIGNAL o_hpixs,o_hpix0,o_hpix1,o_hpix2,o_hpix3 : type_pix; + SIGNAL o_hpixq,o_vpixq,o_vpixq1 : arr_pix(0 TO 3); + + SIGNAL o_vpe : std_logic; + SIGNAL o_div,o_div2 : unsigned(18 DOWNTO 0); --uint12; + SIGNAL o_dir,o_dir2 : unsigned(11 DOWNTO 0); + SIGNAL o_vdivi : unsigned(12 DOWNTO 0); + SIGNAL o_vdivr : unsigned(24 DOWNTO 0); + SIGNAL o_divstart : std_logic; + SIGNAL o_divrun : std_logic; + SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0); + + ----------------------------------------------------------------------------- + FUNCTION shift_ishift(shift : unsigned(0 TO 119); + pix : type_pix; + format : unsigned(1 DOWNTO 0)) RETURN unsigned IS + BEGIN + CASE format IS + WHEN "01" => -- 24bpp + RETURN shift(24 TO 119) & pix.r & pix.g & pix.b; + WHEN "10" => -- 32bpp + RETURN shift(32 TO 119) & pix.r & pix.g & pix.b & x"00"; + WHEN OTHERS => -- 16bpp 565 + RETURN shift(16 TO 119) & + pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & + pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); + END CASE; + END FUNCTION; + + FUNCTION shift_ipack(i_dw : unsigned(N_DW-1 DOWNTO 0); + acpt : natural RANGE 0 TO 15; + shift : unsigned(0 TO 119); + pix : type_pix; + format : unsigned(1 DOWNTO 0)) RETURN unsigned IS + VARIABLE dw : unsigned(N_DW-1 DOWNTO 0); + BEGIN + dw:=i_dw; + CASE format IS + WHEN "01" => -- 24bpp + IF N_DW=128 THEN + IF acpt=5 THEN dw:=shift(0 TO 119) & pix.r; + ELSIF acpt=10 THEN dw:=shift(8 TO 119) & pix.r & pix.g; + ELSIF acpt=15 THEN dw:=shift(16 TO 119) & pix.r & pix.g & pix.b; + END IF; + ELSE -- N_DW=64 + IF (acpt MOD 8)=2 THEN dw:=shift(72 TO 119) & pix.r & pix.g; + ELSIF (acpt MOD 8)=5 THEN dw:=shift(64 TO 119) & pix.r; + ELSIF (acpt MOD 8)=7 THEN dw:=shift(80 TO 119) & pix.r & pix.g & pix.b; + END IF; + END IF; + WHEN "10" => -- 32bpp + IF (N_DW=128 AND (acpt MOD 4)=3) OR (N_DW=64 AND (acpt MOD 8)=7) THEN + dw:=shift(128-N_DW+24 TO 119) & pix.r & pix.g & pix.b & x"00"; + END IF; + WHEN OTHERS => -- 16bpp 565 + IF (N_DW=128 AND (acpt MOD 8)=7) OR (N_DW=64 AND (acpt MOD 4)=3) THEN + dw:=shift(128-N_DW+8 TO 119) & pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & + pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); + END IF; + END CASE; + RETURN dw; + END FUNCTION; + + FUNCTION shift_inext (acpt : natural RANGE 0 TO 15; + format : unsigned(1 DOWNTO 0)) RETURN boolean IS + BEGIN + CASE format IS + WHEN "01" => -- 24bpp + RETURN (N_DW=128 AND (acpt=5 OR acpt=10 OR acpt=15)) OR + (N_DW=64 AND ((acpt MOD 8)=2 OR (acpt MOD 8)=5 OR (acpt MOD 8)=7)); + WHEN "10" => -- 32bpp + RETURN (N_DW=128 AND ((acpt MOD 4)=3)) OR + (N_DW=64 AND ((acpt MOD 2)=1)); + WHEN OTHERS => -- 16bpp + RETURN (N_DW=128 AND ((acpt MOD 8)=7)) OR + (N_DW=64 AND ((acpt MOD 4)=3)); + END CASE; + END FUNCTION; + + FUNCTION shift_opack(acpt : natural RANGE 0 TO 15; + shift : unsigned(0 TO N_DW+15); + dr : unsigned(N_DW-1 DOWNTO 0); + format : unsigned(5 DOWNTO 0)) RETURN unsigned IS + VARIABLE shift_v : unsigned(0 TO N_DW+15); + BEGIN + CASE format(2 DOWNTO 0) IS + WHEN "011" => -- 8bpp + IF (N_DW=128 AND acpt=0) OR (N_DW=64 AND (acpt MOD 8)=0) THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSE + shift_v:=shift(8 TO N_DW+15) & dr(7 DOWNTO 0); + END IF; + + WHEN "100" => -- 16bpp + IF (N_DW=128 AND (acpt MOD 8)=0) OR (N_DW=64 AND (acpt MOD 4)=0) THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSE + shift_v:=shift(16 TO N_DW+15) & dr(15 DOWNTO 0); + END IF; + + WHEN "101" => -- 24bpp + IF N_DW=128 THEN + IF acpt=0 THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSIF acpt=5 THEN + shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); + ELSIF acpt=10 THEN + shift_v:=shift(24 TO 39) & dr; + ELSE + shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); + END IF; + ELSE -- N_DW=64 + IF (acpt MOD 8)=0 THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSIF (acpt MOD 8)=2 THEN + shift_v:=shift(24 TO 39) & dr; + ELSIF (acpt MOD 8)=5 THEN + shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); + ELSE + shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); + END IF; + END IF; + WHEN OTHERS => -- 32bpp + IF (N_DW=128 AND (acpt MOD 4)=0) OR (N_DW=64 AND (acpt MOD 2)=0) THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSE + shift_v:=shift(32 TO N_DW+15) & dr(31 DOWNTO 0); + END IF; + END CASE; + RETURN shift_v; + END FUNCTION; + + FUNCTION shift_onext (acpt : natural RANGE 0 TO 15; + format : unsigned(5 DOWNTO 0)) RETURN boolean IS + BEGIN + CASE format(2 DOWNTO 0) IS + WHEN "011" => -- 8bpp + RETURN (N_DW=128 AND acpt=0) OR + (N_DW=64 AND ((acpt MOD 8)=0)); + WHEN "100" => -- 16bpp + RETURN (N_DW=128 AND ((acpt MOD 8)=0)) OR + (N_DW=64 AND ((acpt MOD 4)=0)); + WHEN "101" => -- 24bpp + RETURN (N_DW=128 AND (acpt=0 OR acpt=5 OR acpt=10)) OR + (N_DW=64 AND ((acpt MOD 8)=0 OR (acpt MOD 8)=2 OR (acpt MOD 8)=5)); + WHEN OTHERS => -- 32bpp + RETURN (N_DW=128 AND ((acpt MOD 4)=0)) OR + (N_DW=64 AND ((acpt MOD 2)=0)); + END CASE; + END FUNCTION; + + FUNCTION shift_opix (shift : unsigned(0 TO N_DW+15); + format : unsigned(5 DOWNTO 0)) RETURN type_pix IS + BEGIN + CASE format(3 DOWNTO 0) IS + WHEN "0100" => -- 16bpp 565 + RETURN (b=>shift(8 TO 12) & shift(8 TO 10), + g=>shift(13 TO 15) & shift(0 TO 2) & shift(13 TO 14), + r=>shift(3 TO 7) & shift(3 TO 5)); + WHEN "1100" => -- 16bpp 1555 + RETURN (b=>shift(9 TO 13) & shift(9 TO 11), + g=>shift(14 TO 15) & shift(0 TO 2) & shift(14 TO 15) & shift(0), + r=>shift(3 TO 7) & shift(3 TO 5)); + WHEN "0101" | "0110" => -- 24bpp / 32bpp + RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); + + WHEN OTHERS => + RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); + + END CASE; + END FUNCTION; + + FUNCTION pixoffset(adrs : unsigned(31 DOWNTO 0); + format : unsigned (5 DOWNTO 0)) RETURN natural IS + BEGIN + CASE format(2 DOWNTO 0) IS + WHEN "011" => -- 8bbp + RETURN to_integer(adrs(NB_LA-1 DOWNTO 0)); + WHEN "100" => -- 16bpp 565 + RETURN to_integer(adrs(NB_LA-1 DOWNTO 1)); + WHEN OTHERS => -- 32bpp + RETURN to_integer(adrs(NB_LA-1 DOWNTO 2)); + END CASE; + END FUNCTION; + + FUNCTION swap(d : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS + VARIABLE e : unsigned(N_DW-1 DOWNTO 0); + BEGIN + IF BYTESWAP THEN + FOR i IN 0 TO N_DW/8-1 LOOP + e(i*8+7 DOWNTO i*8):=d(N_DW-i*8-1 DOWNTO N_DW-i*8-8); + END LOOP; + RETURN e; + ELSE + RETURN d; + END IF; + END FUNCTION swap; + + ----------------------------------------------------------------------------- + FUNCTION altx (a : unsigned(1 DOWNTO 0)) RETURN unsigned IS + BEGIN + CASE a IS + WHEN "00" => RETURN "0001"; + WHEN "01" => RETURN "0010"; + WHEN "10" => RETURN "0100"; + WHEN OTHERS => RETURN "1000"; + END CASE; + END FUNCTION; + + ----------------------------------------------------------------------------- + FUNCTION bound(a : unsigned; + s : natural) RETURN unsigned IS + BEGIN + IF a(a'left)='1' THEN + RETURN x"00"; + ELSIF a(a'left DOWNTO s)/=0 THEN + RETURN x"FF"; + ELSE + RETURN a(s-1 DOWNTO s-8); + END IF; + END FUNCTION bound; + + ----------------------------------------------------------------------------- + -- Nearest + FUNCTION near_frac(f : unsigned) RETURN unsigned IS + VARIABLE x : unsigned(FRAC-1 DOWNTO 0); + BEGIN + x:=(OTHERS =>f(f'left)); + RETURN x; + END FUNCTION; + + SIGNAL o_h_frac2,o_v_frac : unsigned(FRAC-1 DOWNTO 0); + SIGNAL o_h_bil_pix,o_v_bil_pix : type_pix; + + ----------------------------------------------------------------------------- + -- Nearest + Bilinear + Sharp Bilinear + FUNCTION bil_frac(f : unsigned) RETURN unsigned IS + BEGIN + RETURN f(f'left DOWNTO f'left+1-FRAC); + END FUNCTION; + + TYPE type_bil_t IS RECORD + r,g,b : unsigned(8+FRAC DOWNTO 0); + END RECORD; + FUNCTION bil_calc(f : unsigned(FRAC-1 DOWNTO 0); + p : arr_pix(0 TO 3)) RETURN type_bil_t IS + VARIABLE fp,fn : unsigned(FRAC DOWNTO 0); + VARIABLE u : unsigned(8+FRAC DOWNTO 0); + VARIABLE x : type_bil_t; + CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); + BEGIN + fp:='0' & f; + fn:=('1' & Z) - fp; + u:=p(2).r * fp + p(1).r * fn; + x.r:=u; + u:=p(2).g * fp + p(1).g * fn; + x.g:=u; + u:=p(2).b * fp + p(1).b * fn; + x.b:=u; + RETURN x; + END FUNCTION; + SIGNAL o_h_bil_t,o_v_bil_t : type_bil_t; + SIGNAL i_h_bil_t : type_bil_t; + + ----------------------------------------------------------------------------- + -- Sharp Bilinear + -- <0.5 : x*x*x*4 + -- >0.5 : 1 - (1-x)*(1-x)*(1-x)*4 + + TYPE type_sbil_tt IS RECORD + f : unsigned(FRAC-1 DOWNTO 0); + s : unsigned(FRAC-1 DOWNTO 0); + END RECORD; + + SIGNAL o_h_sbil_t,o_v_sbil_t : type_sbil_tt; + + FUNCTION sbil_frac1(f : unsigned(11 DOWNTO 0)) RETURN type_sbil_tt IS + VARIABLE u : unsigned(FRAC-1 DOWNTO 0); + VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); + VARIABLE x : type_sbil_tt; + BEGIN + IF f(11)='0' THEN + u:=f(11 DOWNTO 12-FRAC); + ELSE + u:=NOT f(11 DOWNTO 12-FRAC); + END IF; + v:=u*u; + x.f:=u; + x.s:=v(2*FRAC-2 DOWNTO FRAC-1); + RETURN x; + END FUNCTION; + + FUNCTION sbil_frac2(f : unsigned(11 DOWNTO 0); + t : type_sbil_tt) RETURN unsigned IS + VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); + BEGIN + v:=t.f*t.s; + IF f(11)='0' THEN + RETURN v(2*FRAC-2 DOWNTO FRAC-1); + ELSE + RETURN NOT v(2*FRAC-2 DOWNTO FRAC-1); + END IF; + END FUNCTION; + + ----------------------------------------------------------------------------- + -- Bicubic + TYPE type_bic_abcd IS RECORD + a : unsigned(7 DOWNTO 0); -- 0.8 + b : signed(8 DOWNTO 0); -- 0.9 + c : signed(11 DOWNTO 0); -- 3.9 + d : signed(10 DOWNTO 0); -- 2.9 + xx : signed(8 DOWNTO 0); -- X.X 1.8 + END RECORD; + TYPE type_bic_pix_abcd IS RECORD + r,g,b : type_bic_abcd; + END RECORD; + TYPE type_bic_tt1 IS RECORD -- Intermediate result + r_bx,g_bx,b_bx : signed(8 DOWNTO 0); -- B.X 1.8 + r_cxx,g_cxx,b_cxx : signed(11 DOWNTO 0); -- C.XX 3.9 + r_dxx,g_dxx,b_dxx : signed(10 DOWNTO 0); -- D.XX 2.9 + END RECORD; + TYPE type_bic_tt2 IS RECORD -- Intermediate result + r_abxcxx,g_abxcxx,b_abxcxx : signed(9 DOWNTO 0); -- A + B.X + C.XX 2.8 + r_dxxx,g_dxxx,b_dxxx : signed(9 DOWNTO 0); -- D.X.X.X 2.8 + END RECORD; + + ---------------------------------------------------------- + -- Y = A + B.X + C.X.X + D.X.X.X = A + X.(B + X.(C + X.D)) + -- A = Y(0) 0 .. 1 unsigned + -- B = Y(1)/2 - Y(-1)/2 -1/2 .. +1/2 signed + -- C = Y(-1) - 5*Y(0)/2 + 2*Y(1) - Y(2)/2 -3 .. +3 signed + -- D = -Y(-1)/2 + 3*Y(0)/2 - 3*Y(1)/2 + Y(2)/2 -2 .. +2 signed + + FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); + pm,p0,p1,p2 : unsigned(7 DOWNTO 0)) RETURN type_bic_abcd IS + VARIABLE xx : signed(2*FRAC+1 DOWNTO 0); -- 2.(2*FRAC) + BEGIN + xx := signed('0' & f(11 DOWNTO 12-FRAC)) * + signed('0' & f(11 DOWNTO 12-FRAC)); -- 2.(2*FRAC) + RETURN type_bic_abcd'( + a=>p0,-- 0.8 + b=>signed(('0' & p1) - ('0' & pm)), -- 0.9 + c=>signed(("000" & pm & '0') - ("00" & p0 & "00") - ("0000" & p0) + + ("00" & p1 & "00") - ("0000" & p2)), -- 3.9 + d=>signed(("00" & p0 & '0') - ("00" & p1 & '0') - ("000" & p1) + + ("000" & p0) + ("000" & p2) - ("000" & pm)), -- 2.9 + xx=>xx(2*FRAC DOWNTO 2*FRAC-8)); -- 1.8 + END FUNCTION; + FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); + p : arr_pix(0 TO 3)) RETURN type_bic_pix_abcd IS + BEGIN + RETURN type_bic_pix_abcd'(r=>bic_calc0(f,p(0).r,p(1).r,p(2).r,p(3).r), + g=>bic_calc0(f,p(0).g,p(1).g,p(2).g,p(3).g), + b=>bic_calc0(f,p(0).b,p(1).b,p(2).b,p(3).b)); + END FUNCTION; + + ---------------------------------------------------------- + -- Calc : B.X, C.XX, D.XX + FUNCTION bic_calc1(f : unsigned(11 DOWNTO 0); + abcd : type_bic_pix_abcd) RETURN type_bic_tt1 IS + VARIABLE t : type_bic_tt1; + VARIABLE bx : signed(9+FRAC DOWNTO 0); -- 1.(FRAC+9) + VARIABLE cxx : signed(20 DOWNTO 0); -- 4.17 + VARIABLE dxx : signed(19 DOWNTO 0); -- 3.17 + BEGIN + bx := abcd.r.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) + t.r_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 + cxx:= abcd.r.c * abcd.r.xx; -- 3.9 * 1.8 = 4.17 + t.r_cxx:=cxx(19 DOWNTO 8); -- 3.9 + dxx:= abcd.r.d * abcd.r.xx; -- 2.9 * 1.8 = 3.17 + t.r_dxx:=dxx(18 DOWNTO 8); -- 2.9 + bx := abcd.g.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) + t.g_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 + cxx:= abcd.g.c * abcd.g.xx; -- 3.9 * 1.8 = 4.17 + t.g_cxx:=cxx(19 DOWNTO 8); -- 3.9 + dxx:= abcd.g.d * abcd.g.xx; -- 2.9 * 1.8 = 3.17 + t.g_dxx:=dxx(18 DOWNTO 8); -- 2.9 + bx := abcd.b.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) + t.b_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 + cxx:= abcd.b.c * abcd.b.xx; -- 3.9 * 1.8 = 4.17 + t.b_cxx:=cxx(19 DOWNTO 8); -- 3.9 + dxx:= abcd.b.d * abcd.b.xx; -- 2.9 * 1.8 = 3.17 + t.b_dxx:=dxx(18 DOWNTO 8); -- 2.9 + RETURN t; + END FUNCTION; + + ---------------------------------------------------------- + -- Calc A + BX + CXX , X.DXX + FUNCTION bic_calc2(f : unsigned(11 DOWNTO 0); + t : type_bic_tt1; + abcd : type_bic_pix_abcd) RETURN type_bic_tt2 IS + VARIABLE u : type_bic_tt2; + VARIABLE x : signed(11+FRAC DOWNTO 0); -- 3.(9+FRAC) + BEGIN + u.r_abxcxx:=(t.r_bx(8) & t.r_bx) + ("00" & signed(abcd.r.a)) + t.r_cxx(10 DOWNTO 1); -- 2.8 + u.g_abxcxx:=(t.g_bx(8) & t.g_bx) + ("00" & signed(abcd.g.a)) + t.g_cxx(10 DOWNTO 1); -- 2.8 + u.b_abxcxx:=(t.b_bx(8) & t.b_bx) + ("00" & signed(abcd.b.a)) + t.b_cxx(10 DOWNTO 1); -- 2.8 + + x:=t.r_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) + u.r_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 + x:=t.g_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) + u.g_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 + x:=t.b_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) + u.b_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 + RETURN u; + END FUNCTION; + + ---------------------------------------------------------- + -- Calc (A + BX + CXX) + (DXXX) + FUNCTION bic_calc3(f : unsigned(11 DOWNTO 0); + t : type_bic_tt2; + abcd : type_bic_pix_abcd) RETURN type_pix IS + VARIABLE x : type_pix; + VARIABLE v : signed(9 DOWNTO 0); -- 2.8 + BEGIN + v:=t.r_abxcxx + t.r_dxxx; + x.r:=bound(unsigned(v),8); + v:=t.g_abxcxx + t.g_dxxx; + x.g:=bound(unsigned(v),8); + v:=t.b_abxcxx + t.b_dxxx; + x.b:=bound(unsigned(v),8); + RETURN x; + END FUNCTION; + + ----------------------------------------------------------------------------- + SIGNAL o_h_bic_pix,o_v_bic_pix : type_pix; + SIGNAL o_h_bic_abcd1,o_h_bic_abcd2 : type_bic_pix_abcd; + SIGNAL o_v_bic_abcd1,o_v_bic_abcd2 : type_bic_pix_abcd; + SIGNAL o_h_bic_tt1,o_v_bic_tt1 : type_bic_tt1; + SIGNAL o_h_bic_tt2,o_v_bic_tt2 : type_bic_tt2; + + ----------------------------------------------------------------------------- + -- Polyphase + + CONSTANT POLY16 : arr_int9 := ( + -24,-21,-15,-9,-5,-1,4,8,6,8,5,4,3,1,0,0, + 176,174,169,160,150,131,115,85,58,27,4,-6,-20,-24,-26,-25, + -24,-25,-26,-24,-20,-6,4,27,58,85,115,131,150,160,169,174, + 0,0,0,1,3,4,5,8,6,8,4,-1,-5,-9,-15,-21); + + CONSTANT POLY32 : arr_int9 := ( + -24,-22,-20,-18,-16,-13,-11,-8,-6,-3,-1,0,2,3,5,5,6,6,6,5,5,4,4,3,2,1,1,0,0,0,0,0, + 176,175,174,172,169,164,160,153,147,138,129,119,109,96,84,71,58,40,22,12,3,-4,-12,-16,-20,-22,-25,-25,-26,-25,-25,-25, + -24,-25,-26,-26,-26,-24,-23,-19,-16,-10,-4,4,11,22,32,45,58,77,96,108,119,129,140,147,154,159,165,168,172,173,175,175, + 0,0,0,0,1,1,2,2,3,3,4,5,6,7,7,7,6,5,4,3,1,-1,-4,-6,-8,-10,-13,-15,-18,-20,-22,-22); + + FUNCTION init_poly RETURN arr_uv36 IS + VARIABLE m : arr_uv36(0 TO 2**FRAC-1) :=(OTHERS =>x"000000000"); + BEGIN + IF FRAC=4 THEN + FOR i IN 0 TO 15 LOOP + m(i):=unsigned(to_signed(POLY16(i),9) & to_signed(POLY16(i+16),9) & + to_signed(POLY16(i+32),9) & to_signed(POLY16(i+48),9)); + END LOOP; + ELSIF FRAC=5 THEN + FOR i IN 0 TO 31 LOOP + m(i):=unsigned(to_signed(POLY32(i),9) & to_signed(POLY32(i+32),9) & + to_signed(POLY32(i+64),9) & to_signed(POLY32(i+96),9)); + END LOOP; + END IF; + RETURN m; + END FUNCTION; + + SIGNAL o_h_poly : arr_uv36(0 TO 2**FRAC-1):=init_poly; + SIGNAL o_v_poly : arr_uv36(0 TO 2**FRAC-1):=init_poly; + ATTRIBUTE ramstyle OF o_h_poly : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_v_poly : SIGNAL IS "no_rw_check"; + SIGNAL o_h_poly_a,o_v_poly_a : integer RANGE 0 TO 2**FRAC-1; + SIGNAL o_h_poly_dr,o_h_poly_dr2,o_v_poly_dr,o_v_poly_dr2 : unsigned(35 DOWNTO 0); + SIGNAL o_h_poly_pix,o_v_poly_pix : type_pix; + SIGNAL poly_h_wr,poly_v_wr : std_logic; + SIGNAL poly_tdw : unsigned(35 DOWNTO 0); + SIGNAL poly_a2 : unsigned(FRAC-1 DOWNTO 0); + + TYPE type_poly_t IS RECORD + r0,r1,b0,b1,g0,g1 : signed(17 DOWNTO 0); + END RECORD; + + SIGNAL o_h_poly_t,o_v_poly_t : type_poly_t; + + FUNCTION poly_calc1(fi : unsigned(35 DOWNTO 0); + p : arr_pix(0 TO 3)) RETURN type_poly_t IS + VARIABLE t : type_poly_t; + BEGIN + -- 2.7 * 1.8 = 3.15 + t.r0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).r) + + signed(fi(26 DOWNTO 18)) * signed('0' & p(1).r)); + t.r1:=(signed(fi(17 DOWNTO 9)) * signed('0' & p(2).r) + + signed(fi( 8 DOWNTO 0)) * signed('0' & p(3).r)); + t.g0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).g) + + signed(fi(26 DOWNTO 18)) * signed('0' & p(1).g)); + t.g1:=(signed(fi(17 DOWNTO 9)) * signed('0' & p(2).g) + + signed(fi( 8 DOWNTO 0)) * signed('0' & p(3).g)); + t.b0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).b) + + signed(fi(26 DOWNTO 18)) * signed('0' & p(1).b)); + t.b1:=(signed(fi(17 DOWNTO 9)) * signed('0' & p(2).b) + + signed(fi( 8 DOWNTO 0)) * signed('0' & p(3).b)); + RETURN t; + END FUNCTION; + + FUNCTION poly_calc2(t : type_poly_t) RETURN type_pix IS + VARIABLE p : type_pix; + BEGIN + p.r:=bound(unsigned(t.r0+t.r1),15); + p.g:=bound(unsigned(t.g0+t.g1),15); + p.b:=bound(unsigned(t.b0+t.b1),15); + RETURN p; + END FUNCTION; + +BEGIN + + ----------------------------------------------------------------------------- + i_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(i_clk); + o_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(o_clk); + avl_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(avl_clk); + + ----------------------------------------------------------------------------- + -- Input pixels FIFO and shreg + InAT:PROCESS(i_clk,i_reset_na) IS + CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); + VARIABLE frac_v : unsigned(FRAC-1 DOWNTO 0); + VARIABLE div_v : unsigned(16 DOWNTO 0); + VARIABLE dir_v : unsigned(11 DOWNTO 0); + VARIABLE bil_t_v : type_bil_t; + BEGIN + IF i_reset_na='0' THEN + i_write<='0'; + + ELSIF rising_edge(i_clk) THEN + i_push<='0'; + i_pushhead<='0'; + i_eol<='0'; -- End Of Line + i_freeze <=freeze; -- + i_iauto<=iauto; -- + i_wreq<='0'; + i_wr<='0'; + + ------------------------------------------------------ + i_head(127 DOWNTO 120)<=x"01"; -- Header type + i_head(119 DOWNTO 112)<="000000" & i_format; -- Header format + i_head(111 DOWNTO 96)<="0000" & to_unsigned(N_BURST,12); -- Header size + i_head(95 DOWNTO 80)<=x"0000"; -- Attributes. TBD + i_head(80)<=i_inter; + i_head(81)<=i_flm; + i_head(82)<=i_hdown; + i_head(83)<=i_vdown; + i_head(84)<=i_mode(3); + i_head(87 DOWNTO 85)<=i_count; + i_head(79 DOWNTO 64)<="0000" & to_unsigned(i_hrsize,12); -- Image width + i_head(63 DOWNTO 48)<="0000" & to_unsigned(i_vrsize,12); -- Image height + i_head(47 DOWNTO 32)<= + to_unsigned(N_BURST * i_hburst,16); -- Line Length. Bytes + i_head(31 DOWNTO 16)<="0000" & to_unsigned(i_ohsize,12); + i_head(15 DOWNTO 0) <="0000" & to_unsigned(i_ovsize,12); + + ------------------------------------------------------ + i_ppix<=(i_r,i_g,i_b); + i_pvs<=i_vs; + i_pfl<=i_fl; + i_pde<=i_de; + i_pce<=i_ce; + + ------------------------------------------------------ + IF i_pce='1' THEN + ---------------------------------------------------- + i_vs_pre<=i_pvs; + i_de_pre<=i_pde; + i_fl_pre<=i_pfl; + + ---------------------------------------------------- + -- Detect interlaced video + IF NOT INTER THEN + i_intercnt<=0; + ELSIF i_pfl/=i_fl_pre THEN + i_intercnt<=3; + ELSIF i_pvs='1' AND i_vs_pre='0' AND i_intercnt>0 THEN + i_intercnt<=i_intercnt-1; + END IF; + i_inter<=to_std_logic(i_intercnt>0); + + ---------------------------------------------------- + IF i_pvs='1' AND i_vs_pre='0' THEN + i_sof<='1'; + END IF; + + IF i_pde='1' AND i_de_pre='0' THEN + i_flm<=i_pfl; + END IF; + + IF i_pde='1' AND i_sof='1' THEN + i_sof<='0'; + i_vcpt<=0; + IF i_inter='1' AND i_flm='0' AND i_half='0' AND INTER THEN + i_line<='1'; + i_adrsi<=to_unsigned(N_BURST * i_hburst,32) + + to_unsigned(N_BURST * to_integer( + unsigned'("00") & to_std_logic(HEADER)),32); + ELSE + i_line<='0'; + i_adrsi<=to_unsigned(N_BURST * to_integer( + unsigned'("00") & to_std_logic(HEADER)),32); + END IF; + END IF; + + i_ven<=to_std_logic(i_hcpt>=i_hmin AND i_hcpt<=i_hmax AND + i_vcpt>=i_vmin AND i_vcpt<=i_vmax); + + -- Detects end of frame for triple buffering. + i_endframe0<=i_vs AND (NOT i_inter OR i_flm); + i_endframe1<=i_vs AND (NOT i_inter OR NOT i_flm); + + i_vss<=to_std_logic(i_vcpt>=i_vmin AND i_vcpt<=i_vmax); + + ---------------------------------------------------- + IF i_pde='1' AND i_de_pre='0' THEN + i_vimax<=i_vcpt; + i_hcpt<=0; + ELSE + i_hcpt<=(i_hcpt+1) MOD 4096; + END IF; + + IF i_pde='0' AND i_de_pre='1' THEN + i_himax<=i_hcpt; + END IF; + + IF i_iauto='1' THEN + -- Auto-size + i_hmin<=0; + i_hmax<=i_himax; + i_vmin<=0; + IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN + i_vmax<=i_vimax; + END IF; + ELSE + -- Forced image + i_hmin<=himin; -- + i_hmax<=himax; -- + i_vmin<=vimin; -- + IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN + i_vmax<=vimax; -- + END IF; + END IF; + + IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN + i_vdmax<=i_vimax; + END IF; + i_hdmax<=i_himax; + + IF i_format="00" OR i_format="11" THEN -- 16bpp + i_hburst<=(i_hrsize*2 + N_BURST - 1) / N_BURST; + ELSIF i_format="01" THEN -- 24bpp + i_hburst<=(i_hrsize*3 + N_BURST - 1) / N_BURST; + ELSE -- 32bpp + i_hburst<=(i_hrsize*4 + N_BURST - 1) / N_BURST; + END IF; + ---------------------------------------------------- + i_mode<=mode; -- + i_format<=format; -- + + -- Downscaling : Nearest or bilinear + i_bil<=to_std_logic(i_mode(2 DOWNTO 0)/="000" AND DOWNSCALE); + + i_hdown<=to_std_logic(i_hsize>i_ohsize AND DOWNSCALE); --H downscale + i_vdown<=to_std_logic(i_vsize>i_ovsize AND DOWNSCALE); --V downscale + + ---------------------------------------------------- + i_hsize <=(4096+i_hmax-i_hmin+1) MOD 4096; + i_vmaxmin<=(4096+i_vmax-i_vmin+1) MOD 4096; + + IF i_inter='0' THEN + -- Non interlaced + i_vsize<=i_vmaxmin; + i_half <='0'; + ELSIF i_ovsize<2*i_vmaxmin THEN + -- Interlaced, but downscaling, use only half frames + i_vsize<=i_vmaxmin; + i_half <='1'; + ELSE + -- Interlaced : Double image height + i_vsize<=2*i_vmaxmin; + i_half <='0'; + END IF; + + i_ohsize<=o_hsize; -- + i_ovsize<=o_vsize; -- + + ---------------------------------------------------- + -- Downscaling vertical + i_divstart<='0'; + IF i_de_delay=16 THEN + IF (i_vacc + 2*i_ovsize) < 2*i_vsize THEN + i_vacc<=(i_vacc + 2*i_ovsize) MOD 8192; + i_vnp<='0'; + ELSE + i_vacc<=(i_vacc + 2*i_ovsize - 2*i_vsize + 8192) MOD 8192; + i_vnp<='1'; + END IF; + i_divstart<='1'; + + IF i_vcpt=i_vmin THEN + i_vacc<=(i_vsize - i_ovsize + 8192) MOD 8192; + i_vnp<='1'; -- + END IF; + END IF; + + IF i_vdown='0' THEN + i_vnp<='1'; + END IF; + + -- Downscaling horizontal + IF i_ven='1' THEN + IF i_hacc + 2*i_ohsize < 2*i_hsize THEN + i_hacc<=(i_hacc + 2*i_ohsize) MOD 8192; + i_hnp<='0'; -- Skip. pix. + ELSE + i_hacc<=(i_hacc + 2*i_ohsize - 2*i_hsize + 8192) MOD 8192; + i_hnp<='1'; + END IF; + END IF; + IF i_hdown='0' THEN + i_hnp<='1'; + END IF; + + ---------------------------------------------------- + -- Downscaling interpolation + i_hpixp<=i_ppix; + i_hpix0<=i_hpixp; + i_hpix1<=i_hpix0; + i_hpix2<=i_hpix1; + i_hpix3<=i_hpix2; + i_hpix4<=i_hpix3; + + i_hnp1<=i_hnp; i_hnp2<=i_hnp1; i_hnp3<=i_hnp2; i_hnp4<=i_hnp3; + i_ven1<=i_ven; i_ven2<=i_ven1; i_ven3<=i_ven2; i_ven4<=i_ven3; + i_ven5<=i_ven4; i_ven6<=i_ven5; + + -- C1 : DIV 1. Pipelined 4 bits non-restoring divider + dir_v:=x"000"; + div_v:=to_unsigned(i_hacc * 16,17); + + div_v:=div_v-to_unsigned(i_hsize*16,17); + dir_v(11):=NOT div_v(16); + IF div_v(16)='0' THEN + div_v:=div_v-to_unsigned(i_hsize*8,17); + ELSE + div_v:=div_v+to_unsigned(i_hsize*8,17); + END IF; + dir_v(10):=NOT div_v(16); + i_div<=div_v; + i_dir<=dir_v; + + -- C2 : DIV 2. + div_v:=i_div; + dir_v:=i_dir; + IF div_v(16)='0' THEN + div_v:=div_v-to_unsigned(i_hsize*4,17); + ELSE + div_v:=div_v+to_unsigned(i_hsize*4,17); + END IF; + dir_v(9):=NOT div_v(16); + + IF div_v(16)='0' THEN + div_v:=div_v-to_unsigned(i_hsize*2,17); + ELSE + div_v:=div_v+to_unsigned(i_hsize*2,17); + END IF; + dir_v(8):=NOT div_v(16); + i_h_frac<=dir_v; + + -- C4 : Horizontal Bilinear + IF i_bil='0' THEN + frac_v:=near_frac(i_h_frac); + ELSE + frac_v:=bil_frac(i_h_frac); + END IF; + + i_h_bil_t<=bil_calc(frac_v,(i_hpix2,i_hpix2,i_hpix3,i_hpix3)); + i_hpix.r<=bound(i_h_bil_t.r,8+FRAC); + i_hpix.g<=bound(i_h_bil_t.g,8+FRAC); + i_hpix.b<=bound(i_h_bil_t.b,8+FRAC); + + IF i_hdown='0' THEN + i_hpix<=i_hpix4; + END IF; + + -- C5 : Vertical Bilinear + IF i_bil='0' THEN + frac_v:=near_frac(i_v_frac(11 DOWNTO 0)); + ELSE + frac_v:=bil_frac(i_v_frac(11 DOWNTO 0)); + END IF; + + bil_t_v:=bil_calc(frac_v,(i_hpix,i_hpix,i_ldrm,i_ldrm)); + i_pix.r<=bound(bil_t_v.r,8+FRAC); + i_pix.g<=bound(bil_t_v.g,8+FRAC); + i_pix.b<=bound(bil_t_v.b,8+FRAC); + + IF i_vdown='0' THEN + i_pix<=i_hpix; + END IF; + + ---------------------------------------------------- + -- VNP : Vert. downscaling line enable + -- HNP : Horiz. downscaling pix. enable + -- VEN : Enable pixel within displayed window + + IF (i_hnp4='1' AND i_ven6='1') OR i_pushend='1' THEN + i_shift<=shift_ishift(i_shift,i_pix,i_format); + i_dw<=shift_ipack(i_dw,i_acpt,i_shift,i_pix,i_format); + + IF shift_inext(i_acpt,i_format) AND i_vnp='1' THEN + i_push<='1'; + i_pushend<='0'; + END IF; + i_acpt<=(i_acpt+1) MOD 16; + END IF; + + IF i_ven6='1' AND i_ven5='0' AND i_vnp='1' THEN + i_pushend<='1'; + END IF; + i_pushend2<=i_pushend; + + IF i_pushend2='1' AND i_pushend='0' THEN + i_eol<='1'; + END IF; + + IF i_pde='0' AND i_de_pre='1' THEN + i_de_delay<=0; + ELSIF i_de_delay<18 THEN + i_de_delay<=i_de_delay+1; + END IF; + + IF i_de_delay=16 THEN + i_lwad<=0; + i_lrad<=0; + i_vcpt<=i_vcpt+1; + i_hacc<=(i_hsize - i_ohsize + 8192) MOD 8192; + i_hbcpt<=0; + END IF; + IF i_de_delay=17 THEN + i_acpt<=0; + i_wad<=2*BLEN-1; + END IF; + + IF i_pvs='0' AND i_vs_pre='1' THEN + -- Push header + i_pushhead<=to_std_logic(HEADER); + END IF; + + END IF; -- IF i_pce='1' + + ------------------------------------------------------ + -- Push pixels to downscaling line buffer + i_lwr<=i_hnp4 AND i_ven5 AND i_pce; + IF i_lwr='1' THEN + i_lwad<=(i_lwad+1) MOD OHRES; + END IF; + i_ldw<=i_hpix; + + IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN + i_lrad<=(i_lrad+1) MOD OHRES; + END IF; + + ------------------------------------------------------ + -- Write image properties header + i_pushhead2<=i_pushhead; i_pushhead3<=i_pushhead2; + + IF i_pushhead='1' AND i_freeze='0' THEN + i_dw<=i_head(127 DOWNTO 128-N_DW); + i_count<=i_count+1; + i_wr<='1'; + i_wad<=0; + IF N_DW=128 THEN + i_alt<='0'; + i_wreq<=NOT i_freeze; + i_adrs<=(OTHERS =>'0'); + END IF; + END IF; + + IF i_pushhead2='1' AND i_freeze='0' AND N_DW=64 THEN + i_dw<=i_head(N_DW-1 DOWNTO 0); + i_wr<='1'; + i_wad<=1; + i_wreq<=NOT i_freeze; + i_alt<='0'; + i_adrs<=(OTHERS =>'0'); + END IF; + IF i_pushhead3='1' THEN + i_wad<=BLEN-1; + END IF; + + ------------------------------------------------------ + -- Push pixels to DPRAM + IF i_push='1' AND i_freeze='0' THEN + i_wr<='1'; + i_wad<=(i_wad+1) MOD (BLEN*2); + IF (i_wad+1) MOD BLEN=BLEN-1 AND i_hbcpt 12 + IDividers:PROCESS (i_clk,i_reset_na) IS + BEGIN + IF i_reset_na='0' THEN +--pragma synthesis_off + i_v_frac<=x"000"; +--pragma synthesis_on + NULL; + ELSIF rising_edge(i_clk) THEN + i_vdivi<=to_unsigned(2*i_vsize,13); + i_vdivr<=to_unsigned(i_vacc*4096,25); + + ------------------------------------------------------ + IF i_divstart='1' THEN + i_divcpt<=0; + i_divrun<='1'; + + ELSIF i_divrun='1' THEN + ---------------------------------------------------- + IF i_divcpt=6 THEN + i_divrun<='0'; + i_v_frac<=i_vdivr(4 DOWNTO 0) & NOT i_vdivr(24) & "000000"; + ELSE + i_divcpt<=i_divcpt+1; + END IF; + + IF i_vdivr(24)='0' THEN + i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) - i_vdivi; + ELSE + i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) + i_vdivi; + END IF; + i_vdivr(11 DOWNTO 0)<=i_vdivr(10 DOWNTO 0) & NOT i_vdivr(24); + + ---------------------------------------------------- + END IF; + END IF; + END PROCESS IDividers; + + ----------------------------------------------------------------------------- + -- DPRAM Input. Double buffer for RAM bursts. + PROCESS (i_clk) IS + BEGIN + IF rising_edge(i_clk) THEN + IF i_wr='1' THEN + i_dpram(i_wad)<=i_dw; + END IF; + END IF; + END PROCESS; + + avl_dr<=i_dpram(avl_rad_c) WHEN rising_edge(avl_clk); + + -- Line buffer for downscaling with interpolation + DownLine:IF DOWNSCALE GENERATE + ILBUF:PROCESS(i_clk) IS + BEGIN + IF rising_edge(i_clk) THEN + IF i_lwr='1' THEN + i_mem(i_lwad MOD IHRES)<=i_ldw; + END IF; + IF i_pce='1' THEN + i_ldrm<=i_mem(i_lrad MOD IHRES); + END IF; + END IF; + END PROCESS ILBUF; + END GENERATE DownLine; + + ----------------------------------------------------------------------------- + -- AVALON interface + Avaloir:PROCESS(avl_clk,avl_reset_na) IS + VARIABLE adr_v : unsigned(31 DOWNTO 0); + BEGIN + IF avl_reset_na='0' THEN + avl_state<=sIDLE; + avl_write_sr<='0'; + avl_read_sr<='0'; + avl_readdataack<='0'; + avl_readack<='0'; + + ELSIF rising_edge(avl_clk) THEN + ---------------------------------- + avl_write_sync<=i_write; -- + avl_write_sync2<=avl_write_sync; + avl_write_pulse<=avl_write_sync XOR avl_write_sync2; + IF avl_write_pulse='1' THEN + avl_wadrs <=i_wadrs AND (RAMSIZE - 1); -- + avl_wline <=i_wline; -- + avl_walt <=i_walt; -- + END IF; + + ---------------------------------- + avl_read_sync<=o_read; -- + avl_read_sync2<=avl_read_sync; + avl_read_pulse<=avl_read_sync XOR avl_read_sync2; + avl_radrs <=o_adrs; -- + avl_rline <=o_rline; -- + + -------------------------------------------- + avl_o_vs_sync<=o_vsv(0); -- + avl_o_vs<=avl_o_vs_sync; + + avl_fb_ena<=o_fb_ena; -- + IF avl_fb_ena='0' THEN + IF HEADER THEN + avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE) + N_BURST; -- + avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE) + N_BURST; -- + ELSE + avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE); -- + avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE); -- + END IF; + ELSIF avl_o_vs_sync='0' AND avl_o_vs='1' THEN + -- Copy framebuffer base address at VS falling edge + avl_o_offset0<=o_fb_base; -- + avl_o_offset1<=o_fb_base; -- + END IF; + + avl_i_offset0<=buf_offset(o_ibuf0,RAMBASE,RAMSIZE); -- + avl_i_offset1<=buf_offset(o_ibuf1,RAMBASE,RAMSIZE); -- + + -------------------------------------------- + avl_dw<=swap(unsigned(avl_readdata)); + avl_read_i<='0'; + avl_write_i<='0'; + + avl_write_sr<=(avl_write_sr OR avl_write_pulse) AND NOT avl_write_clr; + avl_read_sr <=(avl_read_sr OR avl_read_pulse) AND NOT avl_read_clr; + avl_write_clr<='0'; + avl_read_clr <='0'; + + avl_rad<=avl_rad_c; + + -------------------------------------------- + CASE avl_state IS + WHEN sIDLE => + IF avl_write_sr='1' THEN + avl_state<=sWRITE; + avl_write_clr<='1'; + IF avl_walt='0' THEN + avl_rad<=0; + ELSE + avl_rad<=BLEN; + END IF; + IF avl_wline='0' THEN + avl_address<=std_logic_vector( + avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + + avl_i_offset0(N_AW+NB_LA-1 DOWNTO NB_LA)); + ELSE + avl_address<=std_logic_vector( + avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + + avl_i_offset1(N_AW+NB_LA-1 DOWNTO NB_LA)); + END IF; + ELSIF avl_read_sr='1' THEN + avl_state<=sREAD; + avl_read_clr<='1'; + END IF; + + WHEN sWRITE => + avl_write_i<='1'; + IF avl_write_i='1' AND avl_waitrequest='0' THEN + IF (avl_rad MOD BLEN)=BLEN-1 THEN + avl_write_i<='0'; + avl_state<=sIDLE; + END IF; + END IF; + + WHEN sREAD => + IF avl_rline='0' THEN + adr_v:=avl_radrs + avl_o_offset0; + ELSE + adr_v:=avl_radrs + avl_o_offset1; + END IF; + avl_address<=std_logic_vector(adr_v(N_AW+NB_LA-1 DOWNTO NB_LA)); + + avl_read_i<='1'; + IF avl_read_i='1' AND avl_waitrequest='0' THEN + avl_state<=sIDLE; + avl_read_i<='0'; + avl_readack<=NOT avl_readack; + END IF; + END CASE; + + -------------------------------------------- + -- Pipelined data read + avl_wr<='0'; + IF avl_readdatavalid='1' THEN + avl_wr<='1'; + avl_wad<=(avl_wad+1) MOD (2*BLEN); + IF (avl_wad MOD BLEN)=BLEN-2 THEN + avl_readdataack<=NOT avl_readdataack; + END IF; + END IF; + + IF avl_o_vs_sync='0' AND avl_o_vs='1' THEN + avl_wad<=2*BLEN-1; + END IF; + + -------------------------------------------- + END IF; + END PROCESS Avaloir; + + avl_read<=avl_read_i; + avl_write<=avl_write_i; + avl_writedata<=std_logic_vector(swap(avl_dr)); + avl_burstcount<=std_logic_vector(to_unsigned(BLEN,8)); + avl_byteenable<=(OTHERS =>'1'); + + avl_rad_c<=(avl_rad+1) MOD (2*BLEN) + WHEN avl_write_i='1' AND avl_waitrequest='0' ELSE avl_rad; + + ----------------------------------------------------------------------------- + -- DPRAM Output. Double buffer for RAM bursts. + PROCESS (avl_clk) IS + BEGIN + IF rising_edge(avl_clk) THEN + IF avl_wr='1' THEN + o_dpram(avl_wad)<=avl_dw; + END IF; + END IF; + END PROCESS; + + o_dr<=o_dpram(o_ad3) WHEN rising_edge(o_clk); + + ----------------------------------------------------------------------------- + -- Output Vertical Divider + -- Vfrac = Vacc / Vsize + ODivider:PROCESS (o_clk,o_reset_na) IS + BEGIN + IF o_reset_na='0' THEN +--pragma synthesis_off + o_vfrac<=x"000"; +--pragma synthesis_on + ELSIF rising_edge(o_clk) THEN + o_vdivi<=to_unsigned(2*o_vsize,13); + o_vdivr<=to_unsigned(o_vacc*4096,25); + ------------------------------------------------------ + IF o_divstart='1' THEN + o_divcpt<=0; + o_divrun<='1'; + + ELSIF o_divrun='1' THEN + ---------------------------------------------------- + IF o_divcpt=12 THEN + o_divrun<='0'; + o_vfrac<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); + ELSE + o_divcpt<=o_divcpt+1; + END IF; + + IF o_vdivr(24)='0' THEN + o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) - o_vdivi; + ELSE + o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) + o_vdivi; + END IF; + o_vdivr(11 DOWNTO 0)<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); + ---------------------------------------------------- + END IF; + END IF; + END PROCESS ODivider; + + ----------------------------------------------------------------------------- + Scalaire:PROCESS (o_clk,o_reset_na) IS + VARIABLE lev_inc_v,lev_dec_v : std_logic; + VARIABLE prim_v,last_v,bib_v : std_logic; + VARIABLE shift_v : unsigned(0 TO N_DW+15); + VARIABLE hpix_v : type_pix; + VARIABLE hcarry_v,vcarry_v : boolean; + VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1; + VARIABLE off_v : natural RANGE 0 TO 15; + BEGIN + IF o_reset_na='0' THEN + o_copy<=sWAIT; + o_state<=sDISP; + o_read_pre<='0'; + o_readlev<=0; + o_copylev<=0; + o_hsp<='0'; + + ELSIF rising_edge(o_clk) THEN + ------------------------------------------------------ + o_mode <=mode; -- ? + o_format <="0001" & format; -- ? + + o_run <=run; -- ? + + o_htotal <=htotal; -- ? + o_hsstart<=hsstart; -- ? + o_hsend <=hsend; -- ? + o_hdisp <=hdisp; -- ? + o_hmin <=hmin; -- ? + o_hmax <=hmax; -- ? + + o_vtotal <=vtotal; -- ? + o_vsstart<=vsstart; -- ? + o_vsend <=vsend; -- ? + o_vdisp <=vdisp; -- ? + o_vmin <=vmin; -- ? + o_vmax <=vmax; -- ? + + o_hsize <=o_hmax - o_hmin + 1; + o_vsize <=o_vmax - o_vmin + 1; + + -------------------------------------------- + -- Triple buffering. + -- For intelaced video, half frames are updated independently + -- Input : Toggle buffer at end of input frame + o_freeze <= freeze; + o_inter <=i_inter; -- + o_iendframe0<=i_endframe0; -- + o_iendframe02<=o_iendframe0; + IF o_iendframe0='1' AND o_iendframe02='0' THEN + o_ibuf0<=buf_next(o_ibuf0,o_obuf0,o_freeze); + o_bufup0<='1'; + END IF; + o_iendframe1<=i_endframe1; -- + o_iendframe12<=o_iendframe1; + IF o_iendframe1='1' AND o_iendframe12='0' THEN + o_ibuf1<=buf_next(o_ibuf1,o_obuf1,o_freeze); + o_bufup1<='1'; + END IF; + -- Output : Change framebuffer, and image properties, at VS falling edge + IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup1='1' THEN + o_obuf1<=buf_next(o_obuf1,o_ibuf1,o_freeze); + o_bufup1<='0'; + o_ihsize<=i_hrsize; -- + o_ivsize<=i_vrsize; -- + o_hdown<=i_hdown; -- + o_vdown<=i_vdown; -- + END IF; + -- Framebuffer mode. + IF o_fb_ena='1' THEN + o_ihsize<=o_fb_hsize; + o_ivsize<=o_fb_vsize; + o_format<=o_fb_format; + o_hdown<='0'; + o_vdown<='0'; + END IF; + + o_ihsize_temp <= o_ihsize * to_integer(o_format(2 DOWNTO 0) - 2); + o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1); + o_hburst <= o_ihsize_temp2 / N_BURST; + + IF o_fb_ena='1' AND o_fb_stride /= 0 THEN + o_stride<=o_fb_stride; + ELSE + o_stride<=to_unsigned(o_ihsize_temp2,14); + o_stride(NB_BURST-1 DOWNTO 0)<=(OTHERS =>'0'); + END IF; + + IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN + o_obuf0<=buf_next(o_obuf0,o_ibuf0,o_freeze); + o_bufup0<='0'; + END IF; + + IF o_inter='0' THEN + o_ibuf1<=o_ibuf0; + o_obuf1<=o_obuf0; + END IF; + + -- Triple buffer disabled + IF o_mode(3)='0' THEN + o_obuf0<=0; + o_obuf1<=0; + o_ibuf0<=0; + o_ibuf1<=0; + END IF; + + ------------------------------------------------------ + o_hmode<=o_mode; + IF o_hdown='1' AND DOWNSCALE THEN + -- Force nearest if downscaling : Downscaled framebuffer + o_hmode(2 DOWNTO 0)<="000"; + END IF; + + o_vmode<=o_mode; + IF o_vdown='1' AND DOWNSCALE THEN + -- Force nearest if downscaling : Downscaled framebuffer + o_vmode(2 DOWNTO 0)<="000"; + END IF; + + ------------------------------------------------------ + -- End DRAM READ + o_readack_sync<=avl_readack; -- + o_readack_sync2<=o_readack_sync; + o_readack<=o_readack_sync XOR o_readack_sync2; + + o_readdataack_sync<=avl_readdataack; -- + o_readdataack_sync2<=o_readdataack_sync; + o_readdataack<=o_readdataack_sync XOR o_readdataack_sync2; + + ------------------------------------------------------ + lev_inc_v:='0'; + lev_dec_v:='0'; + + -- acpt : Pixel position within current data word + -- dcpt : Destination image position + + -- Force preload 2 lines at top of screen + IF o_hsv(0)='1' AND o_hsv(1)='0' THEN + IF o_vcpt_pre3=o_vmin THEN + o_fload<=2; + o_bibu<='0'; + END IF; + o_hsp<='1'; + END IF; + + o_vpe<=to_std_logic(o_vcpt_pre=o_vmin); + o_divstart<='0'; + o_adrsa<='0'; + o_adrsb<=o_adrsa; + + o_vacc_ini<=(o_vsize - o_ivsize + 8192) MOD 8192; + o_hacc_ini<=(o_hsize + o_ihsize + 8192) MOD 8192; + + --Alternate phase + --o_vacc_ini<=o_ivsize; + --o_hacc_ini<=(2*o_hsize - o_ihsize + 8192) MOD 8192; + + CASE o_state IS + -------------------------------------------------- + WHEN sDISP => + IF o_hsp='1' THEN + o_state<=sHSYNC; + o_hsp<='0'; + END IF; + + -------------------------------------------------- + WHEN sHSYNC => + dif_v:=(o_vacc_next - 2*o_vsize + 16384) MOD 16384; + IF dif_v>=8192 THEN + o_vacc <=o_vacc_next; + o_vacc_next<=(o_vacc_next + 2*o_ivsize) MOD 8192; + vcarry_v:=false; + ELSE + o_vacc <=dif_v; + o_vacc_next<=(dif_v + 2*o_ivsize + 8192) MOD 8192; + vcarry_v:=true; + END IF; + o_divstart<='1'; + IF o_vcpt_pre2=o_vmin THEN + o_vacc <=o_vacc_ini; + o_vacc_next<=o_vacc_ini + 2*o_ivsize; + o_vacpt<=x"001"; + vcarry_v:=false; + END IF; + + IF vcarry_v THEN + o_vacpt<=o_vacpt+1; + END IF; + o_hbcpt<=0; -- Clear burst counter on line + IF (o_vpe='1' AND vcarry_v) OR o_fload>0 THEN + o_state<=sREAD; + ELSE + o_state<=sDISP; + END IF; + + WHEN sREAD => + -- Read a block + IF o_readlev<2 AND o_adrsb='1' THEN + lev_inc_v:='1'; + o_read_pre<=NOT o_read_pre; + o_state <=sWAITREAD; + o_bibu<=NOT o_bibu; + END IF; + prim_v:=to_std_logic(o_hbcpt=0); + last_v:=to_std_logic(o_hbcpt=o_hburst-1); + bib_v :=o_bibu; + off_v :=pixoffset(o_adrs + o_fb_base(NB_LA-1 DOWNTO 0),o_fb_format); + IF o_fb_ena='0' THEN + off_v:=0; + END IF; + o_adrsa<='1'; + + WHEN sWAITREAD => + IF o_readack='1' THEN + o_hbcpt<=o_hbcpt+1; + IF o_hbcpt=1 THEN + o_fload<=o_fload-1; + END IF; + END IF; + END IF; + + -------------------------------------------------- + END CASE; + + o_read<=o_read_pre AND o_run; + o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video + + o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride); + IF o_adrsa='1' THEN + IF o_fload=2 THEN + o_adrs<=to_unsigned(o_hbcpt * N_BURST,32); + o_alt<="1111"; + ELSIF o_fload=1 THEN + o_adrs<=to_unsigned(o_hbcpt * N_BURST,32) + o_stride; + o_alt<="0100"; + ELSE + o_adrs<=to_unsigned(o_adrs_pre + (o_hbcpt * N_BURST),32); + o_alt<=altx(o_vacpt(1 DOWNTO 0) + 1); + END IF; + END IF; + + ------------------------------------------------------ + -- Copy from buffered memory to pixel lines + o_sh<='0'; + CASE o_copy IS + WHEN sWAIT => + o_copyv(0)<='0'; + IF o_copylev>0 AND o_copyv(0)='0' THEN + o_copy<=sCOPY; + IF o_off(0)>0 AND o_primv(0)='1' THEN + o_copy<=sSHIFT; + END IF; + o_altx<=o_alt; + END IF; + o_adturn<='0'; + o_pshift<=o_off(0) -1; + IF o_primv(0)='1' THEN + -- First memcopy of a horizontal line, carriage return ! + o_ihsizem<=o_ihsize + o_off(0) - 2; + o_hacc <=o_hacc_ini; + o_hacc_next<=o_hacc_ini + 2*o_ihsize; + o_hacpt <=x"000"; + o_dcpt<=0; + o_dshi<=2; + o_acpt<=0; + o_first<='1'; + o_last<='0'; + END IF; + + IF o_bibv(0)='0' THEN + o_ad<=0; + ELSE + o_ad<=BLEN; + END IF; + + WHEN sSHIFT => + o_hacpt<=o_hacpt+1; + o_sh<='1'; + o_acpt<=(o_acpt+1) MOD 16; + IF shift_onext(o_acpt,o_format) THEN + o_ad<=(o_ad+1) MOD (2*BLEN); + END IF; + o_pshift<=o_pshift-1; + IF o_pshift=0 THEN + o_copy<=sCOPY; + END IF; + + WHEN sCOPY => + -- dshi : Force shift first two or three pixels of each line + IF o_dshi=0 THEN + dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES); + IF dif_v>=4*OHRES THEN + o_hacc<=o_hacc_next; + o_hacc_next<=o_hacc_next + 2*o_ihsize; + hcarry_v:=false; + ELSE + o_hacc<=dif_v; + o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES); + hcarry_v:=true; + END IF; + o_dcpt<=(o_dcpt+1) MOD 4096; + ELSE + o_dshi<=o_dshi-1; + hcarry_v:=false; + END IF; + IF o_dshi<=1 THEN + o_copyv(0)<='1'; + END IF; + IF hcarry_v THEN + o_hacpt<=o_hacpt+1; + o_last <=to_std_logic(o_hacpt>=o_ihsizem); + END IF; + + IF hcarry_v OR o_dshi>0 THEN + o_sh<='1'; + o_acpt<=(o_acpt+1) MOD 16; + + -- Shift two more pixels to the right before ending line. + o_last1<=o_last; + o_last2<=o_last1; + + IF shift_onext(o_acpt,o_format) THEN + o_ad<=(o_ad+1) MOD (2*BLEN); + END IF; + + IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND + (((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1') THEN + o_copy<=sWAIT; + lev_dec_v:='1'; + END IF; + + IF o_ad MOD BLEN=4 THEN + o_adturn<='1'; + END IF; + END IF; + END CASE; + + o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3; + o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2; + o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2; o_sh4<=o_sh3; + o_lastt1<=o_last; o_lastt2<=o_lastt1; + o_lastt3<=o_lastt2; o_lastt4<=o_lastt3; + + ------------------------------------------------------ + IF o_sh3='1' THEN + shift_v:=shift_opack(o_acpt4,o_shift,o_dr,o_format); + o_shift<=shift_v; + o_hpixs<=shift_opix(shift_v,o_format); + END IF; + + IF o_sh4='1' THEN + hpix_v:=o_hpixs; + IF o_format(4)='1' THEN -- Swap B <-> R + hpix_v:=(r=>o_hpixs.b,g=>o_hpixs.g,b=>o_hpixs.r); + END IF; + IF o_format(2 DOWNTO 0)="011" THEN + -- 8bpp indexed colour mode + hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8), + b=>o_fb_pal_dr(7 DOWNTO 0)); + END IF; + o_hpix0<=hpix_v; + o_hpix1<=o_hpix0; + o_hpix2<=o_hpix1; + o_hpix3<=o_hpix2; + + IF o_first='1' THEN + -- Left edge. Duplicate first pixel + o_hpix1<=hpix_v; + o_hpix2<=hpix_v; + o_first<='0'; + END IF; + IF o_lastt4='1' THEN + -- Right edge. Keep last pixel. + o_hpix0<=o_hpix0; + END IF; + END IF; + + ------------------------------------------------------ + -- lev_inc : read start + -- lev_dec : end of copy + -- READLEV : Number of ongoing Avalon Reads + IF lev_dec_v='0' AND lev_inc_v='1' THEN + o_readlev<=o_readlev+1; + ELSIF lev_dec_v='1' AND lev_inc_v='0' THEN + o_readlev<=o_readlev-1; + END IF; + + -- COPYLEV : Number of ongoing copies to line buffers + IF lev_dec_v='1' AND o_readdataack='0' THEN + o_copylev<=o_copylev-1; + ELSIF lev_dec_v='0' AND o_readdataack='1' THEN + o_copylev<=o_copylev+1; + END IF; + + -- FIFOs + IF lev_dec_v='1' THEN + o_primv(0 TO 1)<=o_primv(1 TO 2); -- First buffer of line + o_lastv(0 TO 1)<=o_lastv(1 TO 2); -- Last buffer of line + o_bibv (0 TO 1)<=o_bibv (1 TO 2); -- Double buffer select + o_off (0 TO 1)<=o_off (1 TO 2); -- Start offset + END IF; + + IF lev_inc_v='1' THEN + IF o_readlev=0 OR (o_readlev=1 AND lev_dec_v='1') THEN + o_primv(0)<=prim_v; + o_lastv(0)<=last_v; + o_bibv (0)<=bib_v; + o_off (0)<=off_v; + ELSIF (o_readlev=1 AND lev_dec_v='0') OR + (o_readlev=2 AND lev_dec_v='1') THEN + o_primv(1)<=prim_v; + o_lastv(1)<=last_v; + o_bibv (1)<=bib_v; + o_off (1)<=off_v; + END IF; + o_primv(2)<=prim_v; + o_lastv(2)<=last_v; + o_bibv (2)<=bib_v; + o_off (2)<=off_v; + END IF; + + ------------------------------------------------------ + END IF; + END PROCESS Scalaire; + + o_h_poly_a<=to_integer(o_hfrac1(11 DOWNTO 12-FRAC)); + o_v_poly_a<=to_integer(o_vfrac(11 DOWNTO 12-FRAC)); + + o_h_poly_dr<=o_h_poly(o_h_poly_a) WHEN rising_edge(o_clk); + o_v_poly_dr<=o_v_poly(o_v_poly_a) WHEN rising_edge(o_clk); + + -- Framebuffer palette + GenPal1:IF PALETTE GENERATE + Tempera1:PROCESS(pal1_clk) IS + BEGIN + IF rising_edge(pal1_clk) THEN + IF pal1_wr='1' THEN + pal1_mem(to_integer(pal1_a))<=pal1_dw; + END IF; + pal1_dr<=pal1_mem(to_integer(pal1_a)); + END IF; + END PROCESS; + + pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7); + pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk); + o_fb_pal_dr_x2 <= pal1_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk); + END GENERATE GenPal1; + + GenPal2:IF PALETTE and PALETTE2 GENERATE + Tempera2:PROCESS(pal2_clk) IS + BEGIN + IF rising_edge(pal2_clk) THEN + IF pal2_wr='1' THEN + pal2_mem(to_integer(pal2_a))<=pal2_dw; + END IF; + pal2_dr<=pal2_mem(to_integer(pal2_a)); + END IF; + END PROCESS; + + o_fb_pal_dr2 <= pal2_mem(to_integer(pal_idx(7 DOWNTO 0))) WHEN rising_edge(o_clk); + o_fb_pal_dr <= o_fb_pal_dr2 when pal_n = '1' else o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); + END GENERATE GenPal2; + + GenPal1not2:IF PALETTE and not PALETTE2 GENERATE + o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); + END GENERATE GenPal1not2; + + GenNoPal:IF NOT PALETTE GENERATE + o_fb_pal_dr<=x"000000"; + END GENERATE GenNoPal; + + ----------------------------------------------------------------------------- + -- Polyphase ROMs + Polikarpov:PROCESS(poly_clk) IS + BEGIN + IF rising_edge(poly_clk) THEN + IF poly_wr='1' THEN + poly_tdw(8+9*(3-to_integer(poly_a(1 DOWNTO 0))) DOWNTO + 9*(3-to_integer(poly_a(1 DOWNTO 0))))<=poly_dw; + END IF; + + poly_h_wr<=poly_wr AND NOT poly_a(FRAC+2); + poly_v_wr<=poly_wr AND poly_a(FRAC+2); + poly_a2<=poly_a(FRAC+1 DOWNTO 2); + + IF poly_h_wr='1' THEN + o_h_poly(to_integer(poly_a2))<=poly_tdw; + END IF; + IF poly_v_wr='1' THEN + o_v_poly(to_integer(poly_a2))<=poly_tdw; + END IF; + END IF; + END PROCESS Polikarpov; + + ----------------------------------------------------------------------------- + -- Horizontal Scaler + HSCAL:PROCESS(o_clk) IS + VARIABLE div_v : unsigned(18 DOWNTO 0); + VARIABLE dir_v : unsigned(11 DOWNTO 0); + BEGIN + IF rising_edge(o_clk) THEN + -- Pipeline signals + ----------------------------------- + -- Pipelined 6 bits non-restoring divider. Cycle 1 + dir_v:=x"000"; + div_v:=to_unsigned(o_hacc * 64,19); + + div_v:=div_v-to_unsigned(o_hsize*64,19); + dir_v(11):=NOT div_v(18); + IF div_v(18)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*32,19); + ELSE + div_v:=div_v+to_unsigned(o_hsize*32,19); + END IF; + dir_v(10):=NOT div_v(18); + o_div<=div_v; + o_dir<=dir_v; + + -- Cycle 2 + div_v:=o_div; + dir_v:=o_dir; + IF div_v(18)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*16,19); + ELSE + div_v:=div_v+to_unsigned(o_hsize*16,19); + END IF; + dir_v( 9):=NOT div_v(18); + + IF div_v(18)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*8,19); + ELSE + div_v:=div_v+to_unsigned(o_hsize*8,19); + END IF; + dir_v(8):=NOT div_v(18); + o_div2<=div_v; + o_dir2<=dir_v; + + -- Cycle 3 + div_v:=o_div2; + dir_v:=o_dir2; + IF FRAC>4 THEN + IF div_v(18)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*4,19); + ELSE + div_v:=div_v+to_unsigned(o_hsize*4,19); + END IF; + dir_v(7):=NOT div_v(18); + IF div_v(18)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*2,19); + ELSE + div_v:=div_v+to_unsigned(o_hsize*2,19); + END IF; + dir_v(6):=NOT div_v(18); + END IF; + + ----------------------------------- + o_hfrac<=dir_v; + o_hfrac1<=o_hfrac; o_hfrac2<=o_hfrac1; + o_hfrac3<=o_hfrac2; o_hfrac4<=o_hfrac3; + + o_copyv(1 TO 8)<=o_copyv(0 TO 7); + + o_dcptv(1)<=o_dcpt; + IF o_dcptv(1)>=o_hsize THEN + o_copyv(2)<='0'; + END IF; + o_dcptv(2)<=o_dcptv(1) MOD OHRES; + o_dcptv(3 TO 8)<=o_dcptv(2 TO 7); + + o_hpixq<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0); + + -- NEAREST / BILINEAR / SHARP BILINEAR --------------- + -- C1 : Pre-calc Sharp Bilinear + o_h_sbil_t<=sbil_frac1(o_hfrac1); + + -- C2 : Select + o_h_frac2<=(OTHERS =>'0'); + CASE o_hmode(1 DOWNTO 0) IS + WHEN "00" => -- Nearest + IF MASK(MASK_NEAREST)='1' THEN + o_h_frac2<=near_frac(o_hfrac2); + END IF; + WHEN "01" => -- Bilinear + IF MASK(MASK_BILINEAR)='1' THEN + o_h_frac2<=bil_frac(o_hfrac2); + END IF; + WHEN "10" => -- Sharp Bilinear + IF MASK(MASK_SHARP_BILINEAR)='1' THEN + o_h_frac2<=sbil_frac2(o_hfrac2,o_h_sbil_t); + END IF; + WHEN OTHERS => + NULL; + END CASE; + + -- C3 : Opposite frac + o_h_bil_t<=bil_calc(o_h_frac2,o_hpixq); + + -- C4 : Nearest / Bilinear / Sharp Bilinear + o_h_bil_pix.r<=bound(o_h_bil_t.r,8+FRAC); + o_h_bil_pix.g<=bound(o_h_bil_t.g,8+FRAC); + o_h_bil_pix.b<=bound(o_h_bil_t.b,8+FRAC); + + -- BICUBIC ------------------------------------------- + -- C1 : Bicubic coefficients A,B,C,D + + -- C2 : Bicubic calc T1 = X.D + C + o_h_bic_abcd1<=bic_calc0(o_hfrac2,(o_hpix3,o_hpix2,o_hpix1,o_hpix0)); + o_h_bic_tt1<=bic_calc1(o_hfrac2, + bic_calc0(o_hfrac2,(o_hpix3,o_hpix2,o_hpix1,o_hpix0))); + + -- C3 : Bicubic calc T2 = X.T1 + B + o_h_bic_abcd2<=o_h_bic_abcd1; + o_h_bic_tt2<=bic_calc2(o_hfrac3,o_h_bic_tt1,o_h_bic_abcd1); + + -- C4 : Bicubic final Y = X.T2 + A + o_h_bic_pix<=bic_calc3(o_hfrac4,o_h_bic_tt2,o_h_bic_abcd2); + + -- POLYPHASE ----------------------------------------- + -- C1 : Read memory + + -- C2 : Filter calc + o_h_poly_dr2<=o_h_poly_dr; + + -- C3 : Add + o_h_poly_t<=poly_calc1(o_h_poly_dr2,o_hpixq); + + -- C4 : Bounding + o_h_poly_pix<=poly_calc2(o_h_poly_t); + + -- C5 : Select interpoler ---------------------------- + o_wadl<=o_dcptv(8); + o_wr<=o_altx AND (o_copyv(8) & o_copyv(8) & o_copyv(8) & o_copyv(8)); + o_ldw<=(x"00",x"00",x"00"); + + CASE o_hmode(2 DOWNTO 0) IS + WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear + IF MASK(MASK_NEAREST)='1' OR + MASK(MASK_BILINEAR)='1' OR + MASK(MASK_SHARP_BILINEAR)='1' THEN + o_ldw<=o_h_bil_pix; + END IF; + WHEN "011" => -- BiCubic + IF MASK(MASK_BICUBIC)='1' THEN + o_ldw<=o_h_bic_pix; + END IF; + WHEN OTHERS => -- PolyPhase + IF MASK(MASK_POLY)='1' THEN + o_ldw<=o_h_poly_pix; + END IF; + END CASE; + ------------------------------------------------------ + END IF; + END PROCESS HSCAL; + + ----------------------------------------------------------------------------- + -- Line buffers 4 x OHRES x (R+G+B) + OLBUF:PROCESS(o_clk) IS + BEGIN + IF rising_edge(o_clk) THEN + -- WRITES + IF o_wr(0)='1' THEN o_line0(o_wadl)<=o_ldw; END IF; + IF o_wr(1)='1' THEN o_line1(o_wadl)<=o_ldw; END IF; + IF o_wr(2)='1' THEN o_line2(o_wadl)<=o_ldw; END IF; + IF o_wr(3)='1' THEN o_line3(o_wadl)<=o_ldw; END IF; + + -- READS + o_ldr0<=o_line0(o_radl); + o_ldr1<=o_line1(o_radl); + o_ldr2<=o_line2(o_radl); + o_ldr3<=o_line3(o_radl); + END IF; + END PROCESS OLBUF; + + ----------------------------------------------------------------------------- + -- Output video sweep + OSWEEP:PROCESS(o_clk) IS + BEGIN + IF rising_edge(o_clk) THEN + IF o_ce='1' THEN + -- Output pixels count + IF o_hcpt+1=o_vtotal THEN + o_vcpt_pre3<=0; + ELSE + o_vcpt_pre3<=(o_vcpt_pre3+1) MOD 4096; + END IF; + o_vcpt_pre2<=o_vcpt_pre3; + o_vcpt_pre<=o_vcpt_pre2; + o_vcpt<=o_vcpt_pre; + END IF; + + o_end(0)<=to_std_logic(o_vcpt>=o_vdisp); + o_dev(0)<=to_std_logic(o_hcpt=o_hmin AND o_hcpt<=o_hmax AND + o_vcpt>=o_vmin AND o_vcpt<=o_vmax); + o_hsv(0)<=to_std_logic(o_hcpt>=o_hsstart AND o_hcpt=o_hsstart) OR + (o_vcpt>o_vsstart AND o_vcpt=o_vmin AND o_vcpt_pre2<=o_vmax); + o_hsv(1 TO 5)<=o_hsv(0 TO 4); + o_vsv(1 TO 5)<=o_vsv(0 TO 4); + o_dev(1 TO 5)<=o_dev(0 TO 4); + o_pev(1 TO 5)<=o_pev(0 TO 4); + o_end(1 TO 5)<=o_end(0 TO 4); + + IF o_run='0' THEN + o_hsv(2)<='0'; + o_vsv(2)<='0'; + o_dev(2)<='0'; + o_pev(2)<='0'; + o_end(2)<='0'; + END IF; + + END IF; + END IF; + + END PROCESS OSWEEP; + + ----------------------------------------------------------------------------- + -- Vertical Scaler + VSCAL:PROCESS(o_clk) IS + VARIABLE pixq_v : arr_pix(0 TO 3); + BEGIN + IF rising_edge(o_clk) THEN + IF o_ce='1' THEN + -- CYCLE 1 ----------------------------------------- + -- Read mem + o_radl<=(o_hcpt - o_hmin + OHRES) MOD OHRES; + + -- CYCLE 2 ----------------------------------------- + -- Lines reordering + CASE o_vacpt(1 DOWNTO 0) IS + WHEN "10" => pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3); + WHEN "11" => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0); + WHEN "00" => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1); + WHEN OTHERS => pixq_v:=(o_ldr3,o_ldr0,o_ldr1,o_ldr2); + END CASE; + + o_vpixq<=pixq_v; + + -- Bottom edge : replicate last line + IF to_integer(o_vacpt)=o_ivsize THEN + o_vpixq(2)<=pixq_v(2); + END IF; + IF to_integer(o_vacpt)>=o_ivsize+1 THEN + o_vpixq(2)<=pixq_v(1); + o_vpixq(1)<=pixq_v(1); + END IF; + + o_vpixq1<=o_vpixq; + + -- NEAREST / BILINEAR / SHARP BILINEAR ------------- + -- C3 : Pre-calc Sharp Bilinear + o_v_sbil_t<=sbil_frac1(o_vfrac); + + -- C4 : Select + o_v_frac<=(OTHERS =>'0'); + CASE o_vmode(1 DOWNTO 0) IS + WHEN "00" => -- Nearest + IF MASK(MASK_NEAREST)='1' THEN + o_v_frac<=near_frac(o_vfrac); + END IF; + WHEN "01" => -- Bilinear + IF MASK(MASK_BILINEAR)='1' THEN + o_v_frac<=bil_frac(o_vfrac); + END IF; + WHEN "10" => -- Sharp Bilinear + IF MASK(MASK_SHARP_BILINEAR)='1' THEN + o_v_frac<=sbil_frac2(o_vfrac,o_v_sbil_t); + END IF; + WHEN OTHERS => NULL; + END CASE; + + o_v_bil_t<=bil_calc(o_v_frac,o_vpixq1); + + -- C6 : Nearest / Bilinear / Sharp Bilinear + o_v_bil_pix.r<=bound(o_v_bil_t.r,8+FRAC); + o_v_bil_pix.g<=bound(o_v_bil_t.g,8+FRAC); + o_v_bil_pix.b<=bound(o_v_bil_t.b,8+FRAC); + + -- BICUBIC ----------------------------------------- + -- C3 : Bicubic coefficients A,B,C,D + + -- C4 : Bicubic calc T1 = X.D + C + o_v_bic_abcd1<=bic_calc0(o_vfrac,o_vpixq); + o_v_bic_tt1<=bic_calc1(o_vfrac,bic_calc0(o_vfrac,o_vpixq)); + + -- C5 : Bicubic calc T2 = X.T1 + B + o_v_bic_abcd2<=o_v_bic_abcd1; + o_v_bic_tt2<=bic_calc2(o_vfrac,o_v_bic_tt1,o_v_bic_abcd1); + + -- C6 : Bicubic final Y = X.T2 + A + o_v_bic_pix<=bic_calc3(o_vfrac,o_v_bic_tt2,o_v_bic_abcd2); + + -- POLYPHASE --------------------------------------- + -- C3 : Read memory + + -- C4 : Filter calc + o_v_poly_dr2<=o_v_poly_dr; + + -- C5 : Add + o_v_poly_t<=poly_calc1(o_v_poly_dr2,o_vpixq1); + + -- C6 : Bounding + o_v_poly_pix<=poly_calc2(o_v_poly_t); + + -- CYCLE 6 ----------------------------------------- + o_hs<=o_hsv(5); + o_vs<=o_vsv(5); + o_de<=o_dev(5); + o_vbl<=o_end(5); + o_r<=x"00"; + o_g<=x"00"; + o_b<=x"00"; + + CASE o_vmode(2 DOWNTO 0) IS + WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear + IF MASK(MASK_NEAREST)='1' OR + MASK(MASK_BILINEAR)='1' OR + MASK(MASK_SHARP_BILINEAR)='1' THEN + o_r<=o_v_bil_pix.r; + o_g<=o_v_bil_pix.g; + o_b<=o_v_bil_pix.b; + END IF; + WHEN "011" => -- BiCubic + IF MASK(MASK_BICUBIC)='1' THEN + o_r<=o_v_bic_pix.r; + o_g<=o_v_bic_pix.g; + o_b<=o_v_bic_pix.b; + END IF; + + WHEN OTHERS => -- Polyphase + IF MASK(MASK_POLY)='1' THEN + o_r<=o_v_poly_pix.r; + o_g<=o_v_poly_pix.g; + o_b<=o_v_poly_pix.b; + END IF; + END CASE; + + IF o_pev(5)='0' THEN + o_r<=o_border(23 DOWNTO 16); -- Copy border colour + o_g<=o_border(15 DOWNTO 8); + o_b<=o_border(7 DOWNTO 0); + END IF; + + ---------------------------------------------------- + END IF; + END IF; + + END PROCESS VSCAL; + + ----------------------------------------------------------------------------- + -- Low Lag syntoniser interface + o_lltune<=(0 => i_vss, + 1 => i_pde, + 2 => i_inter, + 3 => i_flm, + 4 => o_vss, + 5 => i_pce, + 6 => i_clk, + 7 => o_clk, + OTHERS =>'0'); + + ---------------------------------------------------------------------------- +END ARCHITECTURE rtl; diff --git a/sys/audio_out.v b/sys/audio_out.v new file mode 100644 index 0000000..0f748e0 --- /dev/null +++ b/sys/audio_out.v @@ -0,0 +1,296 @@ + +module audio_out +#( + parameter CLK_RATE = 24576000 +) +( + input reset, + input clk, + + //0 - 48KHz, 1 - 96KHz + input sample_rate, + + input [31:0] flt_rate, + input [39:0] cx, + input [7:0] cx0, + input [7:0] cx1, + input [7:0] cx2, + input [23:0] cy0, + input [23:0] cy1, + input [23:0] cy2, + + input [4:0] att, + input [1:0] mix, + + input is_signed, + input [15:0] core_l, + input [15:0] core_r, + + input [15:0] alsa_l, + input [15:0] alsa_r, + + // I2S + output i2s_bclk, + output i2s_lrclk, + output i2s_data, + + // SPDIF + output spdif, + + // Sigma-Delta DAC + output dac_l, + output dac_r +); + +localparam AUDIO_RATE = 48000; +localparam AUDIO_DW = 16; + +localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8; +localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1; + +wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0]; + +reg mclk_ce; +always @(posedge clk) begin + reg [31:0] cnt; + + mclk_ce = 0; + cnt = cnt + real_ce; + if(cnt >= CLK_RATE) begin + cnt = cnt - CLK_RATE; + mclk_ce = 1; + end +end + +reg i2s_ce; +always @(posedge clk) begin + reg div; + i2s_ce <= 0; + if(mclk_ce) begin + div <= ~div; + i2s_ce <= div; + end +end + +i2s i2s +( + .reset(reset), + + .clk(clk), + .ce(i2s_ce), + + .sclk(i2s_bclk), + .lrclk(i2s_lrclk), + .sdata(i2s_data), + + .left_chan(al), + .right_chan(ar) +); + +spdif toslink +( + .rst_i(reset), + + .clk_i(clk), + .bit_out_en_i(mclk_ce), + + .sample_i({ar,al}), + .spdif_o(spdif) +); + +sigma_delta_dac #(15) sd_l +( + .CLK(clk), + .RESET(reset), + .DACin({~al[15], al[14:0]}), + .DACout(dac_l) +); + +sigma_delta_dac #(15) sd_r +( + .CLK(clk), + .RESET(reset), + .DACin({~ar[15], ar[14:0]}), + .DACout(dac_r) +); + +reg sample_ce; +always @(posedge clk) begin + reg [8:0] div = 0; + reg [1:0] add = 0; + + div <= div + add; + if(!div) begin + div <= 2'd1 << sample_rate; + add <= 2'd1 << sample_rate; + end + + sample_ce <= !div; +end + +reg flt_ce; +always @(posedge clk) begin + reg [31:0] cnt = 0; + + flt_ce = 0; + cnt = cnt + {flt_rate[30:0],1'b0}; + if(cnt >= CLK_RATE) begin + cnt = cnt - CLK_RATE; + flt_ce = 1; + end +end + +reg [15:0] cl,cr; +always @(posedge clk) begin + reg [15:0] cl1,cl2; + reg [15:0] cr1,cr2; + + cl1 <= core_l; cl2 <= cl1; + if(cl2 == cl1) cl <= cl2; + + cr1 <= core_r; cr2 <= cr1; + if(cr2 == cr1) cr <= cr2; +end + +reg a_en1 = 0, a_en2 = 0; +always @(posedge clk, posedge reset) begin + reg [1:0] dly1 = 0; + reg [14:0] dly2 = 0; + + if(reset) begin + dly1 <= 0; + dly2 <= 0; + a_en1 <= 0; + a_en2 <= 0; + end + else begin + if(flt_ce) begin + if(~&dly1) dly1 <= dly1 + 1'd1; + else a_en1 <= 1; + end + + if(sample_ce) begin + if(!dly2[13+sample_rate]) dly2 <= dly2 + 1'd1; + else a_en2 <= 1; + end + end +end + +wire [15:0] acl, acr; +IIR_filter #(.use_params(0)) IIR_filter +( + .clk(clk), + .reset(reset), + + .ce(flt_ce & a_en1), + .sample_ce(sample_ce), + + .cx(cx), + .cx0(cx0), + .cx1(cx1), + .cx2(cx2), + .cy0(cy0), + .cy1(cy1), + .cy2(cy2), + + .input_l({~is_signed ^ cl[15], cl[14:0]}), + .input_r({~is_signed ^ cr[15], cr[14:0]}), + .output_l(acl), + .output_r(acr) +); + +wire [15:0] adl; +DC_blocker dcb_l +( + .clk(clk), + .ce(sample_ce), + .sample_rate(sample_rate), + .mute(~a_en2), + .din(acl), + .dout(adl) +); + +wire [15:0] adr; +DC_blocker dcb_r +( + .clk(clk), + .ce(sample_ce), + .sample_rate(sample_rate), + .mute(~a_en2), + .din(acr), + .dout(adr) +); + +wire [15:0] al, audio_l_pre; +aud_mix_top audmix_l +( + .clk(clk), + .ce(sample_ce), + .att(att), + .mix(mix), + + .core_audio(adl), + .pre_in(audio_r_pre), + .linux_audio(alsa_l), + + .pre_out(audio_l_pre), + .out(al) +); + +wire [15:0] ar, audio_r_pre; +aud_mix_top audmix_r +( + .clk(clk), + .ce(sample_ce), + .att(att), + .mix(mix), + + .core_audio(adr), + .pre_in(audio_l_pre), + .linux_audio(alsa_r), + + .pre_out(audio_r_pre), + .out(ar) +); + +endmodule + +module aud_mix_top +( + input clk, + input ce, + + input [4:0] att, + input [1:0] mix, + + input [15:0] core_audio, + input [15:0] linux_audio, + input [15:0] pre_in, + + output reg [15:0] pre_out = 0, + output reg [15:0] out = 0 +); + +reg signed [16:0] a1, a2, a3, a4; +always @(posedge clk) if (ce) begin + + a1 <= {core_audio[15],core_audio}; + a2 <= a1 + {linux_audio[15],linux_audio}; + + pre_out <= a2[16:1]; + + case(mix) + 0: a3 <= a2; + 1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]); + 2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]); + 3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in}; + endcase + + if(att[4]) a4 <= 0; + else a4 <= a3 >>> att[3:0]; + + //clamping + out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0]; +end + +endmodule diff --git a/sys/build_id.tcl b/sys/build_id.tcl index 8777a14..bb2dc67 100644 --- a/sys/build_id.tcl +++ b/sys/build_id.tcl @@ -1,25 +1,29 @@ # Build TimeStamp Verilog Module # Jeff Wiencrot - 8/1/2011 +# Sorgelig - 02/11/2019 proc generateBuildID_Verilog {} { # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\"" # Create a Verilog file for output set outputFileName "build_id.v" - set outputFile [open $outputFileName "w"] + + set fileData "" + if { [file exists $outputFileName]} { + set outputFile [open $outputFileName "r"] + set fileData [read $outputFile] + close $outputFile + } - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" + if {$buildDate ne $fileData} { + set outputFile [open $outputFileName "w"] + puts -nonewline $outputFile $buildDate + close $outputFile + # Send confirmation message to the Messages window + post_message "Generated: [pwd]/$outputFileName: $buildDate" + } } # Build CDF file diff --git a/sys/ddr_svc.sv b/sys/ddr_svc.sv new file mode 100644 index 0000000..abcd4fa --- /dev/null +++ b/sys/ddr_svc.sv @@ -0,0 +1,108 @@ +// +// Copyright (c) 2020 Alexey Melnikov +// +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// + +// 16-bit version + +module ddr_svc +( + input clk, + + input ram_waitrequest, + output [7:0] ram_burstcnt, + output [28:0] ram_addr, + input [63:0] ram_readdata, + input ram_read_ready, + output reg ram_read, + output [63:0] ram_writedata, + output [7:0] ram_byteenable, + output reg ram_write, + + output [7:0] ram_bcnt, + + input [31:3] ch0_addr, + input [7:0] ch0_burst, + output [63:0] ch0_data, + input ch0_req, + output ch0_ready, + + input [31:3] ch1_addr, + input [7:0] ch1_burst, + output [63:0] ch1_data, + input ch1_req, + output ch1_ready +); + +assign ram_burstcnt = ram_burst; +assign ram_byteenable = 8'hFF; +assign ram_addr = ram_address; +assign ram_writedata = 0; + +assign ch0_data = ram_q[0]; +assign ch1_data = ram_q[1]; +assign ch0_ready = ready[0]; +assign ch1_ready = ready[1]; + +reg [7:0] ram_burst; +reg [63:0] ram_q[2]; +reg [31:3] ram_address; +reg [1:0] ack = 0; +reg [1:0] ready; +reg state = 0; +reg ch = 0; + +always @(posedge clk) begin + ready <= 0; + + if(!ram_waitrequest) begin + ram_read <= 0; + ram_write <= 0; + + case(state) + 0: if(ch0_req != ack[0]) begin + ack[0] <= ch0_req; + ram_address <= ch0_addr; + ram_burst <= ch0_burst; + ram_read <= 1; + ch <= 0; + ram_bcnt <= 8'hFF; + state <= 1; + end + else if(ch1_req != ack[1]) begin + ack[1] <= ch1_req; + ram_address <= ch1_addr; + ram_burst <= ch1_burst; + ram_read <= 1; + ch <= 1; + ram_bcnt <= 8'hFF; + state <= 1; + end + 1: begin + if(ram_read_ready) begin + ram_bcnt <= ram_bcnt + 1'd1; + ram_q[ch] <= ram_readdata; + ready[ch] <= 1; + if ((ram_bcnt+2'd2) == ram_burst) state <= 0; + end + end + endcase + end +end + +endmodule diff --git a/sys/f2sdram_safe_terminator.sv b/sys/f2sdram_safe_terminator.sv new file mode 100644 index 0000000..07085d7 --- /dev/null +++ b/sys/f2sdram_safe_terminator.sv @@ -0,0 +1,250 @@ +// ============================================================================ +// +// f2sdram_safe_terminator for MiSTer platform +// +// ============================================================================ +// Copyright (c) 2021 bellwood420 +// +// Background: +// +// Terminating a transaction of burst writing(/reading) in its midstream +// seems to cause an illegal state to f2sdram interface. +// +// Forced reset request that occurs when loading other core is inevitable. +// +// So if it happens exactly within the transaction period, +// unexpected issues with accessing to f2sdram interface will be caused +// in next loaded core. +// +// It seems that only way to reset broken f2sdram interface is to reset +// whole SDRAM Controller Subsystem from HPS via permodrst register +// in Reset Manager. +// But it cannot be done safely while Linux is running. +// It is usually done when cold or warm reset is issued in HPS. +// +// Main_MiSTer is issuing reset for FPGA <> HPS bridges +// via brgmodrst register in Reset Manager when loading rbf. +// But it has no effect on f2sdram interface. +// f2sdram interface seems to belong to SDRAM Controller Subsystem +// rather than FPGA-to-HPS bridge. +// +// Main_MiSTer is also trying to issuing reset for f2sdram ports +// via fpgaportrst register in SDRAM Controller Subsystem when loading rbf. +// But according to the Intel's document, fpgaportrst register can be +// used to stretch the port reset. +// It seems that it cannot be used to assert the port reset. +// +// According to the Intel's document, there seems to be a reset port on +// Avalon-MM slave interface, but it cannot be found in Qsys generated HDL. +// +// To conclude, the only thing FPGA can do is not to break the transaction. +// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// +// Purpose: +// To prevent the issue, this module completes ongoing transaction +// on behalf of user logic, when reset is asserted. +// +// Usage: +// Insert this module into the bus line between +// f2sdram (Avalon-MM slave) and user logic (Avalon-MM master). +// +// Notice: +// Asynchronous reset request is not supported. +// Please feed reset request synchronized to clock. +// +module f2sdram_safe_terminator #( + parameter DATA_WIDTH = 64, + parameter BURSTCOUNT_WIDTH = 8 +) ( + // clk should be the same as one provided to f2sdram port + // clk should not be stop when reset is asserted + input clk, + // rst_req_sync should be synchronized to clk + // Asynchronous reset request is not supported + input rst_req_sync, + + // Master port: connecting to Alavon-MM slave(f2sdram) + input waitrequest_master, + output [BURSTCOUNT_WIDTH-1:0] burstcount_master, + output [ADDRESS_WITDH-1:0] address_master, + input [DATA_WIDTH-1:0] readdata_master, + input readdatavalid_master, + output read_master, + output [DATA_WIDTH-1:0] writedata_master, + output [BYTEENABLE_WIDTH-1:0] byteenable_master, + output write_master, + + // Slave port: connecting to Alavon-MM master(user logic) + output waitrequest_slave, + input [BURSTCOUNT_WIDTH-1:0] burstcount_slave, + input [ADDRESS_WITDH-1:0] address_slave, + output [DATA_WIDTH-1:0] readdata_slave, + output readdatavalid_slave, + input read_slave, + input [DATA_WIDTH-1:0] writedata_slave, + input [BYTEENABLE_WIDTH-1:0] byteenable_slave, + input write_slave +); + +localparam BYTEENABLE_WIDTH = DATA_WIDTH/8; +localparam ADDRESS_WITDH = 32-$clog2(BYTEENABLE_WIDTH); + +/* +* Capture init reset deaseert +*/ +reg init_reset_deasserted = 1'b0; + +always_ff @(posedge clk) begin + if (!rst_req_sync) begin + init_reset_deasserted <= 1'b1; + end +end + +/* +* Lock stage +*/ +reg lock_stage = 1'b0; + +always_ff @(posedge clk) begin + if (rst_req_sync) begin + // Reset assert + if (init_reset_deasserted) begin + lock_stage <= 1'b1; + end + end + else begin + // Reset deassert + lock_stage <= 1'b0; + end +end + +/* +* Write burst transaction observer +*/ +reg state_write = 1'b0; +wire next_state_write; + +wire burst_write_start = !state_write && next_state_write; +wire valid_write_data = state_write && !waitrequest_master; +wire burst_write_end = state_write && (write_burstcounter == write_burstcount_latch - 1'd1); +wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master; + +reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter = 0; +reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0; +reg [ADDRESS_WITDH-1:0] write_address_latch = 0; + +always_ff @(posedge clk) begin + state_write <= next_state_write; + + if (burst_write_start) begin + write_burstcounter <= waitrequest_master ? 1'd0 : 1'd1; + write_burstcount_latch <= burstcount_slave; + write_address_latch <= address_slave; + end + else if (valid_write_data) begin + write_burstcounter <= write_burstcounter + 1'd1; + end +end + +always_comb begin + if (!state_write) begin + if (valid_non_burst_write) + next_state_write = 1'b0; + else if (write_slave) + next_state_write = 1'b1; + else + next_state_write = 1'b0; + end + else begin + if (burst_write_end) + next_state_write = 1'b0; + else + next_state_write = 1'b1; + end +end + +reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0; +reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch = 0; +reg [ADDRESS_WITDH-1:0] address_latch = 0; + +reg terminating = 0; +reg read_terminating = 0; +reg write_terminating = 0; + +wire on_write_transaction = state_write && next_state_write; +wire on_start_write_transaction = !state_write && next_state_write; + +always_ff @(posedge clk) begin + if (rst_req_sync) begin + // Reset assert + if (init_reset_deasserted) begin + if (!lock_stage) begin + // Even not knowing reading is in progress or not, + // if it is in progress, it will finish at some point, and no need to do anything. + // Assume that reading is in progress when we are not on write transaction. + burstcount_latch <= burstcount_slave; + address_latch <= address_slave; + terminating <= 1; + + if (on_write_transaction) begin + write_terminating <= 1; + burstcount_latch <= write_burstcount_latch; + address_latch <= write_address_latch; + write_terminate_counter <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1; + end + else if (on_start_write_transaction) begin + if (!valid_non_burst_write) begin + write_terminating <= 1; + write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1; + end + end + else if (read_slave && waitrequest_master) begin + // Need to keep read signal, burstcount and address until waitrequest_master deasserted + read_terminating <= 1; + end + end + else if (!waitrequest_master) begin + read_terminating <= 0; + end + end + end + else begin + // Reset deassert + if (!write_terminating) terminating <= 0; + read_terminating <= 0; + end + + if (write_terminating) begin + // Continue write transaction until the end + if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1; + if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0; + end +end + +/* +* Bus mux depending on the stage. +*/ +always_comb begin + if (terminating) begin + burstcount_master = burstcount_latch; + address_master = address_latch; + read_master = read_terminating; + write_master = write_terminating; + byteenable_master = 0; + end + else begin + burstcount_master = burstcount_slave; + address_master = address_slave; + read_master = read_slave; + byteenable_master = byteenable_slave; + write_master = write_slave; + end +end + +// Just passing master <-> slave +assign writedata_master = writedata_slave; +assign readdata_slave = readdata_master; +assign readdatavalid_slave = readdatavalid_master; +assign waitrequest_slave = waitrequest_master; + +endmodule diff --git a/sys/gamma_corr.sv b/sys/gamma_corr.sv new file mode 100644 index 0000000..321b83f --- /dev/null +++ b/sys/gamma_corr.sv @@ -0,0 +1,124 @@ +module gamma_corr +( + input clk_sys, + input clk_vid, + input ce_pix, + input gamma_en, + input gamma_wr, + input [9:0] gamma_wr_addr, + input [7:0] gamma_value, + input HSync, + input VSync, + input HBlank, + input VBlank, + input [23:0] RGB_in, + output reg HSync_out, + output reg VSync_out, + output reg HBlank_out, + output reg VBlank_out, + output reg [23:0] RGB_out +); + +(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768]; + +always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value; +always @(posedge clk_vid) gamma <= gamma_curve[gamma_index]; + +reg [9:0] gamma_index; +reg [7:0] gamma; + +always @(posedge clk_vid) begin + reg [7:0] R_in, G_in, B_in; + reg [7:0] R_gamma, G_gamma; + reg hs,vs,hb,vb; + reg [1:0] ctr = 0; + reg old_ce; + + old_ce <= ce_pix; + if(~old_ce & ce_pix) begin + {R_in,G_in,B_in} <= RGB_in; + hs <= HSync; vs <= VSync; + hb <= HBlank; vb <= VBlank; + + RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in}; + HSync_out <= hs; VSync_out <= vs; + HBlank_out <= hb; VBlank_out <= vb; + + ctr <= 1; + gamma_index <= {2'b00,RGB_in[23:16]}; + end + + if (|ctr) ctr <= ctr + 1'd1; + + case(ctr) + 1: begin gamma_index <= {2'b01,G_in}; end + 2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end + 3: begin G_gamma <= gamma; end + endcase +end + +endmodule + +module gamma_fast +( + input clk_vid, + input ce_pix, + + inout [21:0] gamma_bus, + + input HSync, + input VSync, + input HBlank, + input VBlank, + input DE, + input [23:0] RGB_in, + + output reg HSync_out, + output reg VSync_out, + output reg HBlank_out, + output reg VBlank_out, + output reg DE_out, + output reg [23:0] RGB_out +); + +(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_r[256]; +(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_g[256]; +(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_b[256]; + +assign gamma_bus[21] = 1; +wire clk_sys = gamma_bus[20]; +wire gamma_en = gamma_bus[19]; +wire gamma_wr = gamma_bus[18]; +wire [9:0] gamma_wr_addr = gamma_bus[17:8]; +wire [7:0] gamma_value = gamma_bus[7:0]; + +always @(posedge clk_sys) if (gamma_wr) begin + case(gamma_wr_addr[9:8]) + 0: gamma_curve_r[gamma_wr_addr[7:0]] <= gamma_value; + 1: gamma_curve_g[gamma_wr_addr[7:0]] <= gamma_value; + 2: gamma_curve_b[gamma_wr_addr[7:0]] <= gamma_value; + endcase +end + +reg [7:0] gamma_index_r,gamma_index_g,gamma_index_b; + +always @(posedge clk_vid) begin + reg [7:0] R_in, G_in, B_in; + reg [7:0] R_gamma, G_gamma; + reg hs,vs,hb,vb,de; + + if(ce_pix) begin + {gamma_index_r,gamma_index_g,gamma_index_b} <= RGB_in; + hs <= HSync; vs <= VSync; + hb <= HBlank; vb <= VBlank; + de <= DE; + + RGB_out <= gamma_en ? {gamma_curve_r[gamma_index_r],gamma_curve_g[gamma_index_g],gamma_curve_b[gamma_index_b]} + : {gamma_index_r,gamma_index_g,gamma_index_b}; + HSync_out <= hs; VSync_out <= vs; + HBlank_out <= hb; VBlank_out <= vb; + DE_out <= de; + end +end + +endmodule diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv index 0265c5c..4a0a13d 100644 --- a/sys/hdmi_config.sv +++ b/sys/hdmi_config.sv @@ -2,11 +2,15 @@ module hdmi_config ( // Host Side - input iCLK, - input iRST_N, + input iCLK, + input iRST_N, input dvi_mode, input audio_96k, + input [1:0] limited, + input ypbpr, + + output reg done, // I2C Side output I2C_SCL, @@ -24,13 +28,17 @@ i2c #(50_000_000, 20_000) i2c_av ( .CLK(iCLK), - .I2C_SCL(I2C_SCL), // I2C CLOCK - .I2C_SDA(I2C_SDA), // I2C DATA + .I2C_SCL(I2C_SCL), // I2C CLOCK + .I2C_SDA(I2C_SDA), // I2C DATA - .I2C_DATA({8'h72,init_data[LUT_INDEX]}), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip! - .START(mI2C_GO), // START transfer - .END(mI2C_END), // END transfer - .ACK(mI2C_ACK) // ACK + .I2C_ADDR('h39), // 0x39 is the Slave Address of the ADV7513 chip! + .I2C_WLEN(1), + .I2C_WDATA1(init_data[LUT_INDEX][15:8]), // SUB_ADDR + .I2C_WDATA2(init_data[LUT_INDEX][7:0]), // DATA + .START(mI2C_GO), // START transfer + .READ(0), + .END(mI2C_END), // END transfer + .ACK(mI2C_ACK) // ACK ); ////////////////////// Config Control //////////////////////////// @@ -41,6 +49,7 @@ always@(posedge iCLK or negedge iRST_N) begin LUT_INDEX <= 0; mSetup_ST <= 0; mI2C_GO <= 0; + done <= 0; end else begin if(init_data[LUT_INDEX] != 16'hFFFF) begin case(mSetup_ST) @@ -58,13 +67,14 @@ always@(posedge iCLK or negedge iRST_N) begin end endcase end + else done <= 1; end end //////////////////////////////////////////////////////////////////// ///////////////////// Config Data LUT ////////////////////////// -wire [15:0] init_data[58] = +wire [15:0] init_data[82] = '{ 16'h9803, // ADI required Write. @@ -101,10 +111,32 @@ wire [15:0] init_data[58] = {8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0 - {8'h18, 8'b0100_0110}, // CSC disabled [7]=0. - // CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380. - // CSC Equation 3 [4:0] b00110. + {8'h18, ypbpr ? 8'h86 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited. + {8'h19, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide. + {8'h1A, ypbpr ? 8'h1A : 8'h00}, // CSC Channel A. + {8'h1B, ypbpr ? 8'h3F : 8'h00}, + {8'h1C, ypbpr ? 8'h1E : 8'h00}, + {8'h1D, ypbpr ? 8'hE2 : 8'h00}, + {8'h1E, ypbpr ? 8'h07 : 8'h01}, + {8'h1F, ypbpr ? 8'hE7 : 8'h00}, + {8'h20, ypbpr ? 8'h04 : 8'h00}, // CSC Channel B. + {8'h21, ypbpr ? 8'h1C : 8'h00}, + {8'h22, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E}, + {8'h23, ypbpr ? 8'h11 : limited[0] ? 8'hBC : 8'hFE}, + {8'h24, ypbpr ? 8'h01 : 8'h00}, + {8'h25, ypbpr ? 8'h91 : 8'h00}, + {8'h26, ypbpr ? 8'h01 : 8'h01}, + {8'h27, 8'h00}, + + {8'h28, ypbpr ? 8'h1D : 8'h00}, // CSC Channel C. + {8'h29, ypbpr ? 8'hAE : 8'h00}, + {8'h2A, ypbpr ? 8'h1B : 8'h00}, + {8'h2B, ypbpr ? 8'h73 : 8'h00}, + {8'h2C, ypbpr ? 8'h06 : limited[0] ? 8'h0D : 8'h0E}, + {8'h2D, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE}, + {8'h2E, ypbpr ? 8'h07 : 8'h01}, + {8'h2F, ypbpr ? 8'hE7 : 8'h00}, {8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx. @@ -122,6 +154,11 @@ wire [15:0] init_data[58] = // Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both. // Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None. + {8'h57, 1'b0, // [7] IT Content. 0 - No. 1 - Yes (type set in register h59). + 3'b000, // [6:4] Color space (ignored for RGB) + (ypbpr | limited) ? 2'b01 : 2'b10, // [3:2] RGB Quantization range + 2'b00}, // [1:0] Non-Uniform Scaled: 00 - None. 01 - Horiz. 10 - Vert. 11 - Both. + 16'h7301, {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled. @@ -142,9 +179,9 @@ wire [15:0] init_data[58] = 16'hAA00, // ADI required Write. 16'hAB40, // ADI required Write. - {8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled. + {8'hAF, 6'b0000_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled. // [6:5] must be b00! - // [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?) + // [4]=0 Current frame is unencrypted // [3:2] must be b01! // [1]=1 HDMI Mode. // [0] must be b0! diff --git a/sys/hdmi_lite.sv b/sys/hdmi_lite.sv deleted file mode 100644 index ef80764..0000000 --- a/sys/hdmi_lite.sv +++ /dev/null @@ -1,395 +0,0 @@ -//============================================================================ -// -// HDMI Lite output module -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -//============================================================================ - - -module hdmi_lite -( - input reset, - - input clk_video, - input ce_pixel, - input video_vs, - input video_de, - input [23:0] video_d, - - input clk_hdmi, - input hdmi_hde, - input hdmi_vde, - output reg hdmi_de, - output [23:0] hdmi_d, - - input [11:0] screen_w, - input [11:0] screen_h, - input quadbuf, - - // 0-3 => scale 1-4 - input [1:0] scale_x, - input [1:0] scale_y, - input scale_auto, - - input clk_vbuf, - output [27:0] vbuf_address, - input [127:0] vbuf_readdata, - output [127:0] vbuf_writedata, - output [7:0] vbuf_burstcount, - output [15:0] vbuf_byteenable, - input vbuf_waitrequest, - input vbuf_readdatavalid, - output reg vbuf_read, - output reg vbuf_write -); - -localparam [7:0] burstsz = 64; - -reg [1:0] nbuf = 0; -wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0}; -wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0}; - -assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress; -assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount; - -wire [95:0] hf_out; -wire [7:0] hf_usedw; -reg hf_reset = 0; - -vbuf_fifo out_fifo -( - .aclr(hf_reset), - - .wrclk(clk_vbuf), - .wrreq(vbuf_readdatavalid), - .data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}), - .wrusedw(hf_usedw), - - .rdclk(~clk_hdmi), - .rdreq(hf_rdreq), - .q(hf_out) -); - -reg [11:0] rd_stride; -wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0]; - -reg [27:0] vbuf_raddress; -reg [7:0] vbuf_rburstcount; -always @(posedge clk_vbuf) begin - reg [18:0] rdcnt; - reg [7:0] bcnt; - reg vde1, vde2; - reg [1:0] mcnt; - reg [1:0] my; - reg [18:0] fsz; - reg [11:0] strd; - - vde1 <= hdmi_vde; - vde2 <= vde1; - - if(vbuf_readdatavalid) begin - rdcnt <= rdcnt + 1'd1; - if(bcnt) bcnt <= bcnt - 1'd1; - vbuf_raddress <= vbuf_raddress + 1'd1; - end - - if(!bcnt && reading) reading <= 0; - - vbuf_read <= 0; - if(~vbuf_waitrequest) begin - if(!hf_reset && rdcnt=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt; -wire de_in = hdmi_hde & hdmi_vde; - -always @(posedge clk_hdmi) begin - reg [71:0] px_out; - reg [1:0] mx; - reg vde; - - vde <= hdmi_vde; - - if(vde & ~hdmi_vde) begin - off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0; - off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0; - vh_height <= v_height; - vh_width <= v_width; - mx <= mult_x; - end - - pcnt <= pcnt + 1'd1; - if(pcnt == mx) begin - pcnt <= 0; - hload <= hload + 1'd1; - end - - if(~de_in || x (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11; -wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11; -wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y; -wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y; -wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x; -wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0); -wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0); -wire [23:0] t_fsz = l1_stride * t_height; - -reg [11:0] l1_width; -reg [11:0] l1_stride; -always @(posedge clk_video) begin - reg [7:0] loaded = 0; - reg [11:0] strd = 0; - reg old_de = 0; - reg old_vs = 0; - - old_vs <= video_vs; - if(~old_vs & video_vs) begin - cur_addr<= write_buf; - video_x <= 0; - video_y <= 0; - loaded <= 0; - strd <= 0; - nbuf <= nbuf + 1'd1; - - stride <= l1_stride; - framesz <= t_fsz[18:0]; - v_height<= t_height; - v_width <= t_width; - mult_x <= tmf_x; - mult_y <= tmf_y; - end - - if(pix_wr) begin - case(video_x[1:0]) - 0: pix_acc <= video_d; // zeroes upper bits too - 1: pix_acc[47:24] <= video_d; - 2: pix_acc[71:48] <= video_d; - 3: loaded <= loaded + 1'd1; - endcase - if(video_x= burstsz) || (old_de & ~video_de)) begin - if(loaded + infifo_tail) begin - flush_size <= loaded + infifo_tail; - flush_addr <= cur_addr; - flush_req <= ~flush_req; - loaded <= 0; - strd <= strd + loaded; - end - - cur_addr <= cur_addr + loaded + infifo_tail; - if(~video_de) begin - if(video_y= 10'h3a0); // if u is inside (-16, 16) - wire u_inside = (u < 9'h10 || u >= 9'h1f0); + wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0); // if v is inside (-24, 24) wire v_inside = (v < 10'h18 || v >= 10'h3e8); assign result = !(y_inside && u_inside && v_inside); -endmodule -module InnerBlend -( - input [8:0] Op, - input [7:0] A, - input [7:0] B, - input [7:0] C, - output [7:0] O -); - - function [10:0] mul8x3; - input [7:0] op1; - input [2:0] op2; - begin - mul8x3 = 11'd0; - if(op2[0]) mul8x3 = mul8x3 + op1; - if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0}; - if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [10:0] Amul = mul8x3(A, Op[7:5]); - wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0}); - wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0}); - wire [10:0] At = Amul; - wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [11:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[11:4]; endmodule module Blend ( + input clk, + input clk_en, input [5:0] rule, - input disable_hq2x, input [23:0] E, input [23:0] A, input [23:0] B, @@ -320,66 +309,63 @@ module Blend output [23:0] Result ); - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4 + localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4 + localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4 - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = {11{1'bx}}; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; + reg [23:0] a,b,d,e,h,f; + reg [3:0] bl_rule; + reg [1:0] df_rule; + always @(posedge clk) if (clk_en) begin + {bl_rule,df_rule} <= rule; + a <= A; b <= B; d <= D; e <= E; f <= F; h <= H; end - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [23:0] Input1 = E; - wire [23:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; + wire is_diff; + DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff); + + reg [23:0] i10,i20,i30; + reg [6:0] op0; + always @(posedge clk) if (clk_en) begin + i10 <= e; + case({!is_diff, bl_rule}) + 1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0}; + 2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0}; + 3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0}; + 4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b}; + 5,21: {op0, i20, i30} <= {BLEND2, a, b}; + 6,22: {op0, i20, i30} <= {BLEND2, a, d}; + 25,29: {op0, i20, i30} <= {BLEND5, d, b}; + 26: {op0, i20, i30} <= {BLEND6, d, b}; + 28: {op0, i20, i30} <= {BLEND4, d, b}; + 30: {op0, i20, i30} <= {BLEND3, b, d}; + 31: {op0, i20, i30} <= {BLEND3, d, b}; + default: {op0, i20, i30} <= {BLEND1, e, 24'd0}; + endcase + end + + reg [23:0] i1,i2,i3; + reg [6:0] op; + always @(posedge clk) if (clk_en) begin + op <= op0; i1 <= i10; i2 <= i20; i3 <= i30; + end + + function [34:0] mul24x3; + input [23:0] op1; + input [2:0] op2; + begin + mul24x3 = 0; + if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]}; + if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0}; + if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00}; + end + endfunction + + wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]}); + + always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]}; - wire [23:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]); - InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]); - InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]); endmodule diff --git a/sys/i2c.v b/sys/i2c.v index 1b89b4f..35c8cbd 100644 --- a/sys/i2c.v +++ b/sys/i2c.v @@ -4,7 +4,12 @@ module i2c input CLK, input START, - input [23:0] I2C_DATA, + input READ, + input [6:0] I2C_ADDR, + input I2C_WLEN, // 0 - one byte, 1 - two bytes + input [7:0] I2C_WDATA1, + input [7:0] I2C_WDATA2, + output [7:0] I2C_RDATA, output reg END = 1, output reg ACK = 0, @@ -18,51 +23,80 @@ module i2c parameter CLK_Freq = 50_000_000; // 50 MHz parameter I2C_Freq = 400_000; // 400 KHz -reg I2C_CLOCK; -always@(negedge CLK) begin - integer mI2C_CLK_DIV = 0; - if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin - mI2C_CLK_DIV <= mI2C_CLK_DIV + 1; - end else begin - mI2C_CLK_DIV <= 0; - I2C_CLOCK <= ~I2C_CLOCK; +localparam I2C_FreqX2 = I2C_Freq*2; + +reg I2C_CLOCK; +reg [31:0] cnt; +wire [31:0] cnt_next = cnt + I2C_FreqX2; + +always @(posedge CLK) begin + cnt <= cnt_next; + if(cnt_next >= CLK_Freq) begin + cnt <= cnt_next - CLK_Freq; + I2C_CLOCK <= ~I2C_CLOCK; end end -assign I2C_SCL = SCLK | I2C_CLOCK; -assign I2C_SDA = SDO ? 1'bz : 1'b0; +assign I2C_SCL = (SCLK | I2C_CLOCK) ? 1'bZ : 1'b0; +assign I2C_SDA = SDO[3] ? 1'bz : 1'b0; -reg SCLK = 1, SDO = 1; +reg SCLK; +reg [3:0] SDO; +reg [0:7] rdata; + +reg [5:0] SD_COUNTER; +reg [0:31] SD; + +initial begin + SD_COUNTER = 'b111111; + SD = 'hFFFF; + SCLK = 1; + SDO = 4'b1111; +end + +assign I2C_RDATA = rdata; always @(posedge CLK) begin reg old_clk; reg old_st; - - reg [5:0] SD_COUNTER = 'b111111; - reg [0:31] SD; + reg rd,len; old_clk <= I2C_CLOCK; old_st <= START; + + // delay to make sure SDA changed while SCL is stabilized at low + if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]]; + SDO[3:1] <= SDO[2:0]; if(~old_st && START) begin SCLK <= 1; - SDO <= 1; + SDO <= 4'b1111; ACK <= 0; END <= 0; - SD <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011}; + rd <= READ; + len <= I2C_WLEN; + if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111}; + else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011}; SD_COUNTER <= 0; end else begin if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin SD_COUNTER <= SD_COUNTER + 6'd1; case(SD_COUNTER) - 01: SCLK <= 0; - 10,19,28: ACK <= ACK | I2C_SDA; - 29: SCLK <= 1; - 32: END <= 1; + 01: SCLK <= 0; + 10: ACK <= ACK | I2C_SDA; + 19: if(~rd) begin + ACK <= ACK | I2C_SDA; + if(~len) SD_COUNTER <= 29; + end + 20: if(rd) SCLK <= 1; + 23: if(rd) END <= 1; + 28: if(~rd) ACK <= ACK | I2C_SDA; + 29: if(~rd) SCLK <= 1; + 32: if(~rd) END <= 1; endcase - end - if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]]; + if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA; + end end end diff --git a/sys/i2s.v b/sys/i2s.v index d0480ce..7d4517b 100644 --- a/sys/i2s.v +++ b/sys/i2s.v @@ -1,14 +1,12 @@ module i2s #( - parameter CLK_RATE = 50000000, - parameter AUDIO_DW = 16, - parameter AUDIO_RATE = 96000 + parameter AUDIO_DW = 16 ) ( input reset, - input clk_sys, - input half_rate, + input clk, + input ce, output reg sclk, output reg lrclk, @@ -18,119 +16,39 @@ module i2s input [AUDIO_DW-1:0] right_chan ); -localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4); -localparam ERROR_BASE = 10000; -localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE); - -reg lpf_ce; -wire [AUDIO_DW-1:0] al, ar; - -lpf_i2s lpf_l -( - .CLK(clk_sys), - .CE(lpf_ce), - .IDATA(left_chan), - .ODATA(al) -); - -lpf_i2s lpf_r -( - .CLK(clk_sys), - .CE(lpf_ce), - - .IDATA(right_chan), - .ODATA(ar) -); - -always @(posedge clk_sys) begin - reg [31:0] count_q; - reg [31:0] error_q; +always @(posedge clk) begin reg [7:0] bit_cnt; - reg skip = 0; + reg msclk; reg [AUDIO_DW-1:0] left; reg [AUDIO_DW-1:0] right; - reg msclk; - reg ce; - - lpf_ce <= 0; - if (reset) begin - count_q <= 0; - error_q <= 0; - ce <= 0; - bit_cnt <= 1; - lrclk <= 1; - sclk <= 1; - msclk <= 1; + bit_cnt <= 1; + lrclk <= 1; + sclk <= 1; + msclk <= 1; end - else - begin - if(count_q == WHOLE_CYCLES-1) begin - if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin - error_q <= error_q + ERRORS_PER_BIT[31:0]; - count_q <= 0; - end else begin - error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE; - count_q <= count_q + 1; - end - end else if(count_q == WHOLE_CYCLES) begin - count_q <= 0; - end else begin - count_q <= count_q + 1; - end - + else begin sclk <= msclk; - if(!count_q) begin - ce <= ~ce; - if(~half_rate || ce) begin - msclk <= ~msclk; - if(msclk) begin - skip <= ~skip; - if(skip) lpf_ce <= 1; - if(bit_cnt >= AUDIO_DW) begin - bit_cnt <= 1; - lrclk <= ~lrclk; - if(lrclk) begin - left <= al; - right <= ar; - end + if(ce) begin + msclk <= ~msclk; + if(msclk) begin + if(bit_cnt >= AUDIO_DW) begin + bit_cnt <= 1; + lrclk <= ~lrclk; + if(lrclk) begin + left <= left_chan; + right <= right_chan; end - else begin - bit_cnt <= bit_cnt + 1'd1; - end - sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; end + else begin + bit_cnt <= bit_cnt + 1'd1; + end + sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; end end end end endmodule - -module lpf_i2s -( - input CLK, - input CE, - input [15:0] IDATA, - output reg [15:0] ODATA -); - -reg [511:0] acc; -reg [20:0] sum; - -always @(*) begin - integer i; - sum = 0; - for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]}; -end - -always @(posedge CLK) begin - if(CE) begin - acc <= {acc[495:0], IDATA}; - ODATA <= sum[20:5]; - end -end - -endmodule diff --git a/sys/iir_filter.v b/sys/iir_filter.v new file mode 100644 index 0000000..a5336e9 --- /dev/null +++ b/sys/iir_filter.v @@ -0,0 +1,213 @@ + +// 3-tap IIR filter for 2 channels. +// Copyright (C) 2020 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +// +// Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0) +// +module IIR_filter +#( + parameter use_params = 1, // set to 1 to use following parameters, 0 for input port variables. + parameter stereo = 1, // 0 for mono (input_l) + + parameter coeff_x = 0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9) + parameter coeff_x0 = 3, // Gain scale factor for X0. Integer. Range -7 ... +7 + parameter coeff_x1 = 3, // Gain scale factor for X1. Integer. Range -7 ... +7 + parameter coeff_x2 = 1, // Gain scale factor for X2. Integer. Range -7 ... +7 + parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9) + parameter coeff_y1 = 2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9) + parameter coeff_y2 = -0.96500747158831091000 // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9) +) +( + input clk, + input reset, + + input ce, // must be double of calculated rate for stereo! + input sample_ce, // desired output sample rate + + input [39:0] cx, + input [7:0] cx0, + input [7:0] cx1, + input [7:0] cx2, + input [23:0] cy0, + input [23:0] cy1, + input [23:0] cy2, + + input [15:0] input_l, input_r, // signed samples + output [15:0] output_l, output_r // signed samples +); + +localparam [39:0] pcoeff_x = coeff_x * 40'h8000000000; +localparam [31:0] pcoeff_y0 = coeff_y0 * 24'h200000; +localparam [31:0] pcoeff_y1 = coeff_y1 * 24'h200000; +localparam [31:0] pcoeff_y2 = coeff_y2 * 24'h200000; + +wire [39:0] vcoeff = use_params ? pcoeff_x : cx; +wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0; +wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1; +wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2; + +wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff); + +wire [39:0] x = inp_mul[59:20]; +wire [39:0] y = x + tap0; + +wire [39:0] tap0; +iir_filter_tap iir_tap_0 +( + .clk(clk), + .reset(reset), + .ce(ce), + .ch(ch), + .cx(use_params ? coeff_x0[7:0] : cx0), + .cy(vcoeff_y0), + .x(x), + .y(y), + .z(tap1), + .tap(tap0) +); + +wire [39:0] tap1; +iir_filter_tap iir_tap_1 +( + .clk(clk), + .reset(reset), + .ce(ce), + .ch(ch), + .cx(use_params ? coeff_x1[7:0] : cx1), + .cy(vcoeff_y1), + .x(x), + .y(y), + .z(tap2), + .tap(tap1) +); + +wire [39:0] tap2; +iir_filter_tap iir_tap_2 +( + .clk(clk), + .reset(reset), + .ce(ce), + .ch(ch), + .cx(use_params ? coeff_x2[7:0] : cx2), + .cy(vcoeff_y2), + .x(x), + .y(y), + .z(0), + .tap(tap2) +); + +wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20]; + +reg ch = 0; +reg [15:0] out_l, out_r, out_m; +reg [15:0] inp, inp_m; +always @(posedge clk) if (ce) begin + if(!stereo) begin + ch <= 0; + inp <= input_l; + out_l <= y_clamp; + out_r <= y_clamp; + end + else begin + ch <= ~ch; + if(ch) begin + out_m <= y_clamp; + inp <= inp_m; + end + else begin + out_l <= out_m; + out_r <= y_clamp; + inp <= input_l; + inp_m <= input_r; + end + end +end + +reg [31:0] out; +always @(posedge clk) if (sample_ce) out <= {out_l, out_r}; + +assign {output_l, output_r} = out; + +endmodule + +module iir_filter_tap +( + input clk, + input reset, + + input ce, + input ch, + + input [7:0] cx, + input [23:0] cy, + + input [39:0] x, + input [39:0] y, + input [39:0] z, + output [39:0] tap +); + +wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy); + +function [39:0] x_mul; + input [39:0] x; +begin + x_mul = 0; + if(cx[0]) x_mul = x_mul + {{4{x[39]}}, x[39:4]}; + if(cx[1]) x_mul = x_mul + {{3{x[39]}}, x[39:3]}; + if(cx[2]) x_mul = x_mul + {{2{x[39]}}, x[39:2]}; + if(cx[7]) x_mul = ~x_mul; //cheap NEG +end +endfunction + +(* ramstyle = "logic" *) reg [39:0] intreg[2]; +always @(posedge clk, posedge reset) begin + if(reset) {intreg[0],intreg[1]} <= 80'd0; + else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z; +end + +assign tap = intreg[ch]; + +endmodule + +// simplified IIR 1-tap. +module DC_blocker +( + input clk, + input ce, // 48/96 KHz + input mute, + + input sample_rate, + input [15:0] din, + output [15:0] dout +); + +wire [39:0] x = {din[15], din, 23'd0}; +wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]}); +wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]}); +wire [39:0] y0 = x0 - x1 + y1; + +reg [39:0] x1, y; +always @(posedge clk) if(ce) begin + x1 <= x0; + y <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0; +end + +assign dout = mute ? 16'd0 : y[38:23]; + +endmodule diff --git a/sys/ip/avalon_combiner.v b/sys/ip/avalon_combiner.v deleted file mode 100644 index 3a26c6a..0000000 --- a/sys/ip/avalon_combiner.v +++ /dev/null @@ -1,60 +0,0 @@ -// avalon_combiner.v - -`timescale 1 ps / 1 ps -module avalon_combiner -( - input wire clk, // clock.clk - input wire rst, // reset.reset - - output wire [6:0] mixer_address, // ctl_mixer.address - output wire [3:0] mixer_byteenable, // .byteenable - output wire mixer_write, // .write - output wire [31:0] mixer_writedata, // .writedata - input wire mixer_waitrequest, // .waitrequest - - output wire [6:0] scaler_address, // ctl_scaler.address - output wire [3:0] scaler_byteenable, // .byteenable - input wire scaler_waitrequest, // .waitrequest - output wire scaler_write, // .write - output wire [31:0] scaler_writedata, // .writedata - - output wire [7:0] video_address, // ctl_video.address - output wire [3:0] video_byteenable, // .byteenable - input wire video_waitrequest, // .waitrequest - output wire video_write, // .write - output wire [31:0] video_writedata, // .writedata - - output wire clock, // control.clock - output wire reset, // .reset - input wire [8:0] address, // .address - input wire write, // .write - input wire [31:0] writedata, // .writedata - output wire waitrequest // .waitrequest -); - -assign clock = clk; -assign reset = rst; - -assign mixer_address = address[6:0]; -assign scaler_address = address[6:0]; -assign video_address = address[7:0]; - -assign mixer_byteenable = 4'b1111; -assign scaler_byteenable = 4'b1111; -assign video_byteenable = 4'b1111; - -wire en_scaler = (address[8:7] == 0); -wire en_mixer = (address[8:7] == 1); -wire en_video = address[8]; - -assign mixer_write = en_mixer & write; -assign scaler_write = en_scaler & write; -assign video_write = en_video & write; - -assign mixer_writedata = writedata; -assign scaler_writedata = writedata; -assign video_writedata = writedata; - -assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest); - -endmodule diff --git a/sys/ip/avalon_combiner_hw.tcl b/sys/ip/avalon_combiner_hw.tcl deleted file mode 100644 index 5eede9c..0000000 --- a/sys/ip/avalon_combiner_hw.tcl +++ /dev/null @@ -1,204 +0,0 @@ -# TCL File Generated by Component Editor 17.0 -# Wed Dec 13 01:40:49 CST 2017 -# DO NOT MODIFY - - -# -# avalon_combiner "avalon_combiner" v17.0 -# sorgelig 2017.12.13.01:40:49 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module avalon_combiner -# -set_module_property DESCRIPTION "" -set_module_property NAME avalon_combiner -set_module_property VERSION 17.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR sorgelig -set_module_property DISPLAY_NAME avalon_combiner -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true -add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clk clk Input 1 - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset rst reset Input 1 - - -# -# connection point ctl_mixer -# -add_interface ctl_mixer avalon start -set_interface_property ctl_mixer addressUnits WORDS -set_interface_property ctl_mixer associatedClock clock -set_interface_property ctl_mixer associatedReset reset -set_interface_property ctl_mixer bitsPerSymbol 8 -set_interface_property ctl_mixer burstOnBurstBoundariesOnly false -set_interface_property ctl_mixer burstcountUnits WORDS -set_interface_property ctl_mixer doStreamReads false -set_interface_property ctl_mixer doStreamWrites false -set_interface_property ctl_mixer holdTime 0 -set_interface_property ctl_mixer linewrapBursts false -set_interface_property ctl_mixer maximumPendingReadTransactions 0 -set_interface_property ctl_mixer maximumPendingWriteTransactions 0 -set_interface_property ctl_mixer readLatency 0 -set_interface_property ctl_mixer readWaitTime 1 -set_interface_property ctl_mixer setupTime 0 -set_interface_property ctl_mixer timingUnits Cycles -set_interface_property ctl_mixer writeWaitTime 0 -set_interface_property ctl_mixer ENABLED true -set_interface_property ctl_mixer EXPORT_OF "" -set_interface_property ctl_mixer PORT_NAME_MAP "" -set_interface_property ctl_mixer CMSIS_SVD_VARIABLES "" -set_interface_property ctl_mixer SVD_ADDRESS_GROUP "" - -add_interface_port ctl_mixer mixer_address address Output 7 -add_interface_port ctl_mixer mixer_byteenable byteenable Output 4 -add_interface_port ctl_mixer mixer_write write Output 1 -add_interface_port ctl_mixer mixer_writedata writedata Output 32 -add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1 - - -# -# connection point ctl_scaler -# -add_interface ctl_scaler avalon start -set_interface_property ctl_scaler addressUnits WORDS -set_interface_property ctl_scaler associatedClock clock -set_interface_property ctl_scaler associatedReset reset -set_interface_property ctl_scaler bitsPerSymbol 8 -set_interface_property ctl_scaler burstOnBurstBoundariesOnly false -set_interface_property ctl_scaler burstcountUnits WORDS -set_interface_property ctl_scaler doStreamReads false -set_interface_property ctl_scaler doStreamWrites false -set_interface_property ctl_scaler holdTime 0 -set_interface_property ctl_scaler linewrapBursts false -set_interface_property ctl_scaler maximumPendingReadTransactions 0 -set_interface_property ctl_scaler maximumPendingWriteTransactions 0 -set_interface_property ctl_scaler readLatency 0 -set_interface_property ctl_scaler readWaitTime 1 -set_interface_property ctl_scaler setupTime 0 -set_interface_property ctl_scaler timingUnits Cycles -set_interface_property ctl_scaler writeWaitTime 0 -set_interface_property ctl_scaler ENABLED true -set_interface_property ctl_scaler EXPORT_OF "" -set_interface_property ctl_scaler PORT_NAME_MAP "" -set_interface_property ctl_scaler CMSIS_SVD_VARIABLES "" -set_interface_property ctl_scaler SVD_ADDRESS_GROUP "" - -add_interface_port ctl_scaler scaler_address address Output 7 -add_interface_port ctl_scaler scaler_byteenable byteenable Output 4 -add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1 -add_interface_port ctl_scaler scaler_write write Output 1 -add_interface_port ctl_scaler scaler_writedata writedata Output 32 - - -# -# connection point ctl_video -# -add_interface ctl_video avalon start -set_interface_property ctl_video addressUnits WORDS -set_interface_property ctl_video associatedClock clock -set_interface_property ctl_video associatedReset reset -set_interface_property ctl_video bitsPerSymbol 8 -set_interface_property ctl_video burstOnBurstBoundariesOnly false -set_interface_property ctl_video burstcountUnits WORDS -set_interface_property ctl_video doStreamReads false -set_interface_property ctl_video doStreamWrites false -set_interface_property ctl_video holdTime 0 -set_interface_property ctl_video linewrapBursts false -set_interface_property ctl_video maximumPendingReadTransactions 0 -set_interface_property ctl_video maximumPendingWriteTransactions 0 -set_interface_property ctl_video readLatency 0 -set_interface_property ctl_video readWaitTime 1 -set_interface_property ctl_video setupTime 0 -set_interface_property ctl_video timingUnits Cycles -set_interface_property ctl_video writeWaitTime 0 -set_interface_property ctl_video ENABLED true -set_interface_property ctl_video EXPORT_OF "" -set_interface_property ctl_video PORT_NAME_MAP "" -set_interface_property ctl_video CMSIS_SVD_VARIABLES "" -set_interface_property ctl_video SVD_ADDRESS_GROUP "" - -add_interface_port ctl_video video_address address Output 8 -add_interface_port ctl_video video_byteenable byteenable Output 4 -add_interface_port ctl_video video_waitrequest waitrequest Input 1 -add_interface_port ctl_video video_write write Output 1 -add_interface_port ctl_video video_writedata writedata Output 32 - - -# -# connection point control -# -add_interface control conduit end -set_interface_property control associatedClock clock -set_interface_property control associatedReset reset -set_interface_property control ENABLED true -set_interface_property control EXPORT_OF "" -set_interface_property control PORT_NAME_MAP "" -set_interface_property control CMSIS_SVD_VARIABLES "" -set_interface_property control SVD_ADDRESS_GROUP "" - -add_interface_port control address address Input 9 -add_interface_port control write write Input 1 -add_interface_port control writedata writedata Input 32 -add_interface_port control waitrequest waitrequest Output 1 -add_interface_port control clock clock Output 1 -add_interface_port control reset reset Output 1 - diff --git a/sys/ip/de10_hps_hw.tcl b/sys/ip/de10_hps_hw.tcl deleted file mode 100644 index a166ca0..0000000 --- a/sys/ip/de10_hps_hw.tcl +++ /dev/null @@ -1,3706 +0,0 @@ -# (C) 2001-2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions and other -# software and tools, and its AMPP partner logic functions, and any output -# files any of the foregoing (including device programming or simulation -# files), and any associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License Subscription -# Agreement, Intel MegaCore Function License Agreement, or other applicable -# license agreement, including, without limitation, that your use is for the -# sole purpose of programming logic devices manufactured by Intel and sold by -# Intel or its authorized distributors. Please refer to the applicable -# agreement for further details. - - -# This IP is modified standard Altera HPS IP. -# Direct DDR3 SDRAM access has been removed since it won't work together with HPS DDR3 SDRAM access. -# FPGA access the memory through MPFE (FPGA2SDRAM bridge). -# By removing direct DDR3 SDRAM access synthesis time has been reduced by 3 times! - - -package require -exact qsys 12.0 -package require -exact altera_terp 1.0 -package require quartus::advanced_wysiwyg - -set_module_property NAME altera_hps_lite -set_module_property VERSION 17.0 -set_module_property AUTHOR "Altera Corporation/Sorgelig" -set_module_property SUPPORTED_DEVICE_FAMILIES {CYCLONEV ARRIAV} - -set_module_property DISPLAY_NAME "DE10-nano Hard Processor System" -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE false -set_module_property HIDE_FROM_SOPC true -set_module_property HIDE_FROM_QUARTUS true - -add_documentation_link "HPS User Guide for Cyclone V" "http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf" -add_documentation_link "HPS User Guide for Arria V" "http://www.altera.com/literature/hb/arria-v/av_5v4.pdf" - -set alt_mem_if_tcl_libs_dir "$env(QUARTUS_ROOTDIR)/../ip/altera/alt_mem_if/alt_mem_if_tcl_packages" -if {[lsearch -exact $auto_path $alt_mem_if_tcl_libs_dir] == -1} { - lappend auto_path $alt_mem_if_tcl_libs_dir -} - -package require alt_mem_if::gui::system_info - -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/constants.tcl -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/procedures.tcl -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux.tcl -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux_db.tcl -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/locations.tcl -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/ui.tcl -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clocks.tcl -source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clock_manager.tcl - -proc add_storage_parameter {name { default_value {} } } { - add_parameter $name string $default_value "" - set_parameter_property $name derived true - set_parameter_property $name visible false -} - -proc add_reset_parameters {} { - set group_name "Resets" - add_display_item "FPGA Interfaces" $group_name "group" "" - - add_parameter S2FCLK_COLDRST_Enable boolean false "" - set_parameter_property S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output" - set_parameter_property S2FCLK_COLDRST_Enable group $group_name - - add_parameter S2FCLK_PENDINGRST_Enable boolean false "" - set_parameter_property S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals" - set_parameter_property S2FCLK_PENDINGRST_Enable group $group_name - - add_parameter F2SCLK_DBGRST_Enable boolean false "" - set_parameter_property F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request" - set_parameter_property F2SCLK_DBGRST_Enable group $group_name - - add_parameter F2SCLK_WARMRST_Enable boolean false "" - set_parameter_property F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request" - set_parameter_property F2SCLK_WARMRST_Enable group $group_name - - add_parameter F2SCLK_COLDRST_Enable boolean false "" - set_parameter_property F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request" - set_parameter_property F2SCLK_COLDRST_Enable group $group_name - -} - -proc list_h2f_interrupt_groups {} { - return { - "CAN" "CLOCKPERIPHERAL" "CTI" - "DMA" "EMAC" "FPGAMANAGER" - "GPIO" "I2CEMAC" "I2CPERIPHERAL" - "L4TIMER" "NAND" "OSCTIMER" - "QSPI" "SDMMC" "SPIMASTER" - "SPISLAVE" "UART" "USB" - "WATCHDOG" - } -} - -proc get_h2f_interrupt_descriptions {data_ref} { - upvar 1 $data_ref data - array set data { - "DMA" "Enable DMA interrupts" - "EMAC" "Enable EMAC interrupts (for EMAC0 and EMAC1)" - "USB" "Enable USB interrupts" - "CAN" "Enable CAN interrupts" - "SDMMC" "Enable SD/MMC interrupt" - "NAND" "Enable NAND interrupt" - "QSPI" "Enable Quad SPI interrupt" - "SPIMASTER" "Enable SPI master interrupts" - "SPISLAVE" "Enable SPI slave interrupts" - "I2CPERIPHERAL" "Enable I2C peripheral interrupts (for I2C0 and I2C1)" - "I2CEMAC" "Enable I2C-EMAC interrupts (for I2C2 and I2C3)" - "UART" "Enable UART interrupts" - "GPIO" "Enable GPIO interrupts" - "L4TIMER" "Enable L4 timer interrupts" - "OSCTIMER" "Enable OSC timer interrupts" - "WATCHDOG" "Enable watchdog interrupts" - "CLOCKPERIPHERAL" "Enable clock peripheral interrupts" - "FPGAMANAGER" "Enable FPGA manager interrupt" - "CTI" "Enable CTI interrupts" - } -} - -proc load_h2f_interrupt_table {functions_by_group_ref - width_by_function_ref - inverted_by_function_ref} { - upvar 1 $functions_by_group_ref functions_by_group - upvar 1 $width_by_function_ref width_by_function - upvar 1 $inverted_by_function_ref inverted_by_function - array set functions_by_group { - "DMA" {"dma" "dma_abort" } - "EMAC" {"emac0" "emac1" } - "USB" {"usb0" "usb1" } - "CAN" {"can0" "can1" } - "SDMMC" {"sdmmc" } - "NAND" {"nand" } - "QSPI" {"qspi" } - "SPIMASTER" {"spi0" "spi1" } - "SPISLAVE" {"spi2" "spi3" } - "I2CPERIPHERAL" {"i2c0" "i2c1" } - "I2CEMAC" {"i2c_emac0" "i2c_emac1" } - "UART" {"uart0" "uart1" } - "GPIO" {"gpio0" "gpio1" "gpio2"} - "L4TIMER" {"l4sp0" "l4sp1" } - "OSCTIMER" {"osc0" "osc1" } - "WATCHDOG" {"wdog0" "wdog1" } - "CLOCKPERIPHERAL" {"clkmgr" "mpuwakeup" } - "FPGAMANAGER" {"fpga_man" } - "CTI" {"cti" } - } - array set width_by_function { - "dma" 8 - "cti" 2 - } - array set inverted_by_function { - "cti" 1 - } -} - -proc add_interrupt_parameters {} { - set top_group_name "Interrupts" - add_display_item "FPGA Interfaces" $top_group_name "group" "" - - # add_display_item $group_name "f2h_interrupts_label" "text" "FPGA-to-HPS" - add_parameter F2SINTERRUPT_Enable boolean false - set_parameter_property F2SINTERRUPT_Enable enabled true - set_parameter_property F2SINTERRUPT_Enable display_name "Enable FPGA-to-HPS Interrupts" - set_parameter_property F2SINTERRUPT_Enable group $top_group_name - - set inner_group_name "HPS-to-FPGA" - add_display_item $top_group_name $inner_group_name "group" "" - get_h2f_interrupt_descriptions descriptions_by_group - set interrupt_groups [list_h2f_interrupt_groups] - foreach interrupt_group $interrupt_groups { - set parameter "S2FINTERRUPT_${interrupt_group}_Enable" - add_parameter $parameter boolean false - set_parameter_property $parameter enabled true - set_parameter_property $parameter display_name $descriptions_by_group($interrupt_group) - set_parameter_property $parameter group $inner_group_name - } -} - -proc add_dma_parameters {} { - set group_name "DMA Peripheral Request" - add_display_item "FPGA Interfaces" $group_name "group" "" - add_display_item $group_name "DMA Table" "group" "table" - - add_parameter DMA_PeriphId_DERIVED string_list {0 1 2 3 4 5 6 7} - set_parameter_property DMA_PeriphId_DERIVED display_name "Peripheral Request ID" - set_parameter_property DMA_PeriphId_DERIVED derived true - set_parameter_property DMA_PeriphId_DERIVED display_hint "FIXED_SIZE" - set_parameter_property DMA_PeriphId_DERIVED group "DMA Table" - - add_parameter DMA_Enable string_list {"No" "No" "No" "No" "No" "No" "No" "No"} - set_parameter_property DMA_Enable allowed_ranges {"Yes" "No"} - set_parameter_property DMA_Enable display_name "Enabled" - set_parameter_property DMA_Enable display_hint "FIXED_SIZE" - set_parameter_property DMA_Enable group "DMA Table" -} - -proc range_from_zero {end} { - set result [list] - for {set i 0} {$i <= $end} {incr i} { - lappend result $i - } - return $result -} - -proc create_generic_parameters {} { - - ::alt_mem_if::util::hwtcl_utils::_add_parameter SYS_INFO_DEVICE_FAMILY STRING "" - set_parameter_property SYS_INFO_DEVICE_FAMILY SYSTEM_INFO DEVICE_FAMILY - set_parameter_property SYS_INFO_DEVICE_FAMILY VISIBLE FALSE - - ::alt_mem_if::util::hwtcl_utils::_add_parameter DEVICE_FAMILY STRING "" - set_parameter_property DEVICE_FAMILY DERIVED true - set_parameter_property DEVICE_FAMILY VISIBLE FALSE - - return 1 -} - -create_generic_parameters - -add_display_item "" "FPGA Interfaces" "group" "tab" -add_display_item "" "Peripheral Pins" "group" "tab" -add_display_item "" "HPS Clocks" "group" "tab" -add_clock_tab "HPS Clocks" - -add_display_item "FPGA Interfaces" "General" "group" "" - -add_parameter MPU_EVENTS_Enable boolean true -set_parameter_property MPU_EVENTS_Enable display_name "Enable MPU standby and event signals" -set_parameter_property MPU_EVENTS_Enable description "Enables elaboration of the mpu_events interface." -set_parameter_property MPU_EVENTS_Enable group "General" - -add_parameter GP_Enable boolean false -set_parameter_property GP_Enable display_name "Enable general purpose signals" -set_parameter_property GP_Enable description "Enables elaboration of interface h2f_gp." -set_parameter_property GP_Enable group "General" - -add_parameter DEBUGAPB_Enable boolean false -set_parameter_property DEBUGAPB_Enable display_name "Enable Debug APB interface" -set_parameter_property DEBUGAPB_Enable description "Enables elaboration of Debug APB interfaces." -set_parameter_property DEBUGAPB_Enable group "General" - -add_parameter STM_Enable boolean false -set_parameter_property STM_Enable display_name "Enable System Trace Macrocell hardware events" -set_parameter_property STM_Enable description "Enables elaboration of interface stm_hwevents." -set_parameter_property STM_Enable group "General" - -add_parameter CTI_Enable boolean false -set_parameter_property CTI_Enable display_name "Enable FPGA Cross Trigger Interface" -set_parameter_property CTI_Enable description "Enables elaboration of interface cti_trigger, cti_clk_in." -set_parameter_property CTI_Enable group "General" - -add_parameter TPIUFPGA_Enable boolean false -set_parameter_property TPIUFPGA_Enable display_name "Enable FPGA Trace Port Interface Unit" -set_parameter_property TPIUFPGA_Enable description "Enables elaboration of TPIU FPGA interfaces." -set_parameter_property TPIUFPGA_Enable group "General" - -add_parameter TPIUFPGA_alt boolean false -set_parameter_property TPIUFPGA_alt display_name "Enable FPGA Trace Port Alternate FPGA Interface" -set_parameter_property TPIUFPGA_alt description "When the trace port is enabled, it creates an interface compatible with the Arria 10 Trace Interface. (This just moves the clock_in port into the same conduit)" -set_parameter_property TPIUFPGA_alt group "General" -set_parameter_property TPIUFPGA_alt enabled false - - -add_parameter BOOTFROMFPGA_Enable boolean false -set_parameter_property BOOTFROMFPGA_Enable enabled true -set_parameter_property BOOTFROMFPGA_Enable display_name "Enable boot from fpga signals" -set_parameter_property BOOTFROMFPGA_Enable description "Enables elaboration of interface boot_from_fpga." -set_parameter_property BOOTFROMFPGA_Enable group "General" - -add_parameter TEST_Enable boolean false -set_parameter_property TEST_Enable enabled true -set_parameter_property TEST_Enable display_name "Enable Test Interface" -set_parameter_property TEST_Enable group "General" - -add_parameter HLGPI_Enable boolean false -set_parameter_property HLGPI_Enable enabled true -set_parameter_property HLGPI_Enable display_name "Enable HLGPI Interface" -set_parameter_property HLGPI_Enable group "General" - -add_display_item "FPGA Interfaces" "Boot and Clock Selection" "group" "" -add_parameter BSEL_EN boolean false -set_parameter_property BSEL_EN enabled true -set_parameter_property BSEL_EN display_name "Enable boot selection from FPGA" -set_parameter_property BSEL_EN group "Boot and Clock Selection" -set_parameter_property BSEL_EN visible false -set_parameter_property BSEL_EN enabled false - -add_parameter BSEL integer 1 -set_parameter_property BSEL allowed_ranges {"1:FPGA" "2:NAND Flash (1.8v)" "3:NAND Flash (3.0v)" "4:SD/MMC External Transceiver (1.8v)" "5:SD/MMC Internal Transceiver (3.0v)" "6:Quad SPI Flash (1.8v)" "7:Quad SPI Flash (3.0v)"} -set_parameter_property BSEL display_name "Boot selection from FPGA" -set_parameter_property BSEL group "Boot and Clock Selection" -set_parameter_property BSEL visible false -set_parameter_property BSEL enabled false - -add_parameter CSEL_EN boolean false -set_parameter_property CSEL_EN enabled true -set_parameter_property CSEL_EN display_name "Enable clock selection from FPGA" -set_parameter_property CSEL_EN group "Boot and Clock Selection" -set_parameter_property CSEL_EN visible false -set_parameter_property CSEL_EN enabled false - -add_parameter CSEL integer 0 -set_parameter_property CSEL allowed_ranges {"0:CSEL_0" "1:CSEL_1" "2:CSEL_2" "3:CSEL_3"} -set_parameter_property CSEL display_name "Clock selection from FPGA" -set_parameter_property CSEL group "Boot and Clock Selection" -set_parameter_property CSEL visible false -set_parameter_property CSEL enabled false - -add_display_item "FPGA Interfaces" "AXI Bridges" "group" "" -add_parameter F2S_Width integer 2 -set_parameter_property F2S_Width allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"} -set_parameter_property F2S_Width display_name "FPGA-to-HPS interface width" -set_parameter_property F2S_Width hdl_parameter true -set_parameter_property F2S_Width group "AXI Bridges" - -add_parameter S2F_Width integer 2 -set_parameter_property S2F_Width allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"} -set_parameter_property S2F_Width display_name "HPS-to-FPGA interface width" -set_parameter_property S2F_Width hdl_parameter true -set_parameter_property S2F_Width group "AXI Bridges" - -add_parameter LWH2F_Enable string true -set_parameter_property LWH2F_Enable display_name "Lightweight HPS-to-FPGA interface width" -set_parameter_property LWH2F_Enable description "The lightweight HPS-to-FPGA bridge provides a secondary, fixed-width, smaller address space, lower-performance master interface to the FPGA fabric. Use the lightweight HPS-to-FPGA bridge for high-latency, low-bandwidth traffic, such as memory-mapped register accesses of FPGA peripherals. This approach diverts traffic from the high-performance HPS-to-FPGA bridge, which can improve overall performance." -set_parameter_property LWH2F_Enable allowed_ranges {"true:32-bit" "false:Unused"} -set_parameter_property LWH2F_Enable group "AXI Bridges" - - -set group_name "FPGA-to-HPS SDRAM Interface" -add_display_item "FPGA Interfaces" $group_name "group" "" -add_display_item $group_name "f2sdram_label" "text" "Click the '+' and '-' buttons to add and remove FPGA-to-HPS SDRAM ports." -set table_name "F2SDRAM Settings" -add_display_item $group_name $table_name "group" "table" - -add_parameter F2SDRAM_Name_DERIVED string_list {"f2h_sdram0"} -set_parameter_property F2SDRAM_Name_DERIVED derived true -set_parameter_property F2SDRAM_Name_DERIVED display_name "Name" -set_parameter_property F2SDRAM_Name_DERIVED group $table_name - -add_parameter F2SDRAM_Type string_list [list [F2HSDRAM_AXI3]] -set_parameter_property F2SDRAM_Type allowed_ranges [list [F2HSDRAM_AXI3] [F2HSDRAM_AVM] [F2HSDRAM_AVM_WRITEONLY] [F2HSDRAM_AVM_READONLY]] -set_parameter_property F2SDRAM_Type display_name "Type" -set_parameter_property F2SDRAM_Type group $table_name - -add_parameter F2SDRAM_Width integer_list {"64"} -set_parameter_property F2SDRAM_Width allowed_ranges "32,64,128,256" -set_parameter_property F2SDRAM_Width display_name "Width" -set_parameter_property F2SDRAM_Width group $table_name -set_parameter_update_callback F2SDRAM_Width on_altered_f2sdram_width -# TODO: f2sdram derived parameters for resource counts in the table -# TODO: f2sdram derived parameters for remaining resources, not a part of the table - -add_storage_parameter F2SDRAM_Width_Last_Size 1 -add_storage_parameter F2SDRAM_CMD_PORT_USED 0 -add_storage_parameter F2SDRAM_WR_PORT_USED 0 -add_storage_parameter F2SDRAM_RD_PORT_USED 0 -add_storage_parameter F2SDRAM_RST_PORT_USED 0 -set_parameter_property F2SDRAM_Width_Last_Size group $group_name -set_parameter_property F2SDRAM_CMD_PORT_USED group $group_name -set_parameter_property F2SDRAM_WR_PORT_USED group $group_name -set_parameter_property F2SDRAM_RD_PORT_USED group $group_name -set_parameter_property F2SDRAM_RST_PORT_USED group $group_name - -#Parameter to export Bonding_out signal from fpga2sdram Atom -add_parameter BONDING_OUT_ENABLED boolean false -set_parameter_property BONDING_OUT_ENABLED display_name "Enable BONDING-OUT signals" -set_parameter_property BONDING_OUT_ENABLED group $group_name -set_parameter_property BONDING_OUT_ENABLED enabled false -set_parameter_property BONDING_OUT_ENABLED visible false - - -proc on_altered_f2sdram_width { param } { - set old_size [get_parameter_value F2SDRAM_Width_Last_Size] - set current_value [get_parameter_value F2SDRAM_Width] - set current_size [llength $current_value] - - if {$current_size == $old_size + 1} { ;# look for case of newly added row - set last_element_index [expr {$current_size - 1}] - set new_value [lreplace $current_value $last_element_index $last_element_index "64"] - set_parameter_value F2SDRAM_Width $new_value - } -} - -add_reset_parameters - -add_dma_parameters - -add_interrupt_parameters - - set group_name "EMAC ptp interface" - add_display_item "FPGA Interfaces" $group_name "group" "" - - add_parameter EMAC0_PTP boolean false - set_parameter_property EMAC0_PTP display_name "Enable EMAC0 Precision Time Protocol (PTP) FPGA Interface" - set_parameter_property EMAC0_PTP hdl_parameter false - set_parameter_property EMAC0_PTP enabled false - set_parameter_property EMAC0_PTP group $group_name - set_parameter_property EMAC0_PTP description "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available." - - add_parameter EMAC1_PTP boolean false - set_parameter_property EMAC1_PTP display_name "Enable EMAC1 Precision Time Protocol (PTP) FPGA Interface" - set_parameter_property EMAC1_PTP hdl_parameter false - set_parameter_property EMAC1_PTP enabled false - set_parameter_property EMAC1_PTP group $group_name - set_parameter_property EMAC1_PTP description "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available." - - -proc make_mode_display_name {peripheral} { - set default_suffix "mode" - array set custom_suffix_by_peripheral { - USB0 "PHY interface mode" - USB1 "PHY interface mode" - } - if {[info exists custom_suffix_by_peripheral($peripheral)]} { - set suffix $custom_suffix_by_peripheral($peripheral) - } else { - set suffix $default_suffix - } - - set display_name "${peripheral} ${suffix}" - return $display_name -} - -proc add_peripheral_pin_muxing_parameters {} { - set TOP_LEVEL_GROUP_NAME "Peripheral Pins" - - - foreach group_name [list_group_names] { - add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" - - foreach peripheral_name [peripherals_in_group $group_name] { - set pin_muxing_param_name "${peripheral_name}_PinMuxing" - set mode_param_name "${peripheral_name}_Mode" - add_parameter $pin_muxing_param_name string [UNUSED_MUX_VALUE] - set_parameter_property $pin_muxing_param_name enabled false - set_parameter_property $pin_muxing_param_name display_name "${peripheral_name} pin" - set_parameter_property $pin_muxing_param_name allowed_ranges [UNUSED_MUX_VALUE] - set_parameter_property $pin_muxing_param_name group $group_name - set_parameter_update_callback $pin_muxing_param_name on_altered_peripheral_pin_muxing $peripheral_name - - set mode_display_name [make_mode_display_name $peripheral_name] - add_parameter $mode_param_name string [NA_MODE_VALUE] - set_parameter_property $mode_param_name enabled false - set_parameter_property $mode_param_name display_name $mode_display_name - set_parameter_property $mode_param_name allowed_ranges [NA_MODE_VALUE] - set_parameter_property $mode_param_name group $group_name - - if {[string match "*EMAC*" $peripheral_name]} { - set_parameter_update_callback $mode_param_name on_emac_mode_switch_internal $peripheral_name - } - } - } -} -add_peripheral_pin_muxing_parameters - -proc add_gpio_parameters {} { - set TOP_LEVEL_GROUP_NAME "Peripheral Pins" - set group_name "Peripherals Mux Table" - set table_name "Conflict Table" - - add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" - #add_display_item $group_name $table_name "group" "table" - - add_parameter Customer_Pin_Name_DERIVED string_list {} - set_parameter_property Customer_Pin_Name_DERIVED display_name "Pin Name" - set_parameter_property Customer_Pin_Name_DERIVED derived true - set_parameter_property Customer_Pin_Name_DERIVED display_hint "FIXED_SIZE" - set_parameter_property Customer_Pin_Name_DERIVED visible false - # set_parameter_property Customer_Pin_Name_DERIVED group $table_name - - add_parameter GPIO_Conflict_DERIVED string_list {} - set_parameter_property GPIO_Conflict_DERIVED display_name "Used by" - set_parameter_property GPIO_Conflict_DERIVED derived true - set_parameter_property GPIO_Conflict_DERIVED display_hint "FIXED_SIZE" - set_parameter_property GPIO_Conflict_DERIVED visible false - #set_parameter_property GPIO_Conflict_DERIVED group $table_name - - add_parameter GPIO_Name_DERIVED string_list {} - set_parameter_property GPIO_Name_DERIVED display_name "GPIO" - set_parameter_property GPIO_Name_DERIVED derived true - set_parameter_property GPIO_Name_DERIVED display_hint "FIXED_SIZE" - set_parameter_property GPIO_Name_DERIVED visible false - #set_parameter_property GPIO_Name_DERIVED group $table_name - - # TODO: change? - set max_possible_gpio_options 100 - set enable_list [list] - for {set i 0} {$i < $max_possible_gpio_options} {incr i} { - lappend enable_list "No" - } - - add_parameter GPIO_Enable string_list $enable_list - set_parameter_property GPIO_Enable allowed_ranges {"Yes" "No"} - set_parameter_property GPIO_Enable display_name "GPIO Enabled" - set_parameter_property GPIO_Enable visible false - # set_parameter_property GPIO_Enable group $table_name - - add_parameter LOANIO_Name_DERIVED string_list {} - set_parameter_property LOANIO_Name_DERIVED display_name "Loan I/O" - set_parameter_property LOANIO_Name_DERIVED derived true - set_parameter_property LOANIO_Name_DERIVED display_hint "FIXED_SIZE" - set_parameter_property LOANIO_Name_DERIVED visible false - - add_parameter GPIO_Pin_Used_DERIVED boolean false - set_parameter_property GPIO_Pin_Used_DERIVED display_name "GPIO Pin Used" - set_parameter_property GPIO_Pin_Used_DERIVED derived true - set_parameter_property GPIO_Pin_Used_DERIVED display_hint "GPIO Pin Used" - set_parameter_property GPIO_Pin_Used_DERIVED visible false - - add_parameter LOANIO_Enable string_list $enable_list - set_parameter_property LOANIO_Enable allowed_ranges {"Yes" "No"} - set_parameter_property LOANIO_Enable display_name "Loan I/O Enabled" - set_parameter_property LOANIO_Enable visible false - #set_parameter_property LOANIO_Enable group $table_name - - - -} -add_gpio_parameters - -proc add_reset_parameters {} { - set group_name "Resets" - add_display_item "FPGA Interfaces" $group_name "group" "" - - add_parameter S2FCLK_COLDRST_Enable boolean false "" - set_parameter_property S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output" - set_parameter_property S2FCLK_COLDRST_Enable group $group_name - - add_parameter S2FCLK_PENDINGRST_Enable boolean false "" - set_parameter_property S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals" - set_parameter_property S2FCLK_PENDINGRST_Enable group $group_name - - add_parameter F2SCLK_DBGRST_Enable boolean false "" - set_parameter_property F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request" - set_parameter_property F2SCLK_DBGRST_Enable group $group_name - - add_parameter F2SCLK_WARMRST_Enable boolean false "" - set_parameter_property F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request" - set_parameter_property F2SCLK_WARMRST_Enable group $group_name - - add_parameter F2SCLK_COLDRST_Enable boolean false "" - set_parameter_property F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request" - set_parameter_property F2SCLK_COLDRST_Enable group $group_name - -} - -proc add_java_gui_parameters {} { - set TOP_LEVEL_GROUP_NAME "Peripheral Pins" - set group_name "Peripherals Mux Table" - - add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" - # add_display_item $group_name the_widget "group" "" - - add_parameter JAVA_CONFLICT_PIN string_list {} - set_parameter_property JAVA_CONFLICT_PIN derived true - set_parameter_property JAVA_CONFLICT_PIN visible false - - - add_parameter JAVA_GUI_PIN_LIST string_list {} - set_parameter_property JAVA_GUI_PIN_LIST derived true - set_parameter_property JAVA_GUI_PIN_LIST visible false - - set peripherals [list_peripheral_names] - set widget_parameter [list \ - Customer_Pin_Name_DERIVED Customer_Pin_Name_DERIVED \ - GPIO_Name_DERIVED GPIO_Name_DERIVED \ - LOANIO_Name_DERIVED LOANIO_Name_DERIVED \ - LOANIO_Enable LOANIO_Enable \ - GPIO_Enable GPIO_Enable \ - JAVA_CONFLICT_PIN GUI_Conflict_Pins_List \ - JAVA_GUI_PIN_LIST GUI_GPIO_Pins_List] - - foreach peripheral_name $peripherals { - add_parameter "JAVA_${peripheral_name}_DATA" string "" - set_parameter_property "JAVA_${peripheral_name}_DATA" derived true - set_parameter_property "JAVA_${peripheral_name}_DATA" visible false - - lappend widget_parameter "JAVA_${peripheral_name}_DATA" - lappend widget_parameter "${peripheral_name}_pin_muxing" - lappend widget_parameter "${peripheral_name}_PinMuxing" - lappend widget_parameter "${peripheral_name}_PinMuxing" - lappend widget_parameter "${peripheral_name}_Mode" - lappend widget_parameter "${peripheral_name}_Mode" - } - - add_display_item $group_name the_widget "group" - set_display_item_property the_widget widget [list ../widget/pin_mux_widget.jar Altera_hps_widget] - set_display_item_property the_widget widget_parameter_map $widget_parameter -} - -add_java_gui_parameters - -############################################## -# Clocks! -# -# All clock enable parameters go here. -# Clock frequency parameters also go here. All -# the parameters need to be declared regardless -# of whether the clock will be exercised. -# -# Validation logic will enable/show frequency -# parameters based on whether the actual clock -# is being elaborated. -# -# There are four categories of clocks in this -# component: inputs on SoC I/O -# outputs on SoC I/O -# inputs on FPGA pins -# outputs on FPGA pins -# -# Inputs on SoC I/O have user-input parameters -# so the data can be consumed by downstream -# embedded software tools. -# Outputs on SoC I/O need not have frequency -# information recorded. -# Inputs on FPGA pins have system info parameters -# so the data can be consumed by downstream -# embedded software tools. -# Outputs on FPGA pins have user input parameters -# to be consumed by Quartus via SDC. -# -############################################## -proc add_clock_parameters {} { - set TOP_LEVEL_GROUP_NAME "Input Clocks" - - set group_name "User Clocks" - add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" - - # fake group - set group_name "FPGA Interface Clocks" - add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" - - foreach interface { - f2h_axi_clock h2f_axi_clock h2f_lw_axi_clock - f2h_sdram0_clock f2h_sdram1_clock f2h_sdram2_clock - f2h_sdram3_clock f2h_sdram4_clock f2h_sdram5_clock - h2f_cti_clock h2f_tpiu_clock_in h2f_debug_apb_clock - } { - set parameter "[string toupper ${interface}]_FREQ" - add_parameter $parameter integer 100 "" - set_parameter_property $parameter display_name "${interface} clock frequency" - set_parameter_property $parameter system_info_type "CLOCK_RATE" - set_parameter_property $parameter system_info_arg $interface - set_parameter_property $parameter visible false - set_parameter_property $parameter group $group_name - } - - set peripherals [list_peripheral_names] - - # TODO: Remove the following for 12.0 - set group_name "Peripheral FPGA Clocks" - add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" - - # Add parameter explicitly for cross-emac ptp since it doesn't belong to a single peripheral - set parameter [form_peripheral_fpga_input_clock_frequency_parameter emac_ptp_ref_clock] - add_parameter $parameter integer 100 "" - set_parameter_property $parameter display_name "EMAC emac_ptp_ref_clock clock frequency" - set_parameter_property $parameter group $group_name - set_parameter_property $parameter system_info_type "CLOCK_RATE" - set_parameter_property $parameter system_info_arg emac_ptp_ref_clock - set_parameter_property $parameter visible false - - foreach peripheral $peripherals { - set clocks [get_peripheral_fpga_input_clocks $peripheral] - foreach clock $clocks { - set parameter [form_peripheral_fpga_input_clock_frequency_parameter $clock] - add_parameter $parameter integer 100 "" - set_parameter_property $parameter display_name "${peripheral} ${clock} clock frequency" - set_parameter_property $parameter group $group_name - set_parameter_property $parameter system_info_type "CLOCK_RATE" - set_parameter_property $parameter system_info_arg $clock - set_parameter_property $parameter visible false - } - - set clocks [get_peripheral_fpga_output_clocks $peripheral] - foreach clock $clocks { - set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock] - if { [string match "*emac?_md*" $clock]} { - add_parameter $parameter float 2.5 "" - } elseif { [string match "*emac?_gtx_clk*" $clock] } { - add_parameter $parameter integer 125 "" - } else { - add_parameter $parameter integer 100 "" - if { [string compare $peripheral "SDIO" ] == 0 } { - set_parameter_property $parameter visible false - } - } - set_parameter_property $parameter display_name "${peripheral} ${clock} clock frequency" - set_parameter_property $parameter group $group_name - set_parameter_property $parameter units Megahertz - set_parameter_property $parameter allowedRanges {1:1000} - } - - } -} -add_clock_parameters - -add_parameter hps_device_family string "" "" -set_parameter_property hps_device_family derived true -set_parameter_property hps_device_family visible false - -add_parameter device_name string "" "" -set_parameter_property device_name system_info {DEVICE} -set_parameter_property device_name visible false - -add_parameter quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces boolean "" "" -set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_arg hps_ip_enable_all_peripheral_fpga_interfaces -set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces visible false - -add_parameter quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface boolean "" "" -set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_arg hps_ip_enable_emac0_peripheral_fpga_interface -set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface visible false - -add_parameter quartus_ini_hps_ip_enable_test_interface boolean "" "" -set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_arg hps_ip_enable_test_interface -set_parameter_property quartus_ini_hps_ip_enable_test_interface visible false - -add_parameter quartus_ini_hps_ip_fast_f2sdram_sim_model boolean "" "" -set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_arg hps_ip_fast_f2sdram_sim_model -set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model visible false - -add_parameter quartus_ini_hps_ip_suppress_sdram_synth boolean "" "" -set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_arg hps_ip_suppress_sdram_synth -set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth visible false - -add_parameter quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces boolean "" "" -set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_arg hps_ip_enable_low_speed_serial_fpga_interfaces -set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces visible false - -add_parameter quartus_ini_hps_ip_enable_bsel_csel boolean "" "" -set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_arg hps_ip_enable_bsel_csel -set_parameter_property quartus_ini_hps_ip_enable_bsel_csel visible false - -add_parameter quartus_ini_hps_ip_f2sdram_bonding_out boolean "" "" -set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_type quartus_ini -set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_arg hps_ip_enable_f2sdram_bonding_out -set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out visible false - - -add_parameter quartus_ini_hps_emif_pll boolean "" "" -set_parameter_property quartus_ini_hps_emif_pll system_info_type quartus_ini -set_parameter_property quartus_ini_hps_emif_pll system_info_arg hps_emif_pll -set_parameter_property quartus_ini_hps_emif_pll visible false - - -proc load_test_iface_definition {} { - set csv_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/test_iface.csv - - set data [list] - set count 0 - csv_foreach_row $csv_file cols { - incr count - if {$count == 1} { - continue - } - - lassign_trimmed $cols port width dir - lappend data $port $width $dir - } - return $data -} -add_storage_parameter test_iface_definition [load_test_iface_definition] - -# order of interfaces per peripheral should be kept -# order of ports per interface should be kept -proc load_periph_ifaces_db {} { - set interfaces_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_interfaces.csv - set peripherals_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_atoms.csv - set ports_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_interface_ports.csv - set pins_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_port_pins.csv - set bfm_types_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_bfm_types.csv - - # peripherals and interfaces - set peripherals([ORDERED_NAMES]) [list] - funset interface_ports - set count 0 - set PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START 4 - csv_foreach_row $interfaces_file cols { - incr count - # skip header - if {$count == 1} { - set ordered_names [list] - set length [llength $cols] - for {set col $PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START} {$col < $length} {incr col} { - set col_value [lindex $cols $col] - if {$col_value != ""} { - set property_to_col($col_value) $col - lappend ordered_names $col_value - } - } - set property_to_col([ORDERED_NAMES]) $ordered_names - continue - } - - set peripheral_name [string trim [lindex $cols 0]] - set interface_name [string trim [lindex $cols 1]] - set type [string trim [lindex $cols 2]] - set dir [string trim [lindex $cols 3]] - - funset peripheral - if {[info exists peripherals($peripheral_name)]} { - array set peripheral $peripherals($peripheral_name) - } else { - funset interfaces - set interfaces([ORDERED_NAMES]) [list] - set peripheral(interfaces) [array get interfaces] - set ordered_names $peripherals([ORDERED_NAMES]) - lappend ordered_names $peripheral_name - set peripherals([ORDERED_NAMES]) $ordered_names - } - funset interfaces - array set interfaces $peripheral(interfaces) - set ordered_names $interfaces([ORDERED_NAMES]) - lappend ordered_names $interface_name - set interfaces([ORDERED_NAMES]) $ordered_names - funset interface - set interface(type) $type - set interface(direction) $dir - funset properties - foreach property $property_to_col([ORDERED_NAMES]) { - set col $property_to_col($property) - set property_value [lindex $cols $col] - - if {$property_value != ""} { - # Add Meta Property - if { [string compare [string index ${property} 0] "@" ] == 0 } { - set interface(${property}) ${property_value} - } else { - set properties($property) $property_value - } - } - } - - set interface(properties) [array get properties] - - set interfaces($interface_name) [array get interface] - set peripheral(interfaces) [array get interfaces] - set peripherals($peripheral_name) [array get peripheral] - - funset ports - set ports([ORDERED_NAMES]) [list] - set interface_ports($interface_name) [array get ports] - } - set count 0 - csv_foreach_row $peripherals_file cols { ;# peripheral atom and location table - incr count - - # skip header - if {$count == 1} { - continue - } - - set peripheral_name [string trim [lindex $cols 0]] - set atom_name [string trim [lindex $cols 1]] - - funset peripheral - if {[info exists peripherals($peripheral_name)]} { - array set peripheral $peripherals($peripheral_name) - } else { - # Assume that if a peripheral hasn't be recognized until now, we won't be using it - continue - } - set peripheral(atom_name) $atom_name - set peripherals($peripheral_name) [array get peripheral] - } - add_parameter DB_periph_ifaces string [array get peripherals] "" - set_parameter_property DB_periph_ifaces derived true - set_parameter_property DB_periph_ifaces visible false - - set p [array get peripherals] - send_message debug "DB_periph_ifaces: ${p}" - - # ports - array set ports_to_pins {} - # # prepopulate interface_ports with names of interfaces that are known - # foreach {peripheral_name peripheral_string} [array get peripherals] { - # array set peripheral_array $peripheral_string - # foreach interface_name [array names peripheral_array] { - # set interface_ports($interface_name) {} - # } - # } - set count 0 - csv_foreach_row $ports_file cols { - incr count - - # skip header - if {$count == 1} continue - - set interface_name [string trim [lindex $cols 0]] - set port_name [string trim [lindex $cols 1]] - set role [string trim [lindex $cols 2]] - set dir [string trim [lindex $cols 3]] - set atom_signal_name [string trim [lindex $cols 4]] - - funset interface - array set interface $interface_ports($interface_name) - set ordered_names $interface([ORDERED_NAMES]) - lappend ordered_names $port_name - set interface([ORDERED_NAMES]) $ordered_names - - funset port - set port(role) $role - set port(direction) $dir - set port(atom_signal_name) $atom_signal_name - set interface($port_name) [array get port] - set interface_ports($interface_name) [array get interface] - - set ports_to_pins($port_name) {} - } - add_parameter DB_iface_ports string [array get interface_ports] "" - set_parameter_property DB_iface_ports derived true - set_parameter_property DB_iface_ports visible false - - set p [array get interface_ports] - send_message debug "DB_iface_ports: ${p}" - - # peripheral signals to ports - set count 0 - csv_foreach_row $pins_file cols { - incr count - - # skip header - if {$count == 1} continue - - set peripheral_name [string trim [lindex $cols 0]] - set pin_name [string trim [lindex $cols 1]] - set port_name [string trim [lindex $cols 2]] - - set is_multibit_signal [regexp {^([a-zA-Z0-9_]+)\[([0-9]+)\]} $port_name match real_name bit] - if {$is_multibit_signal == 0} { - set bit 0 - } else { - set port_name $real_name - } - - if {[info exists ports_to_pins($port_name)] == 0} { - send_message error "Peripheral ${peripheral_name} signal ${pin_name} is defined but corresponding FPGA signal ${port_name}\[${bit}\] is not" - } else { - funset port - array set port $ports_to_pins($port_name) - - if {[info exists port($bit)]} { - # collision! - send_message error "Signal ${port_name}\[${bit}\] is having original assignment ${peripheral_name}.${port($bit)} replaced with ${peripheral_name}.${pin_name}" - } - set port($bit) $pin_name - set ports_to_pins($port_name) [array get port] - } - } - add_parameter DB_port_pins string [array get ports_to_pins] "" - set_parameter_property DB_port_pins derived true - set_parameter_property DB_port_pins visible false - - set p [array get ports_to_pins] - send_message debug "DB_port_pins: ${p}" - - # bfm types - set count 0 - funset bfm_types - csv_foreach_row $bfm_types_file cols { - incr count - - # skip header - if {$count == 1} continue - - set bfm_type_name [string trim [lindex $cols 0]] - set property_name [string trim [lindex $cols 1]] - set value [string trim [lindex $cols 2]] - - if {[info exists bfm_types($bfm_type_name)] == 0} { - set bfm_types($bfm_type_name) {} - } - funset bfm_type - array set bfm_type $bfm_types($bfm_type_name) - set bfm_type($property_name) $value - set bfm_types($bfm_type_name) [array get bfm_type] - } - add_parameter DB_bfm_types string [array get bfm_types] "" - set_parameter_property DB_bfm_types derived true - set_parameter_property DB_bfm_types visible false - # TODO: what to do so that mode information on a peripheral.pin basis can be used for elaboration??? -} - -# only run during class creation -load_periph_ifaces_db - -####################### -##### Composition ##### -####################### - -namespace eval ::fpga_interfaces { - source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl -} - -namespace eval ::hps_io { - namespace eval internal { - source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl - } - variable pins - - proc add_peripheral {peripheral_name atom_name location} { - internal::add_module_instance $peripheral_name $atom_name $location - } - - # oe used in tristate output and inout - # out used in output and inout - # in used in input and inout - proc add_pin {peripheral_name pin_name dir location in_port out_port oe_port} { - variable pins - lappend pins [list $peripheral_name $pin_name $dir $location $in_port $out_port $oe_port] - } - - proc process_pins {} { - variable pins - - set interface_name "hps_io" - set hps_io_interface_created 0 - funset ports_used ;# set of inst/ports used - funset port_wire ;# map of ports to aliased wires - foreach pin $pins { ;# Check for multiple uses of the same port and create wires for those cases - lassign $pin peripheral_name pin_name dir location in_port out_port oe_port - - # check to see if port is used multiple times - foreach port_part [list $in_port $out_port $oe_port] { - if {$port_part != "" && [info exists ports_used($port_part)]} { - # Assume only outputs will be used multiple times. Inputs would be an error - if {[info exists port_wire($port_part)] == 0} { - set port_wire($port_part) [internal::allocate_wire] - # Drive new wire with port - internal::set_wire_port_fragments $port_wire($port_part) driven_by $port_part - } - } - set ports_used($port_part) 1 - } - } - - set qip [list] - foreach pin $pins { - lassign $pin peripheral_name pin_name dir location in_port out_port oe_port - foreach port_part_ref {in_port out_port oe_port} { ;# Replace ports with wires if needed - set port_part [set $port_part_ref] - if {[info exists port_wire($port_part)]} { - set $port_part_ref [internal::wire_tofragment $port_wire($port_part)] - } - } - - # Hook things up - set instance_name [string tolower $peripheral_name] ;# is this necessary??? - if {$hps_io_interface_created == 0} { - set hps_io_interface_created 1 - internal::add_interface $interface_name conduit input - } - set export_signal_name "hps_io_${instance_name}_${pin_name}" - internal::add_interface_port $interface_name $export_signal_name $export_signal_name $dir 1 - if {[string compare $dir "input"] == 0} { - internal::set_port_fragments $interface_name $export_signal_name $in_port - internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *" - } elseif {[string compare $dir "output"] == 0} { - if {[string compare $oe_port "" ] == 0} { - internal::set_port_fragments $interface_name $export_signal_name $out_port - internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" - } else { - internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port - internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" - } - } else { - internal::set_port_fragments $interface_name $export_signal_name $in_port - internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port - internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *" - internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" - } - set path_to_pin "hps_io|border|${export_signal_name}\[0\]" - set location_assignment "set_instance_assignment -name HPS_LOCATION ${location} -entity %entityName% -to ${path_to_pin}" - lappend qip $location_assignment - } - set_qip_strings $qip - } - - proc init {} { - internal::init - variable pins [list] - } - - proc serialize {var_name} { - upvar 1 $var_name data - process_pins - internal::serialize data - } -} - -set_module_property composition_callback compose - -proc compose {} { - # synchronize device families between the EMIF and HPS parameter sets - set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] - fpga_interfaces::init - fpga_interfaces::set_bfm_types [array get DB_bfm_types] - - hps_io::init - validate - elab 0 - - update_hps_to_fpga_clock_frequency_parameters - - - fpga_interfaces::serialize fpga_interfaces_data - - add_instance fpga_interfaces altera_interface_generator - set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data] - - expose_border fpga_interfaces $fpga_interfaces_data(interfaces) - - declare_cmsis_svd $fpga_interfaces_data(interfaces) - - clear_array temp_array -} - -proc logicalview_dtg {} { - - set hard_peripheral_logical_view_dir $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/hard_peripheral_logical_view - - source "$hard_peripheral_logical_view_dir/common/hps_utils.tcl" - - source "$hard_peripheral_logical_view_dir/hps_periphs/hps_periphs.tcl" - - set f2h_present [ expr [ get_parameter_value F2S_Width ] != 0] - set h2f_present [ expr [ get_parameter_value S2F_Width ] != 0] - set F2S_Width [ get_parameter_value F2S_Width ] - set S2F_Width [ get_parameter_value S2F_Width ] - set h2f_lw_present [ expr [ string compare [ get_parameter_value LWH2F_Enable ] "true" ] == 0 ] - set LWH2F_Enable [ get_parameter_value LWH2F_Enable ] - set device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] - - # Need to add whole bunch of device tree generation parameters here (dtg) - # Getting whether is it single or dual core by checking the device family. List of single core: - # Cyclone V SE - regsub "^.* V" $device_family "" se_family - regsub " " $se_family "" se_family - - set number_of_a9 0 - if { [string toupper $se_family] == "SE"} { - set number_of_a9 1 - } else { - set number_of_a9 2 - } - - set F2SDRAM_Width [get_parameter_value F2SDRAM_Width] - set F2SDRAM_Type [get_parameter_value F2SDRAM_Type] - set quartus_ini_hps_ip_f2sdram_bonding_out [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] - set BONDING_OUT_ENABLED [get_parameter_value BONDING_OUT_ENABLED] - add_instance clk_0 hps_clk_src - hps_utils_add_instance_clk_reset clk_0 bridges hps_bridge_avalon - set_instance_parameter_value bridges F2S_Width $F2S_Width - set_instance_parameter_value bridges S2F_Width $S2F_Width - set_instance_parameter_value bridges BONDING_OUT_ENABLED $BONDING_OUT_ENABLED - set_instance_parameter_value bridges LWH2F_Enable $LWH2F_Enable - set_instance_parameter_value bridges quartus_ini_hps_ip_f2sdram_bonding_out $quartus_ini_hps_ip_f2sdram_bonding_out - add_interface h2f_reset reset output - set_interface_property h2f_reset EXPORT_OF bridges.h2f_reset - set_interface_property h2f_reset PORT_NAME_MAP "h2f_rst_n h2f_rst_n" - - set rows [llength $F2SDRAM_Width] - set type_list $F2SDRAM_Type - set append_type_list "" - set append_type_width "" - set total_command_port 0 - set total_write_port 0 - set total_read_port 0 - if {$rows > 0} { - for {set i 0} {${i} < $rows} {incr i} { - set type_choice [lindex $type_list $i] - set type_width [lindex $F2SDRAM_Width $i] - if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { - set type_id 1 - set total_command_port [expr $total_command_port + 1] - if {$type_width == 128} { - set total_write_port [expr $total_write_port + 2] - set total_read_port [expr $total_read_port + 2] - } elseif {$type_width == 256 } { - set total_write_port [expr $total_write_port + 4] - set total_read_port [expr $total_read_port + 4] - } else { - set total_write_port [expr $total_write_port + 1] - set total_read_port [expr $total_read_port + 1] - } - } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { - set type_id 2 - set total_command_port [expr $total_command_port + 1] - if {$type_width == 128} { - set total_write_port [expr $total_write_port + 2] - } elseif {$type_width == 256 } { - set total_write_port [expr $total_write_port + 4] - } else { - set total_write_port [expr $total_write_port + 1] - } - } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { - set type_id 3 - set total_command_port [expr $total_command_port + 1] - if {$type_width == 128} { - set total_read_port [expr $total_read_port + 2] - } elseif {$type_width == 256 } { - set total_read_port [expr $total_read_port + 4] - } else { - set total_read_port [expr $total_read_port + 1] - } - } else { - set type_id 0 - if { [ expr $total_command_port % 2 ] } { - incr total_command_port 1 - } - set total_command_port [expr $total_command_port + 2] - if {$type_width == 128} { - set total_write_port [expr $total_write_port + 2] - set total_read_port [expr $total_read_port + 2] - } elseif {$type_width == 256 } { - set total_write_port [expr $total_write_port + 4] - set total_read_port [expr $total_read_port + 4] - } else { - set total_write_port [expr $total_write_port + 1] - set total_read_port [expr $total_read_port + 1] - } - } - - if {$total_command_port > 6} { - if {$type_id == 0} { - send_message error "No command ports available to allocate AXI Interface f2h_sdram${i}" - } else { - send_message error "No command ports available to allocate Avalon-MM Interface f2h_sdram${i}" - } - } - if {$total_read_port > 4} { - if {$type_id == 0} { - send_message error "No read ports available to allocate AXI Interface f2h_sdram${i}" - } else { - send_message error "No read ports available to allocate Avalon-MM Interface f2h_sdram${i}" - } - } - if {$total_write_port > 4} { - if {$type_id == 0} { - send_message error "No write ports available to allocate AXI Interface f2h_sdram${i}" - } else { - send_message error "No write ports available to allocate Avalon-MM Interface f2h_sdram${i}" - } - } - if {$total_command_port < 7 && $total_write_port < 5 && $total_read_port < 5} { - lappend append_type_list $type_id - lappend append_type_width $type_width - } - } - } - set_instance_parameter_value bridges F2SDRAM_Type $append_type_list - set_instance_parameter_value bridges F2SDRAM_Width $append_type_width - set total_command_port 0 - set total_write_port 0 - set total_read_port 0 - set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] - - if {$rows > 0} { - for {set i 0} {${i} < $rows} {incr i} { - - set type_choice [lindex $type_list $i] - set type_width [lindex $F2SDRAM_Width $i] - - if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { - set type "avalon" - set total_command_port [expr $total_command_port + 1] - if {$type_width == 128} { - set total_write_port [expr $total_write_port + 2] - set total_read_port [expr $total_read_port + 2] - } elseif {$type_width == 256 } { - set total_write_port [expr $total_write_port + 4] - set total_read_port [expr $total_read_port + 4] - } else { - set total_write_port [expr $total_write_port + 1] - set total_read_port [expr $total_read_port + 1] - } - set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE" - } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { - set type "avalon" - set total_command_port [expr $total_command_port + 1] - if {$type_width == 128} { - set total_write_port [expr $total_write_port + 2] - } elseif {$type_width == 256 } { - set total_write_port [expr $total_write_port + 4] - } else { - set total_write_port [expr $total_write_port + 1] - } - set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE" - } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { - set type "avalon" - set total_command_port [expr $total_command_port + 1] - if {$type_width == 128} { - set total_read_port [expr $total_read_port + 2] - } elseif {$type_width == 256 } { - set total_read_port [expr $total_read_port + 4] - } else { - set total_read_port [expr $total_read_port + 1] - } - set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ" - } else { - set type "axi" - if { [ expr $total_command_port % 2 ] } { - incr total_command_port 1 - } - set total_command_port [expr $total_command_port + 2] - if {$type_width == 128} { - set total_write_port [expr $total_write_port + 2] - set total_read_port [expr $total_read_port + 2] - } elseif {$type_width == 256 } { - set total_write_port [expr $total_write_port + 4] - set total_read_port [expr $total_read_port + 4] - } else { - set total_write_port [expr $total_write_port + 1] - set total_read_port [expr $total_read_port + 1] - } - set sdram_data "f2h_sdram${i}_ARADDR f2h_sdram${i}_ARADDR f2h_sdram${i}_ARLEN f2h_sdram${i}_ARLEN f2h_sdram${i}_ARID f2h_sdram${i}_ARID f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARBURST f2h_sdram${i}_ARBURST f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARPROT f2h_sdram${i}_ARPROT f2h_sdram${i}_ARVALID f2h_sdram${i}_ARVALID f2h_sdram${i}_ARCACHE f2h_sdram${i}_ARCACHE f2h_sdram${i}_AWADDR f2h_sdram${i}_AWADDR f2h_sdram${i}_AWLEN f2h_sdram${i}_AWLEN f2h_sdram${i}_AWID f2h_sdram${i}_AWID f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWBURST f2h_sdram${i}_AWBURST f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWPROT f2h_sdram${i}_AWPROT f2h_sdram${i}_AWVALID f2h_sdram${i}_AWVALID f2h_sdram${i}_AWCACHE f2h_sdram${i}_AWCACHE f2h_sdram${i}_BRESP f2h_sdram${i}_BRESP f2h_sdram${i}_BID f2h_sdram${i}_BID f2h_sdram${i}_BVALID f2h_sdram${i}_BVALID f2h_sdram${i}_BREADY f2h_sdram${i}_BREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RDATA f2h_sdram${i}_RDATA f2h_sdram${i}_RRESP f2h_sdram${i}_RRESP f2h_sdram${i}_RLAST f2h_sdram${i}_RLAST f2h_sdram${i}_RID f2h_sdram${i}_RID f2h_sdram${i}_RVALID f2h_sdram${i}_RVALID f2h_sdram${i}_WLAST f2h_sdram${i}_WLAST f2h_sdram${i}_WVALID f2h_sdram${i}_WVALID f2h_sdram${i}_WDATA f2h_sdram${i}_WDATA f2h_sdram${i}_WSTRB f2h_sdram${i}_WSTRB f2h_sdram${i}_WREADY f2h_sdram${i}_WREADY f2h_sdram${i}_WID f2h_sdram${i}_WID" - } - - if {$total_command_port > 6 || $total_write_port > 4 || $total_read_port > 4} { - break - } - add_interface f2h_sdram${i}_clock clock Input - set_interface_property f2h_sdram${i}_clock EXPORT_OF bridges.f2h_sdram${i}_clock - set_interface_property f2h_sdram${i}_clock PORT_NAME_MAP "f2h_sdram${i}_clk f2h_sdram${i}_clk" - add_interface f2h_sdram${i}_data $type slave - set_interface_property f2h_sdram${i}_data EXPORT_OF bridges.f2h_sdram${i}_data - set_interface_property f2h_sdram${i}_data PORT_NAME_MAP "$sdram_data" - } - - if $bonding_out_signal { - set bon_out_signal "f2h_sdram_BONOUT_1 f2h_sdram_BONOUT_1 f2h_sdram_BONOUT_2 f2h_sdram_BONOUT_2" - add_interface f2h_sdram_bon_out conduit Output - set_interface_property f2h_sdram_bon_out EXPORT_OF bridges.f2h_sdram_bon_out - set_interface_property f2h_sdram_bon_out PORT_NAME_MAP "$bon_out_signal" - } - - } - - set declared_svd_file 0 - set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd] - if { $h2f_present } { - hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f {0xc0000000} - if { $number_of_a9 > 1 } { - hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f {0xc0000000} - } - - add_interface h2f_axi_clock clock Input - set_interface_property h2f_axi_clock EXPORT_OF bridges.h2f_axi_clock - set_interface_property h2f_axi_clock PORT_NAME_MAP "h2f_axi_clk h2f_axi_clk" - - add_interface h2f_axi_master axi master - set_interface_property h2f_axi_master EXPORT_OF bridges.h2f - set_interface_property h2f_axi_master PORT_NAME_MAP "h2f_AWID h2f_AWID h2f_AWADDR h2f_AWADDR h2f_AWLEN h2f_AWLEN h2f_AWSIZE h2f_AWSIZE h2f_AWBURST h2f_AWBURST h2f_AWLOCK h2f_AWLOCK h2f_AWCACHE h2f_AWCACHE h2f_AWPROT h2f_AWPROT h2f_AWVALID h2f_AWVALID h2f_AWREADY h2f_AWREADY h2f_WID h2f_WID h2f_WDATA h2f_WDATA h2f_WSTRB h2f_WSTRB h2f_WLAST h2f_WLAST h2f_WVALID h2f_WVALID h2f_WREADY h2f_WREADY h2f_BID h2f_BID h2f_BRESP h2f_BRESP h2f_BVALID h2f_BVALID h2f_BREADY h2f_BREADY h2f_ARID h2f_ARID h2f_ARADDR h2f_ARADDR h2f_ARLEN h2f_ARLEN h2f_ARSIZE h2f_ARSIZE h2f_ARBURST h2f_ARBURST h2f_ARLOCK h2f_ARLOCK h2f_ARCACHE h2f_ARCACHE h2f_ARPROT h2f_ARPROT h2f_ARVALID h2f_ARVALID h2f_ARREADY h2f_ARREADY h2f_RID h2f_RID h2f_RDATA h2f_RDATA h2f_RRESP h2f_RRESP h2f_RLAST h2f_RLAST h2f_RVALID h2f_RVALID h2f_RREADY h2f_RREADY" - set_interface_property h2f_axi_master SVD_ADDRESS_GROUP "hps" - set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000 - if {!$declared_svd_file} { - set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path - set declared_svd_file 1 - } - } - - if { $f2h_present } { - add_interface f2h_axi_clock clock Input - set_interface_property f2h_axi_clock EXPORT_OF bridges.f2h_axi_clock - set_interface_property f2h_axi_clock PORT_NAME_MAP "f2h_axi_clk f2h_axi_clk" - - add_interface f2h_axi_slave axi slave - set_interface_property f2h_axi_slave EXPORT_OF bridges.f2h - set_interface_property f2h_axi_slave PORT_NAME_MAP "f2h_AWID f2h_AWID f2h_AWADDR f2h_AWADDR f2h_AWLEN f2h_AWLEN f2h_AWSIZE f2h_AWSIZE f2h_AWBURST f2h_AWBURST f2h_AWLOCK f2h_AWLOCK f2h_AWCACHE f2h_AWCACHE f2h_AWPROT f2h_AWPROT f2h_AWVALID f2h_AWVALID f2h_AWREADY f2h_AWREADY f2h_AWUSER f2h_AWUSER f2h_WID f2h_WID f2h_WDATA f2h_WDATA f2h_WSTRB f2h_WSTRB f2h_WLAST f2h_WLAST f2h_WVALID f2h_WVALID f2h_WREADY f2h_WREADY f2h_BID f2h_BID f2h_BRESP f2h_BRESP f2h_BVALID f2h_BVALID f2h_BREADY f2h_BREADY f2h_ARID f2h_ARID f2h_ARADDR f2h_ARADDR f2h_ARLEN f2h_ARLEN f2h_ARSIZE f2h_ARSIZE f2h_ARBURST f2h_ARBURST f2h_ARLOCK f2h_ARLOCK f2h_ARCACHE f2h_ARCACHE f2h_ARPROT f2h_ARPROT f2h_ARVALID f2h_ARVALID f2h_ARREADY f2h_ARREADY f2h_ARUSER f2h_ARUSER f2h_RID f2h_RID f2h_RDATA f2h_RDATA f2h_RRESP f2h_RRESP f2h_RLAST f2h_RLAST f2h_RVALID f2h_RVALID f2h_RREADY f2h_RREADY" - } - - if { $h2f_lw_present } { - hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f_lw {0xff200000} - if { $number_of_a9 > 1 } { - hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f_lw {0xff200000} - } - - add_interface h2f_lw_axi_clock clock Input - set_interface_property h2f_lw_axi_clock EXPORT_OF bridges.h2f_lw_axi_clock - set_interface_property h2f_lw_axi_clock PORT_NAME_MAP "h2f_lw_axi_clk h2f_lw_axi_clk" - - add_interface h2f_lw_axi_master axi start - set_interface_property h2f_lw_axi_master EXPORT_OF bridges.h2f_lw - set_interface_property h2f_lw_axi_master PORT_NAME_MAP "h2f_lw_AWID h2f_lw_AWID h2f_lw_AWADDR h2f_lw_AWADDR h2f_lw_AWLEN h2f_lw_AWLEN h2f_lw_AWSIZE h2f_lw_AWSIZE h2f_lw_AWBURST h2f_lw_AWBURST h2f_lw_AWLOCK h2f_lw_AWLOCK h2f_lw_AWCACHE h2f_lw_AWCACHE h2f_lw_AWPROT h2f_lw_AWPROT h2f_lw_AWVALID h2f_lw_AWVALID h2f_lw_AWREADY h2f_lw_AWREADY h2f_lw_WID h2f_lw_WID h2f_lw_WDATA h2f_lw_WDATA h2f_lw_WSTRB h2f_lw_WSTRB h2f_lw_WLAST h2f_lw_WLAST h2f_lw_WVALID h2f_lw_WVALID h2f_lw_WREADY h2f_lw_WREADY h2f_lw_BID h2f_lw_BID h2f_lw_BRESP h2f_lw_BRESP h2f_lw_BVALID h2f_lw_BVALID h2f_lw_BREADY h2f_lw_BREADY h2f_lw_ARID h2f_lw_ARID h2f_lw_ARADDR h2f_lw_ARADDR h2f_lw_ARLEN h2f_lw_ARLEN h2f_lw_ARSIZE h2f_lw_ARSIZE h2f_lw_ARBURST h2f_lw_ARBURST h2f_lw_ARLOCK h2f_lw_ARLOCK h2f_lw_ARCACHE h2f_lw_ARCACHE h2f_lw_ARPROT h2f_lw_ARPROT h2f_lw_ARVALID h2f_lw_ARVALID h2f_lw_ARREADY h2f_lw_ARREADY h2f_lw_RID h2f_lw_RID h2f_lw_RDATA h2f_lw_RDATA h2f_lw_RRESP h2f_lw_RRESP h2f_lw_RLAST h2f_lw_RLAST h2f_lw_RVALID h2f_lw_RVALID h2f_lw_RREADY h2f_lw_RREADY" - set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP "hps" - set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000 - if {!$declared_svd_file} { - set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path - set declared_svd_file 1 - } - } - - if {!$declared_svd_file} { - set_module_assignment "cmsis.svd.file" $svd_path - set_module_assignment "cmsis.svd.suffix" "hps" - } - - clocks_logicalview_dtg - - if { $number_of_a9 > 0 } { - hps_utils_add_instance_clk_reset clk_0 arm_a9_0 arm_a9 - } - - if { $number_of_a9 > 1 } { - hps_utils_add_instance_clk_reset clk_0 arm_a9_1 arm_a9 - } - - - hps_instantiate_arm_gic_0 $number_of_a9 - - hps_instantiate_L2 $number_of_a9 - - hps_instantiate_dma $number_of_a9 - - hps_instantiate_sysmgr $number_of_a9 - - hps_instantiate_clkmgr $number_of_a9 - - hps_instantiate_rstmgr $number_of_a9 - - hps_instantiate_fpgamgr $number_of_a9 - - hps_instantiate_uart0 $number_of_a9 "UART0_PinMuxing" [get_parameter_value l4_sp_clk_mhz] - - hps_instantiate_uart1 $number_of_a9 "UART1_PinMuxing" [get_parameter_value l4_sp_clk_mhz] - - hps_instantiate_timer0 $number_of_a9 - - hps_instantiate_timer1 $number_of_a9 - - hps_instantiate_timer2 $number_of_a9 - - hps_instantiate_timer3 $number_of_a9 - - hps_instantiate_wd_timer0 $number_of_a9 - - hps_instantiate_wd_timer1 $number_of_a9 - - hps_instantiate_gpio0 $number_of_a9 - - hps_instantiate_gpio1 $number_of_a9 - - hps_instantiate_gpio2 $number_of_a9 - - hps_instantiate_i2c0 $number_of_a9 "I2C0_PinMuxing" - - hps_instantiate_i2c1 $number_of_a9 "I2C1_PinMuxing" - - hps_instantiate_i2c2 $number_of_a9 "I2C2_PinMuxing" - - hps_instantiate_i2c3 $number_of_a9 "I2C3_PinMuxing" - - hps_instantiate_nand0 $number_of_a9 "NAND_PinMuxing" - - hps_instantiate_spim0 $number_of_a9 "SPIM0_PinMuxing" - - hps_instantiate_spim1 $number_of_a9 "SPIM1_PinMuxing" - - hps_instantiate_qspi $number_of_a9 "QSPI_PinMuxing" - - hps_instantiate_sdmmc $number_of_a9 "SDIO_PinMuxing" - - hps_instantiate_usb0 $number_of_a9 "USB0_PinMuxing" - - hps_instantiate_usb1 $number_of_a9 "USB1_PinMuxing" - - hps_instantiate_gmac0 $number_of_a9 "EMAC0_PinMuxing" - - hps_instantiate_gmac1 $number_of_a9 "EMAC1_PinMuxing" - - hps_instantiate_dcan0 $number_of_a9 "CAN0_PinMuxing" - - hps_instantiate_dcan1 $number_of_a9 "CAN1_PinMuxing" - - hps_instantiate_l3regs $number_of_a9 - - hps_instantiate_sdrctl $number_of_a9 - - hps_instantiate_axi_ocram $number_of_a9 - - hps_instantiate_axi_sdram $number_of_a9 - - hps_instantiate_timer $number_of_a9 - - hps_instantiate_scu $number_of_a9 - - add_connection arm_gic_0.arm_gic_ppi timer.interrupt_sender - set_connection_parameter_value arm_gic_0.arm_gic_ppi/timer.interrupt_sender irqNumber 13 - - if { $f2h_present } { - hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave0 {0xfffed000} - hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave1 {0xfffec100} - hps_utils_add_slave_interface bridges.axi_f2h L2.axi_slave0 {0xfffef000} - hps_utils_add_slave_interface bridges.axi_f2h dma.axi_slave0 {0xffe01000} - hps_utils_add_slave_interface bridges.axi_f2h sysmgr.axi_slave0 {0xffd08000} - hps_utils_add_slave_interface bridges.axi_f2h clkmgr.axi_slave0 {0xffd04000} - hps_utils_add_slave_interface bridges.axi_f2h rstmgr.axi_slave0 {0xffd05000} - hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave0 {0xff706000} - hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave1 {0xffb90000} - hps_utils_add_slave_interface bridges.axi_f2h uart0.axi_slave0 {0xffc02000} - hps_utils_add_slave_interface bridges.axi_f2h uart1.axi_slave0 {0xffc03000} - hps_utils_add_slave_interface bridges.axi_f2h timer0.axi_slave0 {0xffc08000} - hps_utils_add_slave_interface bridges.axi_f2h timer1.axi_slave0 {0xffc09000} - hps_utils_add_slave_interface bridges.axi_f2h timer2.axi_slave0 [hps_timer2_base] - hps_utils_add_slave_interface bridges.axi_f2h timer3.axi_slave0 [hps_timer3_base] - hps_utils_add_slave_interface bridges.axi_f2h gpio0.axi_slave0 {0xff708000} - hps_utils_add_slave_interface bridges.axi_f2h gpio1.axi_slave0 {0xff709000} - hps_utils_add_slave_interface bridges.axi_f2h gpio2.axi_slave0 {0xff70a000} - hps_utils_add_slave_interface bridges.axi_f2h i2c0.axi_slave0 {0xffc04000} - hps_utils_add_slave_interface bridges.axi_f2h i2c1.axi_slave0 {0xffc05000} - hps_utils_add_slave_interface bridges.axi_f2h i2c2.axi_slave0 {0xffc06000} - hps_utils_add_slave_interface bridges.axi_f2h i2c3.axi_slave0 {0xffc07000} - hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave0 {0xff900000} - hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave1 {0xffb80000} - hps_utils_add_slave_interface bridges.axi_f2h spim0.axi_slave0 [hps_spim0_base] - hps_utils_add_slave_interface bridges.axi_f2h spim1.axi_slave0 [hps_spim1_base] - hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave0 {0xff705000} - hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave1 {0xffa00000} - hps_utils_add_slave_interface bridges.axi_f2h sdmmc.axi_slave0 {0xff704000} - hps_utils_add_slave_interface bridges.axi_f2h usb0.axi_slave0 {0xffb00000} - hps_utils_add_slave_interface bridges.axi_f2h usb1.axi_slave0 {0xffb40000} - hps_utils_add_slave_interface bridges.axi_f2h gmac0.axi_slave0 {0xff700000} - hps_utils_add_slave_interface bridges.axi_f2h gmac1.axi_slave0 {0xff702000} - hps_utils_add_slave_interface bridges.axi_f2h axi_ocram.axi_slave0 {0xffff0000} - hps_utils_add_slave_interface bridges.axi_f2h axi_sdram.axi_slave0 [hps_sdram_base] - hps_utils_add_slave_interface bridges.axi_f2h timer.axi_slave0 {0xfffec600} - hps_utils_add_slave_interface bridges.axi_f2h dcan0.axi_slave0 [hps_dcan0_base] - hps_utils_add_slave_interface bridges.axi_f2h dcan1.axi_slave0 [hps_dcan1_base] - hps_utils_add_slave_interface bridges.axi_f2h l3regs.axi_slave0 [hps_l3regs_base] - hps_utils_add_slave_interface bridges.axi_f2h sdrctl.axi_slave0 [hps_sdrctl_base] - } - - ##### F2H ##### - if [is_enabled F2SINTERRUPT_Enable] { - set any_interrupt_enabled 1 - set iname "f2h_irq" - set pname "f2h_irq" - add_interface "${iname}0" interrupt receiver - set_interface_property f2h_irq0 EXPORT_OF arm_gic_0.f2h_irq_0_irq_rx_offset_40 - set_interface_property f2h_irq0 PORT_NAME_MAP "f2h_irq_p0 irq_siq_40" - - add_interface "${iname}1" interrupt receiver - set_interface_property f2h_irq1 EXPORT_OF arm_gic_0.f2h_irq_32_irq_rx_offset_72 - set_interface_property f2h_irq1 PORT_NAME_MAP "f2h_irq_p1 irq_siq_72" - } -} - -set_module_property OPAQUE_ADDRESS_MAP false -set_module_property STRUCTURAL_COMPOSITION_CALLBACK compose_logicalview -proc compose_logicalview {} { - # synchronize device families between the EMIF and HPS parameter sets - set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] - fpga_interfaces::init - fpga_interfaces::set_bfm_types [array get DB_bfm_types] - - hps_io::init - validate - elab 1 - - update_hps_to_fpga_clock_frequency_parameters - - - fpga_interfaces::serialize fpga_interfaces_data - - add_instance fpga_interfaces altera_interface_generator - set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data] - - expose_border fpga_interfaces $fpga_interfaces_data(interfaces) - - #declare_cmsis_svd $fpga_interfaces_data(interfaces) - - logicalview_dtg -} - -proc declare_cmsis_svd {interfaces_str} { - array set interfaces $interfaces_str - set interface_names $interfaces([ORDERED_NAMES]) - - set h2f_exists 0 - set lwh2f_exists 0 - foreach interface_name $interface_names { - if {[string compare $interface_name "h2f_axi_master"] == 0} { - set h2f_exists 1 - } elseif {[string compare $interface_name "h2f_lw_axi_master"] == 0} { - set lwh2f_exists 1 - } - } - - set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd] - set address_group hps - set declared_svd_file 0 - - if {$h2f_exists} { - if {!$declared_svd_file} { - set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path - set declared_svd_file 1 - } - set_interface_property h2f_axi_master SVD_ADDRESS_GROUP $address_group - set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000 - } - if {$lwh2f_exists} { - if {!$declared_svd_file} { - set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path - set declared_svd_file 1 - } - set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP $address_group - set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000 - } - if {!$declared_svd_file} { - set_module_assignment "cmsis.svd.file" $svd_path - set_module_assignment "cmsis.svd.suffix" $address_group - } -} - - -###################### -##### Validation ##### -###################### - -proc validate {} { - set device_family [get_parameter_value hps_device_family] - set device [get_device] - ensure_pin_muxing_data $device_family - update_table_derived_parameters - - validate_F2SDRAM - update_S2F_CLK_mux_options - update_pin_muxing_ui $device_family - - # funset placement_by_pin - validate_pin_muxing $device_family placement_by_pin - update_gpio_ui placement_by_pin - - validate_TEST - - validate_interrupt $device_family - - validate_clocks - -} - -proc validate_TEST {} { - set ini [get_parameter_value quartus_ini_hps_ip_enable_test_interface] - set_parameter_property TEST_Enable visible $ini -} - -proc hide_param { paramName hide} { - -} -proc update_hps_to_fpga_clock_frequency_parameters {} { - set u0 [get_parameter_value S2FCLK_USER0CLK_Enable] - set u1 [get_parameter_value S2FCLK_USER1CLK_Enable] - #set u2 [get_parameter_value S2FCLK_USER2CLK_Enable] - - for { set i 0 } { $i < 2 } { incr i } { - set_parameter_property "S2FCLK_USER${i}CLK_FREQ" enabled [expr "\$u${i}"] - - if { [string compare true [expr "\$u${i}"] ] == 0 } { - fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRateKnown true - fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRate [expr [get_parameter_value "S2FCLK_USER${i}CLK_FREQ"] * 1000000 ] - } - } -} - -proc update_table_derived_parameters {} { - update_f2sdram_names - update_dma_peripheral_ids -} - -proc update_f2sdram_names {} { - set num_rows [llength [get_parameter_value F2SDRAM_Width]] - set names [list] - - for {set index 0} {$index < $num_rows} {incr index} { - set name "f2h_sdram${index}" - lappend names $name - } - set_parameter_value F2SDRAM_Name_DERIVED ${names} -} - -proc update_dma_peripheral_ids {} { - set periph_id_list {0 1 2 3 4 5 6 7} - set_parameter_value DMA_PeriphId_DERIVED $periph_id_list -} - -proc is_enabled {parameter} { - if { [string compare [get_parameter_value $parameter] "true" ] == 0 } { - return 1 - } else { - return 0 - } -} - -proc validate_F2SDRAM {} { - set type_list [get_parameter_value F2SDRAM_Type] - set width_list [get_parameter_value F2SDRAM_Width] - set rows [llength $width_list] - - set command_ports_bit 0 - set read_ports_bit 0 - set write_ports_bit 0 - - set command_ports_mask 0 - set read_ports_mask 0 - set write_ports_mask 0 - set reset_ports_mask 0 - - for {set index 0} {${index} < ${rows}} {incr index} { - # check for invalid combinations of type/width - set mytype [lindex $type_list $index] - set mywidth [lindex $width_list $index] - - if {$mywidth < 64} { - send_message warning "Setting the slave port width of interface f2h_sdram${index} to ${mywidth} results in bandwidth under-utilization. Altera recommends you set the interface data width to 64-bit or greater." - } - - # count used ports - # command - if { [string compare $mytype [F2HSDRAM_AXI3]] == 0 } { - if { [ expr $command_ports_bit % 2 ] } { - incr command_ports_bit 1 - } - set command_ports_mask [ expr $command_ports_mask | ( 3 << $command_ports_bit) ] - incr command_ports_bit 2 - } else { - set command_ports_mask [ expr $command_ports_mask | ( 1 << $command_ports_bit) ] - incr command_ports_bit 1 - } - - # read - if {$mytype != [F2HSDRAM_AVM_WRITEONLY]} { - if {$mywidth <= 64} { - set read_ports_mask [ expr $read_ports_mask | ( 1 << $read_ports_bit) ] - incr read_ports_bit 1 - } elseif {$mywidth == 128} { - set read_ports_mask [ expr $read_ports_mask | ( 3 << $read_ports_bit) ] - incr read_ports_bit 2 - } else { - set read_ports_mask [ expr $read_ports_mask | ( 15 << $read_ports_bit) ] - incr read_ports_bit 4 - } - } - - # write - if {$mytype != [F2HSDRAM_AVM_READONLY]} { - if {$mywidth <= 64} { - set write_ports_mask [ expr $write_ports_mask | ( 1 << $write_ports_bit) ] - incr write_ports_bit 1 - } elseif {$mywidth == 128} { - set write_ports_mask [ expr $write_ports_mask | ( 3 << $write_ports_bit) ] - incr write_ports_bit 2 - } else { - set write_ports_mask [ expr $write_ports_mask | ( 15 << $write_ports_bit) ] - incr write_ports_bit 4 - } - } - - # reset - set reset_ports_mask [ expr ($command_ports_mask << 8) | ($write_ports_mask << 4) | ($read_ports_mask) ] - - } - # check for port over-use - if {$command_ports_bit > 6} { - send_message error "The current FPGA to SDRAM configuration is using more command ports than are available." - } - if {$read_ports_bit > 4} { - send_message error "The current FPGA to SDRAM configuration is using more read ports than are available." - } - if {$write_ports_bit > 4} { - send_message error "The current FPGA to SDRAM configuration is using more write ports than are available." - } - - # Store ports used & number of elements to determine when new rows are added - set_parameter_value F2SDRAM_Width_Last_Size $rows - set_parameter_value F2SDRAM_CMD_PORT_USED [ format "0x%X" $command_ports_mask ] - set_parameter_value F2SDRAM_RD_PORT_USED [ format "0x%X" $read_ports_mask ] - set_parameter_value F2SDRAM_WR_PORT_USED [ format "0x%X" $write_ports_mask ] - set_parameter_value F2SDRAM_RST_PORT_USED [ format "0x%X" $reset_ports_mask ] - - # Bonding_out signals will be exported if f2sdram selected - if { ${rows} > 0 } { - set param [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] - set_parameter_property BONDING_OUT_ENABLED visible $param - set_parameter_property BONDING_OUT_ENABLED enabled $param - } else { - set_parameter_property BONDING_OUT_ENABLED enabled false - } - -} - -proc update_S2F_CLK_mux_options {} { - # TODO: retrieve mux options - # TODO: set allowed_ranges on muxes -} - -proc dec2bin {i} { - set res {} - while {$i>0} { - set res [ expr {$i%2} ]$res - set i [expr {$i/2}] - } - if {$res == {}} { - set res 0 - } - return $res -} - -##################################################################### -# -# Gets valid modes for a peripheral with a given pin muxing option. -# Parameters: * peripheral_ref: name of an array pointing to the -# Peripheral HPS I/O Data -# -# Update parameter value with label -proc get_valid_modes {peripheral_name pin_muxing_option peripheral_ref fpga_available} { -##################################################################### - upvar 1 $peripheral_ref peripheral - - if {[info exists peripheral(pin_sets)]} { - array set pin_sets $peripheral(pin_sets) - } - - if {[info exists pin_sets($pin_muxing_option)]} { - array set pin_set $pin_sets($pin_muxing_option) - set pin_set_modes $pin_set(valid_modes) - if {[string match -nocase "trace" $peripheral_name]} { - set valid_modes [list "HPS:8-bit Data" "HPSx4:4-bit Data"] - } elseif {[string match -nocase "usb*" $peripheral_name]} { - set valid_modes [list "SDR:SDR with PHY clock output mode" "SDR without external clock:SDR with PHY clock input mode"] - } else { - set valid_modes [lsort -ascii -increasing $pin_set_modes] - } - } elseif {$fpga_available && [string compare $pin_muxing_option [FPGA_MUX_VALUE]] == 0} { - set valid_modes [list "Full"] - } else { - set valid_modes [list [NA_MODE_VALUE]] - } - return $valid_modes -} - -proc is_peripheral_low_speed_serial_interface {peripheral_name} { - if {[string match -nocase "i2c*" $peripheral_name] || - [string match -nocase "can*" $peripheral_name] || - [string match -nocase "spi*" $peripheral_name] || - [string match -nocase "uart*" $peripheral_name] - } { - return 1 - } - return 0 -} - -# updates the _PinMuxing and _Mode parameter allowed ranges -# -uses a data structure to keep track of choices -# -allowed ranges can come from FPGA Peripheral Interfaces or IOs -# -when a pin muxing option is selected, the mode allowed ranges are -# set according to what's specified from the source (FPGA or pin i/o) -proc update_pin_muxing_ui {device_family} { - - set peripheral_names [list_peripheral_names] - foreach peripheral $peripheral_names { - - get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral\ - selected_pin_muxing_option pin_muxing_options mode_options - - set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral] - set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral] - - set pin_muxing_options [lsort -ascii $pin_muxing_options] - set pin_muxing_options [linsert $pin_muxing_options 0 [UNUSED_MUX_VALUE]] - set_parameter_property $pin_muxing_param_name enabled true - set_parameter_property $pin_muxing_param_name visible true - set_parameter_property $pin_muxing_param_name allowed_ranges $pin_muxing_options - set_parameter_property $mode_param_name visible true - - - set selected_mode_option [get_parameter_value $mode_param_name] - - # Disable I2C parameters so they can only be changed by altering EMAC parameters - # in the HPS IP GUI - if {([string compare $peripheral "I2C2" ] == 0 || [string compare $peripheral "I2C3" ] == 0) - && [string match "*EMAC*" $selected_mode_option]} { - set_parameter_property $pin_muxing_param_name enabled false - set_parameter_property $mode_param_name enabled false - } else { - set_parameter_property $mode_param_name enabled true - } - set_parameter_property $mode_param_name allowed_ranges $mode_options - - # Disabled peripherals that not supported by certain device family - if {[check_device_family_equivalence $device_family ARRIAV]} { - foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] { - if {[string compare $excluded_peripheral $peripheral] == 0} { - set_parameter_property $pin_muxing_param_name enabled false - set_parameter_property $pin_muxing_param_name visible false - set_parameter_property $mode_param_name enabled false - set_parameter_property $mode_param_name visible false - } - } - } - } - - # Only show I2C's "Used by EMACx" modes when EMAC is using I2C - if {[is_pin_mux_data_available hps_ip_pin_muxing_model]} { - foreach emac {EMAC0 EMAC1} { - set emac_pin_set [get_parameter_value [format [PIN_MUX_PARAM_FORMAT] $emac]] - set emac_mode [get_parameter_value [format [MODE_PARAM_FORMAT] $emac]] - - funset i2c_name - get_linked_peripheral hps_ip_pin_muxing_model $emac $emac_pin_set\ - i2c_name i2c_pin_set i2c_mode - - if {[info exists i2c_name] && ![string match "*${i2c_name}*" $emac_mode]} { - # remove EMAC mode - set i2c_mode_param [format [MODE_PARAM_FORMAT] $i2c_name] - set i2c_valid_modes [get_parameter_property $i2c_mode_param ALLOWED_RANGES] - - set new_i2c_valid_modes [list] - foreach mode $i2c_valid_modes { - if {![string match "*${emac}*" $mode]} { - lappend new_i2c_valid_modes $mode - } - } - set_parameter_property $i2c_mode_param ALLOWED_RANGES $new_i2c_valid_modes - } - } - } -} - -proc validate_interrupt {device_family} { - set interrupt_groups [list_h2f_interrupt_groups] - set excluded "CAN" - foreach interrupt_group $interrupt_groups { - set parameter "S2FINTERRUPT_${interrupt_group}_Enable" - set_parameter_property $parameter enabled true - set_parameter_property $parameter visible true - if {[check_device_family_equivalence $device_family ARRIAV] && [string compare $excluded $interrupt_group] == 0} { - set_parameter_property $parameter enabled false - set_parameter_property $parameter visible false - } - } -} - -proc update_gpio_ui {placement_by_pin_ref} { - upvar 1 $placement_by_pin_ref placement_by_pin - # TODO: caching of what needs to be updated? - set customer_pin_names [list] - set gpio_names [list] - set loanio_names [list] - set conflicts [list] - - set customer_pin_names [hps_ip_pin_muxing_model::get_customer_pin_names] - - foreach_gpio_entry hps_ip_pin_muxing_model\ - entry gpio_index gpio_name pin gplin_used gplin_select\ - { - lappend gpio_names $gpio_name - - set conflict "" - if {[info exists placement_by_pin($pin)]} { - set conflict [join $placement_by_pin($pin) ", "] - } - lappend conflicts $conflict - } - foreach_loan_io_entry hps_ip_pin_muxing_model\ - entry loanio_index loanio_name pin gplin_used gplin_select\ - { - lappend loanio_names $loanio_name - } - set_parameter_value Customer_Pin_Name_DERIVED $customer_pin_names - set_parameter_value GPIO_Name_DERIVED $gpio_names - set_parameter_value LOANIO_Name_DERIVED $loanio_names - set_parameter_value GPIO_Conflict_DERIVED $conflicts -} - -proc peripheral_to_wys_atom_name {device_family peripheral} { - set generic_atom_name [hps_io_peripheral_to_generic_atom_name $peripheral] - set wys_atom_name [generic_atom_to_wys_atom $device_family $generic_atom_name] - return $wys_atom_name -} - -# TODO: deal with going out of bounds (gpio_index > 70) -proc gpio_index_to_gpio_port_index {gpio_index} { - set group [expr {$gpio_index / 29}] - set port_index [expr {$gpio_index % 29}] - - set result [list $group $port_index] - return $result -} - - - -proc validate_pin_muxing {device_family placement_by_pin_ref} { - upvar 1 $placement_by_pin_ref placement_by_pin - - # see which pins are being used more than once - # peripherals - funset pin_to_peripheral ;# pin names to peripheral that is occupying - funset conflict_pin_list ; - - foreach peripheral_name [list_peripheral_names] { - set pins_used 0 - set mapping_msg "Peripheral $peripheral_name pin mapping:" - set comma " " - set periph_inst [string tolower "${peripheral_name}_inst"] - foreach_used_peripheral_pin hps_ip_pin_muxing_model $peripheral_name\ - signal_name\ - map\ - pin\ - location\ - mux_select\ - { - # Validate - set entry_exists [info exists pin_to_peripheral($pin)] - if {$entry_exists == 1} { - set conflicting_peripheral $pin_to_peripheral($pin) - # only emit an error once per unique pair of conflicting peripherals - if {[info exists known_conflicts($conflicting_peripheral)] == 0} { - set known_conflicts($conflicting_peripheral) 1 - # TODO: more detailed error message e.g. which pins? explicitly say the bank and modes? - send_message error "Refer to the Peripherals Mux Table for more details. The selected peripherals '$conflicting_peripheral' and '$peripheral_name' are conflicting. " - } - set conflict_pin_list($pin) 1 - } else { - set pin_to_peripheral($pin) $peripheral_name - } - - # Render pins - lassign $map in_port out_port oe_port - set goes_out 0 - set goes_in 0 - - # by default, all signals are assumed to be from the same instance - if {$in_port != ""} { - set in_port "${periph_inst}:${in_port}" - set goes_in 1 - } - if {$out_port != ""} { - set out_port "${periph_inst}:${out_port}" - set goes_out 1 - } - if {$oe_port != ""} { - set oe_port "${periph_inst}:${oe_port}" - set goes_out 1 - } - - if {$goes_in && $goes_out} { - set dir bidir - } elseif {$goes_out} { - set dir output - } else { - set dir input - } - - hps_io::add_pin $periph_inst $signal_name $dir $location $in_port $out_port $oe_port - - if {[info exists placement_by_pin($pin)] == 0} { - set placement_by_pin($pin) [list] - } - lappend placement_by_pin($pin) "${peripheral_name}.${signal_name}" - - set mapping_msg "${mapping_msg}${comma}${signal_name}:${pin}" - set comma ", " - set pins_used 1 - } - if {$pins_used} { - # send_message info $mapping_msg - set wys_atom_name [peripheral_to_wys_atom_name $device_family $peripheral_name] - set location [locations::get_hps_io_peripheral_location $peripheral_name] - hps_io::add_peripheral ${periph_inst} $wys_atom_name $location - } - } - - # HLGPI input only pins - set hlgpi_pins [hps_ip_pin_muxing_model::get_hlgpi_pins] - set hlgpi_count [llength $hlgpi_pins] - set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] - set periph_inst "gpio_inst" - set gpio_unused 1 - set device [get_device] - - if { [ string range $device 0 3 ] == "5CSE" && [ string range $device 8 9 ] == "19" } { - send_message info "HLGPI is not available for Device $device (484 pins)" - set_parameter_property HLGPI_Enable enabled false - } else { - set_parameter_property HLGPI_Enable enabled true - } - - if { [is_enabled HLGPI_Enable] && [get_parameter_property HLGPI_Enable enabled] } { - for {set hlgpi_pin_index 0} {$hlgpi_pin_index < $hlgpi_count} {incr hlgpi_pin_index} { - # HLGPI connected to gpio[26:13] - set gpio_port_index [ expr {$hlgpi_pin_index + 13} ] - set hlgpi_pin [ lindex $hlgpi_pins $hlgpi_pin_index] - - if {$gpio_unused} { - set atom_location [locations::get_hps_io_peripheral_location "GPIO"] - hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location - set gpio_unused 0 - } - - set signal_name "HLGPI${hlgpi_pin_index}" - set pin_location [::pin_mux_db::get_location_of_pin $hlgpi_pin] - set in_port "${periph_inst}:GPIO2_PORTA_I($gpio_port_index:$gpio_port_index)" - set out_port "" - set oe_port "" - - hps_io::add_pin ${periph_inst} $signal_name input $pin_location $in_port $out_port $oe_port - } - } - - # gpio - funset gpio_port_placement_set ;# set of gpio ports that are being used - set enable_list [get_parameter_value GPIO_Enable] - set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] - set periph_inst "gpio_inst" - - # check and set GPIO_Pin_Used_DERIVED parameter - set_parameter_value GPIO_Pin_Used_DERIVED false - - foreach_gpio_entry hps_ip_pin_muxing_model\ - entry gpio_index gpio_name pin gplin_used gplin_select\ - { - set enabled 0 - set enable_value [lindex $enable_list $entry] - if { [string compare $enable_value "Yes" ] == 0 } { - set enabled 1 - } - if {$enabled} { - set entry_exists [info exists pin_to_peripheral($pin)] - if {$entry_exists} { - set conflicting_peripheral $pin_to_peripheral($pin) - send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral '$conflicting_peripheral' and '${gpio_name}' are conflicting." - set conflict_pin_list($pin) 1 - } else { - set pin_to_peripheral($pin) $gpio_name - } - - if {[info exists gpio_port_placement_set($gpio_index)]} { - send_message error "Refer to the Peripherals Mux Table for more details. GPIO${gpio_index} cannot be used twice." - set conflict_pin_list($pin) 1 - } else { - set gpio_port_placement_set($gpio_index) 1 - } - - if {$gpio_unused} { - set atom_location [locations::get_hps_io_peripheral_location "GPIO"] - hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location - set gpio_unused 0 - } - - lassign [gpio_index_to_gpio_port_index $gpio_index] gpio_group gpio_port_index - set in_port "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)" - set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)" - set oe_port "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)" - - set pin_location [::pin_mux_db::get_location_of_pin $pin] - hps_io::add_pin $periph_inst $gpio_name bidir $pin_location $in_port $out_port $oe_port - - # set GPIO_Pin_Used_DERIVED to true if GPIO pins used - set_parameter_value GPIO_Pin_Used_DERIVED true - } - } - - # loan i/o - set enable_list [get_parameter_value LOANIO_Enable] - set loanio_used 0 - set loanio_count 0 - foreach_loan_io_entry hps_ip_pin_muxing_model\ - entry loanio_index loanio_name pin gplin_used gplin_select\ - { - if {$loanio_count < $loanio_index} { - set loanio_count $loanio_index - } - set enabled 0 - set enable_value [lindex $enable_list $entry] - if { [string compare $enable_value "Yes" ] == 0 } { - set enabled 1 - } - - if {$enabled} { - set entry_exists [info exists pin_to_peripheral($pin)] - if {$entry_exists} { - set conflicting_peripheral $pin_to_peripheral($pin) - send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral for '$conflicting_peripheral' and '${loanio_name}' are conflicting." - set conflict_pin_list($pin) 1 - } else { - set pin_to_peripheral($pin) $loanio_name - } - - if {[info exists gpio_port_placement_set($loanio_index)]} { - send_message error "Refer to the Peripherals Mux Table for more details. GPIO${loanio_index} cannot be used twice." - set conflict_pin_list($pin) 1 - } else { - set gpio_port_placement_set($loanio_index) 1 - } - - set loanio_used 1 - if {$gpio_unused} { - set atom_location [locations::get_hps_io_peripheral_location "GPIO"] - hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location - set gpio_unused 0 - } - - lassign [gpio_index_to_gpio_port_index $loanio_index] gpio_group gpio_port_index - set in_port "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)" - set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)" - set oe_port "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)" - - set pin_location [::pin_mux_db::get_location_of_pin $pin] - hps_io::add_pin $periph_inst $loanio_name bidir $pin_location $in_port $out_port $oe_port - - } - } - incr loanio_count ;# count is one greater than the highest index - if $loanio_used { - set wys_atom_name [peripheral_to_wys_atom_name $device_family "LOANIO"] - set location {} - set periph_inst "loan_io_inst" - set iface_name "h2f_loan_io" - set z "h2f_loan_" - fpga_interfaces::add_module_instance ${periph_inst} $wys_atom_name $location - fpga_interfaces::add_interface $iface_name conduit Input - set pin_muxing [get_parameter_value pin_muxing] - fpga_interfaces::add_interface_port $iface_name "${z}in" in Output ${loanio_count} $periph_inst loanio_in - fpga_interfaces::add_interface_port $iface_name "${z}out" out Input ${loanio_count} $periph_inst loanio_out - fpga_interfaces::add_interface_port $iface_name "${z}oe" oe Input ${loanio_count} $periph_inst loanio_oe - - # add loanIO to GPIO atom connection - set loanio_periph_inst "loan_io_inst" - set loanio_iface_name "loanio_gpio" - set loanio_z "loanio_gpio_" - set gpio_periph_inst "gpio_inst" - set gpio_iface_name "gpio_loanio" - set gpio_z "gpio_loanio_" - set gpio_port_size 29 - set start_index 0 - - if {$gpio_unused} { - set gpio_wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] - set gpio_atom_location [locations::get_hps_io_peripheral_location "GPIO"] - hps_io::add_peripheral ${gpio_periph_inst} ${gpio_wys_atom_name} ${gpio_atom_location} - set gpio_unused 0 - } - - fpga_interfaces::add_interface $loanio_iface_name conduit Input "NO_EXPORT" - ::hps_io::internal::add_interface $gpio_iface_name conduit Output "NO_EXPORT" - - for {set i 0} {$i <= 2} {incr i} { - if {[expr ($loanio_count - $start_index)] < $gpio_port_size} { - set gpio_port_size [expr ($loanio_count - $start_index)] - } - set end_index [expr ($start_index + $gpio_port_size - 1)] - - fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_i" "loanio${i}_i" Input ${gpio_port_size} - fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_oe" "loanio${i}_oe" Output ${gpio_port_size} - fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_o" "loanio${i}_o" Output ${gpio_port_size} - - fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_i" "${loanio_periph_inst}:GPIO_IN($end_index:$start_index)" - fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_oe" "${loanio_periph_inst}:GPIO_OE($end_index:$start_index)" - fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_o" "${loanio_periph_inst}:GPIO_OUT($end_index:$start_index)" - - ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_i" "loanio${i}_i" Output ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_I" - ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_oe" "loanio${i}_oe" Input ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_OE" - ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_o" "loanio${i}_o" Input ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_O" - - set start_index [expr ($end_index + 1)] - } - } - set conflicts [list] - set pins [list] - foreach_gpio_entry hps_ip_pin_muxing_model\ - entry gpio_index gpio_name pin gplin_used gplin_select\ - { - set entry_exists [info exists conflict_pin_list($pin)] - if {$entry_exists} { - set conflict "Yes" - } else { - set conflict "No" - } - lappend conflicts $conflict - lappend pins $pin - } - set_parameter_value JAVA_CONFLICT_PIN $conflicts - set_parameter_value JAVA_GUI_PIN_LIST $pins -} - -##################################################### -# -# Sets a valid mode for the peripheral when its pin -# muxing option changes. Will try to retain the -# original mode if available. -# -proc on_altered_peripheral_pin_muxing {peripheral_name} { -##################################################### - set mode_param_name "${peripheral_name}_Mode" - set mode_option [get_parameter_value $mode_param_name] - - get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral_name\ - selected_pin_muxing_option pin_muxing_options new_valid_modes - - # filter the label name of the parameter value if exist - if {[lsearch $new_valid_modes $mode_option] == -1} { - regsub ":.*" [lindex $new_valid_modes 0] "" new_mode_option - } else { - set new_mode_option $mode_option - } - set_parameter_value $mode_param_name $new_mode_option - - if {[string match "*EMAC*" $peripheral_name]} { - on_emac_mode_switch_internal $peripheral_name - } -} - -# Adds the pin muxing model argument -proc on_emac_mode_switch_internal {peripheral_name} { - on_emac_mode_switch hps_ip_pin_muxing_model $peripheral_name -} - -proc validate_and_update_ddr {} { - set desired_operational_freq [get_parameter_value DDR_DesiredFreq] - if {$desired_operational_freq < 0.0} { - send_message error "The operational frequency of the DDR Controller cannot be negative." - } else { - send_message warning "The recommended DDR Controller clock frequency and phase shift information is not correct." - - set_parameter_value DDR_PLLC0RecommendedFreq_DERIVED $desired_operational_freq - set_parameter_value DDR_PLLC1RecommendedFreq_DERIVED [expr $desired_operational_freq * 2.0] - set_parameter_value DDR_PLLC2RecommendedFreq_DERIVED $desired_operational_freq - set_parameter_value DDR_PLLC3RecommendedFreq_DERIVED $desired_operational_freq - - set_parameter_value DDR_PLLC0RecommendedPhase_DERIVED 0.0 - set_parameter_value DDR_PLLC1RecommendedPhase_DERIVED 1.0 - set_parameter_value DDR_PLLC2RecommendedPhase_DERIVED 2.0 - set_parameter_value DDR_PLLC3RecommendedPhase_DERIVED 3.0 - } - - for {set index 0} {${index} < 4} {incr index} { - set p_name "DDR_PLLC${index}ActualFreq" - set value [get_parameter_value $p_name] - if {$value < 0.0} { - send_message error "DDR PLL Output C${index} cannot have a negative clock frequency." - } - - set p_name "DDR_PLLC${index}ActualPhase" - set value [get_parameter_value $p_name] - if {$value < 0.0} { - send_message error "DDR PLL Output C${index} cannot have a negative clock phase shift." - } - } -} - - -###################### -##### Elaboration ##### -###################### - -proc elab {logical_view} { - # TODO: add RTL information for each - set device_family [get_parameter_value hps_device_family] - - elab_clocks_resets $device_family - - elab_MPU_EVENTS $device_family - elab_DEBUGAPB $device_family - elab_STM $device_family - elab_CTI $device_family - elab_TPIUFPGA $device_family - elab_GP $device_family - elab_BOOTFROMFPGA $device_family - - if {$logical_view == 0} { - elab_F2S $device_family - elab_LWH2F $device_family - elab_S2F $device_family - elab_F2SDRAM $device_family - - } - - elab_DMA $device_family - elab_INTERRUPTS $device_family $logical_view - - elab_emac_ptp $device_family - - elab_TEST $device_family - - # Handle Special Case EMAC signal... ptp_ref_clk - set emac0_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC0] - set emac1_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC1] - set emac0_pin_mux_value [get_parameter_value $emac0_pin_mux_param_name] - set emac1_pin_mux_value [get_parameter_value $emac1_pin_mux_param_name] - set emac0_pin_mux_allowed_ranges [get_parameter_property $emac0_pin_mux_param_name allowed_ranges] - set emac1_pin_mux_allowed_ranges [get_parameter_property $emac1_pin_mux_param_name allowed_ranges] - - set emac0_ptp_enabled [expr {[string compare $emac0_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac0_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}] - set emac1_ptp_enabled [expr {[string compare $emac1_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac1_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}] - - set emac0_io_enabled [expr {[string compare $emac0_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac0_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}] - set emac1_io_enabled [expr {[string compare $emac1_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac1_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}] - - set emac0_ptp [get_parameter_value EMAC0_PTP] - set emac1_ptp [get_parameter_value EMAC1_PTP] - - if {$emac0_ptp && $emac0_io_enabled} { - set emac0_ptp_enabled 1 - } - if {$emac1_ptp && $emac1_io_enabled} { - set emac1_ptp_enabled 1 - } - - if {$emac0_ptp_enabled || $emac1_ptp_enabled } { - set instance_name clocks_resets - fpga_interfaces::add_interface emac_ptp_ref_clock clock Input - fpga_interfaces::add_interface_port emac_ptp_ref_clock emac_ptp_ref_clk clk Input 1 $instance_name ptp_ref_clk - } - - # TODO: elab peripherals that mux signals to the fpga - elab_FPGA_Peripheral_Signals $device_family - - set_parameter_value DEVICE_FAMILY [get_parameter_value SYS_INFO_DEVICE_FAMILY] -} - -proc elab_MPU_EVENTS {device_family} { - if [is_enabled MPU_EVENTS_Enable] { - set instance_name mpu_events - set atom_name hps_interface_mpu_event_standby - set location [locations::get_fpga_location $instance_name $atom_name] - - set iface_name "h2f_mpu_events" - set z "h2f_mpu_" - fpga_interfaces::add_interface $iface_name conduit Input - fpga_interfaces::add_interface_port $iface_name ${z}eventi eventi Input 1 $instance_name eventi - fpga_interfaces::add_interface_port $iface_name ${z}evento evento Output 1 $instance_name evento - fpga_interfaces::add_interface_port $iface_name ${z}standbywfe standbywfe Output 2 $instance_name standbywfe - fpga_interfaces::add_interface_port $iface_name ${z}standbywfi standbywfi Output 2 $instance_name standbywfi - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } -} - -proc elab_DEBUGAPB {device_family} { - set instance_name debug_apb - set atom_name hps_interface_dbg_apb - set location [locations::get_fpga_location $instance_name $atom_name] - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - - if [is_enabled DEBUGAPB_Enable] { - set clock_name "h2f_debug_apb_clock" - fpga_interfaces::add_interface $clock_name clock Input - fpga_interfaces::add_interface_port $clock_name "h2f_dbg_apb_clk" clk Input 1 $instance_name P_CLK - - set reset_name "h2f_debug_apb_reset" - fpga_interfaces::add_interface $reset_name reset Output - fpga_interfaces::add_interface_port $reset_name "h2f_dbg_apb_rst_n" reset_n Output 1 $instance_name P_RESET_N - fpga_interfaces::set_interface_property $reset_name associatedClock $clock_name - - set iface_name "h2f_debug_apb" - set z "h2f_dbg_apb_" - fpga_interfaces::add_interface $iface_name apb master - fpga_interfaces::add_interface_port $iface_name "${z}PADDR" paddr Output 18 $instance_name P_ADDR - fpga_interfaces::add_interface_port $iface_name "${z}PADDR31" paddr31 Output 1 $instance_name P_ADDR_31 - fpga_interfaces::add_interface_port $iface_name "${z}PENABLE" penable Output 1 $instance_name P_ENABLE - fpga_interfaces::add_interface_port $iface_name "${z}PRDATA" prdata Input 32 $instance_name P_RDATA - fpga_interfaces::add_interface_port $iface_name "${z}PREADY" pready Input 1 $instance_name P_READY - fpga_interfaces::add_interface_port $iface_name "${z}PSEL" psel Output 1 $instance_name P_SEL - fpga_interfaces::add_interface_port $iface_name "${z}PSLVERR" pslverr Input 1 $instance_name P_SLV_ERR - fpga_interfaces::add_interface_port $iface_name "${z}PWDATA" pwdata Output 32 $instance_name P_WDATA - fpga_interfaces::add_interface_port $iface_name "${z}PWRITE" pwrite Output 1 $instance_name P_WRITE - fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name - fpga_interfaces::set_interface_property $iface_name associatedReset $reset_name - - set iface_name "h2f_debug_apb_sideband" - set z "h2f_dbg_apb_" - fpga_interfaces::add_interface $iface_name conduit Input - fpga_interfaces::add_interface_port $iface_name "${z}PCLKEN" pclken Input 1 $instance_name P_CLK_EN - fpga_interfaces::add_interface_port $iface_name "${z}DBG_APB_DISABLE" dbg_apb_disable Input 1 $instance_name DBG_APB_DISABLE - fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name - fpga_interfaces::set_interface_property $iface_name associatedReset $reset_name - - } else { - # Tie low when FPGA debug apb not being used - fpga_interfaces::set_instance_port_termination ${instance_name} "P_CLK_EN" 1 0 0:0 0 - fpga_interfaces::set_instance_port_termination ${instance_name} "DBG_APB_DISABLE" 1 0 0:0 0 - } -} - -proc elab_STM {device_family} { - if [is_enabled STM_Enable] { - set instance_name stm_event - set atom_name hps_interface_stm_event - set location [locations::get_fpga_location $instance_name $atom_name] - - fpga_interfaces::add_interface f2h_stm_hw_events conduit Input - fpga_interfaces::add_interface_port f2h_stm_hw_events f2h_stm_hwevents stm_hwevents Input 28 $instance_name stm_event - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } -} - -proc elab_CTI {device_family} { - set instance_name cross_trigger_interface - set atom_name hps_interface_cross_trigger - set location [locations::get_fpga_location $instance_name $atom_name] - - if [is_enabled CTI_Enable] { - set iface_name "h2f_cti" - set z "h2f_cti_" - fpga_interfaces::add_interface $iface_name conduit Input - fpga_interfaces::add_interface_port $iface_name ${z}trig_in trig_in Input 8 $instance_name trig_in - fpga_interfaces::add_interface_port $iface_name ${z}trig_in_ack trig_in_ack Output 8 $instance_name trig_inack - fpga_interfaces::add_interface_port $iface_name ${z}trig_out trig_out Output 8 $instance_name trig_out - fpga_interfaces::add_interface_port $iface_name ${z}trig_out_ack trig_out_ack Input 8 $instance_name trig_outack - # case:105603 hide asicctl output signal - # fpga_interfaces::add_interface_port $iface_name ${z}asicctl asicctl Output 8 $instance_name asicctl - fpga_interfaces::add_interface_port $iface_name ${z}fpga_clk_en fpga_clk_en Input 1 $instance_name clk_en - fpga_interfaces::set_interface_property $iface_name associatedClock h2f_cti_clock - fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset - - fpga_interfaces::add_interface h2f_cti_clock clock Input - fpga_interfaces::add_interface_port h2f_cti_clock h2f_cti_clk clk Input 1 $instance_name clk - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } -} - -proc elab_TPIUFPGA {device_family} { - set instance_name tpiu - set atom_name hps_interface_tpiu_trace - set location [locations::get_fpga_location $instance_name $atom_name] - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - - if { [string compare [get_parameter_value TPIUFPGA_Enable] "true" ] == 0 } { - set_parameter_property TPIUFPGA_alt enabled true - set iface_name "h2f_tpiu" - set z "h2f_tpiu_" - fpga_interfaces::add_interface $iface_name conduit input - fpga_interfaces::add_interface_port $iface_name ${z}clk_ctl clk_ctl Input 1 $instance_name traceclk_ctl - fpga_interfaces::add_interface_port $iface_name ${z}data data Output 32 $instance_name trace_data - - # case 245159 - if {[string compare [get_parameter_value TPIUFPGA_alt] "true" ] == 0} { - fpga_interfaces::add_interface_port $iface_name ${z}clkin clkin Input 1 $instance_name traceclkin - } else { - set iface_name "h2f_tpiu_clock_in" - fpga_interfaces::add_interface $iface_name clock input - fpga_interfaces::add_interface_port $iface_name ${z}clk_in clk Input 1 $instance_name traceclkin - } - - set clock_in_rate [get_parameter_value H2F_TPIU_CLOCK_IN_FREQ] - set clock_rate [expr {$clock_in_rate / 2}] - set iface_name "h2f_tpiu_clock" - fpga_interfaces::add_interface $iface_name clock output - fpga_interfaces::add_interface_port $iface_name ${z}clk clk Output 1 $instance_name traceclk - fpga_interfaces::set_interface_property $iface_name clockRateKnown true - fpga_interfaces::set_interface_property $iface_name clockRate $clock_rate - - add_clock_constraint_if_valid $clock_rate "*|fpga_interfaces|${instance_name}|traceclk" - - } else { - set_parameter_property TPIUFPGA_alt enabled false - fpga_interfaces::set_instance_port_termination ${instance_name} "traceclk_ctl" 1 1 0:0 1 - } -} - -proc elab_GP {device_family} { - if [is_enabled GP_Enable] { - set instance_name h2f_gp - set atom_name hps_interface_mpu_general_purpose - set location [locations::get_fpga_location $instance_name $atom_name] - - set iface_name "h2f_gp" - set z "h2f_gp_" - fpga_interfaces::add_interface $iface_name conduit Input - fpga_interfaces::add_interface_port $iface_name ${z}in gp_in Input 32 $instance_name gp_in - fpga_interfaces::add_interface_port $iface_name ${z}out gp_out Output 32 $instance_name gp_out - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } -} - -proc elab_BOOTFROMFPGA {device_family} { - set instance_name boot_from_fpga - set atom_name hps_interface_boot_from_fpga - set location [locations::get_fpga_location $instance_name $atom_name] - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - - set bsel_en [expr { [string compare [get_parameter_value BSEL_EN] "true" ] == 0 } ] - set bsel [get_parameter_value BSEL] - set csel_en [expr { [string compare [get_parameter_value CSEL_EN] "true" ] == 0 } ] - set csel [get_parameter_value CSEL] - set boot_from_fpga_enable [expr { [string compare [get_parameter_value BOOTFROMFPGA_Enable] "true" ] == 0 } ] - set ini_string [get_parameter_value quartus_ini_hps_ip_enable_bsel_csel] - set ini_enabled [expr { [string compare $ini_string "true" ] == 0 } ] - - # force disable bsel/csel by default - if {!$ini_enabled} { - set bsel_en 0 - set bsel 1 - set csel_en 0 - set csel 1 - } - - # when INI enabled, the controls should appear in the GUI - foreach parameter {BSEL BSEL_EN CSEL CSEL_EN} { - set_parameter_property $parameter visible $ini_string - set_parameter_property $parameter enabled $ini_string - } - - fpga_interfaces::set_instance_port_termination ${instance_name} "bsel" 3 0 2:0 $bsel - fpga_interfaces::set_instance_port_termination ${instance_name} "csel" 2 0 1:0 $csel - - if {$bsel_en} { - fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 1 - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 0 - } - - if {$csel_en} { - fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 1 - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 0 - } - - if {$boot_from_fpga_enable} { - set iface_name "f2h_boot_from_fpga" - set z "f2h_boot_from_fpga_" - fpga_interfaces::add_interface $iface_name conduit Input - fpga_interfaces::add_interface_port $iface_name "${z}ready" boot_from_fpga_ready Input 1 $instance_name boot_from_fpga_ready - fpga_interfaces::add_interface_port $iface_name "${z}on_failure" boot_from_fpga_on_failure Input 1 $instance_name boot_from_fpga_on_failure - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_ready" 1 0 0:0 0 - fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_on_failure" 1 0 0:0 0 - } - - if {$boot_from_fpga_enable} { - send_message info "Ensure that valid Cortex A9 boot code is available to the HPS system when enabling boot from FPGA and h2f_axi_master interface is connecting to slave component start at address 0x0." - } - - if {$bsel_en && $bsel == 1 && !$boot_from_fpga_enable} { - send_message warning "Boot from FPGA ready must be enabled to correctly boot from the FPGA." - } -} - - -proc elab_F2S {device_family} { - set instance_name fpga2hps - set atom_name hps_interface_fpga2hps - set location [locations::get_fpga_location $instance_name $atom_name] - set termination_value 3 - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - - set addr_width 32 - set width [get_parameter_value F2S_Width] - if {$width > 0} { - set data_width 32 - set strb_width 4 - set termination_value 0 - if {$width == 2} { - set data_width 64 - set strb_width 8 - set termination_value 1 - } elseif {$width == 3} { - set data_width 128 - set strb_width 16 - set termination_value 2 - } - - set clock_name "f2h_axi_clock" - fpga_interfaces::add_interface $clock_name clock Input - fpga_interfaces::add_interface_port $clock_name f2h_axi_clk clk Input 1 $instance_name clk - - set iface_name "f2h_axi_slave" - set z "f2h_" - - fpga_interfaces::add_interface $iface_name axi slave - fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name - fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset - fpga_interfaces::set_interface_property $iface_name readAcceptanceCapability 8 - fpga_interfaces::set_interface_property $iface_name writeAcceptanceCapability 8 - fpga_interfaces::set_interface_property $iface_name combinedAcceptanceCapability 16 - fpga_interfaces::set_interface_property $iface_name readDataReorderingDepth 16 - fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width - fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width - - fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Input 8 $instance_name awid - fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Input $addr_width $instance_name awaddr - fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Input 4 $instance_name awlen - fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Input 3 $instance_name awsize - fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Input 2 $instance_name awburst - fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Input 2 $instance_name awlock - fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Input 4 $instance_name awcache - fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Input 3 $instance_name awprot - fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Input 1 $instance_name awvalid - fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Output 1 $instance_name awready - fpga_interfaces::add_interface_port $iface_name ${z}AWUSER awuser Input 5 $instance_name awuser - - fpga_interfaces::add_interface_port $iface_name ${z}WID wid Input 8 $instance_name wid - fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Input $data_width $instance_name wdata - fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Input $strb_width $instance_name wstrb - fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Input 1 $instance_name wlast - fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Input 1 $instance_name wvalid - fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Output 1 $instance_name wready - - fpga_interfaces::add_interface_port $iface_name ${z}BID bid Output 8 $instance_name bid - fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Output 2 $instance_name bresp - fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Output 1 $instance_name bvalid - fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Input 1 $instance_name bready - - - fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Input 8 $instance_name arid - fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Input $addr_width $instance_name araddr - fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Input 4 $instance_name arlen - fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Input 3 $instance_name arsize - fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Input 2 $instance_name arburst - fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Input 2 $instance_name arlock - fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Input 4 $instance_name arcache - fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Input 3 $instance_name arprot - fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Input 1 $instance_name arvalid - fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Output 1 $instance_name arready - fpga_interfaces::add_interface_port $iface_name ${z}ARUSER aruser Input 5 $instance_name aruser - - fpga_interfaces::add_interface_port $iface_name ${z}RID rid Output 8 $instance_name rid - fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Output $data_width $instance_name rdata - fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Output 2 $instance_name rresp - fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Output 1 $instance_name rlast - fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Output 1 $instance_name rvalid - fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Input 1 $instance_name rready - } - fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0 1:0 $termination_value -} - -proc elab_S2F {device_family} { - set instance_name hps2fpga - set atom_name hps_interface_hps2fpga - set location [locations::get_fpga_location $instance_name $atom_name] - set termination_value 3 - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - - set addr_width 30 - set id_width 12 - set width [get_parameter_value S2F_Width] - if {$width > 0} { - set data_width 32 - set strb_width 4 - set termination_value 0 - - if {$width == 2} { - set data_width 64 - set strb_width 8 - set termination_value 1 - - } elseif {$width == 3} { - set data_width 128 - set strb_width 16 - set termination_value 2 - } - - set clock_name "h2f_axi_clock" - fpga_interfaces::add_interface $clock_name clock Input - fpga_interfaces::add_interface_port $clock_name h2f_axi_clk clk Input 1 $instance_name clk - - set iface_name "h2f_axi_master" - set z "h2f_" - - fpga_interfaces::add_interface $iface_name axi master - fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name - fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset - fpga_interfaces::set_interface_property $iface_name readIssuingCapability 8 - fpga_interfaces::set_interface_property $iface_name writeIssuingCapability 8 - fpga_interfaces::set_interface_property $iface_name combinedIssuingCapability 16 - -# set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps golden_ref_design_CMSIS_1_1_to_arm_v2.svd] -# send_message info "REMOVE! SVD_PATH = $svd_path" -# fpga_interfaces::set_interface_property $iface_name CMSIS_SVD_FILE $svd_path -# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_GROUP hps -# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_OFFSET [expr {0xC0000000}] - fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width - fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width - fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width - - fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Output $id_width $instance_name awid - fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Output $addr_width $instance_name awaddr - fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Output 4 $instance_name awlen - fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Output 3 $instance_name awsize - fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Output 2 $instance_name awburst - fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Output 2 $instance_name awlock - fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Output 4 $instance_name awcache - fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Output 3 $instance_name awprot - fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Output 1 $instance_name awvalid - fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Input 1 $instance_name awready - - fpga_interfaces::add_interface_port $iface_name ${z}WID wid Output $id_width $instance_name wid - fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Output $data_width $instance_name wdata - fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Output $strb_width $instance_name wstrb - fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Output 1 $instance_name wlast - fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Output 1 $instance_name wvalid - fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Input 1 $instance_name wready - - fpga_interfaces::add_interface_port $iface_name ${z}BID bid Input $id_width $instance_name bid - fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Input 2 $instance_name bresp - fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Input 1 $instance_name bvalid - fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Output 1 $instance_name bready - - fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Output $id_width $instance_name arid - fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Output $addr_width $instance_name araddr - fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Output 4 $instance_name arlen - fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Output 3 $instance_name arsize - fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Output 2 $instance_name arburst - fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Output 2 $instance_name arlock - fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Output 4 $instance_name arcache - fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Output 3 $instance_name arprot - fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Output 1 $instance_name arvalid - fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Input 1 $instance_name arready - - fpga_interfaces::add_interface_port $iface_name ${z}RID rid Input $id_width $instance_name rid - fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Input $data_width $instance_name rdata - fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Input 2 $instance_name rresp - fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Input 1 $instance_name rlast - fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Input 1 $instance_name rvalid - fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Output 1 $instance_name rready - - } - fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0 1:0 $termination_value -} - -proc elab_LWH2F {device_family} { - set instance_name hps2fpga_light_weight - set atom_name hps_interface_hps2fpga_light_weight - set location [locations::get_fpga_location $instance_name $atom_name] - - if [is_enabled LWH2F_Enable] { - set addr_width 21 - set data_width 32 - set strb_width 4 - set id_width 12 - set clock_name "h2f_lw_axi_clock" - fpga_interfaces::add_interface $clock_name clock Input - fpga_interfaces::add_interface_port $clock_name h2f_lw_axi_clk clk Input 1 $instance_name clk - - set iface_name "h2f_lw_axi_master" - set z "h2f_lw_" - fpga_interfaces::add_interface $iface_name axi master -# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_GROUP hps -# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_OFFSET [expr {0xFC000000}] - fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name - fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset - fpga_interfaces::set_interface_property $iface_name readIssuingCapability 8 - fpga_interfaces::set_interface_property $iface_name writeIssuingCapability 8 - fpga_interfaces::set_interface_property $iface_name combinedIssuingCapability 16 - fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width - fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width - fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width - - fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Output $id_width $instance_name awid - fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Output $addr_width $instance_name awaddr - fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Output 4 $instance_name awlen - fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Output 3 $instance_name awsize - fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Output 2 $instance_name awburst - fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Output 2 $instance_name awlock - fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Output 4 $instance_name awcache - fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Output 3 $instance_name awprot - fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Output 1 $instance_name awvalid - fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Input 1 $instance_name awready - - fpga_interfaces::add_interface_port $iface_name ${z}WID wid Output $id_width $instance_name wid - fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Output $data_width $instance_name wdata - fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Output $strb_width $instance_name wstrb - fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Output 1 $instance_name wlast - fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Output 1 $instance_name wvalid - fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Input 1 $instance_name wready - - fpga_interfaces::add_interface_port $iface_name ${z}BID bid Input $id_width $instance_name bid - fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Input 2 $instance_name bresp - fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Input 1 $instance_name bvalid - fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Output 1 $instance_name bready - - fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Output $id_width $instance_name arid - fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Output $addr_width $instance_name araddr - fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Output 4 $instance_name arlen - fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Output 3 $instance_name arsize - fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Output 2 $instance_name arburst - fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Output 2 $instance_name arlock - fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Output 4 $instance_name arcache - fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Output 3 $instance_name arprot - fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Output 1 $instance_name arvalid - fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Input 1 $instance_name arready - - fpga_interfaces::add_interface_port $iface_name ${z}RID rid Input $id_width $instance_name rid - fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Input $data_width $instance_name rdata - fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Input 2 $instance_name rresp - fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Input 1 $instance_name rlast - fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Input 1 $instance_name rvalid - fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Output 1 $instance_name rready - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } -} - -proc elab_F2SDRAM {device_family} { - f2sdram::init_registers - - set instance_name f2sdram - set atom_name hps_interface_fpga2sdram - set location [locations::get_fpga_location $instance_name $atom_name] - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - - set use_fast_sim_model [expr { [string compare [get_parameter_value quartus_ini_hps_ip_fast_f2sdram_sim_model] "true" ] == 0 }] - set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] - #newly added - set width_list [get_parameter_value F2SDRAM_Width] - set rows [llength $width_list] - if {$rows > 0} { - # TODO: move outside of 'if' once registers are rendered - - - set type_list [get_parameter_value F2SDRAM_Type] - for {set i 0} {${i} < $rows} {incr i} { - set width [lindex $width_list $i] - set type_choice [lindex $type_list $i] - - set type "axi" - set type_id 0 - if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { - set type "avalon" - set type_id 1 - } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { - set type "avalon" - set type_id 2 - } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { - set type "avalon" - set type_id 3 - } - - set sim_is_synth [expr !$use_fast_sim_model] - - # To make sure bonding_out_signal only being added once even thought there are more than one f2sdram - if {$i == 0 } { - set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] - } else { - set bonding_out_signal 0 - } - - f2sdram::add_port registers $i $type_id $width $instance_name $sim_is_synth $bonding_out_signal - } - f2sdram::add_sdc $use_fast_sim_model - fpga_interfaces::set_property IMPLEMENT_F2SDRAM_MEMORY_BACKED_SIM $use_fast_sim_model - - } - # write the registers out - f2sdram::render_registers registers $instance_name -} - -proc elab_clocks_resets {device_family} { - set instance_name clocks_resets - set atom_name hps_interface_clocks_resets - set location [locations::get_fpga_location $instance_name $atom_name] - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - - fpga_interfaces::add_interface h2f_reset reset Output - fpga_interfaces::add_interface_port h2f_reset h2f_rst_n reset_n Output 1 $instance_name - fpga_interfaces::set_interface_property h2f_reset synchronousEdges none - fpga_interfaces::set_interface_property h2f_reset associatedResetSinks none - - if [is_enabled S2FCLK_COLDRST_Enable] { - fpga_interfaces::add_interface h2f_cold_reset reset Output - fpga_interfaces::add_interface_port h2f_cold_reset h2f_cold_rst_n reset_n Output 1 $instance_name - fpga_interfaces::set_interface_property h2f_cold_reset synchronousEdges none - fpga_interfaces::set_interface_property h2f_cold_reset associatedResetSinks none - } - - if [is_enabled F2SCLK_COLDRST_Enable] { - fpga_interfaces::add_interface f2h_cold_reset_req reset Input - fpga_interfaces::add_interface_port f2h_cold_reset_req f2h_cold_rst_req_n reset_n Input 1 $instance_name - fpga_interfaces::set_interface_property f2h_cold_reset_req synchronousEdges none - fpga_interfaces::set_interface_property h2f_reset associatedResetSinks f2h_cold_reset_req - if [is_enabled S2FCLK_COLDRST_Enable] { - fpga_interfaces::set_interface_property h2f_cold_reset associatedResetSinks f2h_cold_reset_req - } - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_cold_rst_req_n" 1 1 0:0 1 - } - - if [is_enabled S2FCLK_PENDINGRST_Enable] { - fpga_interfaces::add_interface h2f_warm_reset_handshake conduit Output - fpga_interfaces::add_interface_port h2f_warm_reset_handshake h2f_pending_rst_req_n h2f_pending_rst_req_n Output 1 $instance_name - fpga_interfaces::add_interface_port h2f_warm_reset_handshake f2h_pending_rst_ack_n f2h_pending_rst_ack_n Input 1 $instance_name f2h_pending_rst_ack - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_pending_rst_ack" 1 1 0:0 1 - } - - if [is_enabled F2SCLK_DBGRST_Enable] { - fpga_interfaces::add_interface f2h_debug_reset_req reset Input - fpga_interfaces::add_interface_port f2h_debug_reset_req f2h_dbg_rst_req_n reset_n Input 1 $instance_name - fpga_interfaces::set_interface_property f2h_debug_reset_req synchronousEdges none - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_dbg_rst_req_n" 1 1 0:0 1 - } - - if [is_enabled F2SCLK_WARMRST_Enable] { - fpga_interfaces::add_interface f2h_warm_reset_req reset Input - fpga_interfaces::add_interface_port f2h_warm_reset_req f2h_warm_rst_req_n reset_n Input 1 $instance_name - fpga_interfaces::set_interface_property f2h_warm_reset_req synchronousEdges none - - if [is_enabled F2SCLK_COLDRST_Enable] { - fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req f2h_cold_reset_req} - } else { - fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req} - } - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_warm_rst_req_n" 1 1 0:0 1 - } - - if [is_enabled S2FCLK_USER0CLK_Enable] { - fpga_interfaces::add_interface h2f_user0_clock clock Output - fpga_interfaces::add_interface_port h2f_user0_clock h2f_user0_clk clk Output 1 $instance_name - set frequency [get_parameter_value S2FCLK_USER0CLK_FREQ] - set frequency [expr {$frequency * [MHZ_TO_HZ]}] - fpga_interfaces::set_interface_property h2f_user0_clock clockRateKnown true - fpga_interfaces::set_interface_property h2f_user0_clock clockRate $frequency - add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user0_clk" - } - - if [is_enabled S2FCLK_USER1CLK_Enable] { - fpga_interfaces::add_interface h2f_user1_clock clock Output - fpga_interfaces::add_interface_port h2f_user1_clock h2f_user1_clk clk Output 1 $instance_name - set frequency [get_parameter_value S2FCLK_USER1CLK_FREQ] - set frequency [expr {$frequency * [MHZ_TO_HZ]}] - fpga_interfaces::set_interface_property h2f_user1_clock clockRateKnown true - fpga_interfaces::set_interface_property h2f_user1_clock clockRate $frequency - add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user1_clk" - } - - set_parameter_property S2FCLK_USER2CLK enabled false - - if [is_enabled F2SCLK_PERIPHCLK_Enable] { - fpga_interfaces::add_interface f2h_periph_ref_clock clock Input - fpga_interfaces::add_interface_port f2h_periph_ref_clock f2h_periph_ref_clk clk Input 1 $instance_name - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_periph_ref_clk" 1 0 - } - - - if [is_enabled F2SCLK_SDRAMCLK_Enable] { - fpga_interfaces::add_interface f2h_sdram_ref_clock clock Input - fpga_interfaces::add_interface_port f2h_sdram_ref_clock f2h_sdram_ref_clk clk Input 1 $instance_name - } else { - fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_sdram_ref_clk" 1 0 - } -} - -# Elaborate peripheral request interfaces for the fpga and -# the clk/reset per pair -# TODO: Make sure the DMA RTL contains the wrapper -proc elab_DMA {device_family} { - set instance_name dma - set atom_name hps_interface_dma - set location [locations::get_fpga_location $instance_name $atom_name] - - set can_message 0 - set available_list [get_parameter_value DMA_Enable] - if {[llength $available_list] > 0} { - set dma_used 0 - set periph_id 0 - foreach entry $available_list { - if {[string compare $entry "Yes" ] == 0} { - elab_DMA_entry $periph_id $instance_name - set dma_used 1 - if {$periph_id >= 4} { - set can_message 1 - } - } - incr periph_id - } - if $dma_used { - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } - if $can_message { - send_message info "DMA Peripheral Request Interfaces 4-7 may be consumed by an HPS CAN Controller" - } - } -} - -proc elab_DMA_make_conduit_name {periph_id} { - return "f2h_dma_req${periph_id}" -} - -proc elab_DMA_entry {periph_id instance_name} { - set iname [elab_DMA_make_conduit_name $periph_id] - set atom_signal_prefix "channel${periph_id}" - fpga_interfaces::add_interface $iname conduit Output - fpga_interfaces::add_interface_port $iname "${iname}_req" "dma_req" Input 1 $instance_name ${atom_signal_prefix}_req - fpga_interfaces::add_interface_port $iname "${iname}_single" "dma_single" Input 1 $instance_name ${atom_signal_prefix}_single - fpga_interfaces::add_interface_port $iname "${iname}_ack" "dma_ack" Output 1 $instance_name ${atom_signal_prefix}_xx_ack -} - - -proc elab_emac_ptp {device_family} { - # added for case http://fogbugz.altera.com/default.asp?307450 - for {set i 0} {$i < 2} {incr i} { - set emac_fpga_enabled false - set emac_io_enabled false - - set emac_pin_mux_value [get_parameter_value EMAC${i}_PinMuxing] - set emac_ptp [get_parameter_value EMAC${i}_PTP] - - if {[string compare $emac_pin_mux_value [FPGA_MUX_VALUE]] == 0} { - set emac_fpga_enabled true - } - if {[string compare $emac_pin_mux_value "HPS I/O Set 0"] == 0} { - set emac_io_enabled true - } - - set_parameter_property EMAC${i}_PTP enabled $emac_io_enabled - - if {$emac_io_enabled && $emac_ptp } { - set instance_name peripheral_emac${i} - set atom_name hps_interface_peripheral_emac - set wys_atom_name arriav_hps_interface_peripheral_emac - set location [locations::get_fpga_location $instance_name $atom_name] - - set iface_name "emac${i}" - - fpga_interfaces::add_interface $iface_name conduit input - fpga_interfaces::add_interface_port $iface_name emac${i}_ptp_aux_ts_trig_i ptp_aux_ts_trig_i Input 1 $instance_name ptp_aux_ts_trig_i - fpga_interfaces::add_interface_port $iface_name emac${i}_ptp_pps_o ptp_pps_o Output 1 $instance_name ptp_pps_o - - - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } - - } -} - -proc elab_INTERRUPTS {device_family logical_view} { - set instance_name interrupts - set atom_name hps_interface_interrupts - set location [locations::get_fpga_location $instance_name $atom_name] - set any_interrupt_enabled 0 - - ##### F2H ##### - if [is_enabled F2SINTERRUPT_Enable] { - set any_interrupt_enabled 1 - set iname "f2h_irq" - set pname "f2h_irq" - if { $logical_view == 0 } { - fpga_interfaces::add_interface "${iname}0" interrupt receiver - fpga_interfaces::add_interface_port "${iname}0" "${pname}_p0" irq Input 32 - fpga_interfaces::set_port_fragments "${iname}0" "${pname}_p0" "${instance_name}:irq(31:0)" - - fpga_interfaces::add_interface "${iname}1" interrupt receiver - fpga_interfaces::add_interface_port "${iname}1" "${pname}_p1" irq Input 32 - fpga_interfaces::set_port_fragments "${iname}1" "${pname}_p1" "${instance_name}:irq(63:32)" - } - } - - ##### H2F ##### - load_h2f_interrupt_table\ - functions_by_group width_by_function inverted_by_function - - set interrupt_groups [list_h2f_interrupt_groups] - foreach group $interrupt_groups { - set parameter "S2FINTERRUPT_${group}_Enable" - set enabled [is_enabled $parameter] - - if {!$enabled} { - continue - } - set any_interrupt_enabled 1 - - foreach function $functions_by_group($group) { - set width 1 - if {[info exists width_by_function($function)]} { - set width $width_by_function($function) - } - - set suffix "" - set inverted [info exists inverted_by_function($function)] - if {$inverted} { - set suffix "_n" - } - - #skip fpga_interfaces interrupt declaration for uart - if { ($logical_view == 1) && ( - $function == "uart0" || - $function == "uart1" )} { - continue - } - - set prefix "h2f_${function}_" - set interface "${prefix}interrupt" - set port "${prefix}irq" - - if {$width > 1} { ;# for buses, use index in interface/port names - for {set i 0} {$i < $width} {incr i} { - set indexed_interface "${interface}${i}" - set indexed_port "${port}${i}${suffix}" - fpga_interfaces::add_interface\ - $indexed_interface interrupt sender - fpga_interfaces::add_interface_port\ - $indexed_interface $indexed_port irq Output 1\ - $instance_name $indexed_port - } - } else { - set port "$port${suffix}" - fpga_interfaces::add_interface\ - $interface interrupt sender - fpga_interfaces::add_interface_port\ - $interface $port irq Output 1 $instance_name $port - } - } - } - - if {$any_interrupt_enabled} { - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } -} - -proc elab_TEST {device_family} { - set parameter_enabled [expr {[string compare [get_parameter_value TEST_Enable] "true" ] == 0}] - set ini_enabled [expr {[string compare [get_parameter_value quartus_ini_hps_ip_enable_test_interface] "true" ] == 0}] - - if {$parameter_enabled && $ini_enabled} { - set instance_name test_interface - set atom_name hps_interface_test - set location [locations::get_fpga_location $instance_name $atom_name] - - set iname "test" - set z "test_" - - set data [get_parameter_value test_iface_definition] - - fpga_interfaces::add_interface $iname conduit input - foreach {port width dir} $data { - fpga_interfaces::add_interface_port $iname "${z}${port}" $port $dir $width $instance_name $port - } - - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } -} - -# TODO: Mode usage data -proc elab_FPGA_Peripheral_Signals {device_family} { - # disable and hide all parameters related to fpga outputs - set emac0_fpga [get_parameter_value quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface] - set lssis_fpga [get_parameter_value quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces] - set all_fpga "true" - - set peripherals [list_peripheral_names] - foreach peripheral $peripherals { - if { [string compare $peripheral "SDIO" ] == 0 } { - continue - } - set visible false - if {[string compare $all_fpga "true" ] == 0} { - set visible true - } elseif {[string compare $emac0_fpga "true" ] == 0 && [string compare -nocase $peripheral "emac0"] == 0} { - set visible true - } elseif {[string compare $lssis_fpga "true" ] == 0 && [is_peripheral_low_speed_serial_interface $peripheral_name]} { - set visible true - } - if {[string compare -nocase $peripheral "emac0" ] == 0 || [string compare -nocase $peripheral "emac1" ] == 0} { - set visible true - } - set clocks [get_peripheral_fpga_output_clocks $peripheral] - foreach clock $clocks { - set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock] - set_parameter_property $parameter enabled false - set_parameter_property $parameter visible $visible - set clock_output_set($clock) 1 - } - - set clocks [get_peripheral_fpga_input_clocks $peripheral] - foreach clock $clocks { - set clock_input_set($clock) 1 - } - } - - array set fpga_ifaces [get_parameter_value DB_periph_ifaces] - array set iface_ports [get_parameter_value DB_iface_ports] - array set port_pins [get_parameter_value DB_port_pins] - foreach peripheral_name $fpga_ifaces([ORDERED_NAMES]) { ;# Peripherals - set pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name] - set pin_mux_value [get_parameter_value $pin_mux_param_name] - set allowed_ranges [get_parameter_property $pin_mux_param_name allowed_ranges] - - if {[string compare $pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $allowed_ranges [FPGA_MUX_VALUE]] != -1} { - funset peripheral - array set peripheral $fpga_ifaces($peripheral_name) - funset interfaces - array set interfaces $peripheral(interfaces) - - set instance_name [invent_peripheral_instance_name $peripheral_name] - - foreach interface_name $interfaces([ORDERED_NAMES]) { ;# Interfaces - funset interface - array set interface $interfaces($interface_name) - fpga_interfaces::add_interface $interface_name $interface(type) $interface(direction) - foreach {property_key property_value} $interface(properties) { - fpga_interfaces::set_interface_property $interface_name $property_key $property_value - } - #send_message info "NEA: peripheral_name $peripheral_name interface_name $interface_name " - - if { [string match "EMAC?" $peripheral_name] && [string match "*x_reset" $interface_name ] } { - fpga_interfaces::set_interface_property $interface_name associatedResetSinks none - } - - foreach {meta_property} [array names interface] { - # Meta Property if leading with an @ - if {[string compare [string index ${meta_property} 0] "@"] == 0} { - fpga_interfaces::set_interface_meta_property $interface_name [string replace ${meta_property} 0 0] $interface($meta_property) - } - } - - set once_per_clock 1 - funset ports - array set ports $iface_ports($interface_name) - foreach port_name $ports([ORDERED_NAMES]) { ;# Ports - funset port - array set port $ports($port_name) - - # TODO: determine width based on pins available via mode - set width [calculate_port_width $port_pins($port_name)] - - fpga_interfaces::add_interface_port $interface_name $port_name $port(role) $port(direction) $width $instance_name $port(atom_signal_name) - - set frequency 0 - # enable and show clock frequency parameters for outputs - if {[info exists clock_output_set($interface_name)]} { - set parameter [form_peripheral_fpga_output_clock_frequency_parameter $interface_name] - set_parameter_property $parameter enabled true - set frequency [get_parameter_value $parameter] - set frequency [expr {$frequency * [MHZ_TO_HZ]}] - fpga_interfaces::set_interface_property $interface_name clockRateKnown true - fpga_interfaces::set_interface_property $interface_name clockRate $frequency - } - - if {[string compare -nocase $interface(type) "clock"] == 0 && $once_per_clock} { - set once_per_clock 0 - add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|[string tolower $port(atom_signal_name)]" - } - } - } - - # device-specific atom - set atom_name $peripheral(atom_name) - set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] - set location [locations::get_fpga_location $peripheral_name $atom_name] - - fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location - } - } -} - -# derives the WYS (device family-specific) atom name from the generic one -proc generic_atom_to_wys_atom {device_family atom_name} { - # TODO: base this on a table of data instead of on code - set result "" - if {[check_device_family_equivalence $device_family CYCLONEV]} { - set result "cyclonev_${atom_name}" - } elseif {[check_device_family_equivalence $device_family ARRIAV]} { - set result "arriav_${atom_name}" - } - return $result -} - -# invents an instance name from the peripheral's name -# assumes that the instance name is the same across a peripheral -proc invent_peripheral_instance_name {peripheral_name} { - return "peripheral_[string tolower $peripheral_name]" -} - -# TODO: do width calculation at db load time so we don't do it every elaboration! -# then make it accessible by a mode to width array for every peripheral with fpga periph interface -# TODO: also validate the static data, checking if the mode signals make sense aka only contiguous, 0-indexed mappings -proc calculate_port_width {pin_array_string} { - array set pins $pin_array_string - # TODO: -do we need to be able to support ports that don't start with pins at 0? - # -e.g. pins D0-D7 are indexed 0-7. if want D4-D7, can we do indexes 4-7? - # -for now, no! - set bit_index 0 - while {[info exists pins($bit_index)]} { - incr bit_index - } - return $bit_index -} - -proc pin_to_bank {pin} { - set io_index [string first "IO" $pin] - return [string range $pin 0 [expr {$io_index - 1}]] -} - -proc sort_pins {pins} { - set pin_suffixes [list] - foreach pin $pins { - set io_index [string first "IO" $pin] - set suffix_start [expr {$io_index + 2}] - set length [string length $pin] - set suffix [string range $pin $suffix_start [expr {$length - 1}]] - lappend pin_suffixes $suffix - } - set result [list] - set indices [lsort-indices -increasing -integer $pin_suffixes] - foreach index $indices { - lappend result [lindex $pins $index] - } - return $result -} - -proc set_peripheral_pin_muxing_description {peripheral_name pin_muxing_description mode_description} { - set parameter "[string toupper $peripheral_name]_PinMuxing" - set_display_item_property $parameter DESCRIPTION $pin_muxing_description - - set parameter "[string toupper $peripheral_name]_Mode" - set_display_item_property $parameter DESCRIPTION $mode_description -} - -# Expects same set of keys between both parameters -proc create_pin_muxing_description_table_html {signals_by_option_str pins_by_option_str} { - array set pins_by_option $pins_by_option_str - - set options [list] - foreach {option signals} $signals_by_option_str { - lappend options $option - - set pins $pins_by_option($option) - - foreach signal $signals pin $pins { - set key "${option}.${signal}" - set pins_by_option_and_signal($key) $pin - set signal_set($signal) 1 - } - } - - set sorted_signals [lsort -increasing -ascii [array names signal_set]] - set sorted_options [lsort -increasing -ascii $options] - - set ALIGN_CENTER {align="center"} - - set html "" ;# start of table, first row cell empty for signal column - foreach option $sorted_options { - set html "${html}" - } - set html "${html}" - foreach signal $sorted_signals { - set html "${html}" ;# new row w/ first cell (header) being the signal name - foreach option $sorted_options { - set key "${option}.${signal}" - if {[info exists pins_by_option_and_signal($key)]} { - set pin $pins_by_option_and_signal($key) - } else { - set pin "" - } - set html "${html}" - } - set html "${html}" - } - set html "${html}
${option}
${signal}${pin}
" - return $html -} - -proc create_mode_description_table_html {signals_by_mode_str} { - set modes [list] - - foreach {mode signals} $signals_by_mode_str { - lappend modes $mode - foreach signal $signals { - set key "${mode}.${signal}" - set membership_by_mode_and_signal($key) 1 - set signal_set($signal) 1 - } - } - - set sorted_signals [lsort -increasing -ascii [array names signal_set]] - set sorted_modes [lsort -increasing -ascii $modes] - - set ALIGN_CENTER {align="center"} - - set html "" ;# start of table, first row cell empty for signal column - foreach mode $sorted_modes { - set html "${html}" - } - set html "${html}" - foreach signal $sorted_signals { - set html "${html}" ;# new row w/ first cell (header) being the signal name - - foreach mode $sorted_modes { - set key "${mode}.${signal}" - if {[info exists membership_by_mode_and_signal($key)]} { - set member_marker "X" - } else { - set member_marker "" - } - set html "${html}" - } - set html "${html}" - } - set html "${html}
${mode}
${signal}${member_marker}
" - return $html -} - -proc get_quartus_edition {} { - set code { - set version "" - regexp {([a-zA-Z]+) (Edition|Version)$} $quartus(version) total version - return $version - } - set safe_code [string map {\n ; \t ""} $code] - set package_name "advanced_device" - set result [lindex [run_quartus_tcl_command "${package_name}:${safe_code}"] 0] - return $result -} - -proc is_soc_device {device} { - return [::pin_mux_db::verify_soc_device $device] -} - -proc set_peripheral_pin_muxing_descriptions {peripherals_ref} { - upvar 1 $peripherals_ref peripherals - - foreach peripheral_name [array names peripherals] { - set signals_by_option [list] - set pins_by_option [list] - - funset peripheral - array set peripheral $peripherals($peripheral_name) - funset pin_sets - array set pin_sets $peripheral(pin_sets) - - foreach pin_set_name [array names pin_sets] { - funset pin_set - array set pin_set $pin_sets($pin_set_name) - set signals $pin_set(signals) - lappend signals_by_option $pin_set_name $signals - set pins $pin_set(pins) - lappend pins_by_option $pin_set_name $pins - } - set signals_by_mode $peripheral(signals_by_mode) - - set table_html [create_pin_muxing_description_table_html $signals_by_option $pins_by_option] - set pin_muxing_description "" - - set table_html [create_mode_description_table_html $signals_by_mode] - set mode_description "Signal Membership Per Mode Usage Option:
${table_html}" - set_peripheral_pin_muxing_description $peripheral_name $pin_muxing_description $mode_description - } -} - -# Add pin muxing details to soc_io peripheral/signal data -add_storage_parameter pin_muxing {} -add_storage_parameter pin_muxing_check "" -proc ensure_pin_muxing_data {device_family} { - if {[check_device_family_equivalence $device_family [get_module_property SUPPORTED_DEVICE_FAMILIES]] == 0} { - return - } - - set device [get_device] - - if {![is_soc_device $device]} { - send_message error "Selected device '${device}' is not an SoC device. Please choose a valid SoC device to use the Hard Processor System." - return - } - - set device_configuration "${device_family}+${device}" - - set old_device_configuration [get_parameter_value pin_muxing_check] - if {$old_device_configuration == $device_configuration} { - return - } - - set load_rc [::pin_mux_db::load $device] - if {!$load_rc} { - send_message error "The pin information for the Hard Processor System could not be determined. Please check whether your edition of Quartus Prime supports the selected device." - return - } - locations::load $device - - load_peripherals_pin_muxing_model pin_muxing_peripherals - set_peripheral_pin_muxing_descriptions pin_muxing_peripherals - - set gpio_pins [::pin_mux_db::get_gpio_pins] - set loanio_pins [::pin_mux_db::get_loan_io_pins] - set customer_pin_names [::pin_mux_db::get_customer_pin_names] - set hlgpi_pins [::pin_mux_db::get_hlgpi_pins] - - set pin_muxing [list [array get pin_muxing_peripherals] $gpio_pins $loanio_pins $customer_pin_names $hlgpi_pins] - set_parameter_value pin_muxing $pin_muxing - set_parameter_value pin_muxing_check $device_configuration - - #### update pin_muxing data to use in java GUI #### - set pinmux_peripherals [array get pin_muxing_peripherals] - array set periph_key_value $pinmux_peripherals - - foreach {key value} [array get periph_key_value] { - set_parameter_value JAVA_${key}_DATA "$key \{$value\}" - } -} - -proc get_device {} { - - set device_name [get_parameter_value device_name] - return $device_name -} - -proc construct_hps_parameter_map {} { - set parameters [get_parameters] - foreach parameter $parameters { - set value [get_parameter_value $parameter] - set result($parameter) $value - } - return [array get result] -} - -################################################################################ -# Implements interface of util/pin_mux.tcl -# -namespace eval hps_ip_pin_muxing_model { -################################################################################ - proc get_peripherals_model {} { - set pin_muxing [get_parameter_value pin_muxing] - set peripherals [lindex $pin_muxing 0] - return $peripherals - } - proc get_emac0_fpga_ini {} { - return [is_enabled quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface] - } - proc get_lssis_fpga_ini {} { - return [is_enabled quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces] - } - proc get_all_fpga_ini {} { - return [is_enabled quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces] - } - proc get_peripheral_pin_muxing_selection {peripheral_name} { - set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name] - set selection [get_parameter_value $pin_muxing_param_name] - return $selection - } - proc get_peripheral_mode_selection {peripheral_name} { - set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral_name] - set selection [get_parameter_value $mode_param_name] - return $selection - } - proc get_gpio_pins {} { - set pin_muxing [get_parameter_value pin_muxing] - set pins [lindex $pin_muxing 1] - return $pins - } - proc get_loanio_pins {} { - set pin_muxing [get_parameter_value pin_muxing] - set pins [lindex $pin_muxing 2] - return $pins - } - proc get_customer_pin_names {} { - set pin_muxing [get_parameter_value pin_muxing] - set pins [lindex $pin_muxing 3] - return $pins - } - proc get_hlgpi_pins {} { - set pin_muxing [get_parameter_value pin_muxing] - set pins [lindex $pin_muxing 4] - return $pins - } - proc get_unsupported_peripheral {peripheral_name} { - set device_family [get_parameter_value hps_device_family] - set skip 0 - if {[check_device_family_equivalence $device_family ARRIAV]} { - foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] { - if {[string compare $excluded_peripheral $peripheral_name] == 0} { - set skip 1 - } - } - } - return $skip - } -} - - -## Add documentation links for user guide and/or release notes -add_documentation_link "User Guide" https://www.altera.com/products/soc/overview.html diff --git a/sys/ip/in_split.v b/sys/ip/in_split.v deleted file mode 100644 index e750ff9..0000000 --- a/sys/ip/in_split.v +++ /dev/null @@ -1,52 +0,0 @@ -// in_split.v - - -`timescale 1 ps / 1 ps -module in_split ( - input wire clk, // input.clk - input wire ce, // .ce - input wire de, // .de - input wire h_sync, // .h_sync - input wire v_sync, // .v_sync - input wire f, // .f - input wire [23:0] data, // .data - output wire vid_clk, // Output.vid_clk - output reg vid_datavalid, // .vid_datavalid - output reg [1:0] vid_de, // .vid_de - output reg [1:0] vid_f, // .vid_f - output reg [1:0] vid_h_sync, // .vid_h_sync - output reg [1:0] vid_v_sync, // .vid_v_sync - output reg [47:0] vid_data, // .vid_data - output wire vid_locked, // .vid_locked - output wire [7:0] vid_color_encoding, // .vid_color_encoding - output wire [7:0] vid_bit_width, // .vid_bit_width - input wire clipping, // .clipping - input wire overflow, // .overflow - input wire sof, // .sof - input wire sof_locked, // .sof_locked - input wire refclk_div, // .refclk_div - input wire padding // .padding - ); - - assign vid_bit_width = 0; - assign vid_color_encoding = 0; - assign vid_locked = 1; - assign vid_clk = clk; - - always @(posedge clk) begin - reg odd = 0; - - vid_datavalid <= 0; - if(ce) begin - vid_de[odd] <= de; - vid_f[odd] <= f; - vid_h_sync[odd] <= h_sync; - vid_v_sync[odd] <= v_sync; - if(odd) vid_data[47:24] <= data; - else vid_data[23:0] <= data; - - odd <= ~odd; - vid_datavalid <= odd; - end - end -endmodule diff --git a/sys/ip/in_split_hw.tcl b/sys/ip/in_split_hw.tcl deleted file mode 100644 index 403555a..0000000 --- a/sys/ip/in_split_hw.tcl +++ /dev/null @@ -1,104 +0,0 @@ -# TCL File Generated by Component Editor 17.0 -# Thu Jan 25 18:50:29 CST 2018 -# DO NOT MODIFY - - -# -# in_split "Input Splitter" v17.0 -# Sorgelig 2018.01.25.18:50:29 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module in_split -# -set_module_property DESCRIPTION "" -set_module_property NAME in_split -set_module_property VERSION 17.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR Sorgelig -set_module_property DISPLAY_NAME "Input Splitter" -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true -add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point input -# -add_interface input conduit end -set_interface_property input associatedClock "" -set_interface_property input associatedReset "" -set_interface_property input ENABLED true -set_interface_property input EXPORT_OF "" -set_interface_property input PORT_NAME_MAP "" -set_interface_property input CMSIS_SVD_VARIABLES "" -set_interface_property input SVD_ADDRESS_GROUP "" - -add_interface_port input clk clk Input 1 -add_interface_port input ce ce Input 1 -add_interface_port input de de Input 1 -add_interface_port input h_sync h_sync Input 1 -add_interface_port input v_sync v_sync Input 1 -add_interface_port input f f Input 1 -add_interface_port input data data Input 24 - - -# -# connection point Output -# -add_interface Output conduit end -set_interface_property Output associatedClock "" -set_interface_property Output associatedReset "" -set_interface_property Output ENABLED true -set_interface_property Output EXPORT_OF "" -set_interface_property Output PORT_NAME_MAP "" -set_interface_property Output CMSIS_SVD_VARIABLES "" -set_interface_property Output SVD_ADDRESS_GROUP "" - -add_interface_port Output vid_clk vid_clk Output 1 -add_interface_port Output vid_datavalid vid_datavalid Output 1 -add_interface_port Output vid_de vid_de Output 2 -add_interface_port Output vid_f vid_f Output 2 -add_interface_port Output vid_h_sync vid_h_sync Output 2 -add_interface_port Output vid_v_sync vid_v_sync Output 2 -add_interface_port Output vid_data vid_data Output 48 -add_interface_port Output vid_locked vid_locked Output 1 -add_interface_port Output vid_color_encoding vid_color_encoding Output 8 -add_interface_port Output vid_bit_width vid_bit_width Output 8 -add_interface_port Output clipping clipping Input 1 -add_interface_port Output overflow overflow Input 1 -add_interface_port Output sof sof Input 1 -add_interface_port Output sof_locked sof_locked Input 1 -add_interface_port Output refclk_div refclk_div Input 1 -add_interface_port Output padding padding Input 1 - diff --git a/sys/ip/out_mix.v b/sys/ip/out_mix.v deleted file mode 100644 index e135b1c..0000000 --- a/sys/ip/out_mix.v +++ /dev/null @@ -1,44 +0,0 @@ -// out_mix.v - -`timescale 1 ps / 1 ps -module out_mix ( - input wire clk, // Output.clk - output reg de, // .de - output reg h_sync, // .h_sync - output reg v_sync, // .v_sync - output reg [23:0] data, // .data - output reg vid_clk, // input.vid_clk - input wire [1:0] vid_datavalid, // .vid_datavalid - input wire [1:0] vid_h_sync, // .vid_h_sync - input wire [1:0] vid_v_sync, // .vid_v_sync - input wire [47:0] vid_data, // .vid_data - input wire underflow, // .underflow - input wire vid_mode_change, // .vid_mode_change - input wire [1:0] vid_std, // .vid_std - input wire [1:0] vid_f, // .vid_f - input wire [1:0] vid_h, // .vid_h - input wire [1:0] vid_v // .vid_v - ); - - reg r_de; - reg r_h_sync; - reg r_v_sync; - reg [23:0] r_data; - - always @(posedge clk) begin - vid_clk <= ~vid_clk; - - if(~vid_clk) begin - {r_de,de} <= vid_datavalid; - {r_h_sync, h_sync} <= vid_h_sync; - {r_v_sync, v_sync} <= vid_v_sync; - {r_data, data} <= vid_data; - end else begin - de <= r_de; - h_sync <= r_h_sync; - v_sync <= r_v_sync; - data <= r_data; - end - end - -endmodule diff --git a/sys/ip/out_mix_hw.tcl b/sys/ip/out_mix_hw.tcl deleted file mode 100644 index b388891..0000000 --- a/sys/ip/out_mix_hw.tcl +++ /dev/null @@ -1,97 +0,0 @@ -# TCL File Generated by Component Editor 17.0 -# Thu Jan 25 06:51:26 CST 2018 -# DO NOT MODIFY - - -# -# out_mix "Output Mixer" v1.0 -# Sorgelig 2018.01.25.06:51:26 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module out_mix -# -set_module_property DESCRIPTION "" -set_module_property NAME out_mix -set_module_property VERSION 17.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR Sorgelig -set_module_property DISPLAY_NAME "Output Mixer" -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true -add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point Output -# -add_interface Output conduit end -set_interface_property Output associatedClock "" -set_interface_property Output associatedReset "" -set_interface_property Output ENABLED true -set_interface_property Output EXPORT_OF "" -set_interface_property Output PORT_NAME_MAP "" -set_interface_property Output CMSIS_SVD_VARIABLES "" -set_interface_property Output SVD_ADDRESS_GROUP "" - -add_interface_port Output clk clk Input 1 -add_interface_port Output de de Output 1 -add_interface_port Output h_sync h_sync Output 1 -add_interface_port Output v_sync v_sync Output 1 -add_interface_port Output data data Output 24 - - -# -# connection point input -# -add_interface input conduit end -set_interface_property input associatedClock "" -set_interface_property input associatedReset "" -set_interface_property input ENABLED true -set_interface_property input EXPORT_OF "" -set_interface_property input PORT_NAME_MAP "" -set_interface_property input CMSIS_SVD_VARIABLES "" -set_interface_property input SVD_ADDRESS_GROUP "" - -add_interface_port input vid_clk vid_clk Output 1 -add_interface_port input vid_datavalid vid_datavalid Input 2 -add_interface_port input vid_h_sync vid_h_sync Input 2 -add_interface_port input vid_v_sync vid_v_sync Input 2 -add_interface_port input vid_data vid_data Input 48 -add_interface_port input underflow underflow Input 1 -add_interface_port input vid_mode_change vid_mode_change Input 1 -add_interface_port input vid_std vid_std Input 2 -add_interface_port input vid_f vid_f Input 2 -add_interface_port input vid_h vid_h Input 2 -add_interface_port input vid_v vid_v Input 2 - diff --git a/sys/ip/reset_source.v b/sys/ip/reset_source.v deleted file mode 100644 index 1b81394..0000000 --- a/sys/ip/reset_source.v +++ /dev/null @@ -1,50 +0,0 @@ -// reset_source.v - -// This file was auto-generated as a prototype implementation of a module -// created in component editor. It ties off all outputs to ground and -// ignores all inputs. It needs to be edited to make it do something -// useful. -// -// This file will not be automatically regenerated. You should check it in -// to your version control system if you want to keep it. - -`timescale 1 ps / 1 ps -module reset_source -( - input wire clk, // clock.clk - input wire reset_hps, // reset_hps.reset - output wire reset_sys, // reset_sys.reset - output wire reset_cold, // reset_cold.reset - input wire cold_req, // reset_ctl.cold_req - output wire reset, // .reset - input wire reset_req, // .reset_req - input wire reset_vip, // .reset_vip - input wire warm_req, // .warm_req - output wire reset_warm // reset_warm.reset -); - -assign reset_cold = cold_req; -assign reset_warm = warm_req; - -wire reset_m = sys_reset | reset_hps | reset_req; -assign reset = reset_m; -assign reset_sys = reset_m | reset_vip; - -reg sys_reset = 1; -always @(posedge clk) begin - integer timeout = 0; - reg reset_lock = 0; - - reset_lock <= reset_lock | cold_req; - - if(timeout < 2000000) begin - sys_reset <= 1; - timeout <= timeout + 1; - reset_lock <= 0; - end - else begin - sys_reset <= reset_lock; - end -end - -endmodule diff --git a/sys/ip/reset_source_hw.tcl b/sys/ip/reset_source_hw.tcl deleted file mode 100644 index cba39f7..0000000 --- a/sys/ip/reset_source_hw.tcl +++ /dev/null @@ -1,152 +0,0 @@ -# TCL File Generated by Component Editor 17.0 -# Tue Feb 20 07:55:55 CST 2018 -# DO NOT MODIFY - - -# -# reset_source "reset_source" v17.0 -# Sorgelig 2018.02.20.07:55:55 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module reset_source -# -set_module_property DESCRIPTION "" -set_module_property NAME reset_source -set_module_property VERSION 17.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR Sorgelig -set_module_property DISPLAY_NAME reset_source -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true -add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clk clk Input 1 - - -# -# connection point reset_hps -# -add_interface reset_hps reset end -set_interface_property reset_hps associatedClock "" -set_interface_property reset_hps synchronousEdges NONE -set_interface_property reset_hps ENABLED true -set_interface_property reset_hps EXPORT_OF "" -set_interface_property reset_hps PORT_NAME_MAP "" -set_interface_property reset_hps CMSIS_SVD_VARIABLES "" -set_interface_property reset_hps SVD_ADDRESS_GROUP "" - -add_interface_port reset_hps reset_hps reset Input 1 - - -# -# connection point reset_sys -# -add_interface reset_sys reset start -set_interface_property reset_sys associatedClock "" -set_interface_property reset_sys associatedDirectReset "" -set_interface_property reset_sys associatedResetSinks "" -set_interface_property reset_sys synchronousEdges NONE -set_interface_property reset_sys ENABLED true -set_interface_property reset_sys EXPORT_OF "" -set_interface_property reset_sys PORT_NAME_MAP "" -set_interface_property reset_sys CMSIS_SVD_VARIABLES "" -set_interface_property reset_sys SVD_ADDRESS_GROUP "" - -add_interface_port reset_sys reset_sys reset Output 1 - - -# -# connection point reset_ctl -# -add_interface reset_ctl conduit end -set_interface_property reset_ctl associatedClock "" -set_interface_property reset_ctl associatedReset "" -set_interface_property reset_ctl ENABLED true -set_interface_property reset_ctl EXPORT_OF "" -set_interface_property reset_ctl PORT_NAME_MAP "" -set_interface_property reset_ctl CMSIS_SVD_VARIABLES "" -set_interface_property reset_ctl SVD_ADDRESS_GROUP "" - -add_interface_port reset_ctl cold_req cold_req Input 1 -add_interface_port reset_ctl reset reset Output 1 -add_interface_port reset_ctl reset_req reset_req Input 1 -add_interface_port reset_ctl warm_req warm_req Input 1 -add_interface_port reset_ctl reset_vip reset_vip Input 1 - - -# -# connection point reset_warm -# -add_interface reset_warm reset start -set_interface_property reset_warm associatedClock "" -set_interface_property reset_warm associatedDirectReset "" -set_interface_property reset_warm associatedResetSinks "" -set_interface_property reset_warm synchronousEdges NONE -set_interface_property reset_warm ENABLED true -set_interface_property reset_warm EXPORT_OF "" -set_interface_property reset_warm PORT_NAME_MAP "" -set_interface_property reset_warm CMSIS_SVD_VARIABLES "" -set_interface_property reset_warm SVD_ADDRESS_GROUP "" - -add_interface_port reset_warm reset_warm reset Output 1 - - -# -# connection point reset_cold -# -add_interface reset_cold reset start -set_interface_property reset_cold associatedClock "" -set_interface_property reset_cold associatedDirectReset "" -set_interface_property reset_cold associatedResetSinks "" -set_interface_property reset_cold synchronousEdges NONE -set_interface_property reset_cold ENABLED true -set_interface_property reset_cold EXPORT_OF "" -set_interface_property reset_cold PORT_NAME_MAP "" -set_interface_property reset_cold CMSIS_SVD_VARIABLES "" -set_interface_property reset_cold SVD_ADDRESS_GROUP "" - -add_interface_port reset_cold reset_cold reset Output 1 - diff --git a/sys/lpf48k.sv b/sys/lpf48k.sv deleted file mode 100644 index 2a32981..0000000 --- a/sys/lpf48k.sv +++ /dev/null @@ -1,100 +0,0 @@ -// low pass filter -// Revision 1.00 -// -// Copyright (c) 2008 Takayuki Hara. -// All rights reserved. -// -// Redistribution and use of this source code or any derivative works, are -// permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// 3. Redistributions may not be sold, nor may they be used in a commercial -// product or activity without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// -// LPF (cut off 48kHz at 3.58MHz) - -module lpf48k #(parameter MSB = 15) -( - input RESET, - input CLK, - input CE, - input ENABLE, - - input [MSB:0] IDATA, - output [MSB:0] ODATA -); - -wire [7:0] LPF_TAP_DATA[0:71] = -'{ - 8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09, - 8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B, - 8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D, - 8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, - 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, - 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D, - 8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B, - 8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09, - 8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51 -}; - -reg [7:0] FF_ADDR = 0; -reg [MSB+10:0] FF_INTEG = 0; -wire [MSB+8:0] W_DATA; -wire W_ADDR_END; - -assign W_ADDR_END = ((FF_ADDR == 71)); - -reg [MSB:0] OUT; - -assign ODATA = ENABLE ? OUT : IDATA; - -always @(posedge RESET or posedge CLK) begin - if (RESET) FF_ADDR <= 0; - else - begin - if (CE) begin - if (W_ADDR_END) FF_ADDR <= 0; - else FF_ADDR <= FF_ADDR + 1'd1; - end - end -end - -assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA; - -always @(posedge RESET or posedge CLK) begin - if (RESET) FF_INTEG <= 0; - else - begin - if (CE) begin - if (W_ADDR_END) FF_INTEG <= 0; - else FF_INTEG <= FF_INTEG + W_DATA; - end - end -end - -always @(posedge RESET or posedge CLK) begin - if (RESET) OUT <= 0; - else - begin - if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10]; - end -end - -endmodule diff --git a/sys/ltc2308.sv b/sys/ltc2308.sv new file mode 100644 index 0000000..33134fd --- /dev/null +++ b/sys/ltc2308.sv @@ -0,0 +1,162 @@ +//============================================================================ +// +// LTC2308 controller +// Copyright (C) 2019 Sorgelig +// +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + + +// NUM_CH 1..8 +// Sampling rate = ADC_RATE/NUM_CH +// ADC_RATE max is ~500KHz +// CLK_RATE max is ~80MHz +module ltc2308 #(parameter NUM_CH = 2, ADC_RATE = 96000, CLK_RATE = 50000000) +( + input reset, + input clk, + + inout [3:0] ADC_BUS, + + output reg dout_sync, // toggle with every ADC round + output reg [(NUM_CH*12)-1:0] dout // 12 bits per channel (unsigned) +); + +localparam TCONV = CLK_RATE/625000; + +reg sck; +wire sdo = cfg[5]; + +assign ADC_BUS[3] = sck; +wire sdi = ADC_BUS[2]; +assign ADC_BUS[1] = sdo; +assign ADC_BUS[0] = convst; + +reg convst; +reg [5:0] cfg; + +reg [31:0] sum; +wire [31:0] next_sum = sum + ADC_RATE; + +reg [2:0] pin; +wire [2:0] next_pin = (pin == (NUM_CH-1)) ? 3'd0 : (pin + 1'd1); + +always @(posedge clk) begin + reg [7:0] tconv; + reg [3:0] bitcnt; + reg [10:0] adcin; + + convst <= 0; + + if(reset) begin + sum <= 0; + tconv <= 0; + bitcnt <= 0; + sck <= 0; + cfg <= 0; + dout <= 0; + pin <= NUM_CH[2:0]-1'd1; + end + else begin + sum <= next_sum; + if(next_sum >= CLK_RATE) begin + sum <= next_sum - CLK_RATE; + tconv <= TCONV[7:0]; + convst <= 1; + bitcnt <= 12; + cfg <= {1'b1, next_pin[0], next_pin[2:1], 1'b1, 1'b0}; + if(!next_pin) dout_sync <= ~dout_sync; + end + + if(tconv) tconv <= tconv - 1'd1; + else if(bitcnt) begin + sck <= ~sck; + + if(sck) cfg <= cfg<<1; + else begin + adcin <= {adcin[9:0],sdi}; + bitcnt <= bitcnt - 1'd1; + if(bitcnt == 1) begin + dout[pin*12 +:12] <= {adcin,sdi}; + pin <= next_pin; + end + end + end + else sck <= 0; + end +end + +endmodule + +module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000) +( + input reset, + input clk, + + inout [3:0] ADC_BUS, + output reg dout, + output active +); + +wire [11:0] adc_data; +wire adc_sync; +ltc2308 #(1, ADC_RATE, CLK_RATE) adc +( + .reset(reset), + .clk(clk), + + .ADC_BUS(ADC_BUS), + .dout(adc_data), + .dout_sync(adc_sync) +); + +always @(posedge clk) begin + reg [13:0] data1,data2,data3,data4, sum; + reg adc_sync_d; + + adc_sync_d<=adc_sync; + if(adc_sync_d ^ adc_sync) begin + data1 <= data2; + data2 <= data3; + data3 <= data4; + data4 <= adc_data; + + sum <= data1+data2+data3+data4; + + if(sum[13:2]HIST_HIGH) dout <= 1; + end +end + +assign active = |act; + +reg [1:0] act; +always @(posedge clk) begin + reg [31:0] onesec; + reg old_dout; + + onesec <= onesec + 1; + if(onesec>CLK_RATE) begin + onesec <= 0; + if(act) act <= act - 1'd1; + end + + old_dout <= dout; + if(old_dout ^ dout) act <= 2; +end + +endmodule diff --git a/sys/math.sv b/sys/math.sv new file mode 100644 index 0000000..1cf327f --- /dev/null +++ b/sys/math.sv @@ -0,0 +1,109 @@ + +// result = num/div +module sys_udiv +#( + parameter NB_NUM, + parameter NB_DIV +) +( + input clk, + input start, + output busy, + + input [NB_NUM-1:0] num, + input [NB_DIV-1:0] div, + output reg [NB_NUM-1:0] result, + output reg [NB_DIV-1:0] remainder +); + +reg run; +assign busy = run; + +always @(posedge clk) begin + reg [5:0] cpt; + reg [NB_NUM+NB_DIV+1:0] rem; + + if (start) begin + cpt <= 0; + run <= 1; + rem <= num; + end + else if (run) begin + cpt <= cpt + 1'd1; + run <= (cpt != NB_NUM + 1'd1); + remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1]; + if (!rem[NB_DIV + NB_NUM + 1'd1]) + rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0}; + else + rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0}; + result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]}; + end +end + +endmodule + +// result = mul1*mul2 +module sys_umul +#( + parameter NB_MUL1, + parameter NB_MUL2 +) +( + input clk, + input start, + output busy, + + input [NB_MUL1-1:0] mul1, + input [NB_MUL2-1:0] mul2, + output reg [NB_MUL1+NB_MUL2-1:0] result +); + +reg run; +assign busy = run; + +always @(posedge clk) begin + reg [NB_MUL1+NB_MUL2-1:0] add; + reg [NB_MUL2-1:0] map; + + if (start) begin + run <= 1; + result <= 0; + add <= mul1; + map <= mul2; + end + else if (run) begin + if(!map) run <= 0; + if(map[0]) result <= result + add; + add <= add << 1; + map <= map >> 1; + end +end + +endmodule + +// result = (mul1*mul2)/div +module sys_umuldiv +#( + parameter NB_MUL1, + parameter NB_MUL2, + parameter NB_DIV +) +( + input clk, + input start, + output busy, + + input [NB_MUL1-1:0] mul1, + input [NB_MUL2-1:0] mul2, + input [NB_DIV-1:0] div, + output [NB_MUL1+NB_MUL2-1:0] result, + output [NB_DIV-1:0] remainder +); + +wire mul_run; +wire [NB_MUL1+NB_MUL2-1:0] mul_res; +sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res); + +sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder); + +endmodule diff --git a/sys/mcp23009.sv b/sys/mcp23009.sv new file mode 100644 index 0000000..40cbf5e --- /dev/null +++ b/sys/mcp23009.sv @@ -0,0 +1,113 @@ +// +// MCP23009 +// (C) 2019 Alexey Melnikov +// +module mcp23009 +( + input clk, + + output reg [2:0] btn, + input [2:0] led, + output reg sd_cd, + + output scl, + inout sda +); + + +reg start = 0; +wire ready; +wire error; +reg rw; +wire [7:0] dout; +reg [15:0] din; + +i2c #(50_000_000, 500_000) i2c +( + .CLK(clk), + .START(start), + .READ(rw), + .I2C_ADDR('h20), + .I2C_WLEN(1), + .I2C_WDATA1(din[15:8]), + .I2C_WDATA2(din[7:0]), + .I2C_RDATA(dout), + .END(ready), + .ACK(error), + .I2C_SCL(scl), + .I2C_SDA(sda) +); + +always@(posedge clk) begin + reg [3:0] idx = 0; + reg [1:0] state = 0; + reg [15:0] timeout = 0; + + if(~&timeout) begin + timeout <= timeout + 1'd1; + start <= 0; + state <= 0; + idx <= 0; + btn <= 0; + rw <= 0; + sd_cd <= 1; + end + else begin + if(~&init_data[idx]) begin + case(state) + 0: begin + start <= 1; + state <= 1; + din <= init_data[idx]; + end + 1: if(~ready) state <= 2; + 2: begin + start <= 0; + if(ready) begin + state <= 0; + if(!error) idx <= idx + 1'd1; + end + end + endcase + end + else begin + case(state) + 0: begin + start <= 1; + state <= 1; + din <= {8'h09,5'b00000,led}; + end + 1: if(~ready) state <= 2; + 2: begin + start <= 0; + if(ready) begin + state <= 0; + rw <= 0; + if(!error) begin + if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]}; + rw <= ~rw; + end + end + end + endcase + end + end +end + +wire [15:0] init_data[12] = +'{ + 16'h00F8, + 16'h0138, + 16'h0200, + 16'h0300, + 16'h0400, + 16'h0524, + 16'h06FF, + 16'h0700, + 16'h0800, + 16'h0900, + 16'h0A00, + 16'hFFFF +}; + +endmodule diff --git a/sys/mt32pi.sv b/sys/mt32pi.sv new file mode 100644 index 0000000..cafa880 --- /dev/null +++ b/sys/mt32pi.sv @@ -0,0 +1,283 @@ +// +// Communication module to MT32-pi (external MIDI emulator on RPi) +// (C) 2020 Sorgelig, Kitrinx +// +// https://github.com/dwhinham/mt32-pi +// + +module mt32pi +( + input CLK_AUDIO, + + input CLK_VIDEO, + input CE_PIXEL, + input VGA_VS, + input VGA_DE, + + input [6:0] USER_IN, + output [6:0] USER_OUT, + + input reset, + input midi_tx, + output midi_rx, + + output reg [15:0] mt32_i2s_r, + output reg [15:0] mt32_i2s_l, + + output reg mt32_available, + + input mt32_mode_req, + input [1:0] mt32_rom_req, + input [7:0] mt32_sf_req, + + output reg [7:0] mt32_mode, + output reg [7:0] mt32_rom, + output reg [7:0] mt32_sf, + output reg mt32_newmode, + + output reg mt32_lcd_en, + output reg mt32_lcd_pix, + output reg mt32_lcd_update +); + +// +// Pin | USB Name | Signal +// ----+----------+-------------- +// 0 | D+ | I/O I2C_SDA / RX (midi in) +// 1 | D- | O TX (midi out) +// 2 | TX- | I I2S_WS (1 == right) +// 3 | GND_d | I I2C_SCL +// 4 | RX+ | I I2S_BCLK +// 5 | RX- | I I2S_DAT +// 6 | TX+ | - none +// + +assign USER_OUT[0] = sda_out; +assign USER_OUT[1] = midi_tx; +assign USER_OUT[6:2] = '1; + + +// +// crossed/straight cable selection +// + +generate + genvar i; + for(i = 0; i<2; i++) begin : clk_rate + wire clk_in = i ? USER_IN[6] : USER_IN[4]; + reg [4:0] cnt; + always @(posedge CLK_AUDIO) begin : clkr + reg clk_sr, clk, old_clk; + reg [4:0] cnt_tmp; + + clk_sr <= clk_in; + if (clk_sr == clk_in) clk <= clk_sr; + + if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1; + else cnt <= '1; + + old_clk <= clk; + if(~old_clk & clk) begin + cnt <= cnt_tmp; + cnt_tmp <= 0; + end + end + end + + reg crossed; + always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt); +endgenerate + +wire i2s_ws = crossed ? USER_IN[2] : USER_IN[5]; +wire i2s_data = crossed ? USER_IN[5] : USER_IN[2]; +wire i2s_bclk = crossed ? USER_IN[4] : USER_IN[6]; +assign midi_rx = ~mt32_available ? USER_IN[0] : crossed ? USER_IN[6] : USER_IN[4]; + + +// +// i2s receiver +// + +always @(posedge CLK_AUDIO) begin : i2s_proc + reg [15:0] i2s_buf = 0; + reg [4:0] i2s_cnt = 0; + reg clk_sr; + reg i2s_clk = 0; + reg old_clk, old_ws; + reg i2s_next = 0; + + // Debounce clock + clk_sr <= i2s_bclk; + if (clk_sr == i2s_bclk) i2s_clk <= clk_sr; + + // Latch data and ws on rising edge + old_clk <= i2s_clk; + if (i2s_clk && ~old_clk) begin + + if (~i2s_cnt[4]) begin + i2s_cnt <= i2s_cnt + 1'd1; + i2s_buf[~i2s_cnt[3:0]] <= i2s_data; + end + + // Word Select will change 1 clock before the new word starts + old_ws <= i2s_ws; + if (old_ws != i2s_ws) i2s_next <= 1; + end + + if (i2s_next) begin + i2s_next <= 0; + i2s_cnt <= 0; + i2s_buf <= 0; + + if (i2s_ws) mt32_i2s_l <= i2s_buf; + else mt32_i2s_r <= i2s_buf; + end + + if (reset) begin + i2s_buf <= 0; + mt32_i2s_l <= 0; + mt32_i2s_r <= 0; + end +end + + +// +// i2c slave +// + +reg sda_out; +reg [7:0] lcd_data[1024]; +reg lcd_sz; + +reg reset_r = 0; +wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1; +wire [7:0] rom_req = {6'd0, mt32_rom_req}; + +always @(posedge CLK_AUDIO) begin : i2c_slave + reg sda_sr, scl_sr; + reg old_sda, old_scl; + reg sda, scl; + reg [7:0] tmp; + reg [3:0] cnt = 0; + reg [10:0] bcnt = 0; + reg ack; + reg i2c_rw; + reg disp, dispdata; + reg [2:0] div; + reg old_reset; + + old_reset <= reset; + if(old_reset & ~reset) sda_out <= 1; + + div <= div + 1'd1; + if(!div) begin + sda_sr <= USER_IN[0]; + if(sda_sr == USER_IN[0]) sda <= sda_sr; + old_sda <= sda; + + scl_sr <= USER_IN[3]; + if(scl_sr == USER_IN[3]) scl <= scl_sr; + old_scl <= scl; + + //start + if(old_scl & scl & old_sda & ~sda) begin + cnt <= 9; + bcnt <= 0; + ack <= 0; + i2c_rw <= 0; + disp <= 0; + dispdata <= 0; + end + + //stop + if(old_scl & scl & ~old_sda & sda) begin + cnt <= 0; + if(dispdata) begin + lcd_sz <= ~bcnt[9]; + mt32_lcd_update <= ~mt32_lcd_update; + end + end + + //data latch + if(~old_scl && scl && cnt) begin + tmp <= {tmp[6:0], sda}; + cnt <= cnt - 1'd1; + end + + if(!cnt) sda_out <= 1; + + //data set + if(old_scl && ~scl) begin + sda_out <= 1; + if(cnt == 1) begin + if(!bcnt) begin + if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin + disp <= (tmp[7:1] == 'h3c); + sda_out <= 0; + mt32_available <= 1; + ack <= 1; + i2c_rw <= tmp[0]; + bcnt <= bcnt + 1'd1; + cnt <= 10; + end + else begin + // wrong address, stop + cnt <= 0; + end + end + else if(ack) begin + if(~i2c_rw) begin + if(disp) begin + if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01); + else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp; + end + else begin + if(bcnt == 1) mt32_mode <= tmp; + if(bcnt == 2) mt32_rom <= tmp; + if(bcnt == 3) mt32_sf <= tmp; + if(bcnt == 3) mt32_newmode <= ~mt32_newmode; + end + end + if(~&bcnt) bcnt <= bcnt + 1'd1; + sda_out <= 0; + cnt <= 10; + end + end + else if(i2c_rw && ack && cnt && ~disp) begin + if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2]; + if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2]; + if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2]; + if(bcnt == 3) reset_r <= 0; + end + end + end + + if(reset) begin + reset_r <= 1; + mt32_available <= 0; + end +end + +always @(posedge CLK_VIDEO) begin + reg old_de, old_vs; + reg [7:0] hcnt; + reg [6:0] vcnt; + reg [7:0] sh; + + if(CE_PIXEL) begin + old_de <= VGA_DE; + old_vs <= VGA_VS; + + if(~&hcnt) hcnt <= hcnt + 1'd1; + sh <= (sh << 1) | (~old_de & VGA_DE); + if(sh[7]) hcnt <= 0; + + if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1; + if(~old_vs & VGA_VS) vcnt <= 0; + + mt32_lcd_en <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]); + mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]]; + end +end + +endmodule diff --git a/sys/osd.v b/sys/osd.v index f6e8915..782fc81 100644 --- a/sys/osd.v +++ b/sys/osd.v @@ -4,40 +4,58 @@ module osd ( input clk_sys, - input io_osd, input io_strobe, input [15:0] io_din, input clk_video, input [23:0] din, - output [23:0] dout, input de_in, - output reg de_out + input vs_in, + input hs_in, + output [23:0] dout, + output reg de_out, + output reg vs_out, + output reg hs_out, + + output reg osd_status ); parameter OSD_COLOR = 3'd4; -parameter OSD_X_OFFSET = 12'd0; -parameter OSD_Y_OFFSET = 12'd0; localparam OSD_WIDTH = 12'd256; localparam OSD_HEIGHT = 12'd64; -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096]; +`ifdef OSD_HEADER +localparam OSD_HDR = 12'd24; +`else +localparam OSD_HDR = 12'd0; +`endif + +reg osd_enable; +(* ramstyle="no_rw_check" *) reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096]; -reg highres = 0; reg info = 0; reg [8:0] infoh; reg [8:0] infow; -reg [11:0] infox; +reg [21:0] infox; reg [21:0] infoy; +reg [21:0] osd_h; +reg [21:0] osd_t; +reg [21:0] osd_w; + +reg [1:0] rot = 0; always@(posedge clk_sys) begin - reg [11:0] bcnt; + reg [12:0] bcnt; reg [7:0] cmd; reg has_cmd; reg old_strobe; + reg highres = 0; + + osd_t <= rot[0] ? OSD_WIDTH : (OSD_HEIGHT<<1); + osd_h <= rot[0] ? (info ? infow : OSD_WIDTH) : info ? infoh : (OSD_HEIGHT<> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0; + pixsz <= (((cnt+1'b1) >> (9-rot[0])) > 1) ? (((cnt+1'b1) >> (9-rot[0])) - 1'd1) : 22'd0; pixcnt <= 0; end end -reg [23:0] h_cnt; -reg [21:0] v_cnt; -reg [21:0] dsp_width; -reg [21:0] dsp_height; -reg [7:0] osd_byte; -reg [21:0] osd_vcnt; -reg [21:0] fheight; +reg [2:0] osd_de; +reg osd_pixel; +reg [21:0] v_cnt; +reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4; +reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5; +reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5; -reg [21:0] finfoy; -wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT<>1))>>1; + v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1; + v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1; + v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1; + v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1; + v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1; + + v_info_start_h <= rot[0] ? infox : infoy; + v_info_start_1 <= rot[0] ? infox : infoy; + v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1); + v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1)); + v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2); + v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2)); +end always @(posedge clk_video) begin - reg deD; - reg [1:0] osd_div; - reg [1:0] multiscan; - + reg deD; + reg [2:0] osd_div; + reg [2:0] multiscan; + reg [7:0] osd_byte; + reg [23:0] h_cnt; + reg [21:0] dsp_width; + reg [21:0] osd_vcnt; + reg [21:0] h_osd_start; + reg [21:0] v_osd_start; + reg [21:0] osd_hcnt; + reg [21:0] osd_hcnt2; + reg osd_de1,osd_de2; + reg [1:0] osd_en; + reg f1; + reg half; + if(ce_pix) begin deD <= de_in; if(~&h_cnt) h_cnt <= h_cnt + 1'd1; + if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1; + if(~&osd_hcnt2) osd_hcnt2 <= osd_hcnt2 + 1'd1; + + if (h_cnt == h_osd_start) begin + osd_de[0] <= osd_en[1] && osd_h && ( + osd_vcnt[11] ? (osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19)) : + (info && (rot == 3)) ? !osd_vcnt[21:8] : + (osd_vcnt < osd_h) + ); + osd_hcnt <= 0; + osd_hcnt2 <= 0; + if(info && rot == 1) osd_hcnt2 <= 22'd128-infoh; + end + if (osd_hcnt+1 == osd_w) osd_de[0] <= 0; + // falling edge of de if(!de_in && deD) dsp_width <= h_cnt[21:0]; // rising edge of de if(de_in && !deD) begin + h_cnt <= 0; v_cnt <= v_cnt + 1'd1; - if(h_cnt > {dsp_width, 2'b00}) begin - v_cnt <= 0; - dsp_height <= v_cnt; + h_osd_start <= info ? (rot[0] ? infoy : infox) : (((dsp_width - osd_w)>>1) - 2'd2); - if(osd_enable) begin - if(v_cnt<320) begin + if(h_cnt > {dsp_width, 2'b00}) begin + v_cnt <= 1; + f1 <= ~f1; // skip every other frame for interlace compatibility. + if(~f1) begin + + osd_en <= (osd_en << 1) | osd_enable; + if(~osd_enable) osd_en <= 0; + + half <= 0; + if(v_cnt_h) begin multiscan <= 0; - fheight <= hrheight; - finfoy <= infoy; + v_osd_start <= info ? v_info_start_h : v_osd_start_h; + half <= 1; end - else if(v_cnt<640) begin + else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin + multiscan <= 0; + v_osd_start <= info ? v_info_start_1 : v_osd_start_1; + end + else if(rot[0] ? v_cnt_3 : v_cnt_2) begin multiscan <= 1; - fheight <= hrheight << 1; - finfoy <= infoy << 1; + v_osd_start <= info ? v_info_start_2 : v_osd_start_2; end - else if(v_cnt<960) begin + else if(rot[0] ? v_cnt_4 : v_cnt_3) begin multiscan <= 2; - fheight <= hrheight + (hrheight<<1); - finfoy <= infoy + (infoy << 1); + v_osd_start <= info ? v_info_start_3 : v_osd_start_3; + end + else if(rot[0] | v_cnt_4) begin + multiscan <= 3; + v_osd_start <= info ? v_info_start_4 : v_osd_start_4; end else begin - multiscan <= 3; - fheight <= hrheight << 2; - finfoy <= infoy << 2; + multiscan <= 4; + v_osd_start <= info ? v_info_start_5 : v_osd_start_5; end end - else begin - fheight <= 0; - end end - h_cnt <= 0; - + osd_div <= osd_div + 1'd1; if(osd_div == multiscan) begin osd_div <= 0; - osd_vcnt <= osd_vcnt + 1'd1; + if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1 + half; + if(osd_vcnt == 'b100010011111 && ~info) osd_vcnt <= 0; + end + if(v_osd_start == v_cnt) begin + {osd_div,osd_vcnt} <= 0; + if(info && rot == 3) osd_vcnt <= 22'd256-infow; + else if(OSD_HDR && !rot) osd_vcnt <= {~info, 3'b000, ~info, 7'b0000000}; end - if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0; end - - osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}]; + + osd_byte <= osd_buffer[rot[0] ? ({osd_hcnt2[6:3], osd_vcnt[7:0]} ^ { {4{~rot[1]}}, {8{rot[1]}} }) : {osd_vcnt[7:3], osd_hcnt[7:0]}]; + osd_pixel <= osd_byte[rot[0] ? ((osd_hcnt2[2:0]-1'd1) ^ {3{~rot[1]}}) : osd_vcnt[2:0]]; + osd_de[2:1] <= osd_de[1:0]; end end -// area in which OSD is being displayed -wire [21:0] h_osd_start = info ? infox : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET; -wire [21:0] h_osd_end = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH); -wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET; -wire [21:0] v_osd_end = v_osd_start + fheight; - -wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1; - -wire osd_de = osd_enable && fheight && - (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) && - (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -wire osd_pixel = osd_byte[osd_vcnt[2:0]]; - reg [23:0] rdout; assign dout = rdout; - + always @(posedge clk_video) begin - rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]}, - {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]}, - {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; - de_out <= de_in; + reg [23:0] ordout1, nrdout1, rdout2, rdout3; + reg de1,de2,de3; + reg osd_mux; + reg vs1,vs2,vs3; + reg hs1,hs2,hs3; + + nrdout1 <= din; + ordout1 <= {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},// 23:16 + {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},// 15:8 + {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; // 7:0 + + osd_mux <= ~osd_de[2]; + rdout2 <= osd_mux ? nrdout1 : ordout1; + rdout3 <= rdout2; + + de1 <= de_in; de2 <= de1; de3 <= de2; + hs1 <= hs_in; hs2 <= hs1; hs3 <= hs2; + vs1 <= vs_in; vs2 <= vs1; vs3 <= vs2; + + rdout <= rdout3; + de_out <= de3; + hs_out <= hs3; + vs_out <= vs3; end endmodule diff --git a/sys/pattern_vg.v b/sys/pattern_vg.v deleted file mode 100644 index 1392e1b..0000000 --- a/sys/pattern_vg.v +++ /dev/null @@ -1,120 +0,0 @@ -module pattern_vg -#( - parameter B=8, // number of bits per channel - X_BITS=13, - Y_BITS=13, - FRACTIONAL_BITS = 12 -) - -( - input reset, clk_in, - input wire [X_BITS-1:0] x, - input wire [Y_BITS-1:0] y, - input wire vn_in, hn_in, dn_in, - input wire [B-1:0] r_in, g_in, b_in, - output reg vn_out, hn_out, den_out, - output reg [B-1:0] r_out, g_out, b_out, - input wire [X_BITS-1:0] total_active_pix, - input wire [Y_BITS-1:0] total_active_lines, - input wire [7:0] pattern, - input wire [B+FRACTIONAL_BITS-1:0] ramp_step -); - -reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values - - -//wire bar_0 = y<90; -wire bar_1 = y>=90 & y<180; -wire bar_2 = y>=180 & y<270; -wire bar_3 = y>=270 & y<360; -wire bar_4 = y>=360 & y<450; -wire bar_5 = y>=450 & y<540; -wire bar_6 = y>=540 & y<630; -wire bar_7 = y>=630 & y<720; - - -wire red_enable = bar_1 | bar_3 | bar_5 | bar_7; -wire green_enable = bar_2 | bar_3 | bar_6 | bar_7; -wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7; - -always @(posedge clk_in) - begin - vn_out <= vn_in; - hn_out <= hn_in; - den_out <= dn_in; - if (reset) - ramp_values <= 0; - else if (pattern == 8'b0) // no pattern - begin - r_out <= r_in; - g_out <= g_in; - b_out <= b_in; - end - else if (pattern == 8'b1) // border - begin - if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1))) - begin - r_out <= 8'hFF; - g_out <= 8'hFF; - b_out <= 8'hFF; - end - else // Double-border (OzOnE)... - if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20))) - begin - r_out <= 8'hD0; - g_out <= 8'hB0; - b_out <= 8'hB0; - end - else - begin - r_out <= r_in; - g_out <= g_in; - b_out <= b_in; - end - end - else if (pattern == 8'd2) // moireX - begin - if ((dn_in) && x[0] == 1'b1) - begin - r_out <= 8'hFF; - g_out <= 8'hFF; - b_out <= 8'hFF; - end - else - begin - r_out <= 8'b0; - g_out <= 8'b0; - b_out <= 8'b0; - end - end - else if (pattern == 8'd3) // moireY - begin - if ((dn_in) && y[0] == 1'b1) - begin - r_out <= 8'hFF; - g_out <= 8'hFF; - b_out <= 8'hFF; - end - else - begin - r_out <= 8'b0; - g_out <= 8'b0; - b_out <= 8'b0; - end - end - else if (pattern == 8'd4) // Simple RAMP - begin - r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; - g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; - b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; - - if ((x == total_active_pix - 1) && (dn_in)) - ramp_values <= 0; - else if ((x == 0) && (dn_in)) - ramp_values <= ramp_step; - else if (dn_in) - ramp_values <= ramp_values + ramp_step; - end -end - -endmodule diff --git a/sys/pll.13.qip b/sys/pll.13.qip new file mode 100644 index 0000000..a6a1dca --- /dev/null +++ b/sys/pll.13.qip @@ -0,0 +1,17 @@ +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON + +set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v +set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v + +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" + +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_audio.13.qip b/sys/pll_audio.13.qip new file mode 100644 index 0000000..e987931 --- /dev/null +++ b/sys/pll_audio.13.qip @@ -0,0 +1,17 @@ +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON + +set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"] +set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"] + +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" + +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_audio.qip b/sys/pll_audio.qip new file mode 100644 index 0000000..abb013b --- /dev/null +++ b/sys/pll_audio.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"] +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlv" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlvXzAwMDI=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuNTc2::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTUyODMyMTE2Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTc=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuNTc2MDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw5LDgsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDE3Ljc5MiBNSHosMTUyODMyMTE2Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"] +set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"] +set_global_assignment -library "pll_audio" -name QIP_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.qip"] + +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_audio.v b/sys/pll_audio.v new file mode 100644 index 0000000..e96b248 --- /dev/null +++ b/sys/pll_audio.v @@ -0,0 +1,252 @@ +// megafunction wizard: %Altera PLL v17.0% +// GENERATION: XML +// pll_audio.v + +// Generated using ACDS version 17.0 602 + +`timescale 1 ps / 1 ps +module pll_audio ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0 // outclk0.clk + ); + + pll_audio_0002 pll_audio_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .locked () // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll_audio.vo +// RELATED_FILES: pll_audio.v, pll_audio_0002.v diff --git a/sys/pll_audio/pll_audio_0002.qip b/sys/pll_audio/pll_audio_0002.qip new file mode 100644 index 0000000..dadd4b8 --- /dev/null +++ b/sys/pll_audio/pll_audio_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" diff --git a/sys/pll_audio/pll_audio_0002.v b/sys/pll_audio/pll_audio_0002.v new file mode 100644 index 0000000..37eea13 --- /dev/null +++ b/sys/pll_audio/pll_audio_0002.v @@ -0,0 +1,87 @@ +`timescale 1ns/10ps +module pll_audio_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("direct"), + .number_of_clocks(1), + .output_clock_frequency0("24.576000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("0 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/sys/pll_cfg.qip b/sys/pll_cfg.qip new file mode 100644 index 0000000..c3394be --- /dev/null +++ b/sys/pll_cfg.qip @@ -0,0 +1,44 @@ +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"] +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" +set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A=" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc=" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" + +set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"] +set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"] +set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"] + +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_cfg.v b/sys/pll_cfg.v new file mode 100644 index 0000000..2a2f078 --- /dev/null +++ b/sys/pll_cfg.v @@ -0,0 +1,86 @@ +// megafunction wizard: %Altera PLL Reconfig v17.0% +// GENERATION: XML +// pll_cfg.v + +// Generated using ACDS version 17.0 598 + +`timescale 1 ps / 1 ps +module pll_cfg #( + parameter ENABLE_BYTEENABLE = 0, + parameter BYTEENABLE_WIDTH = 4, + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + parameter reconf_width = 64, + parameter WAIT_FOR_LOCK = 1 + ) ( + input wire mgmt_clk, // mgmt_clk.clk + input wire mgmt_reset, // mgmt_reset.reset + output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest + input wire mgmt_read, // .read + input wire mgmt_write, // .write + output wire [31:0] mgmt_readdata, // .readdata + input wire [5:0] mgmt_address, // .address + input wire [31:0] mgmt_writedata, // .writedata + output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll + ); + + altera_pll_reconfig_top #( + .device_family ("Cyclone V"), + .ENABLE_MIF (0), + .MIF_FILE_NAME ("sys/pll_cfg.mif"), + .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), + .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), + .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), + .reconf_width (reconf_width), + .WAIT_FOR_LOCK (WAIT_FOR_LOCK) + ) pll_cfg_inst ( + .mgmt_clk (mgmt_clk), // mgmt_clk.clk + .mgmt_reset (mgmt_reset), // mgmt_reset.reset + .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest + .mgmt_read (mgmt_read), // .read + .mgmt_write (mgmt_write), // .write + .mgmt_readdata (mgmt_readdata), // .readdata + .mgmt_address (mgmt_address), // .address + .mgmt_writedata (mgmt_writedata), // .writedata + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll + .mgmt_byteenable (4'b0000) // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll_cfg.vo +// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v diff --git a/sys/pll_cfg/altera_pll_reconfig_core.v b/sys/pll_cfg/altera_pll_reconfig_core.v new file mode 100644 index 0000000..d06a746 --- /dev/null +++ b/sys/pll_cfg/altera_pll_reconfig_core.v @@ -0,0 +1,2184 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ps/1ps + +module altera_pll_reconfig_core +#( + parameter reconf_width = 64, + parameter device_family = "Stratix V", + // MIF Streaming parameters + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + parameter ROM_ADDR_WIDTH = 9, + parameter ROM_DATA_WIDTH = 32, + parameter ROM_NUM_WORDS = 512 +) ( + + //input + input wire mgmt_clk, + input wire mgmt_reset, + + + //conduits + output wire [reconf_width-1:0] reconfig_to_pll, + input wire [reconf_width-1:0] reconfig_from_pll, + + // user data (avalon-MM slave interface) + output wire [31:0] mgmt_readdata, + output wire mgmt_waitrequest, + input wire [5:0] mgmt_address, + input wire mgmt_read, + input wire mgmt_write, + input wire [31:0] mgmt_writedata, + + //other + output wire mif_start_out, + output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr +); + localparam mode_WR = 1'b0; + localparam mode_POLL = 1'b1; + localparam MODE_REG = 6'b000000; + localparam STATUS_REG = 6'b000001; + localparam START_REG = 6'b000010; + localparam N_REG = 6'b000011; + localparam M_REG = 6'b000100; + localparam C_COUNTERS_REG = 6'b000101; + localparam DPS_REG = 6'b000110; + localparam DSM_REG = 6'b000111; + localparam BWCTRL_REG = 6'b001000; + localparam CP_CURRENT_REG = 6'b001001; + localparam ANY_DPRIO = 6'b100000; + localparam CNT_BASE = 5'b001010; + localparam VCO_REG = 6'b011100; + localparam MIF_REG = 6'b011111; + + //C Counters + localparam number_of_counters = 5'd18; + localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2, + CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5, + CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8, + CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11, + CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14, + CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17; + //C counter addresses + localparam C_CNT_0_DIV_ADDR = 5'h00; + localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; + localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; + localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; + localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; + localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; + //N counter addresses + localparam N_CNT_DIV_ADDR = 5'h13; + localparam N_CNT_BYPASS_EN_ADDR = 5'h15; + localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; + //M counter addresses + localparam M_CNT_DIV_ADDR = 5'h12; + localparam M_CNT_BYPASS_EN_ADDR = 5'h15; + localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; + + //DSM address + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; + localparam DSM_K_READY_ADDR = 5'h17; + localparam DSM_K_DITHER_ADDR = 5'h17; + localparam DSM_OUT_SEL_ADDR = 6'h30; + + //Other DSM params + localparam DSM_K_READY_BIT_INDEX = 4'd11; + //BWCTRL address + //Bit 0-3 of addr + localparam BWCTRL_ADDR = 6'h30; + //CP_CURRENT address + //Bit 0-2 of addr + localparam CP_CURRENT_ADDR = 6'h31; + + // VCODIV address + localparam VCO_ADDR = 5'h17; + + localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, + FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, + ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; + localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; + + wire clk; + wire reset; + wire gnd; + + wire [5: 0] slave_address; + wire slave_read; + wire slave_write; + wire [31: 0] slave_writedata; + + reg [31: 0] slave_readdata_d; + reg [31: 0] slave_readdata_q; + wire slave_waitrequest; + reg slave_mode; + + assign clk = mgmt_clk; + + assign slave_address = mgmt_address; + assign slave_read = mgmt_read; + assign slave_write = mgmt_write; + assign slave_writedata = mgmt_writedata; + + reg read_waitrequest; + // Outputs + assign mgmt_readdata = slave_readdata_q; + assign mgmt_waitrequest = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode + + //internal signals + wire locked_orig; + wire locked; + + wire pll_start; + wire pll_start_valid; + reg status_read; + wire read_slave_mode_asserted; + + wire pll_start_asserted; + + reg [1:0] current_state; + reg [1:0] next_state; + + reg status;//0=busy, 1=ready + //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); + //declaring the init wires. These will have 0 on them for 64 clk cycles + wire [ 5:0] init_dprio_address; + wire init_dprio_read; + wire [ 1:0] init_dprio_byteen; + wire init_dprio_write; + wire [15:0] init_dprio_writedata; + + wire init_atpgmode; + wire init_mdio_dis; + wire init_scanen; + wire init_ser_shift_load; + wire dprio_init_done; + + //DPRIO output signals after initialization is done + wire dprio_clk; + reg avmm_dprio_write; + reg avmm_dprio_read; + reg [5:0] avmm_dprio_address; + reg [15:0] avmm_dprio_writedata; + reg [1:0] avmm_dprio_byteen; + wire avmm_atpgmode; + wire avmm_mdio_dis; + wire avmm_scanen; + + //Final output wires that are muxed between the init and avmm wires. + wire dprio_init_reset; + wire [5:0] dprio_address /*synthesis keep*/; + wire dprio_read/*synthesis keep*/; + wire [1:0] dprio_byteen/*synthesis keep*/; + wire dprio_write/*synthesis keep*/; + wire [15:0] dprio_writedata/*synthesis keep*/; + wire dprio_mdio_dis/*synthesis keep*/; + wire dprio_ser_shift_load/*synthesis keep*/; + wire dprio_atpgmode/*synthesis keep*/; + wire dprio_scanen/*synthesis keep*/; + + + //other PLL signals for dyn ph shift + wire phase_done/*synthesis keep*/; + wire phase_en/*synthesis keep*/; + wire up_dn/*synthesis keep*/; + wire [4:0] cnt_sel; + + //DPRIO input signals + wire [15:0] dprio_readdata; + + //internal logic signals + //storage registers for user sent data + reg dprio_temp_read_1; + reg dprio_temp_read_2; + reg dprio_start; + reg mif_start_assert; + reg dps_start_assert; + wire usr_valid_changes; + reg [3:0] dprio_cur_state; + reg [3:0] dprio_next_state; + reg [15:0] dprio_temp_m_n_c_readdata_1_d; + reg [15:0] dprio_temp_m_n_c_readdata_2_d; + reg [15:0] dprio_temp_m_n_c_readdata_1_q; + reg [15:0] dprio_temp_m_n_c_readdata_2_q; + reg dprio_write_done; + //C counters signals + reg [7:0] usr_c_cnt_lo; + reg [7:0] usr_c_cnt_hi; + reg usr_c_cnt_bypass_en; + reg usr_c_cnt_odd_duty_div_en; + reg [7:0] temp_c_cnt_lo [0:17]; + reg [7:0] temp_c_cnt_hi [0:17]; + reg temp_c_cnt_bypass_en [0:17]; + reg temp_c_cnt_odd_duty_div_en [0:17]; + reg any_c_cnt_changed; + reg all_c_cnt_done_q; + reg all_c_cnt_done_d; + reg [17:0] c_cnt_changed; + reg [17:0] c_cnt_done_d; + reg [17:0] c_cnt_done_q; + //N counter signals + reg [7:0] usr_n_cnt_lo; + reg [7:0] usr_n_cnt_hi; + reg usr_n_cnt_bypass_en; + reg usr_n_cnt_odd_duty_div_en; + reg n_cnt_changed; + reg n_cnt_done_d; + reg n_cnt_done_q; + //M counter signals + reg [7:0] usr_m_cnt_lo; + reg [7:0] usr_m_cnt_hi; + reg usr_m_cnt_bypass_en; + reg usr_m_cnt_odd_duty_div_en; + reg m_cnt_changed; + reg m_cnt_done_d; + reg m_cnt_done_q; + //dyn phase regs + reg [15:0] usr_num_shifts; + reg [4:0] usr_cnt_sel /*synthesis preserve*/; + reg usr_up_dn; + reg dps_changed; + wire dps_changed_valid; + wire dps_done; + + //DSM Signals + reg [31:0] usr_k_value; + reg dsm_k_changed; + reg dsm_k_done_d; + reg dsm_k_done_q; + reg dsm_k_ready_false_done_d; + //BW signals + reg [3:0] usr_bwctrl_value; + reg bwctrl_changed; + reg bwctrl_done_d; + reg bwctrl_done_q; + //CP signals + reg [2:0] usr_cp_current_value; + reg cp_current_changed; + reg cp_current_done_d; + reg cp_current_done_q; + //VCO signals + reg usr_vco_value; + reg vco_changed; + reg vco_done_d; + reg vco_done_q; + //Manual DPRIO signals + reg manual_dprio_done_q; + reg manual_dprio_done_d; + reg manual_dprio_changed; + reg [5:0] usr_dprio_address; + reg [15:0] usr_dprio_writedata_0; + reg usr_r_w; + //keeping track of which operation happened last + reg [5:0] operation_address; + // Address wires for all C_counter DPRIO registers + // These are outputs of LUTS, changing depending + // on whether PLL_0 or PLL_1 being used + + + //Fitter will tell if FPLL1 is being used + wire fpll_1; + + // other + reg mif_reg_asserted; + // MAIN FSM + + // Synchronize locked signal + altera_std_synchronizer #( + .depth(3) + ) altera_std_synchronizer_inst ( + .clk(mgmt_clk), + .reset_n(~mgmt_reset), + .din(locked_orig), + .dout(locked) + ); + + always @(posedge clk) + begin + if (reset) + begin + dprio_cur_state <= DPRIO_IDLE; + current_state <= IDLE; + end + else + begin + current_state <= next_state; + dprio_cur_state <= dprio_next_state; + end + end + + always @(*) + begin + case(current_state) + IDLE: + begin + if (pll_start & !slave_waitrequest & usr_valid_changes) + next_state = WAIT_ON_LOCK; + else + next_state = IDLE; + end + WAIT_ON_LOCK: + begin + if (locked & dps_done & dprio_write_done) // received locked high from PLL + begin + if (slave_mode==mode_WR) //if the mode is waitrequest, then + // goto IDLE state directly + next_state = IDLE; + else + next_state = LOCKED; //otherwise go the locked state + end + else + next_state = WAIT_ON_LOCK; + end + + LOCKED: + begin + if (status_read) // stay in LOCKED until user reads status + next_state = IDLE; + else + next_state = LOCKED; + end + + default: next_state = 2'bxx; + + endcase + end + + + // ask the pll to start reconfig + assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; + assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; + + + + // WRITE OPERATIONS + assign pll_start_asserted = slave_write & (slave_address == START_REG); + assign mif_start_out = pll_start & mif_reg_asserted; + + //reading the mode register to determine what mode the slave will operate + //in. + always @(posedge clk) + begin + if (reset) + slave_mode <= mode_WR; + else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) + slave_mode <= slave_writedata[0]; + end + + //record which values user wants to change. + + //reading in the actual values that need to be reconfigged and sending + //them to the PLL + always @(posedge clk) + begin + if (reset) + begin + //reset all regs here + //BW signals reset + usr_bwctrl_value <= 0; + bwctrl_changed <= 0; + bwctrl_done_q <= 0; + //CP signals reset + usr_cp_current_value <= 0; + cp_current_changed <= 0; + cp_current_done_q <= 0; + //VCO signals reset + usr_vco_value <= 0; + vco_changed <= 0; + vco_done_q <= 0; + //DSM signals reset + usr_k_value <= 0; + dsm_k_changed <= 0; + dsm_k_done_q <= 0; + //N counter signals reset + usr_n_cnt_lo <= 0; + usr_n_cnt_hi <= 0; + usr_n_cnt_bypass_en <= 0; + usr_n_cnt_odd_duty_div_en <= 0; + n_cnt_changed <= 0; + n_cnt_done_q <= 0; + //M counter signals reset + usr_m_cnt_lo <= 0; + usr_m_cnt_hi <= 0; + usr_m_cnt_bypass_en <= 0; + usr_m_cnt_odd_duty_div_en <= 0; + m_cnt_changed <= 0; + m_cnt_done_q <= 0; + //C counter signals reset + usr_c_cnt_lo <= 0; + usr_c_cnt_hi <= 0; + usr_c_cnt_bypass_en <= 0; + usr_c_cnt_odd_duty_div_en <= 0; + any_c_cnt_changed <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + //generic signals + dprio_start <= 0; + mif_start_assert <= 0; + dps_start_assert <= 0; + dprio_temp_m_n_c_readdata_1_q <= 0; + dprio_temp_m_n_c_readdata_2_q <= 0; + c_cnt_done_q <= 0; + //DPS signals + usr_up_dn <= 0; + usr_cnt_sel <= 0; + usr_num_shifts <= 0; + dps_changed <= 0; + //manual DPRIO signals + manual_dprio_changed <= 0; + usr_dprio_address <= 0; + usr_dprio_writedata_0 <= 0; + usr_r_w <= 0; + operation_address <= 0; + mif_reg_asserted <= 0; + mif_base_addr <= 0; + end + else + begin + if (dprio_temp_read_1) + begin + dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; + end + if (dprio_temp_read_2) + begin + dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; + end + if ((dps_done)) dps_changed <= 0; + if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; + if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; + if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; + if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; + if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; + if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; + if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; + if (vco_done_d) vco_done_q <= vco_done_d; + if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; + + if (mif_start_out == 1'b1) + mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle + + if (dps_done != 1'b1) + dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle + + if (dprio_next_state == ONE) + dprio_start <= 0; + if (dprio_write_done) + begin + bwctrl_done_q <= 0; + cp_current_done_q <= 0; + vco_done_q <= 0; + dsm_k_done_q <= 0; + dsm_k_done_q <= 0; + n_cnt_done_q <= 0; + m_cnt_done_q <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + dsm_k_changed <= 0; + n_cnt_changed <= 0; + m_cnt_changed <= 0; + any_c_cnt_changed <= 0; + bwctrl_changed <= 0; + cp_current_changed <= 0; + vco_changed <= 0; + manual_dprio_changed <= 0; + manual_dprio_done_q <= 0; + if (dps_changed | dps_changed_valid | !dps_done ) + begin + usr_cnt_sel <= usr_cnt_sel; + end + else + begin + usr_cnt_sel <= 0; + end + mif_reg_asserted <= 0; + end + else + begin + dsm_k_changed <= dsm_k_changed; + n_cnt_changed <= n_cnt_changed; + m_cnt_changed <= m_cnt_changed; + any_c_cnt_changed <= any_c_cnt_changed; + manual_dprio_changed <= manual_dprio_changed; + mif_reg_asserted <= mif_reg_asserted; + usr_cnt_sel <= usr_cnt_sel; + end + + + if(slave_write & !slave_waitrequest) + begin + case(slave_address) + //read in the values here from the user and act on them + DSM_REG: + begin + operation_address <= DSM_REG; + usr_k_value <= slave_writedata[31:0]; + dsm_k_changed <= 1'b1; + dsm_k_done_q <= 0; + dprio_start <= 1'b1; + end + N_REG: + begin + operation_address <= N_REG; + usr_n_cnt_lo <= slave_writedata[7:0]; + usr_n_cnt_hi <= slave_writedata[15:8]; + usr_n_cnt_bypass_en <= slave_writedata[16]; + usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; + n_cnt_changed <= 1'b1; + n_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + M_REG: + begin + operation_address <= M_REG; + usr_m_cnt_lo <= slave_writedata[7:0]; + usr_m_cnt_hi <= slave_writedata[15:8]; + usr_m_cnt_bypass_en <= slave_writedata[16]; + usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; + m_cnt_changed <= 1'b1; + m_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + DPS_REG: + begin + operation_address <= DPS_REG; + usr_num_shifts <= slave_writedata[15:0]; + usr_cnt_sel <= slave_writedata[20:16]; + usr_up_dn <= slave_writedata[21]; + dps_changed <= 1; + dps_start_assert <= 1; + end + C_COUNTERS_REG: + begin + operation_address <= C_COUNTERS_REG; + usr_c_cnt_lo <= slave_writedata[7:0]; + usr_c_cnt_hi <= slave_writedata[15:8]; + usr_c_cnt_bypass_en <= slave_writedata[16]; + usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; + usr_cnt_sel <= slave_writedata[22:18]; + any_c_cnt_changed <= 1'b1; + all_c_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + BWCTRL_REG: + begin + usr_bwctrl_value <= slave_writedata[3:0]; + bwctrl_changed <= 1'b1; + bwctrl_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= BWCTRL_REG; + end + CP_CURRENT_REG: + begin + usr_cp_current_value <= slave_writedata[2:0]; + cp_current_changed <= 1'b1; + cp_current_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= CP_CURRENT_REG; + end + VCO_REG: + begin + usr_vco_value <= slave_writedata[0]; + vco_changed <= 1'b1; + vco_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= VCO_REG; + end + ANY_DPRIO: + begin + operation_address <= ANY_DPRIO; + manual_dprio_changed <= 1'b1; + usr_dprio_address <= slave_writedata[5:0]; + usr_dprio_writedata_0 <= slave_writedata[21:6]; + usr_r_w <= slave_writedata[22]; + manual_dprio_done_q <= 0; + dprio_start <= 1'b1; + end + MIF_REG: + begin + mif_reg_asserted <= 1'b1; + mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0]; + mif_start_assert <= 1'b1; + end + endcase + end + end + end + //C Counter assigning values to the 2-d array of values for each C counter + + reg [4:0] j; + always @(posedge clk) + begin + + if (reset) + begin + c_cnt_changed[17:0] <= 0; + for (j = 0; j < number_of_counters; j = j + 1'b1) + begin : c_cnt_reset + temp_c_cnt_bypass_en[j] <= 0; + temp_c_cnt_odd_duty_div_en[j] <= 0; + temp_c_cnt_lo[j][7:0] <= 0; + temp_c_cnt_hi[j][7:0] <= 0; + end + end + else + begin + if (dprio_write_done) + begin + c_cnt_changed <= 0; + end + if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) + begin + case (cnt_sel) + CNT_0: + begin + temp_c_cnt_lo [0] <= usr_c_cnt_lo; + temp_c_cnt_hi [0] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [0] <= 1'b1; + end + CNT_1: + begin + temp_c_cnt_lo [1] <= usr_c_cnt_lo; + temp_c_cnt_hi [1] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [1] <= 1'b1; + end + CNT_2: + begin + temp_c_cnt_lo [2] <= usr_c_cnt_lo; + temp_c_cnt_hi [2] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [2] <= 1'b1; + end + CNT_3: + begin + temp_c_cnt_lo [3] <= usr_c_cnt_lo; + temp_c_cnt_hi [3] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [3] <= 1'b1; + end + CNT_4: + begin + temp_c_cnt_lo [4] <= usr_c_cnt_lo; + temp_c_cnt_hi [4] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [4] <= 1'b1; + end + CNT_5: + begin + temp_c_cnt_lo [5] <= usr_c_cnt_lo; + temp_c_cnt_hi [5] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [5] <= 1'b1; + end + CNT_6: + begin + temp_c_cnt_lo [6] <= usr_c_cnt_lo; + temp_c_cnt_hi [6] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [6] <= 1'b1; + end + CNT_7: + begin + temp_c_cnt_lo [7] <= usr_c_cnt_lo; + temp_c_cnt_hi [7] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [7] <= 1'b1; + end + CNT_8: + begin + temp_c_cnt_lo [8] <= usr_c_cnt_lo; + temp_c_cnt_hi [8] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [8] <= 1'b1; + end + CNT_9: + begin + temp_c_cnt_lo [9] <= usr_c_cnt_lo; + temp_c_cnt_hi [9] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [9] <= 1'b1; + end + CNT_10: + begin + temp_c_cnt_lo [10] <= usr_c_cnt_lo; + temp_c_cnt_hi [10] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [10] <= 1'b1; + end + CNT_11: + begin + temp_c_cnt_lo [11] <= usr_c_cnt_lo; + temp_c_cnt_hi [11] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [11] <= 1'b1; + end + CNT_12: + begin + temp_c_cnt_lo [12] <= usr_c_cnt_lo; + temp_c_cnt_hi [12] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [12] <= 1'b1; + end + CNT_13: + begin + temp_c_cnt_lo [13] <= usr_c_cnt_lo; + temp_c_cnt_hi [13] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [13] <= 1'b1; + end + CNT_14: + begin + temp_c_cnt_lo [14] <= usr_c_cnt_lo; + temp_c_cnt_hi [14] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [14] <= 1'b1; + end + CNT_15: + begin + temp_c_cnt_lo [15] <= usr_c_cnt_lo; + temp_c_cnt_hi [15] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [15] <= 1'b1; + end + CNT_16: + begin + temp_c_cnt_lo [16] <= usr_c_cnt_lo; + temp_c_cnt_hi [16] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [16] <= 1'b1; + end + CNT_17: + begin + temp_c_cnt_lo [17] <= usr_c_cnt_lo; + temp_c_cnt_hi [17] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [17] <= 1'b1; + end + endcase + + end + end + end + + + //logic to handle which writes the user indicated and wants to start. + assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; + + + //start the reconfig operations by writing to the DPRIO + reg break_loop; + reg [4:0] i; + always @(*) + begin + dprio_temp_read_1 = 0; + dprio_temp_read_2 = 0; + dprio_temp_m_n_c_readdata_1_d = 0; + dprio_temp_m_n_c_readdata_2_d = 0; + break_loop = 0; + dprio_next_state = DPRIO_IDLE; + avmm_dprio_write = 0; + avmm_dprio_read = 0; + avmm_dprio_address = 0; + avmm_dprio_writedata = 0; + avmm_dprio_byteen = 0; + dprio_write_done = 1; + manual_dprio_done_d = 0; + n_cnt_done_d = 0; + dsm_k_done_d = 0; + dsm_k_ready_false_done_d = 0; + m_cnt_done_d = 0; + c_cnt_done_d[17:0] = 0; + all_c_cnt_done_d = 0; + bwctrl_done_d = 0; + cp_current_done_d = 0; + vco_done_d = 0; + i = 0; + + // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) + if (dprio_start | mif_start_assert) + dprio_write_done = 0; + + if (current_state == WAIT_ON_LOCK) + begin + case (dprio_cur_state) + ONE: + begin + if (n_cnt_changed & !n_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = N_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_n_cnt_lo; + avmm_dprio_writedata[15:8] = usr_n_cnt_hi; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = M_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_m_cnt_lo; + avmm_dprio_writedata[15:8] = usr_m_cnt_hi; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_hilo + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; + else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; + avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i]; + avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i]; + //To break from the loop, since only one counter + //is addressed at a time + break_loop = 1'b1; + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (cp_current_changed & !cp_current_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (vco_changed & !vco_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_write = usr_r_w; + avmm_dprio_address = usr_dprio_address; + avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; + end + else dprio_next_state = DPRIO_IDLE; + end + + TWO: + begin + //handle reading the two setting bits on n_cnt, then + //writing them back while preserving other bits. + //Issue two consecutive reads then wait; readLatency=3 + dprio_write_done = 0; + dprio_next_state = THREE; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + //reading the K ready 16 bit word. Need to write 0 to it + //afterwards to indicate that K has not been done writing + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + dprio_next_state = FOUR; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + dprio_next_state = FOUR; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + dprio_next_state = FOUR; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + dprio_next_state = FOUR; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + avmm_dprio_read = ~usr_r_w; + avmm_dprio_address = usr_dprio_address; + dprio_next_state = DPRIO_DONE; + end + else dprio_next_state = DPRIO_IDLE; + end + THREE: + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + dprio_next_state = FOUR; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + else dprio_next_state = DPRIO_IDLE; + end + FOUR: + begin + dprio_temp_read_1 = 1'b1; + dprio_write_done = 0; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + dprio_temp_m_n_c_readdata_1_d = dprio_readdata; + dprio_next_state = FIVE; + end + else dprio_next_state = DPRIO_IDLE; + end + FIVE: + begin + dprio_write_done = 0; + dprio_temp_read_2 = 1'b1; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + //this is where DSM ready value comes. + //Need to store in a register to be used later + dprio_temp_m_n_c_readdata_2_d = dprio_readdata; + dprio_next_state = SIX; + end + else dprio_next_state = DPRIO_IDLE; + end + SIX: + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = SEVEN; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_write = 0; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_write = 0; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_write = 0; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_write = 0; + end + else dprio_next_state = DPRIO_IDLE; + end + SEVEN: + begin + dprio_write_done = 0; + dprio_next_state = EIGHT; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; + n_cnt_done_d = 1'b1; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; + m_cnt_done_d = 1'b1; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; + dsm_k_ready_false_done_d = 1'b1; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + avmm_dprio_writedata[3:0] = usr_bwctrl_value; + bwctrl_done_d = 1'b1; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + avmm_dprio_writedata[2:0] = usr_cp_current_value; + cp_current_done_d = 1'b1; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + avmm_dprio_writedata[8] = usr_vco_value; + vco_done_d = 1'b1; + end + + + //if all C_cnt that were changed are done, then assert all_c_cnt_done + if (c_cnt_done_d == c_cnt_changed) + all_c_cnt_done_d = 1'b1; + if (n_cnt_changed & n_cnt_done_d) + dprio_next_state = DPRIO_DONE; + if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) + dprio_next_state = ONE; + else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) + dprio_next_state = ONE; + else if (dsm_k_changed & !dsm_k_ready_false_done_d) + dprio_next_state = TWO; + else if (dsm_k_changed & !dsm_k_done_q) + dprio_next_state = EIGHT; + else if (bwctrl_changed & !bwctrl_done_d) + dprio_next_state = TWO; + else if (cp_current_changed & !cp_current_done_d) + dprio_next_state = TWO; + else if (vco_changed & !vco_done_d) + dprio_next_state = TWO; + else + begin + dprio_next_state = DPRIO_DONE; + dprio_write_done = 1'b1; + end + end + //finish the rest of the DSM reads/writes + //writing k value, writing k_ready to 1. + EIGHT: + begin + dprio_write_done = 0; + dprio_next_state = NINE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; + avmm_dprio_writedata[15:0] = usr_k_value[15:0]; + end + end + NINE: + begin + dprio_write_done = 0; + dprio_next_state = TEN; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; + avmm_dprio_writedata[15:0] = usr_k_value[31:16]; + end + end + TEN: + begin + dprio_write_done = 0; + dprio_next_state = ONE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + //already have the readdata for DSM_K_READY_ADDR since we read it + //earlier. Just reuse here + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; + dsm_k_done_d = 1'b1; + end + end + DPRIO_DONE: + begin + dprio_write_done = 1'b1; + if (dprio_start) dprio_next_state = DPRIO_IDLE; + else dprio_next_state = DPRIO_DONE; + end + DPRIO_IDLE: + begin + if (dprio_start) dprio_next_state = ONE; + else dprio_next_state = DPRIO_IDLE; + end + default: dprio_next_state = 4'bxxxx; + endcase + end + + end + + + //assert the waitreq signal according to the state of the slave + assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; + + // Read operations + always @(*) + begin + status = 0; + if (slave_mode == mode_POLL) + //asserting status to 1 if the slave is done. + status = (current_state == LOCKED); + end + //************************************************************// + //************************************************************// + //******************** READ STATE MACHINE ********************// + //************************************************************// + //************************************************************// + reg [1:0] current_read_state; + reg [1:0] next_read_state; + reg [5:0] slave_address_int_d; + reg [5:0] slave_address_int_q; + reg dprio_read_1; + reg [5:0] dprio_address_1; + reg [1:0] dprio_byteen_1; + reg [4:0] usr_cnt_sel_1; + localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; + + always @(*) + begin + if(next_read_state == READ_IDLE) + begin + read_waitrequest <= 1'b0; + end + else + begin + read_waitrequest <= 1'b1; + end + end + + always @(posedge clk) + begin + if (reset) + begin + current_read_state <= READ_IDLE; + slave_address_int_q <= 0; + slave_readdata_q <= 0; + end + else + begin + current_read_state <= next_read_state; + slave_address_int_q <= slave_address_int_d; + slave_readdata_q <= slave_readdata_d; + end + end + always @(*) + begin + dprio_read_1 = 0; + dprio_address_1 = 0; + dprio_byteen_1 = 0; + slave_address_int_d = 0; + slave_readdata_d = 0; + status_read = 0; + usr_cnt_sel_1 = 0; + case(current_read_state) + READ_IDLE: + begin + slave_address_int_d = 0; + next_read_state = READ_IDLE; + if ((current_state != WAIT_ON_LOCK) && slave_read) + begin + slave_address_int_d = slave_address; + if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18)) + begin + next_read_state = READ_WAIT; + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE); + if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel; + else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel; + end + else + begin + case (slave_address) + MODE_REG: + begin + next_read_state = READ_WAIT; + slave_readdata_d = slave_mode; + end + STATUS_REG: + begin + next_read_state = READ_WAIT; + status_read = 1'b1; + slave_readdata_d = status; + end + N_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = N_CNT_DIV_ADDR; + next_read_state = READ_WAIT; + end + M_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = M_CNT_DIV_ADDR; + next_read_state = READ_WAIT; + end + BWCTRL_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = BWCTRL_ADDR; + next_read_state = READ_WAIT; + end + CP_CURRENT_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = CP_CURRENT_ADDR; + next_read_state = READ_WAIT; + end + VCO_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = VCO_ADDR; + next_read_state = READ_WAIT; + end + ANY_DPRIO: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = ~slave_writedata[22]; + dprio_address_1 = slave_writedata[5:0]; + next_read_state = READ_WAIT; + end + default : next_read_state = READ_IDLE; + endcase + end + end + else + next_read_state = READ_IDLE; + end + READ_WAIT: + begin + next_read_state = READ; + slave_address_int_d = slave_address_int_q; + case (slave_address_int_q) + MODE_REG: + begin + slave_readdata_d = slave_readdata_q; + end + STATUS_REG: + begin + slave_readdata_d = slave_readdata_q; + end + endcase + end + READ: + begin + next_read_state = READ_POST_WAIT; + slave_address_int_d = slave_address_int_q; + slave_readdata_d = dprio_readdata; + case (slave_address_int_q) + MODE_REG: + begin + slave_readdata_d = slave_readdata_q; + end + STATUS_REG: + begin + slave_readdata_d = slave_readdata_q; + end + BWCTRL_REG: + begin + slave_readdata_d = dprio_readdata[3:0]; + end + CP_CURRENT_REG: + begin + slave_readdata_d = dprio_readdata[2:0]; + end + VCO_REG: + begin + slave_readdata_d = dprio_readdata[8]; + end + ANY_DPRIO: + begin + slave_readdata_d = dprio_readdata; + end + endcase + end + READ_POST_WAIT: + begin + next_read_state = READ_IDLE; + end + default: next_read_state = 2'bxx; + endcase + end + + + dyn_phase_shift dyn_phase_shift_inst ( + .clk(clk), + .reset(reset), + .phase_done(phase_done), + .pll_start_valid(pll_start_valid), + .dps_changed(dps_changed), + .dps_changed_valid(dps_changed_valid), + .dprio_write_done(dprio_write_done), + .usr_num_shifts(usr_num_shifts), + .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1), + .usr_up_dn(usr_up_dn), + .locked(locked), + .dps_done(dps_done), + .phase_en(phase_en), + .up_dn(up_dn), + .cnt_sel(cnt_sel)); + defparam dyn_phase_shift_inst.device_family = device_family; + + assign dprio_clk = clk; + self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); + + dprio_mux dprio_mux_inst ( + .init_dprio_address(init_dprio_address), + .init_dprio_read(init_dprio_read), + .init_dprio_byteen(init_dprio_byteen), + .init_dprio_write(init_dprio_write), + .init_dprio_writedata(init_dprio_writedata), + + + .init_atpgmode(init_atpgmode), + .init_mdio_dis(init_mdio_dis), + .init_scanen(init_scanen), + .init_ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done), + + // Inputs from avmm master + .avmm_dprio_address(avmm_dprio_address | dprio_address_1), + .avmm_dprio_read(avmm_dprio_read | dprio_read_1), + .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1), + .avmm_dprio_write(avmm_dprio_write), + .avmm_dprio_writedata(avmm_dprio_writedata), + + .avmm_atpgmode(avmm_atpgmode), + .avmm_mdio_dis(avmm_mdio_dis), + .avmm_scanen(avmm_scanen), + + // Outputs to fpll + .dprio_address(dprio_address), + .dprio_read(dprio_read), + .dprio_byteen(dprio_byteen), + .dprio_write(dprio_write), + .dprio_writedata(dprio_writedata), + + .atpgmode(dprio_atpgmode), + .mdio_dis(dprio_mdio_dis), + .scanen(dprio_scanen), + .ser_shift_load(dprio_ser_shift_load) + ); + + + fpll_dprio_init fpll_dprio_init_inst ( + .clk(clk), + .reset_n(~reset), + .locked(locked), + + //outputs + .dprio_address(init_dprio_address), + .dprio_read(init_dprio_read), + .dprio_byteen(init_dprio_byteen), + .dprio_write(init_dprio_write), + .dprio_writedata(init_dprio_writedata), + + .atpgmode(init_atpgmode), + .mdio_dis(init_mdio_dis), + .scanen(init_scanen), + .ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done)); + + //address luts, to be reconfigged by the Fitter + //FPLL_1 or 0 address lut + generic_lcell_comb lcell_fpll_0_1 ( + .dataa(1'b0), + .combout (fpll_1)); + defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; + defparam lcell_fpll_0_1.dont_touch = "on"; + defparam lcell_fpll_0_1.family = device_family; + + + wire dprio_read_combout; + generic_lcell_comb lcell_dprio_read ( + .dataa(fpll_1), + .datab(dprio_read), + .datac(1'b0), + .datad(1'b0), + .datae(1'b0), + .dataf(1'b0), + .combout (dprio_read_combout)); + defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; + defparam lcell_dprio_read.dont_touch = "on"; + defparam lcell_dprio_read.family = device_family; + + + + + + //assign reconfig_to_pll signals + assign reconfig_to_pll[0] = dprio_clk; + assign reconfig_to_pll[1] = ~dprio_init_reset; + assign reconfig_to_pll[2] = dprio_write; + assign reconfig_to_pll[3] = dprio_read_combout; + assign reconfig_to_pll[9:4] = dprio_address; + assign reconfig_to_pll[25:10] = dprio_writedata; + assign reconfig_to_pll[27:26] = dprio_byteen; + assign reconfig_to_pll[28] = dprio_ser_shift_load; + assign reconfig_to_pll[29] = dprio_mdio_dis; + assign reconfig_to_pll[30] = phase_en; + assign reconfig_to_pll[31] = up_dn; + assign reconfig_to_pll[36:32] = cnt_sel; + assign reconfig_to_pll[37] = dprio_scanen; + assign reconfig_to_pll[38] = dprio_atpgmode; + //assign reconfig_to_pll[40:37] = clken; + assign reconfig_to_pll[63:39] = 0; + + //assign reconfig_from_pll signals + assign dprio_readdata = reconfig_from_pll [15:0]; + assign locked_orig = reconfig_from_pll [16]; + assign phase_done = reconfig_from_pll [17]; + +endmodule +module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset); + + localparam RESET_COUNTER_VALUE = 3'd2; + localparam INITIAL_WAIT_VALUE = 9'd340; + reg [9:0]counter; + reg local_reset; + reg usr_mode_init_wait; + initial + begin + local_reset = 1'b1; + counter = 0; + usr_mode_init_wait = 0; + end + + always @(posedge clk) + begin + if (mgmt_reset) + begin + counter <= 0; + end + else + begin + if (!usr_mode_init_wait) + begin + if (counter == INITIAL_WAIT_VALUE) + begin + local_reset <= 0; + usr_mode_init_wait <= 1'b1; + counter <= 0; + end + else + begin + counter <= counter + 1'b1; + end + end + else + begin + if (counter == RESET_COUNTER_VALUE) + local_reset <= 0; + else + counter <= counter + 1'b1; + end + end + end + assign reset = mgmt_reset | local_reset; + assign init_reset = local_reset; +endmodule + +module dprio_mux ( + // Inputs from init block + input [ 5:0] init_dprio_address, + input init_dprio_read, + input [ 1:0] init_dprio_byteen, + input init_dprio_write, + input [15:0] init_dprio_writedata, + + input init_atpgmode, + input init_mdio_dis, + input init_scanen, + input init_ser_shift_load, + input dprio_init_done, + + // Inputs from avmm master + input [ 5:0] avmm_dprio_address, + input avmm_dprio_read, + input [ 1:0] avmm_dprio_byteen, + input avmm_dprio_write, + input [15:0] avmm_dprio_writedata, + + input avmm_atpgmode, + input avmm_mdio_dis, + input avmm_scanen, + input avmm_ser_shift_load, + + // Outputs to fpll + output [ 5:0] dprio_address, + output dprio_read, + output [ 1:0] dprio_byteen, + output dprio_write, + output [15:0] dprio_writedata, + + output atpgmode, + output mdio_dis, + output scanen, + output ser_shift_load +); + + assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address; + assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read; + assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen; + assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write; + assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata; + + assign atpgmode = init_atpgmode; + assign scanen = init_scanen; + assign mdio_dis = init_mdio_dis; + assign ser_shift_load = init_ser_shift_load ; +endmodule +module fpll_dprio_init ( + input clk, + input reset_n, + input locked, + + output [ 5:0] dprio_address, + output dprio_read, + output [ 1:0] dprio_byteen, + output dprio_write, + output [15:0] dprio_writedata, + + output reg atpgmode, + output reg mdio_dis, + output reg scanen, + output reg ser_shift_load, + output reg dprio_init_done +); + + reg [1:0] rst_n = 2'b00; + reg [6:0] count = 7'd0; + reg init_done_forever; + + // Internal versions of control signals + wire int_mdio_dis; + wire int_ser_shift_load; + wire int_dprio_init_done; + wire int_atpgmode/*synthesis keep*/; + wire int_scanen/*synthesis keep*/; + + + assign dprio_address = count[6] ? 5'b0 : count[5:0] ; + assign dprio_byteen = 2'b11; // always enabled + assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles + assign dprio_read = 1'b0; + assign dprio_writedata = 16'd0; + + assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1; + assign int_mdio_dis = count[6] ? ~count[2] : 1'b1; + assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0) + : 1'b1; + assign int_atpgmode = 0; + assign int_scanen = 0; + + initial begin + count = 7'd0; + init_done_forever = 0; + mdio_dis = 1'b1; + ser_shift_load = 1'b1; + dprio_init_done = 1'b0; + scanen = 1'b0; + atpgmode = 1'b0; + end + + // reset synch. + always @(posedge clk or negedge reset_n) + if(!reset_n) rst_n <= 2'b00; + else rst_n <= {rst_n[0],1'b1}; + + // counter + always @(posedge clk) + begin + if (!rst_n[1]) + init_done_forever <= 1'b0; + else + begin + if (count[6] && &count[1:0]) + init_done_forever <= 1'b1; + end + end + always @(posedge clk or negedge rst_n[1]) + begin + if(!rst_n[1]) + begin + count <= 7'd0; + end + else if(~int_dprio_init_done) + begin + count <= count + 7'd1; + end + else + begin + count <= count; + end + end + + // outputs + always @(posedge clk) begin + mdio_dis <= int_mdio_dis; + ser_shift_load <= int_ser_shift_load; + dprio_init_done <= int_dprio_init_done; + atpgmode <= int_atpgmode; + scanen <= int_scanen; + end + +endmodule +module dyn_phase_shift +#( + parameter device_family = "Stratix V" +) ( + + input wire clk, + input wire reset, + input wire phase_done, + input wire pll_start_valid, + input wire dps_changed, + input wire dprio_write_done, + input wire [15:0] usr_num_shifts, + input wire [4:0] usr_cnt_sel, + input wire usr_up_dn, + input wire locked, + + //output + output wire dps_done, + output reg phase_en, + output wire up_dn, + output wire dps_changed_valid, + output wire [4:0] cnt_sel); + + + + reg first_phase_shift_d; + reg first_phase_shift_q; + reg [15:0] phase_en_counter; + reg [3:0] dps_current_state; + reg [3:0] dps_next_state; + localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; + localparam PHASE_EN_WAIT_COUNTER = 5'd1; + + reg [15:0] shifts_done_counter; + reg phase_done_final; + wire gnd /*synthesis keep*/; + + //fsm + //always block controlling the state regs + always @(posedge clk) + begin + if (reset) + begin + dps_current_state <= DPS_DONE; + end + else + begin + dps_current_state <= dps_next_state; + end + end + //the combinational part. assigning the next state + //this turns on the phase_done_final signal when phase_done does this: + //_____ ______ + // |______| + always @(*) + begin + phase_done_final = 0; + first_phase_shift_d = 0; + phase_en = 0; + dps_next_state = DPS_DONE; + case (dps_current_state) + DPS_START: + begin + phase_en = 1'b1; + dps_next_state = DPS_WAIT_PHASE_EN; + end + DPS_WAIT_PHASE_EN: + begin + phase_en = 1'b1; + if (first_phase_shift_q) + begin + first_phase_shift_d = 1'b1; + dps_next_state = DPS_WAIT_PHASE_EN; + end + else + begin + if (phase_en_counter == PHASE_EN_WAIT_COUNTER) + dps_next_state = DPS_WAIT_PHASE_DONE; + else dps_next_state = DPS_WAIT_PHASE_EN; + end + end + DPS_WAIT_PHASE_DONE: + begin + if (!phase_done | !locked) + begin + dps_next_state = DPS_WAIT_PHASE_DONE; + end + else + begin + if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0)) + begin + dps_next_state = DPS_START; + phase_done_final = 1'b1; + end + else + begin + dps_next_state = DPS_DONE; + end + + end + end + DPS_DONE: + begin + phase_done_final = 0; + if (dps_changed) + dps_next_state = DPS_CHANGED; + else dps_next_state = DPS_DONE; + + end + DPS_CHANGED: + begin + if (pll_start_valid) + dps_next_state = DPS_WAIT_DPRIO_WRITING; + else + dps_next_state = DPS_CHANGED; + end + DPS_WAIT_DPRIO_WRITING: + begin + if (dprio_write_done) + dps_next_state = DPS_START; + else + dps_next_state = DPS_WAIT_DPRIO_WRITING; + end + + default: dps_next_state = 4'bxxxx; + endcase + + + end + + always @(posedge clk) + begin + + + if (dps_current_state == DPS_WAIT_PHASE_DONE) + phase_en_counter <= 0; + else if (dps_current_state == DPS_WAIT_PHASE_EN) + phase_en_counter <= phase_en_counter + 1'b1; + + if (reset) + begin + phase_en_counter <= 0; + shifts_done_counter <= 1'b1; + first_phase_shift_q <= 1; + end + else + begin + if (first_phase_shift_d) + first_phase_shift_q <= 0; + if (dps_done) + begin + shifts_done_counter <= 1'b1; + end + else + begin + if (phase_done_final & (dps_next_state!= DPS_DONE)) + shifts_done_counter <= shifts_done_counter + 1'b1; + else + shifts_done_counter <= shifts_done_counter; + end + end + end + + assign dps_changed_valid = (dps_current_state == DPS_CHANGED); + assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED); + assign up_dn = usr_up_dn; + assign gnd = 1'b0; + + //cnt select luts (5) + generic_lcell_comb lcell_cnt_sel_0 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[0])); + defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA; + defparam lcell_cnt_sel_0.dont_touch = "on"; + defparam lcell_cnt_sel_0.family = device_family; + generic_lcell_comb lcell_cnt_sel_1 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[1])); + defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC; + defparam lcell_cnt_sel_1.dont_touch = "on"; + defparam lcell_cnt_sel_1.family = device_family; + generic_lcell_comb lcell_cnt_sel_2 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[2])); + defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0; + defparam lcell_cnt_sel_2.dont_touch = "on"; + defparam lcell_cnt_sel_2.family = device_family; + generic_lcell_comb lcell_cnt_sel_3 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[3])); + defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00; + defparam lcell_cnt_sel_3.dont_touch = "on"; + defparam lcell_cnt_sel_3.family = device_family; + generic_lcell_comb lcell_cnt_sel_4 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[4])); + defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000; + defparam lcell_cnt_sel_4.dont_touch = "on"; + defparam lcell_cnt_sel_4.family = device_family; + + +endmodule + +module generic_lcell_comb +#( + //parameter + parameter family = "Stratix V", + parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, + parameter dont_touch = "on" +) ( + + input dataa, + input datab, + input datac, + input datad, + input datae, + input dataf, + + output combout +); + + generate + if (family == "Stratix V") + begin + stratixv_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Arria V") + begin + arriav_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Arria V GZ") + begin + arriavgz_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Cyclone V") + begin + cyclonev_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + endgenerate +endmodule diff --git a/sys/pll_cfg/altera_pll_reconfig_top.v b/sys/pll_cfg/altera_pll_reconfig_top.v new file mode 100644 index 0000000..c6d27bf --- /dev/null +++ b/sys/pll_cfg/altera_pll_reconfig_top.v @@ -0,0 +1,428 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ps/1ps + +module altera_pll_reconfig_top +#( + parameter reconf_width = 64, + parameter device_family = "Stratix V", + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + + parameter ROM_ADDR_WIDTH = 9, + parameter ROM_DATA_WIDTH = 32, + parameter ROM_NUM_WORDS = 512, + + parameter ENABLE_MIF = 0, + parameter MIF_FILE_NAME = "", + + parameter ENABLE_BYTEENABLE = 0, + parameter BYTEENABLE_WIDTH = 4, + parameter WAIT_FOR_LOCK = 1 +) ( + + //input + input wire mgmt_clk, + input wire mgmt_reset, + + + //conduits + output wire [reconf_width-1:0] reconfig_to_pll, + input wire [reconf_width-1:0] reconfig_from_pll, + + // user data (avalon-MM slave interface) + output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata, + output wire mgmt_waitrequest, + input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address, + input wire mgmt_read, + input wire mgmt_write, + input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata, + + //conditional input + input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable +); + +localparam NM28_START_REG = 6'b000010; +localparam NM20_START_REG = 9'b000000000; +localparam NM20_MIFSTART_ADDR = 9'b000010000; + +localparam MIF_STATE_DONE = 2'b00; +localparam MIF_STATE_START = 2'b01; +localparam MIF_STATE_BUSY = 2'b10; + +wire mgmt_byteenable_write; +assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? + ((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : + mgmt_write; + +generate +if (device_family == "Arria 10") +begin:nm20_reconfig + if(ENABLE_MIF == 1) + begin:mif_reconfig_20nm // Generate Reconfig with MIF + + // MIF-related regs/wires + reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; + reg reconfig_mgmt_read; + reg reconfig_mgmt_write; + reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; + wire reconfig_mgmt_waitrequest; + wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; + + wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; + wire mif_busy; + wire mif2reconfig_read; + wire mif2reconfig_write; + wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + reg mif_select; + //wire mif_user_start; // start signal provided by user to start mif + //reg user_start; + + reg [1:0] mif_curstate; + reg [1:0] mif_nextstate; + + wire mif_start; //start signal to mif reader + + assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start; + // Don't output readdata if MIF streaming is taking place + assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; + + //user must lower this by the time mif streaming is done - suggest to lower after 1 cycle + assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR); + + //mif base addr is initially specified by the user + assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0]; + + //MIF statemachine + always @(posedge mgmt_clk) + begin + if(mgmt_reset) + mif_curstate <= MIF_STATE_DONE; + else + mif_curstate <= mif_nextstate; + end + + always @(*) + begin + case (mif_curstate) + MIF_STATE_DONE: + begin + if(mif_start) + mif_nextstate <= MIF_STATE_START; + else + mif_nextstate <= MIF_STATE_DONE; + end + MIF_STATE_START: + begin + mif_nextstate <= MIF_STATE_BUSY; + end + MIF_STATE_BUSY: + begin + if(mif_busy) + mif_nextstate <= MIF_STATE_BUSY; + else + mif_nextstate <= MIF_STATE_DONE; + end + endcase + end + + //Mif muxes + always @(*) + begin + if (mgmt_reset) + begin + reconfig_mgmt_addr <= 0; + reconfig_mgmt_read <= 0; + reconfig_mgmt_write <= 0; + reconfig_mgmt_writedata <= 0; + //user_start <= 0; + end + else + begin + reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; + reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; + reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; + reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; + //user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0; + end + end + + always @(*) + begin + if (mgmt_reset) + begin + mif_select <= 0; + end + else + begin + mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0; + end + end + + twentynm_pll_reconfig_mif_reader + #( + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS), + .DEVICE_FAMILY(device_family), + .ENABLE_MIF(ENABLE_MIF), + .MIF_FILE_NAME(MIF_FILE_NAME) + ) twentynm_pll_reconfig_mif_reader_inst0 ( + .mif_clk(mgmt_clk), + .mif_rst(mgmt_reset), + + //Altera_PLL Reconfig interface + //inputs + .reconfig_waitrequest(reconfig_mgmt_waitrequest), + //.reconfig_read_data(reconfig_mgmt_readdata), + //outputs + .reconfig_write_data(mif2reconfig_writedata), + .reconfig_addr(mif2reconfig_addr), + .reconfig_write(mif2reconfig_write), + .reconfig_read(mif2reconfig_read), + + //MIF Ctrl Interface + //inputs + .mif_base_addr(mif_base_addr), + .mif_start(mif_start), + //outputs + .mif_busy(mif_busy) + ); + + // ------ END MIF-RELATED MANAGEMENT ------ + + twentynm_iopll_reconfig_core + #( + .WAIT_FOR_LOCK(WAIT_FOR_LOCK) + ) twentynm_iopll_reconfig_core_inst ( + // Inputs + .mgmt_clk(mgmt_clk), + .mgmt_rst_n(~mgmt_reset), + .mgmt_read(reconfig_mgmt_read), + .mgmt_write(reconfig_mgmt_write), + .mgmt_address(reconfig_mgmt_addr), + .mgmt_writedata(reconfig_mgmt_writedata), + + // Outputs + .mgmt_readdata(reconfig_mgmt_readdata), + .mgmt_waitrequest(reconfig_mgmt_waitrequest), + + // PLL Conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); + + end // End generate reconfig with MIF + else + begin:reconfig_core_20nm + twentynm_iopll_reconfig_core + #( + .WAIT_FOR_LOCK(WAIT_FOR_LOCK) + ) twentynm_iopll_reconfig_core_inst ( + // Inputs + .mgmt_clk(mgmt_clk), + .mgmt_rst_n(~mgmt_reset), + .mgmt_read(mgmt_read), + .mgmt_write(mgmt_byteenable_write), + .mgmt_address(mgmt_address), + .mgmt_writedata(mgmt_writedata), + + // Outputs + .mgmt_readdata(mgmt_readdata), + .mgmt_waitrequest(mgmt_waitrequest), + + // PLL Conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); + end +end // 20nm reconfig +else +begin:NM28_reconfig + if (ENABLE_MIF == 1) + begin:mif_reconfig // Generate Reconfig with MIF + + // MIF-related regs/wires + reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; + reg reconfig_mgmt_read; + reg reconfig_mgmt_write; + reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; + wire reconfig_mgmt_waitrequest; + wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; + + wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; + wire mif2reconfig_busy; + wire mif2reconfig_read; + wire mif2reconfig_write; + wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + reg mif_select; + reg user_start; + + wire reconfig2mif_start_out; + + assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start; + // Don't output readdata if MIF streaming is taking place + assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; + + always @(posedge mgmt_clk) + begin + if (mgmt_reset) + begin + reconfig_mgmt_addr <= 0; + reconfig_mgmt_read <= 0; + reconfig_mgmt_write <= 0; + reconfig_mgmt_writedata <= 0; + user_start <= 0; + end + else + begin + reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; + reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; + reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; + reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; + user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0; + end + end + + always @(*) + begin + if (mgmt_reset) + begin + mif_select <= 0; + end + else + begin + mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0; + end + end + + altera_pll_reconfig_mif_reader + #( + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS), + .DEVICE_FAMILY(device_family), + .ENABLE_MIF(ENABLE_MIF), + .MIF_FILE_NAME(MIF_FILE_NAME) + ) altera_pll_reconfig_mif_reader_inst0 ( + .mif_clk(mgmt_clk), + .mif_rst(mgmt_reset), + + //Altera_PLL Reconfig interface + //inputs + .reconfig_busy(reconfig_mgmt_waitrequest), + .reconfig_read_data(reconfig_mgmt_readdata), + //outputs + .reconfig_write_data(mif2reconfig_writedata), + .reconfig_addr(mif2reconfig_addr), + .reconfig_write(mif2reconfig_write), + .reconfig_read(mif2reconfig_read), + + //MIF Ctrl Interface + //inputs + .mif_base_addr(mif_base_addr), + .mif_start(reconfig2mif_start_out), + //outputs + .mif_busy(mif2reconfig_busy) + ); + + // ------ END MIF-RELATED MANAGEMENT ------ + + + altera_pll_reconfig_core + #( + .reconf_width(reconf_width), + .device_family(device_family), + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS) + ) altera_pll_reconfig_core_inst0 ( + //inputs + .mgmt_clk(mgmt_clk), + .mgmt_reset(mgmt_reset), + + //PLL interface conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + + //User data outputs + .mgmt_readdata(reconfig_mgmt_readdata), + .mgmt_waitrequest(reconfig_mgmt_waitrequest), + + //User data inputs + .mgmt_address(reconfig_mgmt_addr), + .mgmt_read(reconfig_mgmt_read), + .mgmt_write(reconfig_mgmt_write), + .mgmt_writedata(reconfig_mgmt_writedata), + + // other + .mif_start_out(reconfig2mif_start_out), + .mif_base_addr(mif_base_addr) + ); + + end // End generate reconfig with MIF + else + begin:reconfig_core // Generate Reconfig core only + + wire reconfig2mif_start_out; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + + altera_pll_reconfig_core + #( + .reconf_width(reconf_width), + .device_family(device_family), + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS) + ) altera_pll_reconfig_core_inst0 ( + //inputs + .mgmt_clk(mgmt_clk), + .mgmt_reset(mgmt_reset), + + //PLL interface conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + + //User data outputs + .mgmt_readdata(mgmt_readdata), + .mgmt_waitrequest(mgmt_waitrequest), + + //User data inputs + .mgmt_address(mgmt_address), + .mgmt_read(mgmt_read), + .mgmt_write(mgmt_byteenable_write), + .mgmt_writedata(mgmt_writedata), + + // other + .mif_start_out(reconfig2mif_start_out), + .mif_base_addr(mif_base_addr) + ); + + + end // End generate reconfig core only +end // End 28nm Reconfig +endgenerate + +endmodule + diff --git a/sys/pll_hdmi.13.qip b/sys/pll_hdmi.13.qip new file mode 100644 index 0000000..76def89 --- /dev/null +++ b/sys/pll_hdmi.13.qip @@ -0,0 +1,17 @@ +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON + +set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] +set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] + +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" + +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_hdmi.qip b/sys/pll_hdmi.qip new file mode 100644 index 0000000..be34aeb --- /dev/null +++ b/sys/pll_hdmi.qip @@ -0,0 +1,483 @@ +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk=" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mg==::Y19jbnRfaGlfZGl2MA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::MQ==::Y19jbnRfbG9fZGl2MA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MjA=::cGxsX2NwX2N1cnJlbnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::NDAwMA==::cGxsX2J3Y3RybA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQ1LjQ5OTk5OSBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzkwODQyMDE1Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDQ1LjQ5OTk5OSBNSHosMzkwODQyMDE1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] +set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] +set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"] + +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_hdmi.v b/sys/pll_hdmi.v new file mode 100644 index 0000000..52a9de9 --- /dev/null +++ b/sys/pll_hdmi.v @@ -0,0 +1,256 @@ +// megafunction wizard: %Altera PLL v17.0% +// GENERATION: XML +// pll_hdmi.v + +// Generated using ACDS version 17.0 598 + +`timescale 1 ps / 1 ps +module pll_hdmi ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll + ); + + pll_hdmi_0002 pll_hdmi_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll + .locked () // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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b/sys/pll_hdmi/pll_hdmi_0002.v @@ -0,0 +1,241 @@ +`timescale 1ns/10ps +module pll_hdmi_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'locked' + output wire locked, + + // interface 'reconfig_to_pll' + input wire [63:0] reconfig_to_pll, + + // interface 'reconfig_from_pll' + output wire [63:0] reconfig_from_pll +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("50.0 MHz"), + .pll_fractional_cout(32), + .pll_dsm_out_sel("1st_order"), + .operation_mode("direct"), + .number_of_clocks(1), + .output_clock_frequency0("148.500000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("0 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("Cyclone V"), + .pll_subtype("Reconfigurable"), + .m_cnt_hi_div(4), + .m_cnt_lo_div(4), + .n_cnt_hi_div(256), + .n_cnt_lo_div(256), + .m_cnt_bypass_en("false"), + .n_cnt_bypass_en("true"), + .m_cnt_odd_div_duty_en("false"), + .n_cnt_odd_div_duty_en("false"), + .c_cnt_hi_div0(2), + .c_cnt_lo_div0(1), + .c_cnt_prst0(1), + .c_cnt_ph_mux_prst0(0), + .c_cnt_in_src0("ph_mux_clk"), + .c_cnt_bypass_en0("false"), + .c_cnt_odd_div_duty_en0("true"), + .c_cnt_hi_div1(1), + .c_cnt_lo_div1(1), + .c_cnt_prst1(1), + .c_cnt_ph_mux_prst1(0), + .c_cnt_in_src1("ph_mux_clk"), + .c_cnt_bypass_en1("true"), + .c_cnt_odd_div_duty_en1("false"), + .c_cnt_hi_div2(1), + .c_cnt_lo_div2(1), + .c_cnt_prst2(1), + .c_cnt_ph_mux_prst2(0), + .c_cnt_in_src2("ph_mux_clk"), + .c_cnt_bypass_en2("true"), + .c_cnt_odd_div_duty_en2("false"), + .c_cnt_hi_div3(1), + .c_cnt_lo_div3(1), + .c_cnt_prst3(1), + .c_cnt_ph_mux_prst3(0), + .c_cnt_in_src3("ph_mux_clk"), + .c_cnt_bypass_en3("true"), + .c_cnt_odd_div_duty_en3("false"), + .c_cnt_hi_div4(1), + .c_cnt_lo_div4(1), + .c_cnt_prst4(1), + .c_cnt_ph_mux_prst4(0), + .c_cnt_in_src4("ph_mux_clk"), + .c_cnt_bypass_en4("true"), + .c_cnt_odd_div_duty_en4("false"), + .c_cnt_hi_div5(1), + .c_cnt_lo_div5(1), + .c_cnt_prst5(1), + .c_cnt_ph_mux_prst5(0), + .c_cnt_in_src5("ph_mux_clk"), + .c_cnt_bypass_en5("true"), + .c_cnt_odd_div_duty_en5("false"), + .c_cnt_hi_div6(1), + .c_cnt_lo_div6(1), + .c_cnt_prst6(1), + .c_cnt_ph_mux_prst6(0), + .c_cnt_in_src6("ph_mux_clk"), + .c_cnt_bypass_en6("true"), + .c_cnt_odd_div_duty_en6("false"), + .c_cnt_hi_div7(1), + .c_cnt_lo_div7(1), + .c_cnt_prst7(1), + .c_cnt_ph_mux_prst7(0), + .c_cnt_in_src7("ph_mux_clk"), + .c_cnt_bypass_en7("true"), + .c_cnt_odd_div_duty_en7("false"), + .c_cnt_hi_div8(1), + .c_cnt_lo_div8(1), + .c_cnt_prst8(1), + .c_cnt_ph_mux_prst8(0), + .c_cnt_in_src8("ph_mux_clk"), + .c_cnt_bypass_en8("true"), + .c_cnt_odd_div_duty_en8("false"), + .c_cnt_hi_div9(1), + .c_cnt_lo_div9(1), + .c_cnt_prst9(1), + .c_cnt_ph_mux_prst9(0), + .c_cnt_in_src9("ph_mux_clk"), + .c_cnt_bypass_en9("true"), + .c_cnt_odd_div_duty_en9("false"), + .c_cnt_hi_div10(1), + .c_cnt_lo_div10(1), + .c_cnt_prst10(1), + .c_cnt_ph_mux_prst10(0), + .c_cnt_in_src10("ph_mux_clk"), + .c_cnt_bypass_en10("true"), + .c_cnt_odd_div_duty_en10("false"), + .c_cnt_hi_div11(1), + .c_cnt_lo_div11(1), + .c_cnt_prst11(1), + .c_cnt_ph_mux_prst11(0), + .c_cnt_in_src11("ph_mux_clk"), + .c_cnt_bypass_en11("true"), + .c_cnt_odd_div_duty_en11("false"), + .c_cnt_hi_div12(1), + .c_cnt_lo_div12(1), + .c_cnt_prst12(1), + .c_cnt_ph_mux_prst12(0), + .c_cnt_in_src12("ph_mux_clk"), + .c_cnt_bypass_en12("true"), + .c_cnt_odd_div_duty_en12("false"), + .c_cnt_hi_div13(1), + .c_cnt_lo_div13(1), + .c_cnt_prst13(1), + .c_cnt_ph_mux_prst13(0), + .c_cnt_in_src13("ph_mux_clk"), + .c_cnt_bypass_en13("true"), + .c_cnt_odd_div_duty_en13("false"), + .c_cnt_hi_div14(1), + .c_cnt_lo_div14(1), + .c_cnt_prst14(1), + .c_cnt_ph_mux_prst14(0), + .c_cnt_in_src14("ph_mux_clk"), + .c_cnt_bypass_en14("true"), + .c_cnt_odd_div_duty_en14("false"), + .c_cnt_hi_div15(1), + .c_cnt_lo_div15(1), + .c_cnt_prst15(1), + .c_cnt_ph_mux_prst15(0), + .c_cnt_in_src15("ph_mux_clk"), + .c_cnt_bypass_en15("true"), + .c_cnt_odd_div_duty_en15("false"), + .c_cnt_hi_div16(1), + .c_cnt_lo_div16(1), + .c_cnt_prst16(1), + .c_cnt_ph_mux_prst16(0), + .c_cnt_in_src16("ph_mux_clk"), + .c_cnt_bypass_en16("true"), + .c_cnt_odd_div_duty_en16("false"), + .c_cnt_hi_div17(1), + .c_cnt_lo_div17(1), + .c_cnt_prst17(1), + .c_cnt_ph_mux_prst17(0), + .c_cnt_in_src17("ph_mux_clk"), + .c_cnt_bypass_en17("true"), + .c_cnt_odd_div_duty_en17("false"), + .pll_vco_div(2), + .pll_cp_current(20), + .pll_bwctrl(4000), + .pll_output_clk_frequency("445.499999 MHz"), + .pll_fractional_division("3908420153"), + .mimic_fbclk_type("none"), + .pll_fbclk_mux_1("glb"), + .pll_fbclk_mux_2("m_cnt"), + .pll_m_cnt_in_src("ph_mux_clk"), + .pll_slf_rst("true") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_0}), + .locked (locked), + .reconfig_to_pll (reconfig_to_pll), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk), + .reconfig_from_pll (reconfig_from_pll) + ); +endmodule + diff --git a/sys/pll_hdmi_adj.vhd b/sys/pll_hdmi_adj.vhd new file mode 100644 index 0000000..67287cb --- /dev/null +++ b/sys/pll_hdmi_adj.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +-- HDMI PLL Adjust +-------------------------------------------------------------------------------- + +-- Changes the HDMI PLL frequency according to the scaler suggestions. +-------------------------------------------- +-- LLTUNE : +-- 0 : Input Display Enable +-- 1 : Input Vsync +-- 2 : Input Interlaced mode +-- 3 : Input Interlaced field +-- 4 : Output Image frame +-- 5 : +-- 6 : Input clock +-- 7 : Output clock + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY pll_hdmi_adj IS + PORT ( + -- Scaler + llena : IN std_logic; -- 0=Disabled 1=Enabled + lltune : IN unsigned(15 DOWNTO 0); -- Outputs from scaler + + locked : OUT std_logic; + + -- Signals from reconfig commands + i_waitrequest : OUT std_logic; + i_write : IN std_logic; + i_address : IN unsigned(5 DOWNTO 0); + i_writedata : IN unsigned(31 DOWNTO 0); + + -- Outputs to PLL_HDMI_CFG + o_waitrequest : IN std_logic; + o_write : OUT std_logic; + o_address : OUT unsigned(5 DOWNTO 0); + o_writedata : OUT unsigned(31 DOWNTO 0); + + ------------------------------------ + clk : IN std_logic; + reset_na : IN std_logic + ); + +BEGIN + + +END ENTITY pll_hdmi_adj; + +--############################################################################## + +ARCHITECTURE rtl OF pll_hdmi_adj IS + + SIGNAL i_clk,i_de,i_de2,i_vss,i_vss2,i_vss_delay,i_ce : std_logic; + SIGNAL i_linecpt,i_line : natural RANGE 0 TO 2**12-1; + SIGNAL i_delay : natural RANGE 0 TO 2**14-1; + + SIGNAL pwrite : std_logic; + SIGNAL paddress : unsigned(5 DOWNTO 0); + SIGNAL pdata : unsigned(31 DOWNTO 0); + TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6); + SIGNAL state : enum_state; + SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0); + SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0); + SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0); + SIGNAL mul : unsigned(15 DOWNTO 0); + SIGNAL sign,sign_pre : std_logic; + SIGNAL expand : boolean; + SIGNAL up,modo,phm,dir : std_logic; + SIGNAL cpt : natural RANGE 0 TO 3; + SIGNAL col : natural RANGE 0 TO 15; + + SIGNAL icpt,ocpt,o2cpt,ssh,ofsize,ifsize : natural RANGE 0 TO 2**24-1; + SIGNAL ivss,ivss2,itog : std_logic; + SIGNAL ovss,ovss2,otog : std_logic; + SIGNAL sync,pulse,los,lop : std_logic; + SIGNAL osize,offset,osizep,offsetp : signed(23 DOWNTO 0); + SIGNAL logcpt : natural RANGE 0 TO 31; + SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0; + +BEGIN + + ---------------------------------------------------------------------------- + -- 4 lines delay to input + i_vss<=lltune(0); + i_de <=lltune(1); + i_ce <=lltune(5); + i_clk<=lltune(6); + + Delay:PROCESS(i_clk) IS + BEGIN + IF rising_edge(i_clk) THEN + IF i_ce='1' THEN + -- Measure input line time. + i_de2<=i_de; + + IF i_de='1' AND i_de2='0' THEN + i_linecpt<=0; + IF i_vss='1' THEN + i_line<=i_linecpt; + END IF; + ELSE + i_linecpt<=i_linecpt+1; + END IF; + + -- Delay 4 lines + i_vss2<=i_vss; + IF i_vss/=i_vss2 THEN + i_delay<=0; + ELSIF i_delay=i_line * 4 THEN + i_vss_delay<=i_vss; + ELSE + i_delay<=i_delay+1; + END IF; + END IF; + END IF; + END PROCESS Delay; + + ---------------------------------------------------------------------------- + -- Sample image sizes + Sampler:PROCESS(clk,reset_na) IS + BEGIN + IF reset_na='0' THEN +--pragma synthesis_off + otog<='0'; + itog<='0'; + ivss<='0'; + ivss2<='0'; + ovss<='0'; + ovss2<='0'; +--pragma synthesis_on + + ELSIF rising_edge(clk) THEN + -- Clock domain crossing + + ivss<=i_vss_delay; -- + ivss2<=ivss; + + ovss<=lltune(4); -- + ovss2<=ovss; + + otog<=otog XOR (ovss AND NOT ovss2); + + -- Measure output frame time + IF ovss='1' AND ovss2='0' AND otog='1' THEN + ocpt<=0; + osizep<=to_signed(ocpt,24); + ELSE + ocpt<=ocpt+1; + END IF; + IF ovss='0' AND ovss2='1' AND otog='0' THEN + o2cpt<=0; + ELSE + o2cpt<=o2cpt+1; + END IF; + + -- Measure output image time + IF ovss='0' AND ovss2='1' AND otog='0' THEN + ofsize<=ocpt; + END IF; + + itog<=itog XOR (ivss AND NOT ivss2); + + -- Measure input frame time + IF ivss='1' AND ivss2='0' AND itog='1' THEN + icpt<=0; + osize<=osizep; + udiff<=integer(to_integer(osizep)) - integer(icpt); + sync<='1'; + ELSE + icpt<=icpt+1; + sync<='0'; + END IF; + + -- Measure input image time + IF ivss='0' AND ivss2='1' AND itog='0' THEN + ifsize<=icpt; + END IF; + + expand<=(ofsize>=ifsize); + -- IN | ######### | EXPAND = 1 + -- OUT | ############# | + + -- IN | ######### | EXPAND = 0 + -- OUT | ###### | + + IF expand THEN + IF ivss='1' AND ivss2='0' AND itog='1' THEN + offset<=to_signed(ocpt,24); + END IF; + ELSE + IF ivss='0' AND ivss2='1' AND itog='0' THEN + offset<=to_signed(o2cpt,24); + END IF; + END IF; + + -------------------------------------------- + pulse<='0'; + IF sync='1' THEN + logcpt<=0; + ssh<=to_integer(osize); + los<='0'; + lop<='0'; + + ELSIF logcpt<24 THEN + -- Frequency difference + IF udiff>0 AND ssh=osize/2 AND ssh<(osize-offset) AND lop='0' THEN + tune_phase<='1' & to_unsigned(logcpt,5); + lop<='1'; + END IF; + ssh<=ssh/2; + logcpt<=logcpt+1; + + ELSIF logcpt=24 THEN + pulse<='1'; + ssh<=ssh/2; + logcpt<=logcpt+1; + END IF; + + END IF; + END PROCESS Sampler; + + ---------------------------------------------------------------------------- + -- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf. + -- 000100 : M counter + -- 000111 : M counter Fractional Value K + + Comb:PROCESS(i_write,i_address, + i_writedata,pwrite,paddress,pdata) IS + BEGIN + IF i_write='1' THEN + o_write <=i_write; + o_address <=i_address; + o_writedata <=i_writedata; + ELSE + o_write <=pwrite; + o_address <=paddress; + o_writedata<=pdata; + END IF; + END PROCESS Comb; + + i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0'; + + ---------------------------------------------------------------------------- + Schmurtz:PROCESS(clk,reset_na) IS + VARIABLE off_v,ofp_v : natural RANGE 0 TO 63; + VARIABLE diff_v : unsigned(40 DOWNTO 0); + VARIABLE mulco : unsigned(15 DOWNTO 0); + VARIABLE up_v,sign_v : std_logic; + BEGIN + IF reset_na='0' THEN + modo<='0'; + state<=sIDLE; + ELSIF rising_edge(clk) THEN + ------------------------------------------------------ + -- Snoop accesses to PLL reconfiguration + IF i_address="000100" AND i_write='1' THEN + mfrac (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) + + ('0' & i_writedata(7 DOWNTO 0)); + mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) + + ('0' & i_writedata(7 DOWNTO 0)); + mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) + + ('0' & i_writedata(7 DOWNTO 0)); + mul<=i_writedata(15 DOWNTO 0); + modo<='1'; + END IF; + + IF i_address="000111" AND i_write='1' THEN + mfrac (31 DOWNTO 0)<=i_writedata; + mfrac_ref(31 DOWNTO 0)<=i_writedata; + mfrac_mem(31 DOWNTO 0)<=i_writedata; + modo<='1'; + END IF; + + ------------------------------------------------------ + -- Tuning + off_v:=to_integer('0' & tune_freq(4 DOWNTO 0)); + ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0)); + --IF off_v<8 THEN off_v:=8; END IF; + --IF ofp_v<7 THEN ofp_v:=7; END IF; + IF off_v<4 THEN off_v:=4; END IF; + IF ofp_v<4 THEN ofp_v:=4; END IF; + + IF off_v>=18 AND ofp_v>=18 THEN + locked<=llena; + ELSE + locked<='0'; + END IF; + + up_v:='0'; + IF pulse='1' THEN + cpt<=(cpt+1) MOD 4; + IF llena='0' THEN + -- Recover original freq when disabling low lag mode + cpt<=0; + col<=0; + IF modo='1' THEN + mfrac<=mfrac_mem; + mfrac_ref<=mfrac_mem; + up<='1'; + modo<='0'; + END IF; + + ELSIF phm='0' AND cpt=0 THEN + -- Frequency adjust + sign_v:=tune_freq(5); + IF col<10 THEN col<=col+1; END IF; + IF off_v>=16 AND col>=10 THEN + phm<='1'; + col<=0; + ELSE + off_v:=off_v+1; + IF off_v>17 THEN + off_v:=off_v + 3; + END IF; + up_v:='1'; + up<='1'; + END IF; + + ELSIF cpt=0 THEN + -- Phase adjust + sign_v:=NOT tune_phase(5); + col<=col+1; + IF col>=10 THEN + phm<='0'; + up_v:='1'; + off_v:=31; + col<=0; + ELSE + off_v:=ofp_v + 1; + IF ofp_v>7 THEN + off_v:=off_v + 1; + END IF; + IF ofp_v>14 THEN + off_v:=off_v + 2; + END IF; + IF ofp_v>17 THEN + off_v:=off_v + 3; + END IF; + up_v:='1'; + END IF; + up<='1'; + END IF; + END IF; + + diff_v:=shift_right(mfrac_ref,off_v); + IF sign_v='0' THEN + diff_v:=mfrac_ref + diff_v; + ELSE + diff_v:=mfrac_ref - diff_v; + END IF; + + IF up_v='1' THEN + mfrac<=diff_v; + END IF; + + IF up_v='1' AND phm='0' THEN + mfrac_ref<=diff_v; + END IF; + + ------------------------------------------------------ + -- Update PLL registers + mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32))); + + CASE state IS + WHEN sIDLE => + pwrite<='0'; + IF up='1' THEN + up<='0'; + IF mulco/=mul THEN + state<=sW1; + ELSE + state<=sW3; + END IF; + END IF; + + WHEN sW1 => -- Change M multiplier + mul<=mulco; + pdata<=x"0000" & mulco; + paddress<="000100"; + pwrite<='1'; + state<=sW2; + + WHEN sW2 => + IF pwrite='1' AND o_waitrequest='0' THEN + state<=sW3; + pwrite<='0'; + END IF; + + WHEN sW3 => -- Change M fractional value + pdata<=mfrac(31 DOWNTO 0); + paddress<="000111"; + pwrite<='1'; + state<=sW4; + + WHEN sW4 => + IF pwrite='1' AND o_waitrequest='0' THEN + state<=sW5; + pwrite<='0'; + END IF; + + WHEN sW5 => + pdata<=x"0000_0001"; + paddress<="000010"; + pwrite<='1'; + state<=sW6; + + WHEN sW6 => + IF pwrite='1' AND o_waitrequest='0' THEN + pwrite<='0'; + state<=sIDLE; + END IF; + END CASE; + + END IF; + END PROCESS Schmurtz; + + ---------------------------------------------------------------------------- + +END ARCHITECTURE rtl; + diff --git a/sys/pll_q13.qip b/sys/pll_q13.qip new file mode 100644 index 0000000..13a7ed4 --- /dev/null +++ b/sys/pll_q13.qip @@ -0,0 +1,6 @@ +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] diff --git a/sys/pll_q17.qip b/sys/pll_q17.qip new file mode 100644 index 0000000..85cc84b --- /dev/null +++ b/sys/pll_q17.qip @@ -0,0 +1,4 @@ +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] diff --git a/sys/scandoubler.v b/sys/scandoubler.v index 46274f5..81e7c3f 100644 --- a/sys/scandoubler.v +++ b/sys/scandoubler.v @@ -2,7 +2,7 @@ // scandoubler.v // // Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig +// Copyright (c) 2017-2021 Alexey Melnikov // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published @@ -22,24 +22,21 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) ( // system interface - input clk_sys, - input ce_pix, - output ce_pix_out, - + input clk_vid, input hq2x, // shifter video interface + input ce_pix, input hs_in, input vs_in, input hb_in, input vb_in, - input [DWIDTH:0] r_in, input [DWIDTH:0] g_in, input [DWIDTH:0] b_in, - input mono, // output interface + output ce_pix_out, output reg hs_out, output vs_out, output hb_out, @@ -49,141 +46,166 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) output [DWIDTH:0] b_out ); - localparam DWIDTH = HALF_DEPTH ? 3 : 7; -assign vs_out = vso[3]; -assign ce_pix_out = hq2x ? ce_x4 : ce_x2; - -//Compensate picture shift after HQ2x -assign vb_out = vbo[2]; -assign hb_out = hbo[6]; - reg [7:0] pix_len = 0; wire [7:0] pl = pix_len + 1'b1; -reg ce_x1, ce_x4, ce_x2; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; +reg [7:0] pix_in_cnt = 0; +wire [7:0] pc_in = pix_in_cnt + 1'b1; +reg [7:0] pixsz, pixsz2, pixsz4 = 0; - reg [7:0] pixsz2, pixsz4 = 0; +reg ce_x4i, ce_x1i; +always @(posedge clk_vid) begin + reg old_ce, valid, hs; + + if(~&pix_len) pix_len <= pl; + if(~&pix_in_cnt) pix_in_cnt <= pc_in; + + ce_x4i <= 0; + ce_x1i <= 0; + + // use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4. + if((pc_in == pixsz4) || (pc_in == pixsz2) || (pc_in == (pixsz2+pixsz4))) ce_x4i <= 1; old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x2 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - ce_x4 <= 1; - end - - if(pl == pixsz2) begin - ce_x2 <= 1; - end - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x2 <= 1; - ce_x4 <= 1; + if(valid & ~hb_in & ~vb_in) begin + pixsz <= pl; + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + end pix_len <= 0; + valid <= 1; + end + + hs <= hs_in; + if((~hs & hs_in) || (pc_in >= pixsz)) begin + ce_x4i <= 1; + ce_x1i <= 1; + pix_in_cnt <= 0; + end + + if(hb_in | vb_in) valid <= 0; +end + +reg req_line_reset; +reg [DWIDTH:0] r_d, g_d, b_d; +always @(posedge clk_vid) begin + if(ce_x1i) begin + req_line_reset <= hb_in; + r_d <= r_in; + g_d <= g_in; + b_d <= b_in; end end Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x ( - .clk(clk_sys), - .ce_x4(ce_x4), + .clk(clk_vid), + + .ce_in(ce_x4i), .inputpixel({b_d,g_d,r_d}), - .mono(mono), .disable_hq2x(~hq2x), - .reset_frame(vs_in), + .reset_frame(vb_in), .reset_line(req_line_reset), + + .ce_out(ce_x4o), .read_y(sd_line), - .hblank(hbo[0]&hbo[4]), + .hblank(hbo[0]&hbo[8]), .outpixel({b_out,g_out,r_out}) ); -reg [1:0] sd_line; -reg [2:0] vbo; -reg [6:0] hbo; +reg [7:0] pix_out_cnt = 0; +wire [7:0] pc_out = pix_out_cnt + 1'b1; -reg [DWIDTH:0] r_d; -reg [DWIDTH:0] g_d; -reg [DWIDTH:0] b_d; +reg ce_x4o, ce_x2o; +always @(posedge clk_vid) begin + reg hs; -reg [3:0] vso; + if(~&pix_out_cnt) pix_out_cnt <= pc_out; -reg req_line_reset; -always @(posedge clk_sys) begin + ce_x4o <= 0; + ce_x2o <= 0; - reg [11:0] hs_max,hs_rise; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - reg [11:0] hde_start, hde_end; + // use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4. + if((pc_out == pixsz4) || (pc_out == pixsz2) || (pc_out == (pixsz2+pixsz4))) ce_x4o <= 1; + if( pc_out == pixsz2) ce_x2o <= 1; - reg hs, hs2, vs, hb; - - if(ce_x1) begin - hs <= hs_in; - hb <= hb_in; - - req_line_reset <= hb_in; - - r_d <= r_in; - g_d <= g_in; - b_d <= b_in; - - if(hb && !hb_in) begin - hde_start <= {hcnt,1'b0}; - vbo <= {vbo[1:0], vb_in}; - end - if(!hb && hb_in) hde_end <= {hcnt,1'b0}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - vso <= (vso<<1) | vs_in; - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - hbo[6:1] <= hbo[5:0]; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - - //prepare to read in advance - if(sd_hcnt == (hde_start-2)) begin - sd_line <= sd_line + 1'd1; - end - - if(sd_hcnt == hde_start) hbo[0] <= 0; - if(sd_hcnt == hde_end) hbo[0] <= 1; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; + hs <= hs_out; + if((~hs & hs_out) || (pc_out >= pixsz)) begin + ce_x2o <= 1; + ce_x4o <= 1; + pix_out_cnt <= 0; end end +reg [1:0] sd_line; +reg [3:0] vbo; +reg [3:0] vso; +reg [8:0] hbo; +always @(posedge clk_vid) begin + + reg [31:0] hcnt; + reg [30:0] sd_hcnt; + reg [30:0] hs_start, hs_end; + reg [30:0] hde_start, hde_end; + + reg hs, hb; + + if(ce_x4o) begin + hbo[8:1] <= hbo[7:0]; + end + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + if(sd_hcnt == hde_start) begin + sd_hcnt <= 0; + vbo[3:1] <= vbo[2:0]; + end + + if(sd_hcnt == hs_end) begin + sd_line <= sd_line + 1'd1; + if(&vbo[3:2]) sd_line <= 1; + vso[3:1] <= vso[2:0]; + end + + if(sd_hcnt == hde_start)hbo[0] <= 0; + if(sd_hcnt == hde_end) hbo[0] <= 1; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_end) hs_out <= 0; + if(sd_hcnt == hs_start) hs_out <= 1; + + hs <= hs_in; + hb <= hb_in; + + hcnt <= hcnt + 1'd1; + if(hb && !hb_in) begin + hde_start <= hcnt[31:1]; + hbo[0] <= 0; + hcnt <= 0; + sd_hcnt <= 0; + vbo <= {vbo[2:0],vb_in}; + end + + if(!hb && hb_in) hde_end <= hcnt[31:1]; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_end <= hcnt[31:1]; + vso[0] <= vs_in; + end + + // save position of rising edge + if(!hs && hs_in) hs_start <= hcnt[31:1]; +end + +assign vs_out = vso[3]; +assign ce_pix_out = hq2x ? ce_x4o : ce_x2o; + +//Compensate picture shift after HQ2x +assign vb_out = vbo[3]; +assign hb_out = hbo[6]; + endmodule diff --git a/sys/scanlines.v b/sys/scanlines.v new file mode 100644 index 0000000..59d29bd --- /dev/null +++ b/sys/scanlines.v @@ -0,0 +1,67 @@ +module scanlines #(parameter v2=0) +( + input clk, + + input [1:0] scanlines, + input [23:0] din, + input hs_in,vs_in, + input de_in, + + output reg [23:0] dout, + output reg hs_out,vs_out, + output reg de_out +); + +reg [1:0] scanline; +always @(posedge clk) begin + reg old_hs, old_vs; + + old_hs <= hs_in; + old_vs <= vs_in; + + if(old_hs && ~hs_in) begin + if(v2) begin + scanline <= scanline + 1'd1; + if (scanline == scanlines) scanline <= 0; + end + else scanline <= scanline ^ scanlines; + end + if(old_vs && ~vs_in) scanline <= 0; +end + +wire [7:0] r,g,b; +assign {r,g,b} = din; + +reg [23:0] d; +always @(*) begin + case(scanline) + 1: // reduce 25% = 1/2 + 1/4 + d = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, + {1'b0, g[7:1]} + {2'b00, g[7:2]}, + {1'b0, b[7:1]} + {2'b00, b[7:2]}}; + + 2: // reduce 50% = 1/2 + d = {{1'b0, r[7:1]}, + {1'b0, g[7:1]}, + {1'b0, b[7:1]}}; + + 3: // reduce 75% = 1/4 + d = {{2'b00, r[7:2]}, + {2'b00, g[7:2]}, + {2'b00, b[7:2]}}; + + default: d = {r,g,b}; + endcase +end + +always @(posedge clk) begin + reg [23:0] dout1, dout2; + reg de1,de2,vs1,vs2,hs1,hs2; + + dout <= dout2; dout2 <= dout1; dout1 <= d; + vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in; + hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in; + de_out <= de2; de2 <= de1; de1 <= de_in; +end + +endmodule diff --git a/sys/sd_card.sv b/sys/sd_card.sv new file mode 100644 index 0000000..8cb0560 --- /dev/null +++ b/sys/sd_card.sv @@ -0,0 +1,463 @@ +// +// sd_card.v +// +// Copyright (c) 2014 Till Harbaum +// Copyright (c) 2015-2018 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the Lesser GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// http://elm-chan.org/docs/mmc/mmc_e.html +// +///////////////////////////////////////////////////////////////////////// + +// +// Made module syncrhronous. Total code refactoring. (Sorgelig) +// clk_spi must be at least 2 x sck for proper work. + +module sd_card #(parameter WIDE = 0, OCTAL=0) +( + input clk_sys, + input reset, + + input sdhc, + input img_mounted, + input [63:0] img_size, + + output reg [31:0] sd_lba, + output reg sd_rd, + output reg sd_wr, + input sd_ack, + + input [AW:0] sd_buff_addr, + input [DW:0] sd_buff_dout, + output [DW:0] sd_buff_din, + input sd_buff_wr, + + // SPI interface + input clk_spi, + + input ss, + input sck, + input [SW:0] mosi, + output reg [SW:0] miso +); + +localparam AW = WIDE ? 7 : 8; +localparam DW = WIDE ? 15 : 7; +localparam SZ = OCTAL ? 8 : 1; +localparam SW = SZ-1; + +wire [7:0] DATA_TOKEN_CMD25 = 8'hfc; +wire [7:0] STOP_TRAN = 8'hfd; +wire [7:0] DATA_TOKEN = 8'hfe; +wire [7:0] WRITE_DATA_RESPONSE = 8'h05; + +// number of bytes to wait after a command before sending the reply +localparam NCR = 5+3; // 5 bytes are required (command length) + +localparam RD_STATE_IDLE = 0; +localparam RD_STATE_START = 1; +localparam RD_STATE_WAIT_IO = 2; +localparam RD_STATE_SEND_TOKEN = 3; +localparam RD_STATE_SEND_DATA = 4; +localparam RD_STATE_WAIT_M = 5; + +localparam WR_STATE_IDLE = 0; +localparam WR_STATE_EXP_DTOKEN = 1; +localparam WR_STATE_RECV_DATA = 2; +localparam WR_STATE_RECV_CRC0 = 3; +localparam WR_STATE_RECV_CRC1 = 4; +localparam WR_STATE_SEND_DRESP = 5; +localparam WR_STATE_BUSY = 6; + +localparam PREF_STATE_IDLE = 0; +localparam PREF_STATE_RD = 1; +localparam PREF_STATE_FINISH = 2; + +altsyncram sdbuf +( + .clock0 (clk_sys), + .address_a ({sd_buf,sd_buff_addr}), + .data_a (sd_buff_dout), + .wren_a (sd_ack & sd_buff_wr), + .q_a (sd_buff_din), + + .clock1 (clk_spi), + .address_b ({spi_buf,buffer_ptr}), + .data_b (buffer_din), + .wren_b (buffer_wr), + .q_b (buffer_dout), + + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .eccstatus(), + .rden_a(1'b1), + .rden_b(1'b1) +); +defparam + sdbuf.numwords_a = 1<<(AW+3), + sdbuf.widthad_a = AW+3, + sdbuf.width_a = DW+1, + sdbuf.numwords_b = 2048, + sdbuf.widthad_b = 11, + sdbuf.width_b = 8, + sdbuf.address_reg_b = "CLOCK1", + sdbuf.clock_enable_input_a = "BYPASS", + sdbuf.clock_enable_input_b = "BYPASS", + sdbuf.clock_enable_output_a = "BYPASS", + sdbuf.clock_enable_output_b = "BYPASS", + sdbuf.indata_reg_b = "CLOCK1", + sdbuf.intended_device_family = "Cyclone V", + sdbuf.lpm_type = "altsyncram", + sdbuf.operation_mode = "BIDIR_DUAL_PORT", + sdbuf.outdata_aclr_a = "NONE", + sdbuf.outdata_aclr_b = "NONE", + sdbuf.outdata_reg_a = "UNREGISTERED", + sdbuf.outdata_reg_b = "UNREGISTERED", + sdbuf.power_up_uninitialized = "FALSE", + sdbuf.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + sdbuf.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + sdbuf.width_byteena_a = 1, + sdbuf.width_byteena_b = 1, + sdbuf.wrcontrol_wraddress_reg_b = "CLOCK1"; + +reg [26:0] csd_size; +reg csd_sdhc; +always @(posedge clk_sys) begin + if (img_mounted) begin + csd_sdhc <= sdhc; + if (sdhc) begin + csd_size[0] <= 0; + csd_size[22:1] <= img_size[40:19]; // in 512K units + csd_size[26:23] <= 0; + end + else begin + csd_size[2:0] <= 7; // C_SIZE_MULT + csd_size[14:3] <= 12'b101101101101; + csd_size[26:15] <= img_size[29:18]; // in 256K units ((2**(C_SIZE_MULT+2))*512) + end + end +end + +wire [127:0] CSD = {1'b0,csd_sdhc,6'h00,8'h0e,8'h00,8'h32,8'h5b,8'h59,6'h00,csd_size,7'h7f,8'h80,8'h0a,8'h40,8'h40,8'hf1}; +wire [127:0] CID = {8'hcd,8'hc7,8'h00,8'h93,8'h6f,8'h2f,8'h73,8'h00,8'h00,8'h44,8'h32,8'h38,8'h34,8'h00,8'h00,8'h3e}; + +reg [8:0] buffer_ptr; +reg [7:0] buffer_din; +wire [7:0] buffer_dout; +reg buffer_wr; + +reg [1:0] sd_buf, spi_buf; + +reg [6:0] sbuf; +reg [2:0] bit_cnt; + +wire last_bit = &bit_cnt || OCTAL; +wire [7:0] ibuf = OCTAL ? mosi : {sbuf,mosi[0]}; + +always @(posedge clk_spi) begin + reg [2:0] read_state; + reg [2:0] write_state; + reg [1:0] pref_state; + reg [5:0] cmd; + reg cmd55; + reg [39:0] reply; + reg [3:0] byte_cnt; + reg old_sck; + reg [2:0] ack; + reg [2:0] wait_m_cnt; + reg [31:0] arg; + + ack[1:0] <= {ack[0],sd_ack}; + if(ack[1] == ack[0]) ack[2] <= ack[1]; + + if(~ack[2] & ack[1]) {sd_rd,sd_wr} <= 0; + if( ack[2] & ~ack[1]) begin + sd_buf <= sd_buf + 1'd1; + sd_lba <= sd_lba + 1; + end + + buffer_wr <= 0; + + if(reset) begin + bit_cnt <= 0; + byte_cnt <= '1; + miso <= '1; + cmd <= 0; + sd_wr <= 0; + sd_rd <= 0; + read_state <= RD_STATE_IDLE; + write_state <= WR_STATE_IDLE; + pref_state <= PREF_STATE_IDLE; + end + else begin + + if(buffer_wr) begin + if(~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1; + else begin + spi_buf <= spi_buf + 1'd1; + sd_wr <= 1; + end + end + + case(pref_state) + PREF_STATE_IDLE: + if(((sd_buf - spi_buf) <= 1) && (read_state != RD_STATE_IDLE) && (cmd == 17 || cmd == 18)) begin + sd_rd <= 1; + pref_state <= PREF_STATE_RD; + end + + PREF_STATE_RD: + if(read_state == RD_STATE_IDLE) begin + pref_state <= PREF_STATE_IDLE; + end + else if(ack[2] & ~ack[1]) begin + pref_state <= (cmd == 18) ? PREF_STATE_IDLE : PREF_STATE_FINISH; + end + + PREF_STATE_FINISH: + if(read_state == RD_STATE_IDLE) begin + pref_state <= PREF_STATE_IDLE; + end + endcase + + old_sck <= sck; + if(ss) begin + bit_cnt <= 0; + byte_cnt <= '1; + miso <= '1; + end + else if(old_sck & ~sck) begin + miso <= '1; // default: send 1's (busy/wait) + if(byte_cnt >= NCR) {miso,reply} <= {reply, {SZ{1'b1}}}; + + // ---------- read state machine processing ------------- + case(read_state) + RD_STATE_IDLE: ; + + RD_STATE_START: begin + if(byte_cnt == NCR && last_bit) read_state <= (cmd == 9 || cmd == 10) ? RD_STATE_SEND_TOKEN : RD_STATE_WAIT_IO; + end + + // waiting for io controller to return data + RD_STATE_WAIT_IO: begin + if(sd_buf != spi_buf && last_bit) read_state <= RD_STATE_SEND_TOKEN; + end + + // send data token + RD_STATE_SEND_TOKEN: begin + miso <= DATA_TOKEN[~bit_cnt -:SZ]; + if(last_bit) begin + read_state <= RD_STATE_SEND_DATA; // next: send data + buffer_ptr <= 0; + end + end + + // send data + RD_STATE_SEND_DATA: begin + + miso <= (cmd == 9) ? CSD[{buffer_ptr[3:0],~bit_cnt} -:SZ] : (cmd == 10) ? CID[{buffer_ptr[3:0],~bit_cnt} -:SZ] : buffer_dout[~bit_cnt -:SZ]; + + if(last_bit) begin + + // sent 512 sector data bytes? + if(cmd == 17 && &buffer_ptr) read_state <= RD_STATE_IDLE; + else if(cmd == 18 && &buffer_ptr) begin + read_state <= RD_STATE_WAIT_M; + wait_m_cnt <= 0; + end + + // sent 16 cid/csd data bytes? + else if((cmd == 9 || cmd == 10) && &buffer_ptr[3:0]) read_state <= RD_STATE_IDLE; + + // not done yet -> trigger read of next data byte + else buffer_ptr <= buffer_ptr + 1'd1; + end + end + + RD_STATE_WAIT_M: begin + if(last_bit) begin + wait_m_cnt <= wait_m_cnt + 1'd1; + if(&wait_m_cnt) begin + spi_buf <= spi_buf + 1'd1; + read_state <= RD_STATE_WAIT_IO; + end + end + end + endcase + + // ------------------ write support ---------------------- + // send write data response + if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt -:SZ]; + + // busy after write until the io controller sends ack + if(write_state == WR_STATE_BUSY) miso <= 0; + end + else if(~old_sck & sck) begin + + sbuf[6:0] <= {sbuf[5:0],mosi[0]}; + bit_cnt <= bit_cnt + SZ[2:0]; + + if(last_bit) begin + // finished reading one byte + // byte counter runs against 15 byte boundary + if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1; + + // byte_cnt > 6 -> complete command received + // first byte of valid command is 01xxxxxx + // don't accept new commands once a write or read command has been accepted + if(byte_cnt > 5 && + ((write_state == WR_STATE_IDLE && read_state == RD_STATE_IDLE && ibuf[7:6] == 1) || + (read_state != RD_STATE_IDLE && ibuf == 8'h4c))) begin + byte_cnt <= 0; + cmd <= ibuf[5:0]; + cmd55 <= (cmd == 55); // set cmd55 flag if previous command was 55 + if(ibuf[5:0] == 12) read_state <= RD_STATE_IDLE; + end + + // parse additional command bytes + if(byte_cnt == 0) arg[31:24] <= ibuf; + if(byte_cnt == 1) arg[23:16] <= ibuf; + if(byte_cnt == 2) arg[15:8] <= ibuf; + if(byte_cnt == 3) arg[7:0] <= ibuf; + + // last byte (crc) received, evaluate + if(byte_cnt == 4) begin + + // default: + reply <= 40'h04FFFFFFFF; // illegal command + + case(cmd) + // CMD0: GO_IDLE_STATE + 0: reply[39:32] <= 1; // ok, busy + + // CMD1: SEND_OP_COND + 1: reply[39:32] <= 0; + + // CMD8: SEND_IF_COND (V2 only) + 8: reply <= 40'h01000001AA; // ok, busy + + // CMD9: SEND_CSD + 9, + // CMD10: SEND_CID + 10: begin + reply[39:32] <= 0; + read_state <= RD_STATE_START; + end + + // CMD12: STOP_TRANSMISSION + 12: reply[39:32] <= 0; + + // CMD13: SEND_STATUS + 13: reply[39:24] <= 16'h0000; + + // CMD16: SET_BLOCKLEN + 16: reply[39:32] <= (arg == 512) ? 8'h00 : 8'h40; // we only support a block size of 512 + + // CMD17: READ_SINGLE_BLOCK + 17, + // CMD18: READ_MULTIPLE + 18: begin + reply[39:32] <= 0; + read_state <= RD_STATE_START; + spi_buf <= 0; + sd_buf <= 0; + sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]}; + end + + // ACMD23: SET_WR_BLK_ERASE_COUNT + 23: reply[39:32] <= 0; + + // CMD24: WRITE_BLOCK + 24, + // CMD25: WRITE_MULTIPLE + 25: begin + reply[39:32] <= 0; + write_state <= WR_STATE_EXP_DTOKEN; // expect data token + spi_buf <= 0; + sd_buf <= 0; + sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]}; + end + + // ACMD41: APP_SEND_OP_COND + 41: if(cmd55) reply[39:32] <= 0; // ok, not busy + + // CMD55: APP_COND + 55: reply[39:32] <= 1; // ok, busy + + // CMD58: READ_OCR + 58: reply <= { 8'h00, 1'b1, csd_sdhc, 30'd0 }; // bit 30 = 1 -> high capacity card + + // CMD59: CRC_ON_OFF + 59: reply[39:32] <= 0; + endcase + end + + // ---------- handle write ----------- + case(write_state) + // do nothing in idle state + WR_STATE_IDLE: ; + + // waiting for data token + WR_STATE_EXP_DTOKEN: begin + buffer_ptr <= 0; + if(cmd == 24) begin + if(ibuf == DATA_TOKEN) write_state <= WR_STATE_RECV_DATA; + end + else begin + if(ibuf == DATA_TOKEN_CMD25) write_state <= WR_STATE_RECV_DATA; + if(ibuf == STOP_TRAN) write_state <= WR_STATE_IDLE; + end + end + + // transfer 512 bytes + WR_STATE_RECV_DATA: begin + // push one byte into local buffer + buffer_wr <= 1; + buffer_din <= ibuf; + + // all bytes written? + if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0; + end + + // transfer 1st crc byte + WR_STATE_RECV_CRC0: + write_state <= WR_STATE_RECV_CRC1; + + // transfer 2nd crc byte + WR_STATE_RECV_CRC1: + write_state <= WR_STATE_SEND_DRESP; + + // send data response + WR_STATE_SEND_DRESP: + write_state <= WR_STATE_BUSY; + + // wait for io controller to accept data + WR_STATE_BUSY: + if(spi_buf == sd_buf) write_state <= (cmd == 25) ? WR_STATE_EXP_DTOKEN : WR_STATE_IDLE; + endcase + end + end + end +end + +endmodule diff --git a/sys/spdif.v b/sys/spdif.v index 671dcb2..eee2b08 100644 --- a/sys/spdif.v +++ b/sys/spdif.v @@ -31,132 +31,6 @@ // altera message_off 10240 module spdif - -//----------------------------------------------------------------- -// Params -//----------------------------------------------------------------- -#( - parameter CLK_RATE = 50000000, - parameter AUDIO_RATE = 48000, - - // Generated params - parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128), - parameter ERROR_BASE = 10000, - parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE) -) - -//----------------------------------------------------------------- -// Ports -//----------------------------------------------------------------- -( - input clk_i, - input rst_i, - input half_rate, - - // Output - output spdif_o, - - // Audio interface (16-bit x 2 = RL) - input [15:0] audio_r, - input [15:0] audio_l, - output sample_req_o -); - -reg lpf_ce; -always @(negedge clk_i) begin - reg [3:0] div; - - div <= div + 1'd1; - if(div == 13) div <= 0; - - lpf_ce <= !div; -end - -wire [15:0] al, ar; - -lpf48k #(15) lpf_l -( - .RESET(rst_i), - .CLK(clk_i), - .CE(lpf_ce), - .ENABLE(1), - - .IDATA(audio_l), - .ODATA(al) -); - -lpf48k #(15) lpf_r -( - .RESET(rst_i), - .CLK(clk_i), - .CE(lpf_ce), - .ENABLE(1), - - .IDATA(audio_r), - .ODATA(ar) -); - -reg bit_clk_q; - -// Clock pulse generator -always @ (posedge rst_i or posedge clk_i) begin - reg [31:0] count_q; - reg [31:0] error_q; - reg ce; - - if (rst_i) begin - count_q <= 0; - error_q <= 0; - bit_clk_q <= 1; - ce <= 0; - end - else - begin - if(count_q == WHOLE_CYCLES-1) begin - if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin - error_q <= error_q + ERRORS_PER_BIT[31:0]; - count_q <= 0; - end else begin - error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE; - count_q <= count_q + 1; - end - end else if(count_q == WHOLE_CYCLES) begin - count_q <= 0; - end else begin - count_q <= count_q + 1; - end - - bit_clk_q <= 0; - if(!count_q) begin - ce <= ~ce; - if(~half_rate || ce) bit_clk_q <= 1; - end - end -end - -//----------------------------------------------------------------- -// Core SPDIF -//----------------------------------------------------------------- - -wire [31:0] sample_i = {ar, al}; - -spdif_core -u_core -( - .clk_i(clk_i), - .rst_i(rst_i), - - .bit_out_en_i(bit_clk_q), - - .spdif_o(spdif_o), - - .sample_i(sample_i), - .sample_req_o(sample_req_o) -); - -endmodule - -module spdif_core ( input clk_i, input rst_i, @@ -193,6 +67,8 @@ reg spdif_out_q; reg [5:0] parity_count_q; +reg channel_status_bit_q; + //----------------------------------------------------------------- // Subframe Counter //----------------------------------------------------------------- @@ -268,19 +144,20 @@ assign subframe_w[28] = 1'b0; // Valid assign subframe_w[29] = 1'b0; // Timeslots 30 = Channel status bit -assign subframe_w[30] = 1'b0; +assign subframe_w[30] = channel_status_bit_q ; //was constant 1'b0 enabling copy-bit; // Timeslots 31 = Even Parity bit (31:4) assign subframe_w[31] = 1'b0; //----------------------------------------------------------------- -// Preamble +// Preamble and Channel status bit //----------------------------------------------------------------- -localparam PREAMBLE_Z = 8'b00010111; -localparam PREAMBLE_Y = 8'b00100111; -localparam PREAMBLE_X = 8'b01000111; +localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block +localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data +localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block reg [7:0] preamble_r; +reg channel_status_bit_r; always @ * begin @@ -294,13 +171,30 @@ begin // Left Channel (but not start of block)? else preamble_r = PREAMBLE_X; // X(M) + + if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted + channel_status_bit_r = 1'b1; + else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media + channel_status_bit_r = 1'b1; + else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r) + channel_status_bit_r = 1'b1; + else + channel_status_bit_r = 1'b0; // everything else defaults to 0 end always @ (posedge rst_i or posedge clk_i ) -if (rst_i == 1'b1) - preamble_q <= 8'h00; -else if (load_subframe_q) - preamble_q <= preamble_r; +begin + if (rst_i == 1'b1) + begin + preamble_q <= 8'h00; + channel_status_bit_q <= 1'b0; + end + else if (load_subframe_q) + begin + preamble_q <= preamble_r; + channel_status_bit_q <= channel_status_bit_r; + end +end //----------------------------------------------------------------- // Parity Counter diff --git a/sys/sync_vg.v b/sys/sync_vg.v deleted file mode 100644 index caaf681..0000000 --- a/sys/sync_vg.v +++ /dev/null @@ -1,78 +0,0 @@ -module sync_vg -#( - parameter X_BITS=12, Y_BITS=12 -) -( - input wire clk, - input wire reset, - - input wire [Y_BITS-1:0] v_total, - input wire [Y_BITS-1:0] v_fp, - input wire [Y_BITS-1:0] v_bp, - input wire [Y_BITS-1:0] v_sync, - input wire [X_BITS-1:0] h_total, - input wire [X_BITS-1:0] h_fp, - input wire [X_BITS-1:0] h_bp, - input wire [X_BITS-1:0] h_sync, - input wire [X_BITS-1:0] hv_offset, - - output reg vs_out, - output reg hs_out, - output reg hde_out, - output reg vde_out, - output reg [Y_BITS-1:0] v_count_out, - output reg [X_BITS-1:0] h_count_out, - output reg [X_BITS-1:0] x_out, - output reg [Y_BITS-1:0] y_out -); - -reg [X_BITS-1:0] h_count; -reg [Y_BITS-1:0] v_count; - -/* horizontal counter */ -always @(posedge clk) - if (reset) - h_count <= 0; - else - if (h_count < h_total - 1) - h_count <= h_count + 1'd1; - else - h_count <= 0; - -/* vertical counter */ -always @(posedge clk) - if (reset) - v_count <= 0; - else - if (h_count == h_total - 1) - begin - if (v_count == v_total - 1) - v_count <= 0; - else - v_count <= v_count + 1'd1; - end - -always @(posedge clk) - if (reset) - { vs_out, hs_out, hde_out, vde_out } <= 0; - else begin - hs_out <= ((h_count < h_sync)); - - hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1); - vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1); - - if ((v_count == 0) && (h_count == hv_offset)) - vs_out <= 1'b1; - else if ((v_count == v_sync) && (h_count == hv_offset)) - vs_out <= 1'b0; - - /* H_COUNT_OUT and V_COUNT_OUT */ - h_count_out <= h_count; - v_count_out <= v_count; - - /* X and Y coords for a backend pattern generator */ - x_out <= h_count - (h_sync + h_bp); - y_out <= v_count - (v_sync + v_bp); - end - -endmodule diff --git a/sys/sys.qip b/sys/sys.qip index 0d7b675..2854eaf 100644 --- a/sys/sys.qip +++ b/sys/sys.qip @@ -1,24 +1,33 @@ -set_global_assignment -name VERILOG_FILE sys/sys_top.v -#set_global_assignment -name SDC_FILE sys/sys_top.sdc -#set_global_assignment -name QIP_FILE sys/pll.qip -#set_global_assignment -name QIP_FILE sys/pll_hdmi.qip -#set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip -set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv -set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv -set_global_assignment -name VERILOG_FILE sys/scandoubler.v -set_global_assignment -name SYSTEMVERILOG_FILE sys/video_cleaner.sv -set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv -set_global_assignment -name VERILOG_FILE sys/osd.v -set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv -set_global_assignment -name VERILOG_FILE sys/sync_vg.v -set_global_assignment -name VERILOG_FILE sys/pattern_vg.v -set_global_assignment -name VERILOG_FILE sys/i2c.v -set_global_assignment -name VERILOG_FILE sys/i2s.v -set_global_assignment -name VERILOG_FILE sys/spdif.v -set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v -set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv -set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv -set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv -set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v -set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv -set_global_assignment -name VERILOG_FILE sys/hps_io.v +set_global_assignment -name QIP_FILE [join [list $::quartus(qip_path) pll_q [regexp -inline {[0-9]+} $quartus(version)] .qip] {}] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) math.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ] diff --git a/sys/sys.tcl b/sys/sys.tcl new file mode 100644 index 0000000..8c10190 --- /dev/null +++ b/sys/sys.tcl @@ -0,0 +1,227 @@ +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 + +#============================================================ +# ADC +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*] + +#============================================================ +# I2C LEDS/BUTTONS +#============================================================ +set_location_assignment PIN_U14 -to IO_SCL +set_location_assignment PIN_AG9 -to IO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S* + +#============================================================ +# USER PORT +#============================================================ +set_location_assignment PIN_AF17 -to USER_IO[6] +set_location_assignment PIN_AF15 -to USER_IO[5] +set_location_assignment PIN_AG16 -to USER_IO[4] +set_location_assignment PIN_AH11 -to USER_IO[3] +set_location_assignment PIN_AH12 -to USER_IO[2] +set_location_assignment PIN_AH9 -to USER_IO[1] +set_location_assignment PIN_AG11 -to USER_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*] + +#============================================================ +# SDIO_CD or SPDIF_OUT +#============================================================ +set_location_assignment PIN_AH7 -to SDCD_SPDIF +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_Y11 -to SDRAM_A[0] +set_location_assignment PIN_AA26 -to SDRAM_A[1] +set_location_assignment PIN_AA13 -to SDRAM_A[2] +set_location_assignment PIN_AA11 -to SDRAM_A[3] +set_location_assignment PIN_W11 -to SDRAM_A[4] +set_location_assignment PIN_Y19 -to SDRAM_A[5] +set_location_assignment PIN_AB23 -to SDRAM_A[6] +set_location_assignment PIN_AC23 -to SDRAM_A[7] +set_location_assignment PIN_AC22 -to SDRAM_A[8] +set_location_assignment PIN_C12 -to SDRAM_A[9] +set_location_assignment PIN_AB26 -to SDRAM_A[10] +set_location_assignment PIN_AD17 -to SDRAM_A[11] +set_location_assignment PIN_D12 -to SDRAM_A[12] +set_location_assignment PIN_Y17 -to SDRAM_BA[0] +set_location_assignment PIN_AB25 -to SDRAM_BA[1] +set_location_assignment PIN_E8 -to SDRAM_DQ[0] +set_location_assignment PIN_V12 -to SDRAM_DQ[1] +set_location_assignment PIN_D11 -to SDRAM_DQ[2] +set_location_assignment PIN_W12 -to SDRAM_DQ[3] +set_location_assignment PIN_AH13 -to SDRAM_DQ[4] +set_location_assignment PIN_D8 -to SDRAM_DQ[5] +set_location_assignment PIN_AH14 -to SDRAM_DQ[6] +set_location_assignment PIN_AF7 -to SDRAM_DQ[7] +set_location_assignment PIN_AE24 -to SDRAM_DQ[8] +set_location_assignment PIN_AD23 -to SDRAM_DQ[9] +set_location_assignment PIN_AE6 -to SDRAM_DQ[10] +set_location_assignment PIN_AE23 -to SDRAM_DQ[11] +set_location_assignment PIN_AG14 -to SDRAM_DQ[12] +set_location_assignment PIN_AD5 -to SDRAM_DQ[13] +set_location_assignment PIN_AF4 -to SDRAM_DQ[14] +set_location_assignment PIN_AH3 -to SDRAM_DQ[15] +set_location_assignment PIN_AG13 -to SDRAM_DQML +set_location_assignment PIN_AF13 -to SDRAM_DQMH +set_location_assignment PIN_AD20 -to SDRAM_CLK +set_location_assignment PIN_AG10 -to SDRAM_CKE +set_location_assignment PIN_AA19 -to SDRAM_nWE +set_location_assignment PIN_AA18 -to SDRAM_nCAS +set_location_assignment PIN_Y18 -to SDRAM_nCS +set_location_assignment PIN_W14 -to SDRAM_nRAS + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + +#============================================================ +# SPI SD +#============================================================ +set_location_assignment PIN_AE15 -to SD_SPI_CS +set_location_assignment PIN_AH8 -to SD_SPI_MISO +set_location_assignment PIN_AG8 -to SD_SPI_CLK +set_location_assignment PIN_U13 -to SD_SPI_MOSI +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI* + + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +#============================================================ +# HDMI +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALI2C_X52_Y60_N111 -entity sys_top -to hdmi_i2c + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" + +set_global_assignment -name CDF_FILE jtag.cdf +set_global_assignment -name QIP_FILE sys/sys.qip + diff --git a/sys/sys_analog.tcl b/sys/sys_analog.tcl new file mode 100644 index 0000000..7ffb3ec --- /dev/null +++ b/sys/sys_analog.tcl @@ -0,0 +1,71 @@ +#============================================================ +# SDIO +#============================================================ +set_location_assignment PIN_AF25 -to SDIO_DAT[0] +set_location_assignment PIN_AF23 -to SDIO_DAT[1] +set_location_assignment PIN_AD26 -to SDIO_DAT[2] +set_location_assignment PIN_AF28 -to SDIO_DAT[3] +set_location_assignment PIN_AF27 -to SDIO_CMD +set_location_assignment PIN_AH26 -to SDIO_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_AE17 -to VGA_R[0] +set_location_assignment PIN_AE20 -to VGA_R[1] +set_location_assignment PIN_AF20 -to VGA_R[2] +set_location_assignment PIN_AH18 -to VGA_R[3] +set_location_assignment PIN_AH19 -to VGA_R[4] +set_location_assignment PIN_AF21 -to VGA_R[5] + +set_location_assignment PIN_AE19 -to VGA_G[0] +set_location_assignment PIN_AG15 -to VGA_G[1] +set_location_assignment PIN_AF18 -to VGA_G[2] +set_location_assignment PIN_AG18 -to VGA_G[3] +set_location_assignment PIN_AG19 -to VGA_G[4] +set_location_assignment PIN_AG20 -to VGA_G[5] + +set_location_assignment PIN_AG21 -to VGA_B[0] +set_location_assignment PIN_AA20 -to VGA_B[1] +set_location_assignment PIN_AE22 -to VGA_B[2] +set_location_assignment PIN_AF22 -to VGA_B[3] +set_location_assignment PIN_AH23 -to VGA_B[4] +set_location_assignment PIN_AH21 -to VGA_B[5] + +set_location_assignment PIN_AH22 -to VGA_HS +set_location_assignment PIN_AG24 -to VGA_VS + +set_location_assignment PIN_AH27 -to VGA_EN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* + +#============================================================ +# AUDIO +#============================================================ +set_location_assignment PIN_AC24 -to AUDIO_L +set_location_assignment PIN_AE25 -to AUDIO_R +set_location_assignment PIN_AG26 -to AUDIO_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* + +#============================================================ +# I/O #1 +#============================================================ +set_location_assignment PIN_Y15 -to LED_USER +set_location_assignment PIN_AA15 -to LED_HDD +set_location_assignment PIN_AG28 -to LED_POWER + +set_location_assignment PIN_AH24 -to BTN_USER +set_location_assignment PIN_AG25 -to BTN_OSD +set_location_assignment PIN_AG23 -to BTN_RESET + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* diff --git a/sys/sys_dual_sdram.tcl b/sys/sys_dual_sdram.tcl new file mode 100644 index 0000000..06124e7 --- /dev/null +++ b/sys/sys_dual_sdram.tcl @@ -0,0 +1,50 @@ +#============================================================ +# Secondary SDRAM +#============================================================ +set_location_assignment PIN_Y15 -to SDRAM2_DQ[0] +set_location_assignment PIN_AC24 -to SDRAM2_DQ[1] +set_location_assignment PIN_AA15 -to SDRAM2_DQ[2] +set_location_assignment PIN_AD26 -to SDRAM2_DQ[3] +set_location_assignment PIN_AG28 -to SDRAM2_DQ[4] +set_location_assignment PIN_AF28 -to SDRAM2_DQ[5] +set_location_assignment PIN_AE25 -to SDRAM2_DQ[6] +set_location_assignment PIN_AF27 -to SDRAM2_DQ[7] +set_location_assignment PIN_AG26 -to SDRAM2_DQ[14] +set_location_assignment PIN_AH27 -to SDRAM2_DQ[15] + +set_location_assignment PIN_AG25 -to SDRAM2_DQ[13] +set_location_assignment PIN_AH26 -to SDRAM2_DQ[12] +set_location_assignment PIN_AH24 -to SDRAM2_DQ[11] +set_location_assignment PIN_AF25 -to SDRAM2_DQ[10] +set_location_assignment PIN_AG23 -to SDRAM2_DQ[9] +set_location_assignment PIN_AF23 -to SDRAM2_DQ[8] +set_location_assignment PIN_AG24 -to SDRAM2_A[12] +set_location_assignment PIN_AH22 -to SDRAM2_CLK +set_location_assignment PIN_AH21 -to SDRAM2_A[9] +set_location_assignment PIN_AG21 -to SDRAM2_A[11] +set_location_assignment PIN_AH23 -to SDRAM2_A[7] +set_location_assignment PIN_AA20 -to SDRAM2_A[8] +set_location_assignment PIN_AF22 -to SDRAM2_A[5] +set_location_assignment PIN_AE22 -to SDRAM2_A[6] +set_location_assignment PIN_AG20 -to SDRAM2_nWE +set_location_assignment PIN_AF21 -to SDRAM2_A[4] + +set_location_assignment PIN_AG19 -to SDRAM2_nCAS +set_location_assignment PIN_AH19 -to SDRAM2_nRAS +set_location_assignment PIN_AG18 -to SDRAM2_nCS +set_location_assignment PIN_AH18 -to SDRAM2_BA[0] +set_location_assignment PIN_AF18 -to SDRAM2_BA[1] +set_location_assignment PIN_AF20 -to SDRAM2_A[10] +set_location_assignment PIN_AG15 -to SDRAM2_A[0] +set_location_assignment PIN_AE20 -to SDRAM2_A[1] +set_location_assignment PIN_AE19 -to SDRAM2_A[2] +set_location_assignment PIN_AE17 -to SDRAM2_A[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_* + +set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1" diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index f8f6de6..e7846f5 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -1,53 +1,71 @@ # Specify root clocks -create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] -create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] -create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] +create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck +create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck derive_pll_clocks - -# Specify PLL-generated clock(s) -#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -# -name SDRAM_CLK [get_ports {SDRAM_CLK}] - -#create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ -# -name HDMI_CLK [get_ports HDMI_TX_CLK] - -#create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ -# -name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}] - - derive_clock_uncertainty - -# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) -#set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] -#set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] - -#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ -# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -# -setup 2 - -#set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] -#set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] - # Decouple different clock groups (to simplify routing) -# -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -# -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \ -set_clock_groups -asynchronous \ +set_clock_groups -exclusive \ + -group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \ + -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \ + -group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \ + -group [get_clocks { spi_sck}] \ + -group [get_clocks { hdmi_sck}] \ -group [get_clocks { *|h2f_user0_clk}] \ - -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}] + -group [get_clocks { FPGA_CLK1_50 }] \ + -group [get_clocks { FPGA_CLK2_50 }] \ + -group [get_clocks { FPGA_CLK3_50 }] -#set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] -#set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] +set_false_path -from [get_ports {KEY*}] +set_false_path -from [get_ports {BTN_*}] +set_false_path -to [get_ports {LED_*}] +set_false_path -to [get_ports {VGA_*}] +set_false_path -to [get_ports {AUDIO_SPDIF}] +set_false_path -to [get_ports {AUDIO_L}] +set_false_path -to [get_ports {AUDIO_R}] +set_false_path -to {cfg[*]} +set_false_path -from {cfg[*]} +set_false_path -from {VSET[*]} +set_false_path -to {wcalc[*] hcalc[*]} +set_false_path -to {hdmi_width[*] hdmi_height[*]} -# Put constraints on input ports -set_false_path -from [get_ports {KEY*}] -to * -set_false_path -from [get_ports {BTN_*}] -to * +set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2 +set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1 -# Put constraints on output ports -set_false_path -from * -to [get_ports {LED_*}] -set_false_path -from * -to [get_ports {VGA_*}] -set_false_path -from * -to [get_ports {AUDIO_SPDIF}] -set_false_path -from * -to [get_ports {AUDIO_L}] -set_false_path -from * -to [get_ports {AUDIO_R}] +set_false_path -to {*_osd|v_cnt*} +set_false_path -to {*_osd|v_osd_start*} +set_false_path -to {*_osd|v_info_start*} +set_false_path -to {*_osd|h_osd_start*} +set_false_path -from {*_osd|v_osd_start*} +set_false_path -from {*_osd|v_info_start*} +set_false_path -from {*_osd|h_osd_start*} +set_false_path -from {*_osd|rot*} +set_false_path -from {*_osd|dsp_width*} +set_false_path -to {*_osd|half} + +set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} +set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} +set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} +set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} +set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} +set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} +set_false_path -from {aflt_* acx* acy* areset* arc*} +set_false_path -from {vs_line*} + +set_false_path -from {ascal|o_ihsize*} +set_false_path -from {ascal|o_ivsize*} +set_false_path -from {ascal|o_format*} +set_false_path -from {ascal|o_hdown} +set_false_path -from {ascal|o_vdown} +set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax*} +set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*} +set_false_path -from {ascal|o_htotal* ascal|o_vtotal*} +set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*} +set_false_path -from {ascal|o_hsize* ascal|o_vsize*} + +set_false_path -from {mcp23009|sd_cd} diff --git a/sys/sys_top.v b/sys/sys_top.v index 9818319..31f2ce4 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -1,7 +1,7 @@ //============================================================================ // // MiSTer hardware abstraction module -// (c)2017,2018 Sorgelig +// (c)2017-2020 Alexey Melnikov // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free @@ -21,90 +21,133 @@ module sys_top ( - /////////// CLOCK ////////// - input FPGA_CLK1_50, - input FPGA_CLK2_50, - input FPGA_CLK3_50, + /////////// CLOCK ////////// + input FPGA_CLK1_50, + input FPGA_CLK2_50, + input FPGA_CLK3_50, - //////////// VGA /////////// - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive) - output VGA_VS, - input VGA_EN, // active low + //////////// HDMI ////////// + output HDMI_I2C_SCL, + inout HDMI_I2C_SDA, - /////////// AUDIO ////////// - output AUDIO_L, - output AUDIO_R, - output AUDIO_SPDIF, + output HDMI_MCLK, + output HDMI_SCLK, + output HDMI_LRCLK, + output HDMI_I2S, - //////////// HDMI ////////// -`ifndef LITE - output HDMI_I2C_SCL, - inout HDMI_I2C_SDA, + output HDMI_TX_CLK, + output HDMI_TX_DE, + output [23:0] HDMI_TX_D, + output HDMI_TX_HS, + output HDMI_TX_VS, + + input HDMI_TX_INT, - output HDMI_MCLK, - output HDMI_SCLK, - output HDMI_LRCLK, - output HDMI_I2S, + //////////// SDR /////////// + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE, - output HDMI_TX_CLK, - output HDMI_TX_DE, - output [23:0] HDMI_TX_D, - output HDMI_TX_HS, - output HDMI_TX_VS, - - input HDMI_TX_INT, -`endif +`ifdef MISTER_DUAL_SDRAM + ////////// SDR #2 ////////// + output [12:0] SDRAM2_A, + inout [15:0] SDRAM2_DQ, + output SDRAM2_nWE, + output SDRAM2_nCAS, + output SDRAM2_nRAS, + output SDRAM2_nCS, + output [1:0] SDRAM2_BA, + output SDRAM2_CLK, - //////////// SDR /////////// -`ifndef LITE - output [12:0] SDRAM_A, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nWE, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nCS, - output [1:0] SDRAM_BA, - output SDRAM_CLK, - output SDRAM_CKE, `else - input UART_RX, - output UART_TX, + //////////// VGA /////////// + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive) + output VGA_VS, + input VGA_EN, // active low + + /////////// AUDIO ////////// + output AUDIO_L, + output AUDIO_R, + output AUDIO_SPDIF, + + //////////// SDIO /////////// + inout [3:0] SDIO_DAT, + inout SDIO_CMD, + output SDIO_CLK, + + //////////// I/O /////////// + output LED_USER, + output LED_HDD, + output LED_POWER, + input BTN_USER, + input BTN_OSD, + input BTN_RESET, `endif - //////////// I/O /////////// - output LED_USER, - output LED_HDD, - output LED_POWER, - input BTN_USER, - input BTN_OSD, - input BTN_RESET, + ////////// I/O ALT ///////// + output SD_SPI_CS, + input SD_SPI_MISO, + output SD_SPI_CLK, + output SD_SPI_MOSI, - //////////// SDIO /////////// - inout [3:0] SDIO_DAT, - inout SDIO_CMD, - output SDIO_CLK, - input SDIO_CD, + inout SDCD_SPDIF, + output IO_SCL, + inout IO_SDA, - ////////// MB KEY /////////// - input [1:0] KEY, + ////////// ADC ////////////// + output ADC_SCK, + input ADC_SDO, + output ADC_SDI, + output ADC_CONVST, - ////////// MB SWITCH //////// - input [3:0] SW, + ////////// MB KEY /////////// + input [1:0] KEY, - ////////// MB LED /////////// - output [7:0] LED + ////////// MB SWITCH //////// + input [3:0] SW, + + ////////// MB LED /////////// + output [7:0] LED, + + ///////// USER IO /////////// + inout [6:0] USER_IO ); +////////////////////// Secondary SD /////////////////////////////////// +wire SD_CS, SD_CLK, SD_MOSI; -assign SDIO_DAT[2:1] = 2'bZZ; +`ifndef MISTER_DUAL_SDRAM + wire sd_miso = SW[3] | SDIO_DAT[0]; +`else + wire sd_miso = 1; +`endif +wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO; +`ifndef MISTER_DUAL_SDRAM + assign SDIO_DAT[2:1]= 2'bZZ; + assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS; + assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK; + assign SDIO_CMD = SW[3] ? 1'bZ : SD_MOSI; + assign SD_SPI_CS = mcp_sdcd ? ((~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ) : SD_CS; +`else + assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS; +`endif -////////////////////////// LEDs /////////////////////////////////////// +assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK; +assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI; + +////////////////////// LEDs/Buttons /////////////////////////////////// reg [7:0] led_overtake = 0; reg [7:0] led_state = 0; @@ -112,76 +155,99 @@ reg [7:0] led_state = 0; wire led_p = led_power[1] ? ~led_power[0] : 1'b0; wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); wire led_u = ~led_user; -wire [7:0] led_mb; +wire led_locked; -assign LED = led_mb; -assign LED_POWER = led_p ? 1'bZ : 1'b0; -assign LED_HDD = led_d ? 1'bZ : 1'b0; -assign LED_USER = led_u ? 1'bZ : 1'b0; +`ifndef MISTER_DUAL_SDRAM + assign LED_POWER = (SW[3] | led_p) ? 1'bZ : 1'b0; + assign LED_HDD = (SW[3] | led_d) ? 1'bZ : 1'b0; + assign LED_USER = (SW[3] | led_u) ? 1'bZ : 1'b0; +`endif //LEDs on main board -//assign LED = (led_overtake & led_state) | (~led_overtake & {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); +assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); + +wire btn_r, btn_o, btn_u; +`ifdef MISTER_DUAL_SDRAM + assign {btn_r,btn_o,btn_u} = {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; +`else + assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; +`endif + +wire [2:0] mcp_btn; +wire mcp_sdcd; +mcp23009 mcp23009 +( + .clk(FPGA_CLK2_50), + + .btn(mcp_btn), + .led({led_p, led_d, led_u}), + .sd_cd(mcp_sdcd), + + .scl(IO_SCL), + .sda(IO_SDA) +); -////////////////////////// Buttons /////////////////////////////////// reg btn_user, btn_osd; always @(posedge FPGA_CLK2_50) begin - integer div; - reg [7:0] deb_user; - reg [7:0] deb_osd; + integer div; + reg [7:0] deb_user; + reg [7:0] deb_osd; - div <= div + 1'b1; - if(div > 100000) div <= 0; - - if(!div) begin - deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])}; - if(&deb_user) btn_user <= 1; - if(!deb_user) btn_user <= 0; + div <= div + 1'b1; + if(div > 100000) div <= 0; - deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])}; - if(&deb_osd) btn_osd <= 1; - if(!deb_osd) btn_osd <= 0; - end + if(!div) begin + deb_user <= {deb_user[6:0], btn_u | ~KEY[1]}; + if(&deb_user) btn_user <= 1; + if(!deb_user) btn_user <= 0; + + deb_osd <= {deb_osd[6:0], btn_o | ~KEY[0]}; + if(&deb_osd) btn_osd <= 1; + if(!deb_osd) btn_osd <= 0; + end end -reg btn_reset = 1; -always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET; - - ///////////////////////// HPS I/O ///////////////////////////////////// // gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode) // used to avoid lockups while JTAG loading -wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout}; +wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], SW[3], 8'd0, io_ver, io_ack, io_wide, io_dout}; wire [31:0] gp_out; -wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future. +wire [1:0] io_ver = 1; // 0 - obsolete. 1 - optimized HPS I/O. 2,3 - reserved for future. wire io_wait; wire io_wide; wire [15:0] io_dout; -wire [15:0] io_din = gp_outr[15:0]; -wire io_clk = gp_outr[17]; -wire io_fpga = gp_outr[18]; -wire io_osd = gp_outr[19]; -wire io_uio = gp_outr[20]; -//wire io_sdd = gp_outr[21]; // used only in ST core +wire [15:0] io_din = gp_outr[15:0]; +wire io_clk = gp_outr[17]; +wire io_ss0 = gp_outr[18]; +wire io_ss1 = gp_outr[19]; +wire io_ss2 = gp_outr[20]; + +`ifndef MISTER_DEBUG_NOHDMI +wire io_osd_hdmi = io_ss1 & ~io_ss0; +`endif + +wire io_fpga = ~io_ss1 & io_ss0; +wire io_uio = ~io_ss1 & io_ss2; reg io_ack; reg rack; wire io_strobe = ~rack & io_clk; always @(posedge clk_sys) begin - if(~io_wait | io_strobe) begin - rack <= io_clk; - io_ack <= rack; - end + if(~(io_wait | vs_wait) | io_strobe) begin + rack <= io_clk; + io_ack <= rack; + end end reg [31:0] gp_outr; always @(posedge clk_sys) begin - reg [31:0] gp_outd; - gp_outr <= gp_outd; - gp_outd <= gp_out; + reg [31:0] gp_outd; + gp_outr <= gp_outd; + gp_outd <= gp_out; end wire [7:0] core_type = 'hA7; // A7 - Sharp MZ series core. @@ -191,349 +257,352 @@ wire [31:0] core_magic = {24'h5CA623, core_type}; cyclonev_hps_interface_mpu_general_purpose h2f_gp ( - .gp_in({~gp_out[31] ? core_magic : gp_in}), - .gp_out(gp_out) + .gp_in({~gp_out[31] ? core_magic : gp_in}), + .gp_out(gp_out) ); reg [15:0] cfg; -reg cfg_got = 0; -reg cfg_set = 0; -//wire [2:0] hdmi_res = cfg[10:8]; -wire dvi_mode = cfg[7]; -wire audio_96k = cfg[6]; -wire ypbpr_en = cfg[5]; -wire csync = cfg[3]; +reg cfg_set = 0; +wire vga_fb = cfg[12] | vga_force_scaler; +wire [1:0] hdmi_limited = {cfg[11],cfg[8]}; -wire vga_scaler= cfg[2]; +`ifdef MISTER_DEBUG_NOHDMI +wire direct_video = 1; +`else +wire direct_video = cfg[10]; +`endif + +wire dvi_mode = cfg[7]; +wire audio_96k = cfg[6]; +wire csync_en = cfg[3]; +wire ypbpr_en = cfg[5]; +wire io_osd_vga = io_ss1 & ~io_ss2; +`ifndef MISTER_DUAL_SDRAM + wire sog = cfg[9]; + wire vga_scaler = cfg[2] | vga_force_scaler; +`endif reg cfg_custom_t = 0; reg [5:0] cfg_custom_p1; reg [31:0] cfg_custom_p2; -reg [4:0] vol_att = 0; +reg [4:0] vol_att; +initial vol_att = 5'b11111; + +reg [6:0] coef_addr; +reg [8:0] coef_data; +reg coef_wr = 0; + +wire[12:0] ARX, ARY; +reg [11:0] VSET = 0, HSET = 0; +reg FREESCALE = 0; +reg [2:0] scaler_flt; +reg lowlat = 0; +reg cfg_dis = 0; + +reg vs_wait = 0; +reg [11:0] vs_line = 0; + +reg scaler_out = 0; + +reg [31:0] aflt_rate = 7056000; +reg [39:0] acx = 4258969; +reg [7:0] acx0 = 3; +reg [7:0] acx1 = 3; +reg [7:0] acx2 = 1; +reg [23:0] acy0 = -24'd6216759; +reg [23:0] acy1 = 24'd6143386; +reg [23:0] acy2 = -24'd2023767; +reg areset = 0; +reg [12:0] arc1x = 0; +reg [12:0] arc1y = 0; +reg [12:0] arc2x = 0; +reg [12:0] arc2y = 0; -reg vip_newcfg = 0; always@(posedge clk_sys) begin - reg [7:0] cmd; - reg has_cmd; - reg old_strobe; - reg [7:0] cnt = 0; + reg [7:0] cmd; + reg has_cmd; + reg old_strobe; + reg [7:0] cnt = 0; + reg vs_d0,vs_d1,vs_d2; + reg [4:0] acx_att; - old_strobe <= io_strobe; + old_strobe <= io_strobe; + coef_wr <= 0; - if(~io_uio) has_cmd <= 0; - else - if(~old_strobe & io_strobe) begin - if(!has_cmd) begin - has_cmd <= 1; - cmd <= io_din[7:0]; - cnt <= 0; - end - else begin - if(cmd == 1) begin - cfg <= io_din; - cfg_set <= 1; - end - if(cmd == 'h20) begin - cfg_set <= 0; - cnt <= cnt + 1'd1; - if(cnt<8) begin - if(!cnt) vip_newcfg <= ~cfg_ready; - case(cnt) - 0: if(WIDTH != io_din[11:0]) begin WIDTH <= io_din[11:0]; vip_newcfg <= 1; end - 1: if(HFP != io_din[11:0]) begin HFP <= io_din[11:0]; vip_newcfg <= 1; end - 2: if(HS != io_din[11:0]) begin HS <= io_din[11:0]; vip_newcfg <= 1; end - 3: if(HBP != io_din[11:0]) begin HBP <= io_din[11:0]; vip_newcfg <= 1; end - 4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; vip_newcfg <= 1; end - 5: if(VFP != io_din[11:0]) begin VFP <= io_din[11:0]; vip_newcfg <= 1; end - 6: if(VS != io_din[11:0]) begin VS <= io_din[11:0]; vip_newcfg <= 1; end - 7: if(VBP != io_din[11:0]) begin VBP <= io_din[11:0]; vip_newcfg <= 1; end - endcase - if(cnt == 1) begin - cfg_custom_p1 <= 0; - cfg_custom_p2 <= 0; - cfg_custom_t <= ~cfg_custom_t; - end - end - else begin - if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0]; - if(cnt[1:0]==1) cfg_custom_p2[15:0] <= io_din; - if(cnt[1:0]==2) begin - cfg_custom_p2[31:16] <= io_din; - cfg_custom_t <= ~cfg_custom_t; - cnt[1:0] <= 0; - end - end - end - if(cmd == 'h25) {led_overtake, led_state} <= io_din; - if(cmd == 'h26) vol_att <= io_din[4:0]; - if(cmd == 'h27) VSET <= io_din[11:0]; - end - end -end - -`ifndef LITE -always @(posedge clk_sys) begin - reg vsd, vsd2; - if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; - else begin - vsd <= HDMI_TX_VS; - vsd2 <= vsd; - if(~vsd2 & vsd) cfg_got <= cfg_set; - end -end + if(~io_uio) begin + has_cmd <= 0; + cmd <= 0; + areset <= 0; + acx_att <= 0; + acx <= acx >> acx_att; + end + else + if(~old_strobe & io_strobe) begin + if(!has_cmd) begin + has_cmd <= 1; + cmd <= io_din[7:0]; + cnt <= 0; + if(io_din[7:0] == 'h30) vs_wait <= 1; + if(io_din[7:0] == 'h39) begin + aflt_rate <= 7056000; + acx <= 4258969; + acx0 <= 3; + acx1 <= 3; + acx2 <= 1; + acy0 <= -24'd6216759; + acy1 <= 24'd6143386; + acy2 <= -24'd2023767; + areset <= 1; + end + end + else begin + if(cmd == 1) begin + cfg <= io_din; + cfg_set <= 1; + scaler_out <= 1; + end + if(cmd == 'h20) begin + cfg_set <= 0; + cnt <= cnt + 1'd1; + if(cnt<8) begin + case(cnt[2:0]) + 0: if(WIDTH != io_din[11:0]) WIDTH <= io_din[11:0]; + 1: if(HFP != io_din[11:0]) HFP <= io_din[11:0]; + 2: if(HS != io_din[11:0]) HS <= io_din[11:0]; + 3: if(HBP != io_din[11:0]) HBP <= io_din[11:0]; + 4: if(HEIGHT != io_din[11:0]) HEIGHT <= io_din[11:0]; + 5: if(VFP != io_din[11:0]) VFP <= io_din[11:0]; + 6: if(VS != io_din[11:0]) VS <= io_din[11:0]; + 7: if(VBP != io_din[11:0]) VBP <= io_din[11:0]; + endcase +`ifndef MISTER_DEBUG_NOHDMI + if(cnt == 1) begin + cfg_custom_p1 <= 0; + cfg_custom_p2 <= 0; + cfg_custom_t <= ~cfg_custom_t; + end + end + else begin + if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0]; + if(cnt[1:0]==1) cfg_custom_p2[15:0] <= io_din; + if(cnt[1:0]==2) begin + cfg_custom_p2[31:16] <= io_din; + cfg_custom_t <= ~cfg_custom_t; + cnt[2:0] <= 3'b100; + end + if(cnt == 8) {lowlat,cfg_dis} <= io_din[15:14]; `endif + end + end + if(cmd == 'h2F) begin + cnt <= cnt + 1'd1; + case(cnt[3:0]) + 0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]}; + 1: LFB_BASE[15:0] <= io_din[15:0]; + 2: LFB_BASE[31:16] <= io_din[15:0]; + 3: LFB_WIDTH <= io_din[11:0]; + 4: LFB_HEIGHT <= io_din[11:0]; + 5: LFB_HMIN <= io_din[11:0]; + 6: LFB_HMAX <= io_din[11:0]; + 7: LFB_VMIN <= io_din[11:0]; + 8: LFB_VMAX <= io_din[11:0]; + 9: LFB_STRIDE <= io_din[13:0]; + endcase + end + if(cmd == 'h25) {led_overtake, led_state} <= io_din; + if(cmd == 'h26) vol_att <= io_din[4:0]; + if(cmd == 'h27) VSET <= io_din[11:0]; + if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din}; + if(cmd == 'h2B) scaler_flt <= io_din[2:0]; + if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]}; + if(cmd == 'h38) vs_line <= io_din[11:0]; + if(cmd == 'h39) begin + cnt <= cnt + 1'd1; + case(cnt[3:0]) + 0: acx_att <= io_din[4:0]; + 1: aflt_rate[15:0] <= io_din; + 2: aflt_rate[31:16] <= io_din; + 3: acx[15:0] <= io_din; + 4: acx[31:16] <= io_din; + 5: acx[39:32] <= io_din[7:0]; + 6: acx0 <= io_din[7:0]; + 7: acx1 <= io_din[7:0]; + 8: acx2 <= io_din[7:0]; + 9: acy0[15:0] <= io_din; + 10: acy0[23:16] <= io_din[7:0]; + 11: acy1[15:0] <= io_din; + 12: acy1[23:16] <= io_din[7:0]; + 13: acy2[15:0] <= io_din; + 14: acy2[23:16] <= io_din[7:0]; + endcase + end + if(cmd == 'h3A) begin + cnt <= cnt + 1'd1; + case(cnt[3:0]) + 0: arc1x <= io_din[12:0]; + 1: arc1y <= io_din[12:0]; + 2: arc2x <= io_din[12:0]; + 3: arc2y <= io_din[12:0]; + endcase + end + end + end + + vs_d0 <= HDMI_TX_VS; + if(vs_d0 == HDMI_TX_VS) vs_d1 <= vs_d0; + + vs_d2 <= vs_d1; + if(~vs_d2 & vs_d1) vs_wait <= 0; +end + +cyclonev_hps_interface_peripheral_uart uart +( + .ri(0), + .dsr(uart_dsr), + .dcd(uart_dsr), + .dtr(uart_dtr), + + .cts(uart_cts), + .rts(uart_rts), + .rxd(uart_rxd), + .txd(uart_txd) +); + +wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso; +cyclonev_hps_interface_peripheral_spi_master spi +( + .sclk_out(aspi_sck), + .txd(aspi_mosi), // mosi + .rxd(aspi_miso), // miso + + .ss_0_n(aspi_ss), + .ss_in_n(1) +); + +wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS}; +cyclonev_hps_interface_interrupts interrupts +( + .irq(f2h_irq) +); /////////////////////////// RESET /////////////////////////////////// reg reset_req = 0; always @(posedge FPGA_CLK2_50) begin - reg [1:0] resetd, resetd2; - reg old_reset; + reg [1:0] resetd, resetd2; + reg old_reset; - //latch the reset - old_reset <= reset; - if(~old_reset & reset) reset_req <= 1; + //latch the reset + old_reset <= reset; + if(~old_reset & reset) reset_req <= 1; - //special combination to set/clear the reset - //preventing of accidental reset control - if(resetd==1) reset_req <= 1; - if(resetd==2 && resetd2==0) reset_req <= 0; + //special combination to set/clear the reset + //preventing of accidental reset control + if(resetd==1) reset_req <= 1; + if(resetd==2 && resetd2==0) reset_req <= 0; - resetd <= gp_out[31:30]; - resetd2 <= resetd; + resetd <= gp_out[31:30]; + resetd2 <= resetd; end -wire clk_ctl; - -`ifndef LITE -///////////////////////// VIP version /////////////////////////////// -wire iHdmiClk = ~HDMI_TX_CLK; // Internal HDMI clock, inverted in relation to external clock -wire reset; - -vip vip -( - //Reset/Clock - .reset_reset_req(reset_req | ~cfg_ready), - .reset_reset(reset), - .reset_reset_vip(0), - - //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. - .reset_cold_req(~btn_reset), - .reset_warm_req(0), - - //control - .ctl_address(ctl_address), - .ctl_write(ctl_write), - .ctl_writedata(ctl_writedata), - .ctl_waitrequest(ctl_waitrequest), - .ctl_clock(clk_ctl), - .ctl_reset(ctl_reset), - - //64-bit DDR3 RAM access - .ramclk1_clk(ram_clk), - .ram1_address(ram_address), - .ram1_burstcount(ram_burstcount), - .ram1_waitrequest(ram_waitrequest), - .ram1_readdata(ram_readdata), - .ram1_readdatavalid(ram_readdatavalid), - .ram1_read(ram_read), - .ram1_writedata(ram_writedata), - .ram1_byteenable(ram_byteenable), - .ram1_write(ram_write), - - //Spare 64-bit DDR3 RAM access - //currently unused - //can combine with ram1 to make a wider RAM bus (although will increase the latency) - .ramclk2_clk(0), - .ram2_address(0), - .ram2_burstcount(0), - .ram2_waitrequest(), - .ram2_readdata(), - .ram2_readdatavalid(), - .ram2_read(0), - .ram2_writedata(0), - .ram2_byteenable(0), - .ram2_write(0), - - //Video input - .in_clk(clk_vid), - .in_data({r_out, g_out, b_out}), - .in_de(de), - .in_v_sync(vs), - .in_h_sync(hs), - .in_ce(ce_pix), - .in_f(0), - - //HDMI output - .hdmi_clk(iHdmiClk), - .hdmi_data(hdmi_data), - .hdmi_de(hdmi_de), - .hdmi_v_sync(HDMI_TX_VS), - .hdmi_h_sync(HDMI_TX_HS) -); - -wire [8:0] ctl_address; -wire ctl_write; -wire [31:0] ctl_writedata; -wire ctl_waitrequest; -wire ctl_reset; -wire [7:0] ARX, ARY; - -vip_config vip_config -( - .clk(clk_ctl), - .reset(ctl_reset), - - .ARX(ARX), - .ARY(ARY), - .CFG_SET(vip_newcfg & cfg_got), - - .WIDTH(WIDTH), - .HFP(HFP), - .HBP(HBP), - .HS(HS), - .HEIGHT(HEIGHT), - .VFP(VFP), - .VBP(VBP), - .VS(VS), - .VSET(VSET), - - .address(ctl_address), - .write(ctl_write), - .writedata(ctl_writedata), - .waitrequest(ctl_waitrequest) -); -`endif - - -///////////////////////// Lite version //////////////////////////////// - -//`ifdef LITE - -`ifndef LITE -wire [11:0] x; -wire [11:0] y; - -sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg -( - .clk(iHdmiClk), - .reset(reset), - .v_total(HEIGHT+VFP+VBP+VS), - .v_fp(VFP), - .v_bp(VBP), - .v_sync(VS), - .h_total(WIDTH+HFP+HBP+HS), - .h_fp(HFP), - .h_bp(HBP), - .h_sync(HS), - .hv_offset(0), - .vde_out(vde), - .hde_out(hde), - .vs_out(vs_hdmi), - .v_count_out(), - .h_count_out(), - .x_out(x), - .y_out(y), - .hs_out(hs_hdmi) -); - -wire vde, hde; -wire vs_hdmi; -wire hs_hdmi; - -/* -pattern_vg -#( - .B(8), // Bits per channel - .X_BITS(12), - .Y_BITS(12), - .FRACTIONAL_BITS(12) // Number of fractional bits for ramp pattern -) -pattern_vg -( - .reset(reset), - .clk_in(iHdmiClk), - .x(x), - .y(y), - .vn_in(vs_hdmi), - .hn_in(hs_hdmi), - .dn_in(vde & hde), - .r_in(0), - .g_in(0), - .b_in(0), - .vn_out(HDMI_TX_VS), - .hn_out(HDMI_TX_HS), - .den_out(HDMI_TX_DE), - .r_out(hdmi_data[23:16]), - .g_out(hdmi_data[15:8]), - .b_out(hdmi_data[7:0]), - .total_active_pix(WIDTH), - .total_active_lines(HEIGHT), - .pattern(4), - .ramp_step(20'h0333) -); -*/ - -`endif +//////////////////// SYSTEM MEMORY & SCALER ///////////////////////// wire reset; +wire clk_100m; + sysmem_lite sysmem ( - //Reset/Clock - .reset_reset_req(reset_req), - .reset_reset(reset), - .ctl_clock(clk_ctl), + //Reset/Clock + .reset_core_req(reset_req), + .reset_out(reset), + .clock(clk_100m), - //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. - .reset_cold_req(~btn_reset), - .reset_warm_req(0), + //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. + .reset_hps_cold_req(btn_r), - //64-bit DDR3 RAM access - .ramclk1_clk(ram_clk), - .ram1_address(ram_address), - .ram1_burstcount(ram_burstcount), - .ram1_waitrequest(ram_waitrequest), - .ram1_readdata(ram_readdata), - .ram1_readdatavalid(ram_readdatavalid), - .ram1_read(ram_read), - .ram1_writedata(ram_writedata), - .ram1_byteenable(ram_byteenable), - .ram1_write(ram_write), + //64-bit DDR3 RAM access + .ram1_clk(ram_clk), + .ram1_address(ram_address), + .ram1_burstcount(ram_burstcount), + .ram1_waitrequest(ram_waitrequest), + .ram1_readdata(ram_readdata), + .ram1_readdatavalid(ram_readdatavalid), + .ram1_read(ram_read), + .ram1_writedata(ram_writedata), + .ram1_byteenable(ram_byteenable), + .ram1_write(ram_write), - //Spare 64-bit DDR3 RAM access - //currently unused - //can combine with ram1 to make a wider RAM bus (although will increase the latency) - .ramclk2_clk(0), - .ram2_address(0), - .ram2_burstcount(0), - .ram2_waitrequest(), - .ram2_readdata(), - .ram2_readdatavalid(), - .ram2_read(0), - .ram2_writedata(0), - .ram2_byteenable(0), - .ram2_write(0) + //64-bit DDR3 RAM access + .ram2_clk(clk_audio), + .ram2_address(ram2_address), + .ram2_burstcount(ram2_burstcount), + .ram2_waitrequest(ram2_waitrequest), + .ram2_readdata(ram2_readdata), + .ram2_readdatavalid(ram2_readdatavalid), + .ram2_read(ram2_read), + .ram2_writedata(ram2_writedata), + .ram2_byteenable(ram2_byteenable), + .ram2_write(ram2_write), -`ifndef LITE - , - // HDMI frame buffer - .vbuf_clk(clk_ctl), - .vbuf_address(vbuf_address), - .vbuf_burstcount(vbuf_burstcount), - .vbuf_waitrequest(vbuf_waitrequest), - .vbuf_writedata(vbuf_writedata), - .vbuf_byteenable(vbuf_byteenable), - .vbuf_write(vbuf_write), - .vbuf_readdata(vbuf_readdata), - .vbuf_readdatavalid(vbuf_readdatavalid), - .vbuf_read(vbuf_read) -`endif + //128-bit DDR3 RAM access + // HDMI frame buffer + .vbuf_clk(clk_100m), + .vbuf_address(vbuf_address), + .vbuf_burstcount(vbuf_burstcount), + .vbuf_waitrequest(vbuf_waitrequest), + .vbuf_writedata(vbuf_writedata), + .vbuf_byteenable(vbuf_byteenable), + .vbuf_write(vbuf_write), + .vbuf_readdata(vbuf_readdata), + .vbuf_readdatavalid(vbuf_readdatavalid), + .vbuf_read(vbuf_read) ); -`ifndef LITE +wire [28:0] ram2_address; +wire [7:0] ram2_burstcount; +wire [7:0] ram2_byteenable; +wire ram2_waitrequest; +wire [63:0] ram2_readdata; +wire [63:0] ram2_writedata; +wire ram2_readdatavalid; +wire ram2_read; +wire ram2_write; +wire [7:0] ram2_bcnt; + +ddr_svc ddr_svc +( + .clk(clk_audio), + + .ram_waitrequest(ram2_waitrequest), + .ram_burstcnt(ram2_burstcount), + .ram_addr(ram2_address), + .ram_readdata(ram2_readdata), + .ram_read_ready(ram2_readdatavalid), + .ram_read(ram2_read), + .ram_writedata(ram2_writedata), + .ram_byteenable(ram2_byteenable), + .ram_write(ram2_write), + .ram_bcnt(ram2_bcnt), + + .ch0_addr(alsa_address), + .ch0_burst(1), + .ch0_data(alsa_readdata), + .ch0_req(alsa_req), + .ch0_ready(alsa_ready), + + .ch1_addr(pal_addr), + .ch1_burst(128), + .ch1_data(pal_data), + .ch1_req(pal_req), + .ch1_ready(pal_wr) +); + +wire clk_pal = clk_audio; + + wire [27:0] vbuf_address; wire [7:0] vbuf_burstcount; wire vbuf_waitrequest; @@ -544,57 +613,325 @@ wire [127:0] vbuf_writedata; wire [15:0] vbuf_byteenable; wire vbuf_write; -assign HDMI_TX_VS = vs_hdmi; -assign HDMI_TX_HS = hs_hdmi; +wire [23:0] hdmi_data; +wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl; +wire freeze; -hdmi_lite hdmi_lite +`ifndef MISTER_DEBUG_NOHDMI +wire clk_hdmi = hdmi_clk_out; + +ascal +#( + .RAMBASE(32'h20000000), +`ifndef MISTER_FB + .PALETTE2("false"), +`else + `ifndef MISTER_FB_PALETTE + .PALETTE2("false"), + `endif +`endif + .N_DW(128), + .N_AW(28) +) +ascal ( - .reset(reset), + .reset_na (~reset_req), + .run (1), + .freeze (freeze), - .clk_video(clk_vid), - .ce_pixel(ce_pix), - .video_vs(vs), - .video_de(de), - .video_d({r_out,g_out,b_out}), + .i_clk (clk_ihdmi), + .i_ce (ce_hpix), + .i_r (hr_out), + .i_g (hg_out), + .i_b (hb_out), + .i_hs (hhs_fix), + .i_vs (hvs_fix), + .i_fl (f1), + .i_de (hde_emu), + .iauto (1), + .himin (0), + .himax (0), + .vimin (0), + .vimax (0), - .clk_hdmi(HDMI_TX_CLK), - .hdmi_hde(hde), - .hdmi_vde(vde), - .hdmi_d(hdmi_data), - .hdmi_de(hdmi_de), + .o_clk (clk_hdmi), + .o_ce (scaler_out), + .o_r (hdmi_data[23:16]), + .o_g (hdmi_data[15:8]), + .o_b (hdmi_data[7:0]), + .o_hs (hdmi_hs), + .o_vs (hdmi_vs), + .o_de (hdmi_de), + .o_vbl (hdmi_vbl), + .o_lltune (lltune), + .htotal (WIDTH + HFP + HBP + HS), + .hsstart (WIDTH + HFP), + .hsend (WIDTH + HFP + HS), + .hdisp (WIDTH), + .hmin (hmin), + .hmax (hmax), + .vtotal (HEIGHT + VFP + VBP + VS), + .vsstart (HEIGHT + VFP), + .vsend (HEIGHT + VFP + VS), + .vdisp (HEIGHT), + .vmin (vmin), + .vmax (vmax), - .screen_w(WIDTH), - .screen_h(HEIGHT), - .quadbuf(1), - .scale_x(0), - .scale_y(0), - .scale_auto(1), + .mode ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}), + .poly_clk (clk_sys), + .poly_a (coef_addr), + .poly_dw (coef_data), + .poly_wr (coef_wr), - .clk_vbuf(clk_ctl), - .vbuf_address(vbuf_address), - .vbuf_burstcount(vbuf_burstcount), - .vbuf_waitrequest(vbuf_waitrequest), - .vbuf_writedata(vbuf_writedata), - .vbuf_byteenable(vbuf_byteenable), - .vbuf_write(vbuf_write), - .vbuf_readdata(vbuf_readdata), - .vbuf_readdatavalid(vbuf_readdatavalid), - .vbuf_read(vbuf_read) + .pal1_clk (clk_pal), + .pal1_dw (pal_d), + .pal1_a (pal_a), + .pal1_wr (pal_wr), + +`ifdef MISTER_FB + `ifdef MISTER_FB_PALETTE + .pal2_clk (fb_pal_clk), + .pal2_dw (fb_pal_d), + .pal2_dr (fb_pal_q), + .pal2_a (fb_pal_a), + .pal2_wr (fb_pal_wr), + .pal_n (fb_en), + `endif +`endif + + .o_fb_ena (FB_EN), + .o_fb_hsize (FB_WIDTH), + .o_fb_vsize (FB_HEIGHT), + .o_fb_format (FB_FMT), + .o_fb_base (FB_BASE), + .o_fb_stride (FB_STRIDE), + + .avl_clk (clk_100m), + .avl_waitrequest (vbuf_waitrequest), + .avl_readdata (vbuf_readdata), + .avl_readdatavalid(vbuf_readdatavalid), + .avl_burstcount (vbuf_burstcount), + .avl_writedata (vbuf_writedata), + .avl_address (vbuf_address), + .avl_write (vbuf_write), + .avl_read (vbuf_read), + .avl_byteenable (vbuf_byteenable) +); +`endif + +reg LFB_EN = 0; +reg LFB_FLT = 0; +reg [5:0] LFB_FMT = 0; +reg [11:0] LFB_WIDTH = 0; +reg [11:0] LFB_HEIGHT = 0; +reg [11:0] LFB_HMIN = 0; +reg [11:0] LFB_HMAX = 0; +reg [11:0] LFB_VMIN = 0; +reg [11:0] LFB_VMAX = 0; +reg [31:0] LFB_BASE = 0; +reg [13:0] LFB_STRIDE = 0; + +reg FB_EN = 0; +reg [5:0] FB_FMT = 0; +reg [11:0] FB_WIDTH = 0; +reg [11:0] FB_HEIGHT = 0; +reg [31:0] FB_BASE = 0; +reg [13:0] FB_STRIDE = 0; + +always @(posedge clk_sys) begin + FB_EN <= LFB_EN | fb_en; + if(LFB_EN) begin + FB_FMT <= LFB_FMT; + FB_WIDTH <= LFB_WIDTH; + FB_HEIGHT <= LFB_HEIGHT; + FB_BASE <= LFB_BASE; + FB_STRIDE <= LFB_STRIDE; + end + else begin + FB_FMT <= fb_fmt; + FB_WIDTH <= fb_width; + FB_HEIGHT <= fb_height; + FB_BASE <= fb_base; + FB_STRIDE <= fb_stride; + end +end + +`ifdef MISTER_FB +reg fb_vbl; +always @(posedge clk_vid) fb_vbl <= hdmi_vbl; +`endif + +reg ar_md_start; +wire ar_md_busy; +reg [11:0] ar_md_mul1, ar_md_mul2, ar_md_div; +wire [11:0] ar_md_res; + +sys_umuldiv #(12,12,12) ar_muldiv +( + .clk(clk_vid), + .start(ar_md_start), + .busy(ar_md_busy), + + .mul1(ar_md_mul1), + .mul2(ar_md_mul2), + .div(ar_md_div), + .result(ar_md_res) ); +reg [11:0] hmin; +reg [11:0] hmax; +reg [11:0] vmin; +reg [11:0] vmax; +reg [11:0] hdmi_height; +reg [11:0] hdmi_width; + +always @(posedge clk_vid) begin + reg [11:0] hmini,hmaxi,vmini,vmaxi; + reg [11:0] wcalc,videow,arx; + reg [11:0] hcalc,videoh,ary; + reg [2:0] state; + reg xy; + + hdmi_height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT; + hdmi_width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH; + + if(!ARY) begin + if(ARX == 1) begin + arx <= arc1x[11:0]; + ary <= arc1y[11:0]; + xy <= arc1x[12] | arc1y[12]; + end + else if(ARX == 2) begin + arx <= arc2x[11:0]; + ary <= arc2y[11:0]; + xy <= arc2x[12] | arc2y[12]; + end + else begin + arx <= 0; + ary <= 0; + xy <= 0; + end + end + else begin + arx <= ARX[11:0]; + ary <= ARY[11:0]; + xy <= ARX[12] | ARY[12]; + end + + ar_md_start <= 0; + state <= state + 1'd1; + case(state) + 0: if(LFB_EN) begin + hmini <= LFB_HMIN; + vmini <= LFB_VMIN; + hmaxi <= LFB_HMAX; + vmaxi <= LFB_VMAX; + state <= 0; + end + else if(FREESCALE || !arx || !ary) begin + wcalc <= hdmi_width; + hcalc <= hdmi_height; + state <= 6; + end + else if(xy) begin + wcalc <= arx; + hcalc <= ary; + state <= 6; + end + + 1: begin + ar_md_mul1 <= hdmi_height; + ar_md_mul2 <= arx; + ar_md_div <= ary; + ar_md_start<= 1; + end + 2: begin + wcalc <= ar_md_res; + if(ar_md_start | ar_md_busy) state <= 2; + end + + 3: begin + ar_md_mul1 <= hdmi_width; + ar_md_mul2 <= ary; + ar_md_div <= arx; + ar_md_start<= 1; + end + 4: begin + hcalc <= ar_md_res; + if(ar_md_start | ar_md_busy) state <= 4; + end + + 6: begin + videow <= (wcalc > hdmi_width) ? hdmi_width : wcalc[11:0]; + videoh <= (hcalc > hdmi_height) ? hdmi_height : hcalc[11:0]; + end + + 7: begin + hmini <= ((WIDTH - videow)>>1); + hmaxi <= ((WIDTH - videow)>>1) + videow - 1'd1; + vmini <= ((HEIGHT - videoh)>>1); + vmaxi <= ((HEIGHT - videoh)>>1) + videoh - 1'd1; + end + endcase + + hmin <= hmini; + hmax <= hmaxi; + vmin <= vmini; + vmax <= vmaxi; +end + +`ifndef MISTER_DEBUG_NOHDMI +wire [15:0] lltune; +pll_hdmi_adj pll_hdmi_adj +( + .clk(FPGA_CLK1_50), + .reset_na(~reset_req), + + .llena(lowlat), + .lltune({16{hdmi_config_done | cfg_dis}} & lltune), + .locked(led_locked), + .i_waitrequest(adj_waitrequest), + .i_write(adj_write), + .i_address(adj_address), + .i_writedata(adj_data), + .o_waitrequest(cfg_waitrequest), + .o_write(cfg_write), + .o_address(cfg_address), + .o_writedata(cfg_data) +); +`else + assign led_locked = 0; `endif +wire [63:0] pal_data; +wire [47:0] pal_d = {pal_data[55:32], pal_data[23:0]}; +wire [6:0] pal_a = ram2_bcnt[6:0]; +wire pal_wr; + +reg [28:0] pal_addr; +reg pal_req = 0; +always @(posedge clk_pal) begin + reg old_vs1, old_vs2; + + pal_addr <= LFB_BASE[31:3] - 29'd512; + + old_vs1 <= hdmi_vs; + old_vs2 <= old_vs1; + + if(~old_vs2 & old_vs1 & ~FB_FMT[2] & FB_FMT[1] & FB_FMT[0] & FB_EN) pal_req <= ~pal_req; +end + ///////////////////////// HDMI output ///////////////////////////////// - -`ifndef LITE +`ifndef MISTER_DEBUG_NOHDMI +wire hdmi_clk_out; pll_hdmi pll_hdmi ( - .refclk(FPGA_CLK1_50), - .rst(reset_req), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - .outclk_0(HDMI_TX_CLK) + .refclk(FPGA_CLK1_50), + .rst(reset_req), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + .outclk_0(hdmi_clk_out) ); `endif @@ -607,272 +944,496 @@ reg [11:0] HEIGHT = 1080; reg [11:0] VFP = 4; reg [11:0] VS = 5; reg [11:0] VBP = 36; -reg [11:0] VSET = 0; -`ifndef LITE wire [63:0] reconfig_to_pll; wire [63:0] reconfig_from_pll; -`endif -reg cfg_write; -reg [5:0] cfg_address; -reg [31:0] cfg_data; +wire cfg_waitrequest,adj_waitrequest; +wire cfg_write; +wire [5:0] cfg_address; +wire [31:0] cfg_data; +reg adj_write; +reg [5:0] adj_address; +reg [31:0] adj_data; -`ifndef LITE -pll_hdmi_cfg pll_hdmi_cfg +`ifndef MISTER_DEBUG_NOHDMI +pll_cfg pll_cfg ( - .mgmt_clk(FPGA_CLK1_50), - .mgmt_reset(reset_req), - .mgmt_waitrequest(cfg_waitrequest), - .mgmt_read(0), - .mgmt_readdata(), - .mgmt_write(cfg_write), - .mgmt_address(cfg_address), - .mgmt_writedata(cfg_data), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) + .mgmt_clk(FPGA_CLK1_50), + .mgmt_reset(reset_req), + .mgmt_waitrequest(cfg_waitrequest), + .mgmt_read(0), + .mgmt_readdata(), + .mgmt_write(cfg_write), + .mgmt_address(cfg_address), + .mgmt_writedata(cfg_data), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) ); -`endif -`ifndef LITE -reg cfg_ready = 0; -wire cfg_waitrequest; -`else -reg cfg_ready = 1; -wire cfg_waitrequest = 1; -`endif - -always @(posedge FPGA_CLK1_50) begin - reg gotd = 0, gotd2 = 0; - reg custd = 0, custd2 = 0; - reg old_wait = 0; - - gotd <= cfg_got; - gotd2 <= gotd; - - cfg_write <= 0; - - custd <= cfg_custom_t; - custd2 <= custd; - if(custd2 != custd & ~gotd) begin - cfg_address <= cfg_custom_p1; - cfg_data <= cfg_custom_p2; - cfg_write <= 1; - end - - if(~gotd2 & gotd) begin - cfg_address <= 2; - cfg_data <= 0; - cfg_write <= 1; - end - - old_wait <= cfg_waitrequest; - if(old_wait & ~cfg_waitrequest & gotd) cfg_ready <= 1; +reg cfg_got = 0; +always @(posedge clk_sys) begin + reg vsd, vsd2; + if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; + else begin + vsd <= HDMI_TX_VS; + vsd2 <= vsd; + if(~vsd2 & vsd) cfg_got <= cfg_set; + end end -`ifndef LITE +reg cfg_ready = 0; +always @(posedge FPGA_CLK1_50) begin + reg gotd = 0, gotd2 = 0; + reg custd = 0, custd2 = 0; + reg old_wait = 0; + + gotd <= cfg_got; + gotd2 <= gotd; + + adj_write <= 0; + + custd <= cfg_custom_t; + custd2 <= custd; + if(custd2 != custd & ~gotd) begin + adj_address <= cfg_custom_p1; + adj_data <= cfg_custom_p2; + adj_write <= 1; + end + + if(~gotd2 & gotd) begin + adj_address <= 2; + adj_data <= 0; + adj_write <= 1; + end + + old_wait <= adj_waitrequest; + if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1; +end + +`else + +wire cfg_ready = 1; + +`endif + +wire hdmi_config_done; hdmi_config hdmi_config ( - .iCLK(FPGA_CLK1_50), - .iRST_N(cfg_ready & ~HDMI_TX_INT), + .iCLK(FPGA_CLK1_50), + .iRST_N(cfg_ready & ~HDMI_TX_INT & ~cfg_dis), + .done(hdmi_config_done), - .I2C_SCL(HDMI_I2C_SCL), - .I2C_SDA(HDMI_I2C_SDA), + .I2C_SCL(HDMI_I2C_SCL), + .I2C_SDA(HDMI_I2C_SDA), - .dvi_mode(dvi_mode), - .audio_96k(audio_96k) + .dvi_mode(dvi_mode), + .audio_96k(audio_96k), + .limited(hdmi_limited), + .ypbpr(ypbpr_en & direct_video) ); -wire [23:0] hdmi_data; -wire hdmi_de; +assign HDMI_I2C_SCL = hdmi_scl_en ? 1'b0 : 1'bZ; +assign HDMI_I2C_SDA = hdmi_sda_en ? 1'b0 : 1'bZ; + +wire hdmi_scl_en, hdmi_sda_en; +cyclonev_hps_interface_peripheral_i2c hdmi_i2c +( + .out_clk(hdmi_scl_en), + .scl(HDMI_I2C_SCL), + .out_data(hdmi_sda_en), + .sda(HDMI_I2C_SDA) +); + +`ifndef MISTER_DEBUG_NOHDMI +wire [23:0] hdmi_data_sl; +wire hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl; + +`ifdef MISTER_FB +reg dis_output; +always @(posedge clk_hdmi) begin + reg dis; + dis <= fb_force_blank; + dis_output <= dis; +end +`else +wire dis_output = 0; +`endif + +scanlines #(1) HDMI_scanlines +( + .clk(clk_hdmi), + + .scanlines(scanlines), + .din(dis_output ? 24'd0 : hdmi_data), + .hs_in(hdmi_hs), + .vs_in(hdmi_vs), + .de_in(hdmi_de), + + .dout(hdmi_data_sl), + .hs_out(hdmi_hs_sl), + .vs_out(hdmi_vs_sl), + .de_out(hdmi_de_sl) +); + +wire [23:0] hdmi_data_osd; +wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd; osd hdmi_osd ( - .clk_sys(clk_sys), + .clk_sys(clk_sys), - .io_osd(io_osd), - .io_strobe(io_strobe), - .io_din(io_din), + .io_osd(io_osd_hdmi), + .io_strobe(io_strobe), + .io_din(io_din), - .clk_video(iHdmiClk), - .din(hdmi_data), - .dout(HDMI_TX_D), - .de_in(hdmi_de), - .de_out(HDMI_TX_DE) -); + .clk_video(clk_hdmi), + .din(hdmi_data_sl), + .hs_in(hdmi_hs_sl), + .vs_in(hdmi_vs_sl), + .de_in(hdmi_de_sl), -assign HDMI_MCLK = 0; -i2s i2s -( - .reset(~cfg_ready), - .clk_sys(FPGA_CLK3_50), - .half_rate(~audio_96k), - - .sclk(HDMI_SCLK), - .lrclk(HDMI_LRCLK), - .sdata(HDMI_I2S), - - //Could inverse the MSB but it will shift 0 level to -MAX level - .left_chan (audio_l >> !audio_s), - .right_chan(audio_r >> !audio_s) + .dout(hdmi_data_osd), + .hs_out(hdmi_hs_osd), + .vs_out(hdmi_vs_osd), + .de_out(hdmi_de_osd) ); `endif +wire hdmi_cs_osd; +csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); + +reg [23:0] dv_data; +reg dv_hs, dv_vs, dv_de; +always @(posedge clk_vid) begin + reg [23:0] dv_d1, dv_d2; + reg dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2; + reg [12:0] vsz, vcnt; + reg old_hs, old_vs; + reg vde; + reg [3:0] hss; + + if(ce_pix) begin + hss <= (hss << 1) | vga_hs_osd; + + old_hs <= vga_hs_osd; + if(~old_hs && vga_hs_osd) begin + old_vs <= vga_vs_osd; + if(~&vcnt) vcnt <= vcnt + 1'd1; + if(~old_vs & vga_vs_osd & ~f1) vsz <= vcnt; + if(old_vs & ~vga_vs_osd) vcnt <= 0; + + if(vcnt == 1) vde <= 1; + if(vcnt == vsz - 3) vde <= 0; + end + + dv_de1 <= !{hss,vga_hs_osd} && vde; + dv_hs1 <= csync_en ? vga_cs_osd : vga_hs_osd; + dv_vs1 <= vga_vs_osd; + end + + dv_d1 <= vga_data_osd; + dv_d2 <= dv_d1; + dv_de2 <= dv_de1; + dv_hs2 <= dv_hs1; + dv_vs2 <= dv_vs1; + + dv_data<= dv_d2; + dv_de <= dv_de2; + dv_hs <= dv_hs2; + dv_vs <= dv_vs2; +end + +wire hdmi_tx_clk; +`ifndef MISTER_DEBUG_NOHDMI +cyclonev_clkselect hdmi_clk_sw +( + .clkselect({1'b1, ~vga_fb & direct_video}), + .inclk({clk_vid, hdmi_clk_out, 2'b00}), + .outclk(hdmi_tx_clk) +); +`else +assign hdmi_tx_clk = clk_vid; +`endif + +altddio_out +#( + .extend_oe_disable("OFF"), + .intended_device_family("Cyclone V"), + .invert_output("OFF"), + .lpm_hint("UNUSED"), + .lpm_type("altddio_out"), + .oe_reg("UNREGISTERED"), + .power_up_high("OFF"), + .width(1) +) +hdmiclk_ddr +( + .datain_h(1'b0), + .datain_l(1'b1), + .outclock(hdmi_tx_clk), + .dataout(HDMI_TX_CLK), + .aclr(1'b0), + .aset(1'b0), + .oe(1'b1), + .outclocken(1'b1), + .sclr(1'b0), + .sset(1'b0) +); + +reg hdmi_out_hs; +reg hdmi_out_vs; +reg hdmi_out_de; +reg [23:0] hdmi_out_d; + +always @(posedge hdmi_tx_clk) begin + reg hs,vs,de; + reg [23:0] d; + + hs <= (~vga_fb & direct_video) ? dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd; + vs <= (~vga_fb & direct_video) ? dv_vs : hdmi_vs_osd; + de <= (~vga_fb & direct_video) ? dv_de : hdmi_de_osd; + d <= (~vga_fb & direct_video) ? dv_data : hdmi_data_osd; + + hdmi_out_hs <= hs; + hdmi_out_vs <= vs; + hdmi_out_de <= de; + hdmi_out_d <= d; +end + +assign HDMI_TX_HS = hdmi_out_hs; +assign HDMI_TX_VS = hdmi_out_vs; +assign HDMI_TX_DE = hdmi_out_de; +assign HDMI_TX_D = hdmi_out_d; ///////////////////////// VGA output ////////////////////////////////// -wire [23:0] vga_q; +wire [23:0] vga_data_sl; +wire vga_de_sl, vga_vs_sl, vga_hs_sl; +scanlines #(0) VGA_scanlines +( + .clk(clk_vid), + + .scanlines(scanlines), + .din(de_emu ? {r_out, g_out, b_out} : 24'd0), + .hs_in(hs_fix), + .vs_in(vs_fix), + .de_in(de_emu), + + .dout(vga_data_sl), + .hs_out(vga_hs_sl), + .vs_out(vga_vs_sl), + .de_out(vga_de_sl) +); + +wire [23:0] vga_data_osd; +wire vga_vs_osd, vga_hs_osd; osd vga_osd ( - .clk_sys(clk_sys), + .clk_sys(clk_sys), - .io_osd(io_osd), - .io_strobe(io_strobe), - .io_din(io_din), + .io_osd(io_osd_vga), + .io_strobe(io_strobe), + .io_din(io_din), + .osd_status(osd_status), - .clk_video(clk_vid), - .din(de ? {r_out, g_out, b_out} : 24'd0), - .dout(vga_q), - .de_in(de) + .clk_video(clk_vid), + .din(vga_data_sl), + .hs_in(vga_hs_sl), + .vs_in(vga_vs_sl), + .de_in(vga_de_sl), + + .dout(vga_data_osd), + .hs_out(vga_hs_osd), + .vs_out(vga_vs_osd) ); -wire [23:0] vga_o; +wire vga_cs_osd; +csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); -vga_out vga_out -( - .ypbpr_full(1), - .ypbpr_en(ypbpr_en), - .dout(vga_o), -`ifdef LITE - .din(vga_q) -`else - .din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q) -`endif -); +`ifndef MISTER_DUAL_SDRAM + wire [23:0] vgas_o; + wire vgas_hs, vgas_vs, vgas_cs; + vga_out vga_scaler_out + ( + .clk(clk_hdmi), + .ypbpr_en(ypbpr_en), + .hsync(hdmi_hs_osd), + .vsync(hdmi_vs_osd), + .csync(hdmi_cs_osd), + .dout(vgas_o), + .din({24{hdmi_de_osd}} & hdmi_data_osd), + .hsync_o(vgas_hs), + .vsync_o(vgas_vs), + .csync_o(vgas_cs) + ); -`ifdef LITE - wire vs1 = vs; - wire hs1 = hs; -`else - wire vs1 = vga_scaler ? HDMI_TX_VS : vs; - wire hs1 = vga_scaler ? HDMI_TX_HS : hs; + wire [23:0] vga_o; + wire vga_hs, vga_vs, vga_cs; + vga_out vga_out + ( + .clk(clk_vid), + .ypbpr_en(ypbpr_en), + .hsync(vga_hs_osd), + .vsync(vga_vs_osd), + .csync(vga_cs_osd), + .dout(vga_o), + .din(vga_data_osd), + .hsync_o(vga_hs), + .vsync_o(vga_vs), + .csync_o(vga_cs) + ); + + wire cs1 = (vga_fb | vga_scaler) ? vgas_cs : vga_cs; + + assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : ((vga_fb | vga_scaler) ? ~vgas_vs : ~vga_vs) | csync_en; + assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : (vga_fb | vga_scaler) ? (csync_en ? ~vgas_cs : ~vgas_hs) : (csync_en ? ~vga_cs : ~vga_hs); + assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:18] : vga_o[23:18]; + assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:10] : vga_o[15:10]; + assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:2] : vga_o[7:2] ; `endif -assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1; -assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1; -assign VGA_R = VGA_EN ? 6'bZZZZZZ : vga_o[23:18]; -assign VGA_G = VGA_EN ? 6'bZZZZZZ : vga_o[15:10]; -assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2]; -//assign VGA_VS = ~vs1; -//assign VGA_HS = ~hs1; -//assign VGA_R = vga_o[23:18]; -//assign VGA_G = vga_o[15:10]; -//assign VGA_B = vga_o[7:2]; +reg video_sync = 0; +always @(posedge clk_vid) begin + reg [11:0] line_cnt = 0; + reg [11:0] sync_line = 0; + reg [1:0] hs_cnt = 0; + reg old_hs; -// For core -> VGA direct connectivity, comment out vga_osd, vga_out and the above assign statements, then -// uncomment these signals for direct core -> VGA connectivity. -// -//assign VGA_VS = ~vs; -//assign VGA_HS = ~hs; -//assign VGA_R = r_out; -//assign VGA_G = g_out; -//assign VGA_B = b_out; + old_hs <= hs_fix; + if(~old_hs & hs_fix) begin + + video_sync <= (sync_line == line_cnt); + + line_cnt <= line_cnt + 1'd1; + if(~hs_cnt[1]) begin + hs_cnt <= hs_cnt + 1'd1; + if(hs_cnt[0]) begin + sync_line <= (line_cnt - vs_line); + line_cnt <= 0; + end + end + end + + if(de_emu) hs_cnt <= 0; +end ///////////////////////// Audio output //////////////////////////////// -wire al, ar, aspdif; +assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ; -sigma_delta_dac #(15) dac_l -( - .CLK(FPGA_CLK3_50), - .RESET(reset), - .DACin({audio_l[15] ^ audio_s, audio_l[14:0]}), - .DACout(al) -); +`ifndef MISTER_DUAL_SDRAM + wire analog_l, analog_r; -sigma_delta_dac #(15) dac_r -( - .CLK(FPGA_CLK3_50), - .RESET(reset), - .DACin({audio_r[15] ^ audio_s, audio_r[14:0]}), - .DACout(ar) -); - -spdif toslink -( - .clk_i(FPGA_CLK3_50), - - .rst_i(reset), - .half_rate(0), - - .audio_l(audio_l >> !audio_s), - .audio_r(audio_r >> !audio_s), - - .spdif_o(aspdif) -); - -`ifndef LITE -assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif; -assign AUDIO_R = SW[0] ? HDMI_I2S : ar; -assign AUDIO_L = SW[0] ? HDMI_SCLK : al; -`else -assign AUDIO_SPDIF = aspdif; -assign AUDIO_R = ar; -assign AUDIO_L = al; + assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif; + assign AUDIO_R = SW[3] ? 1'bZ : SW[0] ? HDMI_I2S : analog_r; + assign AUDIO_L = SW[3] ? 1'bZ : SW[0] ? HDMI_SCLK : analog_l; `endif -reg [15:0] audio_l; -reg [15:0] audio_r; +assign HDMI_MCLK = clk_audio; +wire clk_audio; -always @(posedge FPGA_CLK3_50) begin - reg signed [15:0] al; - reg signed [15:0] ar; +pll_audio pll_audio +( + .refclk(FPGA_CLK3_50), + .rst(0), + .outclk_0(clk_audio) +); - case({audio_s,audio_mix}) - 'b000: al <= audio_ls; - 'b001: al <= audio_ls - (audio_ls >> 3) + (audio_rs >> 3); - 'b010: al <= audio_ls - (audio_ls >> 2) + (audio_rs >> 2); - 'b011: al <= (audio_ls >> 1) + (audio_rs >> 1); - 'b100: al <= audio_ls; - 'b101: al <= audio_ls - (audio_ls >>> 3) + (audio_rs >>> 3); - 'b110: al <= audio_ls - (audio_ls >>> 2) + (audio_rs >>> 2); - 'b111: al <= (audio_ls >>> 1) + (audio_rs >>> 1); - endcase +wire spdif; +audio_out audio_out +( + .reset(reset | areset), + .clk(clk_audio), + + .att(vol_att), + .mix(audio_mix), + .sample_rate(audio_96k), + + .flt_rate(aflt_rate), + .cx(acx), + .cx0(acx0), + .cx1(acx1), + .cx2(acx2), + .cy0(acy0), + .cy1(acy1), + .cy2(acy2), + + .is_signed(audio_s), + .core_l(audio_l), + .core_r(audio_r), + + .alsa_l(alsa_l), + .alsa_r(alsa_r), + + .i2s_bclk(HDMI_SCLK), + .i2s_lrclk(HDMI_LRCLK), + .i2s_data(HDMI_I2S), +`ifndef MISTER_DUAL_SDRAM + .dac_l(analog_l), + .dac_r(analog_r), +`endif + .spdif(spdif) +); + + +wire [28:0] alsa_address; +wire [63:0] alsa_readdata; +wire alsa_ready; +wire alsa_req; +wire alsa_late; + +wire [15:0] alsa_l, alsa_r; + +alsa alsa +( + .reset(reset), + .clk(clk_audio), + + .ram_address(alsa_address), + .ram_data(alsa_readdata), + .ram_req(alsa_req), + .ram_ready(alsa_ready), + + .spi_ss(aspi_ss), + .spi_sck(aspi_sck), + .spi_mosi(aspi_mosi), + .spi_miso(aspi_miso), + + .pcm_l(alsa_l), + .pcm_r(alsa_r) +); + +//////////////// User I/O (USB 3.0 connector) ///////////////////////// + +assign USER_IO[0] = !user_out[0] ? 1'b0 : 1'bZ; +assign USER_IO[1] = !user_out[1] ? 1'b0 : 1'bZ; +assign USER_IO[2] = !(SW[1] ? HDMI_I2S : user_out[2]) ? 1'b0 : 1'bZ; +assign USER_IO[3] = !user_out[3] ? 1'b0 : 1'bZ; +assign USER_IO[4] = !(SW[1] ? HDMI_SCLK : user_out[4]) ? 1'b0 : 1'bZ; +assign USER_IO[5] = !(SW[1] ? HDMI_LRCLK : user_out[5]) ? 1'b0 : 1'bZ; +assign USER_IO[6] = !user_out[6] ? 1'b0 : 1'bZ; + +assign user_in[0] = USER_IO[0]; +assign user_in[1] = USER_IO[1]; +assign user_in[2] = SW[1] | USER_IO[2]; +assign user_in[3] = USER_IO[3]; +assign user_in[4] = SW[1] | USER_IO[4]; +assign user_in[5] = SW[1] | USER_IO[5]; +assign user_in[6] = USER_IO[6]; - case({audio_s,audio_mix}) - 'b000: ar <= audio_rs; - 'b001: ar <= audio_rs - (audio_rs >> 3) + (audio_ls >> 3); - 'b010: ar <= audio_rs - (audio_rs >> 2) + (audio_ls >> 2); - 'b011: ar <= (audio_rs >> 1) + (audio_ls >> 1); - 'b100: ar <= audio_rs; - 'b101: ar <= audio_rs - (audio_rs >>> 3) + (audio_ls >>> 3); - 'b110: ar <= audio_rs - (audio_rs >>> 2) + (audio_ls >>> 2); - 'b111: ar <= (audio_rs >>> 1) + (audio_ls >>> 1); - endcase - - if(vol_att[4]) begin - audio_l <= 0; - audio_r <= 0; - end - else - if(audio_s) begin - audio_l <= al >>> vol_att[3:0]; - audio_r <= ar >>> vol_att[3:0]; - end - else - begin - audio_l <= al >> vol_att[3:0]; - audio_r <= ar >> vol_att[3:0]; - end -end /////////////////// User module connection //////////////////////////// -wire signed [15:0] audio_ls, audio_rs; +wire clk_sys; +wire [15:0] audio_l, audio_r; wire audio_s; wire [1:0] audio_mix; -wire [7:0] r_out, g_out, b_out; -wire vs, hs, de; -wire clk_sys, clk_vid, ce_pix; +wire [1:0] scanlines; +wire [7:0] r_out, g_out, b_out, hr_out, hg_out, hb_out; +wire vs_fix, hs_fix, de_emu, vs_emu, hs_emu, f1; +wire hvs_fix, hhs_fix, hde_emu; +wire clk_vid, ce_pix, clk_ihdmi, ce_hpix; +wire vga_force_scaler; wire ram_clk; wire [28:0] ram_address; @@ -888,117 +1449,248 @@ wire ram_write; wire led_user; wire [1:0] led_power; wire [1:0] led_disk; +wire [1:0] btn; -wire vs_emu, hs_emu; -sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs); -sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs); +sync_fix sync_v(clk_vid, vs_emu, vs_fix); +sync_fix sync_h(clk_vid, hs_emu, hs_fix); + +wire [6:0] user_out, user_in; + +assign clk_ihdmi= clk_vid; +assign ce_hpix = ce_pix; +assign hr_out = r_out; +assign hg_out = g_out; +assign hb_out = b_out; +assign hhs_fix = hs_fix; +assign hvs_fix = vs_fix; +assign hde_emu = de_emu; + +wire uart_dtr; +wire uart_dsr; +wire uart_cts; +wire uart_rts; +wire uart_rxd; +wire uart_txd; + +wire osd_status; + +wire fb_en; +wire [4:0] fb_fmt; +wire [11:0] fb_width; +wire [11:0] fb_height; +wire [31:0] fb_base; +wire [13:0] fb_stride; + + +`ifdef MISTER_FB + `ifdef MISTER_FB_PALETTE + wire fb_pal_clk; + wire [7:0] fb_pal_a; + wire [23:0] fb_pal_d; + wire [23:0] fb_pal_q; + wire fb_pal_wr; + `endif + wire fb_force_blank; +`else + assign fb_en = 0; + assign fb_fmt = 0; + assign fb_width = 0; + assign fb_height = 0; + assign fb_base = 0; + assign fb_stride = 0; +`endif emu emu ( - .CLK_50M(FPGA_CLK3_50), - .RESET(reset), + .CLK_50M(FPGA_CLK2_50), + .RESET(reset), + .HPS_BUS({f1, HDMI_TX_VS, + clk_100m, clk_ihdmi, + ce_hpix, hde_emu, hhs_fix, hvs_fix, + io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), - // 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 16b 16b - // 44 43 42 41 40 39 38 37 36 35 34 33 32 31:16 15:0 - .HPS_BUS({HDMI_TX_VS, clk_ctl, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), + .VGA_R(r_out), + .VGA_G(g_out), + .VGA_B(b_out), + .VGA_HS(hs_emu), + .VGA_VS(vs_emu), + .VGA_DE(de_emu), + .VGA_F1(f1), + .VGA_SCALER(vga_force_scaler), - .CLK_VIDEO(clk_vid), - .CE_PIXEL(ce_pix), + .HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width), + .HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height), + .HDMI_FREEZE(freeze), - .VGA_R(r_out), - .VGA_G(g_out), - .VGA_B(b_out), - .VGA_HS(hs_emu), - .VGA_VS(vs_emu), - .VGA_DE(de), + .CLK_VIDEO(clk_vid), + .CE_PIXEL(ce_pix), + .VGA_SL(scanlines), + .VIDEO_ARX(ARX), + .VIDEO_ARY(ARY), - .LED_USER(led_user), - .LED_POWER(led_power), - .LED_DISK(led_disk), - .LED_MB(led_mb), +`ifdef MISTER_FB + .FB_EN(fb_en), + .FB_FORMAT(fb_fmt), + .FB_WIDTH(fb_width), + .FB_HEIGHT(fb_height), + .FB_BASE(fb_base), + .FB_STRIDE(fb_stride), + .FB_VBL(fb_vbl), + .FB_LL(lowlat), + .FB_FORCE_BLANK(fb_force_blank), - `ifndef LITE - .VIDEO_ARX(ARX), - .VIDEO_ARY(ARY), - `endif - - .AUDIO_L(audio_ls), - .AUDIO_R(audio_rs), - .AUDIO_S(audio_s), - .AUDIO_MIX(audio_mix), - //.TAPE_IN(0), - - // SCK -> CLK - // MOSI -> CMD - // MISO <- DAT0 - // Z -> DAT1 - // Z -> DAT2 - // CS -> DAT3 - .SD_SCK(SDIO_CLK), - .SD_MOSI(SDIO_CMD), - .SD_MISO(SDIO_DAT[0]), - .SD_CS(SDIO_DAT[3]), - .SD_CD(VGA_EN ? VGA_HS : SDIO_CD), - - - - .DDRAM_CLK(ram_clk), - .DDRAM_ADDR(ram_address), - .DDRAM_BURSTCNT(ram_burstcount), - .DDRAM_BUSY(ram_waitrequest), - .DDRAM_DOUT(ram_readdata), - .DDRAM_DOUT_READY(ram_readdatavalid), - .DDRAM_RD(ram_read), - .DDRAM_DIN(ram_writedata), - .DDRAM_BE(ram_byteenable), - .DDRAM_WE(ram_write) - -`ifndef LITE - , - .SDRAM_DQ(SDRAM_DQ), - .SDRAM_A(SDRAM_A), - .SDRAM_DQML(SDRAM_DQML), - .SDRAM_DQMH(SDRAM_DQMH), - .SDRAM_BA(SDRAM_BA), - .SDRAM_nCS(SDRAM_nCS), - .SDRAM_nWE(SDRAM_nWE), - .SDRAM_nRAS(SDRAM_nRAS), - .SDRAM_nCAS(SDRAM_nCAS), - .SDRAM_CLK(SDRAM_CLK), - .SDRAM_CKE(SDRAM_CKE) -`else - ,.UART_RX(UART_RX), - .UART_TX(UART_TX) +`ifdef MISTER_FB_PALETTE + .FB_PAL_CLK (fb_pal_clk), + .FB_PAL_ADDR(fb_pal_a), + .FB_PAL_DOUT(fb_pal_d), + .FB_PAL_DIN (fb_pal_q), + .FB_PAL_WR (fb_pal_wr), `endif - ); - endmodule +`endif - module sync_fix - ( - input clk, - - input sync_in, - output sync_out - ); + .LED_USER(led_user), + .LED_POWER(led_power), + .LED_DISK(led_disk), - assign sync_out = sync_in ^ pol; + .CLK_AUDIO(clk_audio), + .AUDIO_L(audio_l), + .AUDIO_R(audio_r), + .AUDIO_S(audio_s), + .AUDIO_MIX(audio_mix), - reg pol; - always @(posedge clk) begin - integer pos = 0, neg = 0, cnt = 0; - reg s1,s2; + .ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}), - s1 <= sync_in; - s2 <= s1; + .DDRAM_CLK(ram_clk), + .DDRAM_ADDR(ram_address), + .DDRAM_BURSTCNT(ram_burstcount), + .DDRAM_BUSY(ram_waitrequest), + .DDRAM_DOUT(ram_readdata), + .DDRAM_DOUT_READY(ram_readdatavalid), + .DDRAM_RD(ram_read), + .DDRAM_DIN(ram_writedata), + .DDRAM_BE(ram_byteenable), + .DDRAM_WE(ram_write), - if(~s2 & s1) neg <= cnt; - if(s2 & ~s1) pos <= cnt; + .SDRAM_DQ(SDRAM_DQ), + .SDRAM_A(SDRAM_A), + .SDRAM_DQML(SDRAM_DQML), + .SDRAM_DQMH(SDRAM_DQMH), + .SDRAM_BA(SDRAM_BA), + .SDRAM_nCS(SDRAM_nCS), + .SDRAM_nWE(SDRAM_nWE), + .SDRAM_nRAS(SDRAM_nRAS), + .SDRAM_nCAS(SDRAM_nCAS), + .SDRAM_CLK(SDRAM_CLK), + .SDRAM_CKE(SDRAM_CKE), - cnt <= cnt + 1; - if(s2 != s1) cnt <= 0; +`ifdef MISTER_DUAL_SDRAM + .SDRAM2_DQ(SDRAM2_DQ), + .SDRAM2_A(SDRAM2_A), + .SDRAM2_BA(SDRAM2_BA), + .SDRAM2_nCS(SDRAM2_nCS), + .SDRAM2_nWE(SDRAM2_nWE), + .SDRAM2_nRAS(SDRAM2_nRAS), + .SDRAM2_nCAS(SDRAM2_nCAS), + .SDRAM2_CLK(SDRAM2_CLK), + .SDRAM2_EN(SW[3]), +`endif - pol <= pos > neg; - end + .BUTTONS(btn), + .OSD_STATUS(osd_status), + + .SD_SCK(SD_CLK), + .SD_MOSI(SD_MOSI), + .SD_MISO(SD_MISO), + .SD_CS(SD_CS), +`ifdef MISTER_DUAL_SDRAM + .SD_CD(mcp_sdcd), +`else + .SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))), +`endif + + .UART_CTS(uart_rts), + .UART_RTS(uart_cts), + .UART_RXD(uart_txd), + .UART_TXD(uart_rxd), + .UART_DTR(uart_dsr), + .UART_DSR(uart_dtr), + + .USER_OUT(user_out), + .USER_IN(user_in) +); + +endmodule + +///////////////////////////////////////////////////////////////////// + +module sync_fix +( + input clk, + + input sync_in, + output sync_out +); + +assign sync_out = sync_in ^ pol; + +reg pol; +always @(posedge clk) begin + integer pos = 0, neg = 0, cnt = 0; + reg s1,s2; + + s1 <= sync_in; + s2 <= s1; + + if(~s2 & s1) neg <= cnt; + if(s2 & ~s1) pos <= cnt; + + cnt <= cnt + 1; + if(s2 != s1) cnt <= 0; + + pol <= pos > neg; +end + +endmodule + +///////////////////////////////////////////////////////////////////// + +// CSync generation +// Shifts HSync left by 1 HSync period during VSync + +module csync +( + input clk, + input hsync, + input vsync, + + output csync +); + +assign csync = (csync_vs ^ csync_hs); + +reg csync_hs, csync_vs; +always @(posedge clk) begin + reg prev_hs; + reg [15:0] h_cnt, line_len, hs_len; + + // Count line/Hsync length + h_cnt <= h_cnt + 1'd1; + + prev_hs <= hsync; + if (prev_hs ^ hsync) begin + h_cnt <= 0; + if (hsync) begin + line_len <= h_cnt - hs_len; + csync_hs <= 0; + end + else hs_len <= h_cnt; + end + + if (~vsync) csync_hs <= hsync; + else if(h_cnt == line_len) csync_hs <= 1; + + csync_vs <= vsync; +end endmodule diff --git a/sys/sysmem.sv b/sys/sysmem.sv index 886b9b3..8c17e86 100644 --- a/sys/sysmem.sv +++ b/sys/sysmem.sv @@ -1,204 +1,243 @@ `timescale 1 ps / 1 ps module sysmem_lite ( - input ramclk1_clk, // ramclk1.clk - input [28:0] ram1_address, // ram1.address - input [7:0] ram1_burstcount, // .burstcount - output ram1_waitrequest, // .waitrequest - output [63:0] ram1_readdata, // .readdata - output ram1_readdatavalid, // .readdatavalid - input ram1_read, // .read - input [63:0] ram1_writedata, // .writedata - input [7:0] ram1_byteenable, // .byteenable - input ram1_write, // .write + output clock, + output reset_out, - input ramclk2_clk, // ramclk2.clk - input [28:0] ram2_address, // ram2.address - input [7:0] ram2_burstcount, // .burstcount - output ram2_waitrequest, // .waitrequest - output [63:0] ram2_readdata, // .readdata - output ram2_readdatavalid, // .readdatavalid - input ram2_read, // .read - input [63:0] ram2_writedata, // .writedata - input [7:0] ram2_byteenable, // .byteenable - input ram2_write, // .write + input reset_hps_cold_req, + input reset_hps_warm_req, + input reset_core_req, - output ctl_clock, - input reset_cold_req, // reset.cold_req - output reset_reset, // .reset - input reset_reset_req, // .reset_req - input reset_warm_req, // .warm_req + input ram1_clk, + input [28:0] ram1_address, + input [7:0] ram1_burstcount, + output ram1_waitrequest, + output [63:0] ram1_readdata, + output ram1_readdatavalid, + input ram1_read, + input [63:0] ram1_writedata, + input [7:0] ram1_byteenable, + input ram1_write, - input vbuf_clk, // vbuf.clk - input [27:0] vbuf_address, // vbuf.address - input [7:0] vbuf_burstcount, // .burstcount - output vbuf_waitrequest, // .waitrequest - output [127:0] vbuf_readdata, // .readdata - output vbuf_readdatavalid, // .readdatavalid - input vbuf_read, // .read - input [127:0] vbuf_writedata, // .writedata - input [15:0] vbuf_byteenable, // .byteenable - input vbuf_write // .write + input ram2_clk, + input [28:0] ram2_address, + input [7:0] ram2_burstcount, + output ram2_waitrequest, + output [63:0] ram2_readdata, + output ram2_readdatavalid, + input ram2_read, + input [63:0] ram2_writedata, + input [7:0] ram2_byteenable, + input ram2_write, + + input vbuf_clk, + input [27:0] vbuf_address, + input [7:0] vbuf_burstcount, + output vbuf_waitrequest, + output [127:0] vbuf_readdata, + output vbuf_readdatavalid, + input vbuf_read, + input [127:0] vbuf_writedata, + input [15:0] vbuf_byteenable, + input vbuf_write ); -assign ctl_clock = clk_vip_clk; +assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req; -wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps -wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n -wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n -wire clk_vip_clk; +//////////////////////////////////////////////////////// +//// f2sdram_safe_terminator_ram1 //// +//////////////////////////////////////////////////////// +wire [28:0] f2h_ram1_address; +wire [7:0] f2h_ram1_burstcount; +wire f2h_ram1_waitrequest; +wire [63:0] f2h_ram1_readdata; +wire f2h_ram1_readdatavalid; +wire f2h_ram1_read; +wire [63:0] f2h_ram1_writedata; +wire [7:0] f2h_ram1_byteenable; +wire f2h_ram1_write; -sysmem_HPS_fpga_interfaces fpga_interfaces ( - .f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n - .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n - .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk - .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n - .f2h_sdram0_clk (vbuf_clk), // f2h_sdram0_clock.clk - .f2h_sdram0_ADDRESS (vbuf_address), // f2h_sdram0_data.address - .f2h_sdram0_BURSTCOUNT (vbuf_burstcount), // .burstcount - .f2h_sdram0_WAITREQUEST (vbuf_waitrequest), // .waitrequest - .f2h_sdram0_READDATA (vbuf_readdata), // .readdata - .f2h_sdram0_READDATAVALID (vbuf_readdatavalid), // .readdatavalid - .f2h_sdram0_READ (vbuf_read), // .read - .f2h_sdram0_WRITEDATA (vbuf_writedata), // .writedata - .f2h_sdram0_BYTEENABLE (vbuf_byteenable), // .byteenable - .f2h_sdram0_WRITE (vbuf_write), // .write - .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk - .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address - .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount - .f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest - .f2h_sdram1_READDATA (ram1_readdata), // .readdata - .f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid - .f2h_sdram1_READ (ram1_read), // .read - .f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata - .f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable - .f2h_sdram1_WRITE (ram1_write), // .write - .f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk - .f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address - .f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount - .f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest - .f2h_sdram2_READDATA (ram2_readdata), // .readdata - .f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid - .f2h_sdram2_READ (ram2_read), // .read - .f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata - .f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable - .f2h_sdram2_WRITE (ram2_write) // .write -); +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_0 = 1'b1; +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_1 = 1'b1; +always @(posedge ram1_clk) begin + ram1_reset_0 <= reset_out; + ram1_reset_1 <= ram1_reset_0; +end -reset_source reset_source ( - .clk (clk_vip_clk), // clock.clk - .reset_hps (~hps_h2f_reset_reset), // reset_hps.reset - .reset_sys (), // reset_sys.reset - .cold_req (reset_cold_req), // reset_ctl.cold_req - .reset (reset_reset), // .reset - .reset_req (reset_reset_req), // .reset_req - .reset_vip (0), // .reset_vip - .warm_req (reset_warm_req), // .warm_req - .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset - .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset -); - -endmodule - -`timescale 1 ps / 1 ps -module sysmem +f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram1 ( - input ramclk1_clk, // ramclk1.clk - input [28:0] ram1_address, // ram1.address - input [7:0] ram1_burstcount, // .burstcount - output ram1_waitrequest, // .waitrequest - output [63:0] ram1_readdata, // .readdata - output ram1_readdatavalid, // .readdatavalid - input ram1_read, // .read - input [63:0] ram1_writedata, // .writedata - input [7:0] ram1_byteenable, // .byteenable - input ram1_write, // .write + .clk (ram1_clk), + .rst_req_sync (ram1_reset_1), - input ramclk2_clk, // ramclk2.clk - input [28:0] ram2_address, // ram2.address - input [7:0] ram2_burstcount, // .burstcount - output ram2_waitrequest, // .waitrequest - output [63:0] ram2_readdata, // .readdata - output ram2_readdatavalid, // .readdatavalid - input ram2_read, // .read - input [63:0] ram2_writedata, // .writedata - input [7:0] ram2_byteenable, // .byteenable - input ram2_write, // .write + .waitrequest_slave (ram1_waitrequest), + .burstcount_slave (ram1_burstcount), + .address_slave (ram1_address), + .readdata_slave (ram1_readdata), + .readdatavalid_slave (ram1_readdatavalid), + .read_slave (ram1_read), + .writedata_slave (ram1_writedata), + .byteenable_slave (ram1_byteenable), + .write_slave (ram1_write), - input reset_cold_req, // reset.cold_req - output reset_reset, // .reset - input reset_reset_req, // .reset_req - input reset_warm_req, // .warm_req - - input [27:0] ram_vip_address, // ram_vip.address - input [7:0] ram_vip_burstcount, // .burstcount - output ram_vip_waitrequest, // .waitrequest - output [127:0] ram_vip_readdata, // .readdata - output ram_vip_readdatavalid, // .readdatavalid - input ram_vip_read, // .read - input [127:0] ram_vip_writedata, // .writedata - input [15:0] ram_vip_byteenable, // .byteenable - input ram_vip_write, // .write - - output clk_vip_clk, // clk_vip.clk - output reset_vip_reset // reset_vip.reset + .waitrequest_master (f2h_ram1_waitrequest), + .burstcount_master (f2h_ram1_burstcount), + .address_master (f2h_ram1_address), + .readdata_master (f2h_ram1_readdata), + .readdatavalid_master (f2h_ram1_readdatavalid), + .read_master (f2h_ram1_read), + .writedata_master (f2h_ram1_writedata), + .byteenable_master (f2h_ram1_byteenable), + .write_master (f2h_ram1_write) ); -wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps -wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n -wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n +//////////////////////////////////////////////////////// +//// f2sdram_safe_terminator_ram2 //// +//////////////////////////////////////////////////////// +wire [28:0] f2h_ram2_address; +wire [7:0] f2h_ram2_burstcount; +wire f2h_ram2_waitrequest; +wire [63:0] f2h_ram2_readdata; +wire f2h_ram2_readdatavalid; +wire f2h_ram2_read; +wire [63:0] f2h_ram2_writedata; +wire [7:0] f2h_ram2_byteenable; +wire f2h_ram2_write; +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_0 = 1'b1; +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_1 = 1'b1; +always @(posedge ram2_clk) begin + ram2_reset_0 <= reset_out; + ram2_reset_1 <= ram2_reset_0; +end + +f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram2 +( + .clk (ram2_clk), + .rst_req_sync (ram2_reset_1), + + .waitrequest_slave (ram2_waitrequest), + .burstcount_slave (ram2_burstcount), + .address_slave (ram2_address), + .readdata_slave (ram2_readdata), + .readdatavalid_slave (ram2_readdatavalid), + .read_slave (ram2_read), + .writedata_slave (ram2_writedata), + .byteenable_slave (ram2_byteenable), + .write_slave (ram2_write), + + .waitrequest_master (f2h_ram2_waitrequest), + .burstcount_master (f2h_ram2_burstcount), + .address_master (f2h_ram2_address), + .readdata_master (f2h_ram2_readdata), + .readdatavalid_master (f2h_ram2_readdatavalid), + .read_master (f2h_ram2_read), + .writedata_master (f2h_ram2_writedata), + .byteenable_master (f2h_ram2_byteenable), + .write_master (f2h_ram2_write) +); + +//////////////////////////////////////////////////////// +//// f2sdram_safe_terminator_vbuf //// +//////////////////////////////////////////////////////// +wire [27:0] f2h_vbuf_address; +wire [7:0] f2h_vbuf_burstcount; +wire f2h_vbuf_waitrequest; +wire [127:0] f2h_vbuf_readdata; +wire f2h_vbuf_readdatavalid; +wire f2h_vbuf_read; +wire [127:0] f2h_vbuf_writedata; +wire [15:0] f2h_vbuf_byteenable; +wire f2h_vbuf_write; + +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_0 = 1'b1; +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_1 = 1'b1; +always @(posedge vbuf_clk) begin + vbuf_reset_0 <= reset_out; + vbuf_reset_1 <= vbuf_reset_0; +end + +f2sdram_safe_terminator #(128, 8) f2sdram_safe_terminator_vbuf +( + .clk (vbuf_clk), + .rst_req_sync (vbuf_reset_1), + + .waitrequest_slave (vbuf_waitrequest), + .burstcount_slave (vbuf_burstcount), + .address_slave (vbuf_address), + .readdata_slave (vbuf_readdata), + .readdatavalid_slave (vbuf_readdatavalid), + .read_slave (vbuf_read), + .writedata_slave (vbuf_writedata), + .byteenable_slave (vbuf_byteenable), + .write_slave (vbuf_write), + + .waitrequest_master (f2h_vbuf_waitrequest), + .burstcount_master (f2h_vbuf_burstcount), + .address_master (f2h_vbuf_address), + .readdata_master (f2h_vbuf_readdata), + .readdatavalid_master (f2h_vbuf_readdatavalid), + .read_master (f2h_vbuf_read), + .writedata_master (f2h_vbuf_writedata), + .byteenable_master (f2h_vbuf_byteenable), + .write_master (f2h_vbuf_write) +); + +//////////////////////////////////////////////////////// +//// HPS <> FPGA interfaces //// +//////////////////////////////////////////////////////// sysmem_HPS_fpga_interfaces fpga_interfaces ( - .f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n - .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n - .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk - .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n - .f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk - .f2h_sdram0_ADDRESS (ram_vip_address), // f2h_sdram0_data.address - .f2h_sdram0_BURSTCOUNT (ram_vip_burstcount), // .burstcount - .f2h_sdram0_WAITREQUEST (ram_vip_waitrequest), // .waitrequest - .f2h_sdram0_READDATA (ram_vip_readdata), // .readdata - .f2h_sdram0_READDATAVALID (ram_vip_readdatavalid), // .readdatavalid - .f2h_sdram0_READ (ram_vip_read), // .read - .f2h_sdram0_WRITEDATA (ram_vip_writedata), // .writedata - .f2h_sdram0_BYTEENABLE (ram_vip_byteenable), // .byteenable - .f2h_sdram0_WRITE (ram_vip_write), // .write - .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk - .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address - .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount - .f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest - .f2h_sdram1_READDATA (ram1_readdata), // .readdata - .f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid - .f2h_sdram1_READ (ram1_read), // .read - .f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata - .f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable - .f2h_sdram1_WRITE (ram1_write), // .write - .f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk - .f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address - .f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount - .f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest - .f2h_sdram2_READDATA (ram2_readdata), // .readdata - .f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid - .f2h_sdram2_READ (ram2_read), // .read - .f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata - .f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable - .f2h_sdram2_WRITE (ram2_write) // .write + .f2h_cold_rst_req_n (~reset_hps_cold_req), + .f2h_warm_rst_req_n (~reset_hps_warm_req), + .h2f_user0_clk (clock), + .h2f_rst_n (hps_h2f_reset_n), + .f2h_sdram0_clk (vbuf_clk), + .f2h_sdram0_ADDRESS (f2h_vbuf_address), + .f2h_sdram0_BURSTCOUNT (f2h_vbuf_burstcount), + .f2h_sdram0_WAITREQUEST (f2h_vbuf_waitrequest), + .f2h_sdram0_READDATA (f2h_vbuf_readdata), + .f2h_sdram0_READDATAVALID (f2h_vbuf_readdatavalid), + .f2h_sdram0_READ (f2h_vbuf_read), + .f2h_sdram0_WRITEDATA (f2h_vbuf_writedata), + .f2h_sdram0_BYTEENABLE (f2h_vbuf_byteenable), + .f2h_sdram0_WRITE (f2h_vbuf_write), + .f2h_sdram1_clk (ram1_clk), + .f2h_sdram1_ADDRESS (f2h_ram1_address), + .f2h_sdram1_BURSTCOUNT (f2h_ram1_burstcount), + .f2h_sdram1_WAITREQUEST (f2h_ram1_waitrequest), + .f2h_sdram1_READDATA (f2h_ram1_readdata), + .f2h_sdram1_READDATAVALID (f2h_ram1_readdatavalid), + .f2h_sdram1_READ (f2h_ram1_read), + .f2h_sdram1_WRITEDATA (f2h_ram1_writedata), + .f2h_sdram1_BYTEENABLE (f2h_ram1_byteenable), + .f2h_sdram1_WRITE (f2h_ram1_write), + .f2h_sdram2_clk (ram2_clk), + .f2h_sdram2_ADDRESS (f2h_ram2_address), + .f2h_sdram2_BURSTCOUNT (f2h_ram2_burstcount), + .f2h_sdram2_WAITREQUEST (f2h_ram2_waitrequest), + .f2h_sdram2_READDATA (f2h_ram2_readdata), + .f2h_sdram2_READDATAVALID (f2h_ram2_readdatavalid), + .f2h_sdram2_READ (f2h_ram2_read), + .f2h_sdram2_WRITEDATA (f2h_ram2_writedata), + .f2h_sdram2_BYTEENABLE (f2h_ram2_byteenable), + .f2h_sdram2_WRITE (f2h_ram2_write) ); -reset_source reset_source ( - .clk (clk_vip_clk), // clock.clk - .reset_hps (~hps_h2f_reset_reset), // reset_hps.reset - .reset_sys (reset_vip_reset), // reset_sys.reset - .cold_req (reset_cold_req), // reset_ctl.cold_req - .reset (reset_reset), // .reset - .reset_req (reset_reset_req), // .reset_req - .warm_req (reset_warm_req), // .warm_req - .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset - .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset -); +wire hps_h2f_reset_n; + +reg init_reset_n = 0; +always @(posedge clock) begin + integer timeout = 0; + + if(timeout < 2000000) begin + init_reset_n <= 0; + timeout <= timeout + 1; + end + else init_reset_n <= 1; +end endmodule + module sysmem_HPS_fpga_interfaces ( // h2f_reset diff --git a/sys/vga_out.sv b/sys/vga_out.sv index e316000..fe8172b 100644 --- a/sys/vga_out.sv +++ b/sys/vga_out.sv @@ -1,44 +1,20 @@ module vga_out ( - input ypbpr_full, + input clk, input ypbpr_en, - input [23:0] din, - output [23:0] dout -); + input hsync, + input vsync, + input csync, -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; + input [23:0] din, + output [23:0] dout, + + output reg hsync_o, + output reg vsync_o, + output reg csync_o +); wire [5:0] red = din[23:18]; wire [5:0] green = din[15:10]; @@ -49,17 +25,44 @@ wire [5:0] blue = din[7:2]; // Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) // Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); +reg [7:0] y, pb, pr; +reg [23:0] rgb; +always @(posedge clk) begin + reg [18:0] y_1r, pb_1r, pr_1r; + reg [18:0] y_1g, pb_1g, pr_1g; + reg [18:0] y_1b, pb_1b, pr_1b; + reg [18:0] y_2, pb_2, pr_2; + reg [23:0] din1, din2; + reg hsync2, vsync2, csync2; + reg hsync1, vsync1, csync1; -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0}); + pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}); + pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}); -assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16]; -assign dout[15:8] = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00} : din[15:8]; -assign dout[7:0] = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0]; + y_1g <= {green, 9'd0} + {green, 2'd0}; + pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0}; + pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}; + y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}; + pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}; + pr_1b <= {blue, 6'd0} + {blue, 3'd0}; + + y_2 <= y_1r + y_1g + y_1b; + pb_2 <= pb_1r - pb_1g + pb_1b; + pr_2 <= pr_1r - pr_1g - pr_1b; + + y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8]; + pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8]; + pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8]; + + hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync; + vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync; + csync_o <= csync2; csync2 <= csync1; csync1 <= csync; + + rgb <= din2; din2 <= din1; din1 <= din; +end + +assign dout = ypbpr_en ? {pr, y, pb} : rgb; endmodule diff --git a/sys/video_cleaner.sv b/sys/video_cleaner.sv index 36227ba..a99894c 100644 --- a/sys/video_cleaner.sv +++ b/sys/video_cleaner.sv @@ -23,6 +23,9 @@ module video_cleaner input HBlank, input VBlank, + //optional de + input DE_in, + // video output signals output reg [7:0] VGA_R, output reg [7:0] VGA_G, @@ -33,7 +36,10 @@ module video_cleaner // optional aligned blank output reg HBlank_out, - output reg VBlank_out + output reg VBlank_out, + + // optional aligned de + output reg DE_out ); wire hs, vs; @@ -49,11 +55,13 @@ always @(posedge clk_vid) begin if(ce_pix) begin HBlank_out <= hbl; - VGA_VS <= vs; VGA_HS <= hs; + if(~VGA_HS & hs) VGA_VS <= vs; + VGA_R <= R; VGA_G <= G; VGA_B <= B; + DE_out <= DE_in; if(HBlank_out & ~hbl) VBlank_out <= vbl; end diff --git a/sys/video_freak.sv b/sys/video_freak.sv new file mode 100644 index 0000000..d542ae7 --- /dev/null +++ b/sys/video_freak.sv @@ -0,0 +1,278 @@ +// +// +// Video crop +// Copyright (c) 2020 Grabulosaure, (c) 2021 Alexey Melnikov +// +// Integer scaling +// Copyright (c) 2021 Alexey Melnikov +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +module video_freak +( + input CLK_VIDEO, + input CE_PIXEL, + input VGA_VS, + input [11:0] HDMI_WIDTH, + input [11:0] HDMI_HEIGHT, + output VGA_DE, + output reg [12:0] VIDEO_ARX, + output reg [12:0] VIDEO_ARY, + + input VGA_DE_IN, + input [11:0] ARX, + input [11:0] ARY, + input [11:0] CROP_SIZE, + input [4:0] CROP_OFF, // -16...+15 + input [2:0] SCALE //0 - normal, 1 - V-integer, 2 - HV-Integer-, 3 - HV-Integer+, 4 - HV-Integer +); + +reg mul_start; +wire mul_run; +reg [11:0] mul_arg1, mul_arg2; +wire [23:0] mul_res; +sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res); + +reg vde; +reg [11:0] arxo,aryo; +reg [11:0] vsize; +reg [11:0] hsize; + +always @(posedge CLK_VIDEO) begin + reg old_de, old_vs,ovde; + reg [11:0] vtot,vcpt,vcrop,voff; + reg [11:0] hcpt; + reg [11:0] vadj; + reg [23:0] ARXG,ARYG; + reg [11:0] arx,ary; + reg [1:0] vcalc; + + if (CE_PIXEL) begin + old_de <= VGA_DE_IN; + old_vs <= VGA_VS; + if (VGA_VS & ~old_vs) begin + vcpt <= 0; + vtot <= vcpt; + vcalc <= 1; + vcrop <= (CROP_SIZE >= vcpt) ? 12'd0 : CROP_SIZE; + end + + if (VGA_DE_IN) hcpt <= hcpt + 1'd1; + if (~VGA_DE_IN & old_de) begin + vcpt <= vcpt + 1'd1; + if(!vcpt) hsize <= hcpt; + hcpt <= 0; + end + end + + arx <= ARX; + ary <= ARY; + + vsize <= vcrop ? vcrop : vtot; + + mul_start <= 0; + + if(!vcrop || !ary || !arx) begin + arxo <= arx; + aryo <= ary; + end + else if (vcalc) begin + if(~mul_start & ~mul_run) begin + vcalc <= vcalc + 1'd1; + case(vcalc) + 1: begin + mul_arg1 <= arx; + mul_arg2 <= vtot; + mul_start <= 1; + end + + 2: begin + ARXG <= mul_res; + mul_arg1 <= ary; + mul_arg2 <= vcrop; + mul_start <= 1; + end + + 3: begin + ARYG <= mul_res; + end + endcase + end + end + else if (ARXG[23] | ARYG[23]) begin + arxo <= ARXG[23:12]; + aryo <= ARYG[23:12]; + end + else begin + ARXG <= ARXG << 1; + ARYG <= ARYG << 1; + end + + vadj <= (vtot-vcrop) + {{6{CROP_OFF[4]}},CROP_OFF,1'b0}; + voff <= vadj[11] ? 12'd0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1]; + ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop; + vde <= ovde; +end + +assign VGA_DE = vde & VGA_DE_IN; + +video_scale_int scale +( + .CLK_VIDEO(CLK_VIDEO), + .HDMI_WIDTH(HDMI_WIDTH), + .HDMI_HEIGHT(HDMI_HEIGHT), + .SCALE(SCALE), + .hsize(hsize), + .vsize(vsize), + .arx_i(arxo), + .ary_i(aryo), + .arx_o(VIDEO_ARX), + .ary_o(VIDEO_ARY) +); + +endmodule + + +module video_scale_int +( + input CLK_VIDEO, + + input [11:0] HDMI_WIDTH, + input [11:0] HDMI_HEIGHT, + + input [2:0] SCALE, + + input [11:0] hsize, + input [11:0] vsize, + + input [11:0] arx_i, + input [11:0] ary_i, + + output reg [12:0] arx_o, + output reg [12:0] ary_o +); + +reg div_start; +wire div_run; +reg [23:0] div_num; +reg [11:0] div_den; +wire [23:0] div_res; +sys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res); + +reg mul_start; +wire mul_run; +reg [11:0] mul_arg1, mul_arg2; +wire [23:0] mul_res; +sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res); + +wire [11:0] wideres = mul_res[11:0] + hsize; + +always @(posedge CLK_VIDEO) begin + reg [11:0] oheight,wres; + reg [12:0] arxf,aryf; + reg [3:0] cnt; + reg narrow; + + div_start <= 0; + mul_start <= 0; + + if (!SCALE || (!ary_i && arx_i)) begin + arxf <= arx_i; + aryf <= ary_i; + end + else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin + cnt <= cnt + 1'd1; + case(cnt) + 0: begin + div_num <= HDMI_HEIGHT; + div_den <= vsize; + div_start <= 1; + end + + 1: if(!div_res[11:0]) begin + // screen resolution is lower than video resolution. + // Integer scaling is impossible. + arxf <= arx_i; + aryf <= ary_i; + cnt <= 0; + end + else begin + mul_arg1 <= vsize; + mul_arg2 <= div_res[11:0]; + mul_start <= 1; + end + + 2: begin + oheight <= mul_res[11:0]; + if(!ary_i) begin + cnt <= 8; + end + end + + 3: begin + mul_arg1 <= mul_res[11:0]; + mul_arg2 <= arx_i; + mul_start <= 1; + end + + 4: begin + div_num <= mul_res; + div_den <= ary_i; + div_start <= 1; + end + + 5: begin + div_num <= div_res; + div_den <= hsize; + div_start <= 1; + end + + 6: begin + mul_arg1 <= hsize; + mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; + mul_start <= 1; + end + + 7: if(mul_res <= HDMI_WIDTH) begin + cnt <= 10; + end + + 8: begin + div_num <= HDMI_WIDTH; + div_den <= hsize; + div_start <= 1; + end + + 9: begin + mul_arg1 <= hsize; + mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; + mul_start <= 1; + end + + 10: begin + narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH); + wres <= wideres; + end + + 11: begin + case(SCALE) + 2: arxf <= {1'b1, mul_res[11:0]}; + 3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres}; + 4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres}; + default: arxf <= {1'b1, div_num[11:0]}; + endcase + aryf <= {1'b1, oheight}; + end + endcase + end + + arx_o <= arxf; + ary_o <= aryf; +end + +endmodule diff --git a/sys/video_freezer.sv b/sys/video_freezer.sv new file mode 100644 index 0000000..cfbdf22 --- /dev/null +++ b/sys/video_freezer.sv @@ -0,0 +1,143 @@ +// +// video freeze with sync +// (C) Alexey Melnikov +// +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + + +module video_freezer +( + input clk, + + output sync, + input freeze, + + input hs_in, + input vs_in, + input hbl_in, + input vbl_in, + + output hs_out, + output vs_out, + output hbl_out, + output vbl_out +); + +sync_lock #(33) vs_lock +( + .clk(clk), + .sync_in(vs_in), + .sync_out(vs_out), + .de_in(vbl_in), + .de_out(vbl_out), + .freeze(freeze) +); + +wire sync_pt; +sync_lock #(21) hs_lock +( + .clk(clk), + .sync_in(hs_in), + .sync_out(hs_out), + .de_in(hbl_in), + .de_out(hbl_out), + .freeze(freeze), + .sync_pt(sync_pt) +); + +reg sync_o; +always @(posedge clk) begin + reg old_hs, old_vs; + reg vs_sync; + + old_vs <= vs_out; + + if(~old_vs & vs_out) vs_sync <= 1; + if(sync_pt & vs_sync) begin + vs_sync <= 0; + sync_o <= ~sync_o; + end +end + +assign sync = sync_o; + +endmodule + + +module sync_lock #(parameter WIDTH) +( + input clk, + + input sync_in, + input de_in, + + output sync_out, + output de_out, + + input freeze, + output sync_pt, + output valid +); + +reg [WIDTH-1:0] f_len, s_len, de_start, de_end; +reg sync_valid; + +reg old_sync; +always @(posedge clk) old_sync <= sync_in; + +always @(posedge clk) begin + reg [WIDTH-1:0] cnti; + reg f_valid; + reg old_de; + + cnti <= cnti + 1'd1; + if(~old_sync & sync_in) begin + if(sync_valid) f_len <= cnti; + f_valid <= 1; + sync_valid <= f_valid; + cnti <= 0; + end + + if(old_sync & ~sync_in & sync_valid) s_len <= cnti; + + old_de <= de_in; + if(~old_de & de_in & sync_valid) de_start <= cnti; + if(old_de & ~de_in & sync_valid) de_end <= cnti; + + if(freeze) {f_valid, sync_valid} <= 0; +end + +reg sync_o, de_o, sync_o_pre; +always @(posedge clk) begin + reg [WIDTH-1:0] cnto; + + cnto <= cnto + 1'd1; + if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2'd2; + if(cnto == f_len) cnto <= 0; + + sync_o_pre <= (cnto == (s_len>>1)); // middle in sync + if(cnto == f_len) sync_o <= 1; + if(cnto == s_len) sync_o <= 0; + if(cnto == de_start) de_o <= 1; + if(cnto == de_end) de_o <= 0; +end + +assign sync_out = freeze ? sync_o : sync_in; +assign valid = sync_valid; +assign sync_pt = sync_o_pre; +assign de_out = freeze ? de_o : de_in; + +endmodule diff --git a/sys/video_mixer.sv b/sys/video_mixer.sv index c9d358d..fd0b08f 100644 --- a/sys/video_mixer.sv +++ b/sys/video_mixer.sv @@ -1,6 +1,6 @@ // // -// Copyright (c) 2017 Sorgelig +// Copyright (c) 2017,2021 Alexey Melnikov // // This program is GPL Licensed. See COPYING for the full license. // @@ -10,50 +10,46 @@ `timescale 1ns / 1ps // -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// +// LINE_LENGTH: Length of display line in pixels when HBlank = 0; // HALF_DEPTH: If =1 then color dept is 4 bits per component -// For half depth 8 bits monochrome is available with -// mono signal enabled and color = {G, R} +// +// altera message_off 10720 +// altera message_off 12161 module video_mixer #( parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0 + parameter HALF_DEPTH = 0, + parameter GAMMA = 0 ) ( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - output ce_pix_out, + input CLK_VIDEO, // should be multiple by (ce_pix*4) + output reg CE_PIXEL, // output pixel clock enable + + input ce_pix, // input pixel clock or clock_enable input scandoubler, + input hq2x, // high quality 2x scaling - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // High quality 2x scaling - input hq2x, + inout [21:0] gamma_bus, // color input [DWIDTH:0] R, input [DWIDTH:0] G, input [DWIDTH:0] B, - // Monochrome mode (for HALF_DEPTH only) - input mono, - // Positive pulses. input HSync, input VSync, input HBlank, input VBlank, + // Freeze engine + // HDMI: displays last frame + // VGA: black screen with HSync and VSync + input HDMI_FREEZE, + output freeze_sync, + // video output signals output reg [7:0] VGA_R, output reg [7:0] VGA_G, @@ -64,22 +60,100 @@ module video_mixer ); localparam DWIDTH = HALF_DEPTH ? 3 : 7; +localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH; +localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH; -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd +wire frz_hs, frz_vs; +wire frz_hbl, frz_vbl; +video_freezer freezer ( - .*, + .clk(CLK_VIDEO), + .freeze(HDMI_FREEZE), .hs_in(HSync), .vs_in(VSync), - .hb_in(HBlank), - .vb_in(VBlank), - .r_in(R), - .g_in(G), - .b_in(B), + .hbl_in(HBlank), + .vbl_in(VBlank), + .sync(freeze_sync), + .hs_out(frz_hs), + .vs_out(frz_vs), + .hbl_out(frz_hbl), + .vbl_out(frz_vbl) +); + +reg frz; +always @(posedge CLK_VIDEO) begin + reg frz1; + + frz1 <= HDMI_FREEZE; + frz <= frz1; +end + +generate + if(GAMMA && HALF_DEPTH) begin + wire [7:0] R_in = frz ? 8'd0 : {R,R}; + wire [7:0] G_in = frz ? 8'd0 : {G,G}; + wire [7:0] B_in = frz ? 8'd0 : {B,B}; + end else begin + wire [DWIDTH:0] R_in = frz ? 1'd0 : R; + wire [DWIDTH:0] G_in = frz ? 1'd0 : G; + wire [DWIDTH:0] B_in = frz ? 1'd0 : B; + end +endgenerate + +wire hs_g, vs_g; +wire hb_g, vb_g; +wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma; + +generate + if(GAMMA) begin + assign gamma_bus[21] = 1; + gamma_corr gamma( + .clk_sys(gamma_bus[20]), + .clk_vid(CLK_VIDEO), + .ce_pix(ce_pix), + + .gamma_en(gamma_bus[19]), + .gamma_wr(gamma_bus[18]), + .gamma_wr_addr(gamma_bus[17:8]), + .gamma_value(gamma_bus[7:0]), + + .HSync(frz_hs), + .VSync(frz_vs), + .HBlank(frz_hbl), + .VBlank(frz_vbl), + .RGB_in({R_in,G_in,B_in}), + + .HSync_out(hs_g), + .VSync_out(vs_g), + .HBlank_out(hb_g), + .VBlank_out(vb_g), + .RGB_out({R_gamma,G_gamma,B_gamma}) + ); + end else begin + assign gamma_bus[21] = 0; + assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in}; + assign {hs_g, vs_g, hb_g, vb_g} = {frz_hs, frz_vs, frz_hbl, frz_vbl}; + end +endgenerate + +wire [DWIDTH_SD:0] R_sd; +wire [DWIDTH_SD:0] G_sd; +wire [DWIDTH_SD:0] B_sd; +wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd +( + .clk_vid(CLK_VIDEO), + .hq2x(hq2x), + + .ce_pix(ce_pix), + .hs_in(hs_g), + .vs_in(vs_g), + .hb_in(hb_g), + .vb_in(vb_g), + .r_in(R_gamma), + .g_in(G_gamma), + .b_in(B_gamma), .ce_pix_out(ce_pix_sd), .hs_out(hs_sd), @@ -91,77 +165,55 @@ scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd .b_out(B_sd) ); -wire [DWIDTH:0] rt = (scandoubler ? R_sd : R); -wire [DWIDTH:0] gt = (scandoubler ? G_sd : G); -wire [DWIDTH:0] bt = (scandoubler ? B_sd : B); +wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma); +wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma); +wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma); -generate - if(HALF_DEPTH) begin - wire [7:0] r = mono ? {gt,rt} : {rt,rt}; - wire [7:0] g = mono ? {gt,rt} : {gt,gt}; - wire [7:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [7:0] r = rt; - wire [7:0] g = gt; - wire [7:0] b = bt; - end -endgenerate - -wire hs = (scandoubler ? hs_sd : HSync); -wire vs = (scandoubler ? vs_sd : VSync); - -assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix; - - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire hde = scandoubler ? ~hb_sd : ~HBlank; -wire vde = scandoubler ? ~vb_sd : ~VBlank; - -always @(posedge clk_sys) begin +always @(posedge CLK_VIDEO) begin + reg [7:0] r,g,b; + reg hde,vde,hs,vs, old_vs; reg old_hde; + reg old_ce; + reg ce_osc, fs_osc; + + old_ce <= ce_pix; + ce_osc <= ce_osc | (old_ce ^ ce_pix); - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]}; - VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]}; - VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]}; - end + old_vs <= vs; + if(~old_vs & vs) begin + fs_osc <= ce_osc; + ce_osc <= 0; + end - 2: begin // reduce 50% = 1/2 - VGA_R <= {1'b0, r[7:1]}; - VGA_G <= {1'b0, g[7:1]}; - VGA_B <= {1'b0, b[7:1]}; - end + CE_PIXEL <= scandoubler ? ce_pix_sd : fs_osc ? (~old_ce & ce_pix) : ce_pix; - 3: begin // reduce 75% = 1/4 - VGA_R <= {2'b00, r[7:2]}; - VGA_G <= {2'b00, g[7:2]}; - VGA_B <= {2'b00, b[7:2]}; - end + if(!GAMMA && HALF_DEPTH) begin + r <= {rt,rt}; + g <= {gt,gt}; + b <= {bt,bt}; + end + else begin + r <= rt; + g <= gt; + b <= bt; + end - default: begin - VGA_R <= r; - VGA_G <= g; - VGA_B <= b; - end - endcase + hde <= scandoubler ? ~hb_sd : ~hb_g; + vde <= scandoubler ? ~vb_sd : ~vb_g; + vs <= scandoubler ? vs_sd : vs_g; + hs <= scandoubler ? hs_sd : hs_g; - VGA_VS <= vs; - VGA_HS <= hs; + if(CE_PIXEL) begin + VGA_R <= r; + VGA_G <= g; + VGA_B <= b; - old_hde <= hde; - if(~old_hde && hde) VGA_DE <= vde; - if(old_hde && ~hde) VGA_DE <= 0; + VGA_VS <= vs; + VGA_HS <= hs; + + old_hde <= hde; + if(old_hde ^ hde) VGA_DE <= vde & hde; + end end endmodule diff --git a/sys/vip.qsys b/sys/vip.qsys deleted file mode 100644 index 1f8a5d7..0000000 --- a/sys/vip.qsys +++ /dev/null @@ -1,1177 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - No,No,No,No,No,No,No,No - - - - - - - - - - - - - - - - - - - - - Avalon-MM Bidirectional,Avalon-MM Bidirectional,Avalon-MM Bidirectional - - - - - - - - - - - - - - - - - - - - - - - - - - - - - No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No - - - - - - - - - - - - - - - - No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/sys/vip_config.sv b/sys/vip_config.sv deleted file mode 100644 index b003798..0000000 --- a/sys/vip_config.sv +++ /dev/null @@ -1,159 +0,0 @@ - -module vip_config -( - input clk, - input reset, - - input [7:0] ARX, - input [7:0] ARY, - input CFG_SET, - - input [11:0] WIDTH, - input [11:0] HFP, - input [11:0] HBP, - input [11:0] HS, - input [11:0] HEIGHT, - input [11:0] VFP, - input [11:0] VBP, - input [11:0] VS, - - input [11:0] VSET, - - output reg [8:0] address, - output reg write, - output reg [31:0] writedata, - input waitrequest -); - - -reg newres = 1; - -wire [21:0] init[23] = -'{ - //video mode - {newres, 2'd2, 7'd04, 12'd0 }, //Bank - {newres, 2'd2, 7'd30, 12'd0 }, //Valid - {newres, 2'd2, 7'd05, 12'd0 }, //Progressive/Interlaced - {newres, 2'd2, 7'd06, w }, //Active pixel count - {newres, 2'd2, 7'd07, h }, //Active line count - {newres, 2'd2, 7'd09, hfp }, //Horizontal Front Porch - {newres, 2'd2, 7'd10, hs }, //Horizontal Sync Length - {newres, 2'd2, 7'd11, hb }, //Horizontal Blanking (HFP+HBP+HSync) - {newres, 2'd2, 7'd12, vfp }, //Vertical Front Porch - {newres, 2'd2, 7'd13, vs }, //Vertical Sync Length - {newres, 2'd2, 7'd14, vb }, //Vertical blanking (VFP+VBP+VSync) - {newres, 2'd2, 7'd30, 12'd1 }, //Valid - {newres, 2'd2, 7'd00, 12'd1 }, //Go - - //mixer - { 1'd1, 2'd1, 7'd03, w }, //Bkg Width - { 1'd1, 2'd1, 7'd04, h }, //Bkg Height - { 1'd1, 2'd1, 7'd08, posx }, //Pos X - { 1'd1, 2'd1, 7'd09, posy }, //Pos Y - { 1'd1, 2'd1, 7'd10, 12'd1 }, //Enable Video 0 - { 1'd1, 2'd1, 7'd00, 12'd1 }, //Go - - //scaler - { 1'd1, 2'd0, 7'd03, videow }, //Output Width - { 1'd1, 2'd0, 7'd04, videoh }, //Output Height - { 1'd1, 2'd0, 7'd00, 12'd1 }, //Go - - 22'h3FFFFF -}; - -reg [11:0] w; -reg [11:0] hfp; -reg [11:0] hbp; -reg [11:0] hs; -reg [11:0] hb; -reg [11:0] h; -reg [11:0] vfp; -reg [11:0] vbp; -reg [11:0] vs; -reg [11:0] vb; - -reg [11:0] videow; -reg [11:0] videoh; - -reg [11:0] posx; -reg [11:0] posy; - -always @(posedge clk) begin - reg [7:0] state = 0; - reg [7:0] arx, ary; - reg [7:0] arxd, aryd; - reg [11:0] vset, vsetd; - reg cfg, cfgd; - reg [31:0] wcalc; - reg [31:0] hcalc; - reg [12:0] timeout = 0; - - arxd <= ARX; - aryd <= ARY; - vsetd <= VSET; - - cfg <= CFG_SET; - cfgd <= cfg; - - write <= 0; - if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin - arx <= arxd; - ary <= aryd; - vset <= vsetd; - timeout <= '1; - state <= 0; - if(reset || (~cfgd && cfg)) newres <= 1; - end - else - if(timeout > 0) - begin - timeout <= timeout - 1'd1; - state <= 1; - if(!(timeout & 'h1f)) case(timeout>>5) - 5: begin - w <= WIDTH; - hfp <= HFP; - hbp <= HBP; - hs <= HS; - h <= HEIGHT; - vfp <= VFP; - vbp <= VBP; - vs <= VS; - end - 4: begin - hb <= hfp+hbp+hs; - vb <= vfp+vbp+vs; - end - 3: begin - wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary; - hcalc <= (w*ary)/arx; - end - 2: begin - videow <= (!vset && (wcalc > w)) ? w : wcalc[11:0]; - videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0]; - end - 1: begin - posx <= (w - videow)>>1; - posy <= (h - videoh)>>1; - end - endcase - end - else - if(~waitrequest && state) - begin - state <= state + 1'd1; - write <= 0; - if((state&3)==3) begin - if(init[state>>2] == 22'h3FFFFF) begin - state <= 0; - newres <= 0; - end - else begin - writedata <= 0; - {write, address, writedata[11:0]} <= init[state>>2]; - end - end - end -end - -endmodule