| debug_print_output |
false |
| debug_use_rbc_taf_method |
false |
| device_family |
CYCLONEV |
| device |
5CSEBA6U23I7 |
| gui_device_speed_grade |
2 |
| gui_pll_mode |
Fractional-N PLL |
| fractional_vco_multiplier |
true |
| gui_reference_clock_frequency |
50.0 |
| reference_clock_frequency |
50.0 MHz |
| gui_channel_spacing |
0.0 |
| gui_operation_mode |
normal |
| gui_feedback_clock |
Global Clock |
| gui_fractional_cout |
32 |
| pll_fractional_cout |
32 |
| gui_dsm_out_sel |
1st_order |
| pll_dsm_out_sel |
1st_order |
| operation_mode |
normal |
| gui_use_locked |
false |
| gui_en_adv_params |
false |
| gui_number_of_clocks |
8 |
| number_of_clocks |
8 |
| number_of_cascade_counters |
0 |
| gui_multiply_factor |
1 |
| gui_frac_multiply_factor |
1 |
| gui_divide_factor_n |
1 |
| gui_cascade_counter0 |
false |
| gui_output_clock_frequency0 |
256.0 |
| gui_divide_factor_c0 |
1 |
| gui_actual_multiply_factor0 |
15 |
| gui_actual_frac_multiply_factor0 |
1546159966 |
| gui_actual_divide_factor0 |
3 |
| gui_actual_output_clock_frequency0 |
120.000000 MHz |
| gui_ps_units0 |
ps |
| gui_phase_shift0 |
0 |
| gui_phase_shift_deg0 |
0.0 |
| gui_actual_phase_shift0 |
0 |
| gui_duty_cycle0 |
50 |
| gui_cascade_counter1 |
false |
| gui_output_clock_frequency1 |
112.0 |
| gui_divide_factor_c1 |
1 |
| gui_actual_multiply_factor1 |
15 |
| gui_actual_frac_multiply_factor1 |
1546159966 |
| gui_actual_divide_factor1 |
7 |
| gui_actual_output_clock_frequency1 |
0 MHz |
| gui_ps_units1 |
ps |
| gui_phase_shift1 |
0 |
| gui_phase_shift_deg1 |
0.0 |
| gui_actual_phase_shift1 |
0 |
| gui_duty_cycle1 |
50 |
| gui_cascade_counter2 |
false |
| gui_output_clock_frequency2 |
64.0 |
| gui_divide_factor_c2 |
1 |
| gui_actual_multiply_factor2 |
15 |
| gui_actual_frac_multiply_factor2 |
1546159966 |
| gui_actual_divide_factor2 |
12 |
| gui_actual_output_clock_frequency2 |
0 MHz |
| gui_ps_units2 |
ps |
| gui_phase_shift2 |
0 |
| gui_phase_shift_deg2 |
0.0 |
| gui_actual_phase_shift2 |
0 |
| gui_duty_cycle2 |
50 |
| gui_cascade_counter3 |
false |
| gui_output_clock_frequency3 |
32.0 |
| gui_divide_factor_c3 |
1 |
| gui_actual_multiply_factor3 |
15 |
| gui_actual_frac_multiply_factor3 |
1546159966 |
| gui_actual_divide_factor3 |
24 |
| gui_actual_output_clock_frequency3 |
32.533324 MHz |
| gui_ps_units3 |
ps |
| gui_phase_shift3 |
0 |
| gui_phase_shift_deg3 |
0.0 |
| gui_actual_phase_shift3 |
0 |
| gui_duty_cycle3 |
50 |
| gui_cascade_counter4 |
false |
| gui_output_clock_frequency4 |
16.0 |
| gui_divide_factor_c4 |
1 |
| gui_actual_multiply_factor4 |
15 |
| gui_actual_frac_multiply_factor4 |
1546159966 |
| gui_actual_divide_factor4 |
48 |
| gui_actual_output_clock_frequency4 |
0 MHz |
| gui_ps_units4 |
ps |
| gui_phase_shift4 |
0 |
| gui_phase_shift_deg4 |
0.0 |
| gui_actual_phase_shift4 |
0 |
| gui_duty_cycle4 |
50 |
| gui_cascade_counter5 |
false |
| gui_output_clock_frequency5 |
8.0 |
| gui_divide_factor_c5 |
1 |
| gui_actual_multiply_factor5 |
15 |
| gui_actual_frac_multiply_factor5 |
1546159966 |
| gui_actual_divide_factor5 |
96 |
| gui_actual_output_clock_frequency5 |
0 MHz |
| gui_ps_units5 |
ps |
| gui_phase_shift5 |
0 |
| gui_phase_shift_deg5 |
0.0 |
| gui_actual_phase_shift5 |
0 |
| gui_duty_cycle5 |
50 |
| gui_cascade_counter6 |
false |
| gui_output_clock_frequency6 |
4.0 |
| gui_divide_factor_c6 |
1 |
| gui_actual_multiply_factor6 |
15 |
| gui_actual_frac_multiply_factor6 |
1546159966 |
| gui_actual_divide_factor6 |
192 |
| gui_actual_output_clock_frequency6 |
0 MHz |
| gui_ps_units6 |
ps |
| gui_phase_shift6 |
0 |
| gui_phase_shift_deg6 |
0.0 |
| gui_actual_phase_shift6 |
0 |
| gui_duty_cycle6 |
50 |
| gui_cascade_counter7 |
false |
| gui_output_clock_frequency7 |
2.0 |
| gui_divide_factor_c7 |
1 |
| gui_actual_multiply_factor7 |
15 |
| gui_actual_frac_multiply_factor7 |
1546159966 |
| gui_actual_divide_factor7 |
384 |
| gui_actual_output_clock_frequency7 |
0 MHz |
| gui_ps_units7 |
ps |
| gui_phase_shift7 |
0 |
| gui_phase_shift_deg7 |
0.0 |
| gui_actual_phase_shift7 |
0 |
| gui_duty_cycle7 |
50 |
| gui_cascade_counter8 |
false |
| gui_output_clock_frequency8 |
1.0 |
| gui_divide_factor_c8 |
1 |
| gui_actual_multiply_factor8 |
1 |
| gui_actual_frac_multiply_factor8 |
1 |
| gui_actual_divide_factor8 |
1 |
| gui_actual_output_clock_frequency8 |
0 MHz |
| gui_ps_units8 |
ps |
| gui_phase_shift8 |
0 |
| gui_phase_shift_deg8 |
0.0 |
| gui_actual_phase_shift8 |
0 |
| gui_duty_cycle8 |
50 |
| gui_cascade_counter9 |
false |
| gui_output_clock_frequency9 |
100.0 |
| gui_divide_factor_c9 |
1 |
| gui_actual_multiply_factor9 |
1 |
| gui_actual_frac_multiply_factor9 |
1 |
| gui_actual_divide_factor9 |
1 |
| gui_actual_output_clock_frequency9 |
0 MHz |
| gui_ps_units9 |
ps |
| gui_phase_shift9 |
0 |
| gui_phase_shift_deg9 |
0.0 |
| gui_actual_phase_shift9 |
0 |
| gui_duty_cycle9 |
50 |
| gui_cascade_counter10 |
false |
| gui_output_clock_frequency10 |
100.0 |
| gui_divide_factor_c10 |
1 |
| gui_actual_multiply_factor10 |
1 |
| gui_actual_frac_multiply_factor10 |
1 |
| gui_actual_divide_factor10 |
1 |
| gui_actual_output_clock_frequency10 |
0 MHz |
| gui_ps_units10 |
ps |
| gui_phase_shift10 |
0 |
| gui_phase_shift_deg10 |
0.0 |
| gui_actual_phase_shift10 |
0 |
| gui_duty_cycle10 |
50 |
| gui_cascade_counter11 |
false |
| gui_output_clock_frequency11 |
100.0 |
| gui_divide_factor_c11 |
1 |
| gui_actual_multiply_factor11 |
1 |
| gui_actual_frac_multiply_factor11 |
1 |
| gui_actual_divide_factor11 |
1 |
| gui_actual_output_clock_frequency11 |
0 MHz |
| gui_ps_units11 |
ps |
| gui_phase_shift11 |
0 |
| gui_phase_shift_deg11 |
0.0 |
| gui_actual_phase_shift11 |
0 |
| gui_duty_cycle11 |
50 |
| gui_cascade_counter12 |
false |
| gui_output_clock_frequency12 |
100.0 |
| gui_divide_factor_c12 |
1 |
| gui_actual_multiply_factor12 |
1 |
| gui_actual_frac_multiply_factor12 |
1 |
| gui_actual_divide_factor12 |
1 |
| gui_actual_output_clock_frequency12 |
0 MHz |
| gui_ps_units12 |
ps |
| gui_phase_shift12 |
0 |
| gui_phase_shift_deg12 |
0.0 |
| gui_actual_phase_shift12 |
0 |
| gui_duty_cycle12 |
50 |
| gui_cascade_counter13 |
false |
| gui_output_clock_frequency13 |
100.0 |
| gui_divide_factor_c13 |
1 |
| gui_actual_multiply_factor13 |
1 |
| gui_actual_frac_multiply_factor13 |
1 |
| gui_actual_divide_factor13 |
1 |
| gui_actual_output_clock_frequency13 |
0 MHz |
| gui_ps_units13 |
ps |
| gui_phase_shift13 |
0 |
| gui_phase_shift_deg13 |
0.0 |
| gui_actual_phase_shift13 |
0 |
| gui_duty_cycle13 |
50 |
| gui_cascade_counter14 |
false |
| gui_output_clock_frequency14 |
100.0 |
| gui_divide_factor_c14 |
1 |
| gui_actual_multiply_factor14 |
1 |
| gui_actual_frac_multiply_factor14 |
1 |
| gui_actual_divide_factor14 |
1 |
| gui_actual_output_clock_frequency14 |
0 MHz |
| gui_ps_units14 |
ps |
| gui_phase_shift14 |
0 |
| gui_phase_shift_deg14 |
0.0 |
| gui_actual_phase_shift14 |
0 |
| gui_duty_cycle14 |
50 |
| gui_cascade_counter15 |
false |
| gui_output_clock_frequency15 |
100.0 |
| gui_divide_factor_c15 |
1 |
| gui_actual_multiply_factor15 |
1 |
| gui_actual_frac_multiply_factor15 |
1 |
| gui_actual_divide_factor15 |
1 |
| gui_actual_output_clock_frequency15 |
0 MHz |
| gui_ps_units15 |
ps |
| gui_phase_shift15 |
0 |
| gui_phase_shift_deg15 |
0.0 |
| gui_actual_phase_shift15 |
0 |
| gui_duty_cycle15 |
50 |
| gui_cascade_counter16 |
false |
| gui_output_clock_frequency16 |
100.0 |
| gui_divide_factor_c16 |
1 |
| gui_actual_multiply_factor16 |
1 |
| gui_actual_frac_multiply_factor16 |
1 |
| gui_actual_divide_factor16 |
1 |
| gui_actual_output_clock_frequency16 |
0 MHz |
| gui_ps_units16 |
ps |
| gui_phase_shift16 |
0 |
| gui_phase_shift_deg16 |
0.0 |
| gui_actual_phase_shift16 |
0 |
| gui_duty_cycle16 |
50 |
| gui_cascade_counter17 |
false |
| gui_output_clock_frequency17 |
100.0 |
| gui_divide_factor_c17 |
1 |
| gui_actual_multiply_factor17 |
1 |
| gui_actual_frac_multiply_factor17 |
1 |
| gui_actual_divide_factor17 |
1 |
| gui_actual_output_clock_frequency17 |
0 MHz |
| gui_ps_units17 |
ps |
| gui_phase_shift17 |
0 |
| gui_phase_shift_deg17 |
0.0 |
| gui_actual_phase_shift17 |
0 |
| gui_duty_cycle17 |
50 |
| output_clock_frequency0 |
255.999872 MHz |
| phase_shift0 |
0 ps |
| duty_cycle0 |
50 |
| output_clock_frequency1 |
109.714257 MHz |
| phase_shift1 |
0 ps |
| duty_cycle1 |
50 |
| output_clock_frequency2 |
63.999981 MHz |
| phase_shift2 |
0 ps |
| duty_cycle2 |
50 |
| output_clock_frequency3 |
31.999989 MHz |
| phase_shift3 |
0 ps |
| duty_cycle3 |
50 |
| output_clock_frequency4 |
15.999994 MHz |
| phase_shift4 |
0 ps |
| duty_cycle4 |
50 |
| output_clock_frequency5 |
7.999996 MHz |
| phase_shift5 |
0 ps |
| duty_cycle5 |
50 |
| output_clock_frequency6 |
3.999998 MHz |
| phase_shift6 |
0 ps |
| duty_cycle6 |
50 |
| output_clock_frequency7 |
1.999999 MHz |
| phase_shift7 |
0 ps |
| duty_cycle7 |
50 |
| output_clock_frequency8 |
0 MHz |
| phase_shift8 |
0 ps |
| duty_cycle8 |
50 |
| output_clock_frequency9 |
0 MHz |
| phase_shift9 |
0 ps |
| duty_cycle9 |
50 |
| output_clock_frequency10 |
0 MHz |
| phase_shift10 |
0 ps |
| duty_cycle10 |
50 |
| output_clock_frequency11 |
0 MHz |
| phase_shift11 |
0 ps |
| duty_cycle11 |
50 |
| output_clock_frequency12 |
0 MHz |
| phase_shift12 |
0 ps |
| duty_cycle12 |
50 |
| output_clock_frequency13 |
0 MHz |
| phase_shift13 |
0 ps |
| duty_cycle13 |
50 |
| output_clock_frequency14 |
0 MHz |
| phase_shift14 |
0 ps |
| duty_cycle14 |
50 |
| output_clock_frequency15 |
0 MHz |
| phase_shift15 |
0 ps |
| duty_cycle15 |
50 |
| output_clock_frequency16 |
0 MHz |
| phase_shift16 |
0 ps |
| duty_cycle16 |
50 |
| output_clock_frequency17 |
0 MHz |
| phase_shift17 |
0 ps |
| duty_cycle17 |
50 |
| gui_pll_auto_reset |
On |
| gui_pll_bandwidth_preset |
Auto |
| gui_en_reconf |
false |
| gui_en_dps_ports |
false |
| gui_en_phout_ports |
false |
| gui_phout_division |
1 |
| pll_vcoph_div |
1 |
| pll_type |
General |
| pll_subtype |
General |
| m_cnt_hi_div |
8 |
| m_cnt_lo_div |
7 |
| n_cnt_hi_div |
256 |
| n_cnt_lo_div |
256 |
| m_cnt_bypass_en |
false |
| n_cnt_bypass_en |
true |
| m_cnt_odd_div_duty_en |
true |
| n_cnt_odd_div_duty_en |
false |
| c_cnt_hi_div0 |
2 |
| c_cnt_lo_div0 |
1 |
| c_cnt_prst0 |
1 |
| c_cnt_ph_mux_prst0 |
0 |
| c_cnt_in_src0 |
ph_mux_clk |
| c_cnt_bypass_en0 |
false |
| c_cnt_odd_div_duty_en0 |
true |
| c_cnt_hi_div1 |
4 |
| c_cnt_lo_div1 |
3 |
| c_cnt_prst1 |
1 |
| c_cnt_ph_mux_prst1 |
0 |
| c_cnt_in_src1 |
ph_mux_clk |
| c_cnt_bypass_en1 |
false |
| c_cnt_odd_div_duty_en1 |
true |
| c_cnt_hi_div2 |
6 |
| c_cnt_lo_div2 |
6 |
| c_cnt_prst2 |
1 |
| c_cnt_ph_mux_prst2 |
0 |
| c_cnt_in_src2 |
ph_mux_clk |
| c_cnt_bypass_en2 |
false |
| c_cnt_odd_div_duty_en2 |
false |
| c_cnt_hi_div3 |
12 |
| c_cnt_lo_div3 |
12 |
| c_cnt_prst3 |
1 |
| c_cnt_ph_mux_prst3 |
0 |
| c_cnt_in_src3 |
ph_mux_clk |
| c_cnt_bypass_en3 |
false |
| c_cnt_odd_div_duty_en3 |
false |
| c_cnt_hi_div4 |
24 |
| c_cnt_lo_div4 |
24 |
| c_cnt_prst4 |
1 |
| c_cnt_ph_mux_prst4 |
0 |
| c_cnt_in_src4 |
ph_mux_clk |
| c_cnt_bypass_en4 |
false |
| c_cnt_odd_div_duty_en4 |
false |
| c_cnt_hi_div5 |
48 |
| c_cnt_lo_div5 |
48 |
| c_cnt_prst5 |
1 |
| c_cnt_ph_mux_prst5 |
0 |
| c_cnt_in_src5 |
ph_mux_clk |
| c_cnt_bypass_en5 |
false |
| c_cnt_odd_div_duty_en5 |
false |
| c_cnt_hi_div6 |
96 |
| c_cnt_lo_div6 |
96 |
| c_cnt_prst6 |
1 |
| c_cnt_ph_mux_prst6 |
0 |
| c_cnt_in_src6 |
ph_mux_clk |
| c_cnt_bypass_en6 |
false |
| c_cnt_odd_div_duty_en6 |
false |
| c_cnt_hi_div7 |
192 |
| c_cnt_lo_div7 |
192 |
| c_cnt_prst7 |
1 |
| c_cnt_ph_mux_prst7 |
0 |
| c_cnt_in_src7 |
ph_mux_clk |
| c_cnt_bypass_en7 |
false |
| c_cnt_odd_div_duty_en7 |
false |
| c_cnt_hi_div8 |
1 |
| c_cnt_lo_div8 |
1 |
| c_cnt_prst8 |
1 |
| c_cnt_ph_mux_prst8 |
0 |
| c_cnt_in_src8 |
ph_mux_clk |
| c_cnt_bypass_en8 |
true |
| c_cnt_odd_div_duty_en8 |
false |
| c_cnt_hi_div9 |
1 |
| c_cnt_lo_div9 |
1 |
| c_cnt_prst9 |
1 |
| c_cnt_ph_mux_prst9 |
0 |
| c_cnt_in_src9 |
ph_mux_clk |
| c_cnt_bypass_en9 |
true |
| c_cnt_odd_div_duty_en9 |
false |
| c_cnt_hi_div10 |
1 |
| c_cnt_lo_div10 |
1 |
| c_cnt_prst10 |
1 |
| c_cnt_ph_mux_prst10 |
0 |
| c_cnt_in_src10 |
ph_mux_clk |
| c_cnt_bypass_en10 |
true |
| c_cnt_odd_div_duty_en10 |
false |
| c_cnt_hi_div11 |
1 |
| c_cnt_lo_div11 |
1 |
| c_cnt_prst11 |
1 |
| c_cnt_ph_mux_prst11 |
0 |
| c_cnt_in_src11 |
ph_mux_clk |
| c_cnt_bypass_en11 |
true |
| c_cnt_odd_div_duty_en11 |
false |
| c_cnt_hi_div12 |
1 |
| c_cnt_lo_div12 |
1 |
| c_cnt_prst12 |
1 |
| c_cnt_ph_mux_prst12 |
0 |
| c_cnt_in_src12 |
ph_mux_clk |
| c_cnt_bypass_en12 |
true |
| c_cnt_odd_div_duty_en12 |
false |
| c_cnt_hi_div13 |
1 |
| c_cnt_lo_div13 |
1 |
| c_cnt_prst13 |
1 |
| c_cnt_ph_mux_prst13 |
0 |
| c_cnt_in_src13 |
ph_mux_clk |
| c_cnt_bypass_en13 |
true |
| c_cnt_odd_div_duty_en13 |
false |
| c_cnt_hi_div14 |
1 |
| c_cnt_lo_div14 |
1 |
| c_cnt_prst14 |
1 |
| c_cnt_ph_mux_prst14 |
0 |
| c_cnt_in_src14 |
ph_mux_clk |
| c_cnt_bypass_en14 |
true |
| c_cnt_odd_div_duty_en14 |
false |
| c_cnt_hi_div15 |
1 |
| c_cnt_lo_div15 |
1 |
| c_cnt_prst15 |
1 |
| c_cnt_ph_mux_prst15 |
0 |
| c_cnt_in_src15 |
ph_mux_clk |
| c_cnt_bypass_en15 |
true |
| c_cnt_odd_div_duty_en15 |
false |
| c_cnt_hi_div16 |
1 |
| c_cnt_lo_div16 |
1 |
| c_cnt_prst16 |
1 |
| c_cnt_ph_mux_prst16 |
0 |
| c_cnt_in_src16 |
ph_mux_clk |
| c_cnt_bypass_en16 |
true |
| c_cnt_odd_div_duty_en16 |
false |
| c_cnt_hi_div17 |
1 |
| c_cnt_lo_div17 |
1 |
| c_cnt_prst17 |
1 |
| c_cnt_ph_mux_prst17 |
0 |
| c_cnt_in_src17 |
ph_mux_clk |
| c_cnt_bypass_en17 |
true |
| c_cnt_odd_div_duty_en17 |
false |
| pll_vco_div |
1 |
| pll_cp_current |
20 |
| pll_bwctrl |
4000 |
| pll_output_clk_frequency |
767.999671 MHz |
| pll_fractional_division |
1546159966 |
| mimic_fbclk_type |
gclk |
| pll_fbclk_mux_1 |
glb |
| pll_fbclk_mux_2 |
fb_1 |
| pll_m_cnt_in_src |
ph_mux_clk |
| pll_slf_rst |
true |
| gui_parameter_list |
M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,C-Counter-5 Hi Divide,C-Counter-5 Low Divide,C-Counter-5 Coarse Phase Shift,C-Counter-5 VCO Phase Tap,C-Counter-5 Input Source,C-Counter-5 Bypass Enable,C-Counter-5 Odd Divide Enable,C-Counter-6 Hi Divide,C-Counter-6 Low Divide,C-Counter-6 Coarse Phase Shift,C-Counter-6 VCO Phase Tap,C-Counter-6 Input Source,C-Counter-6 Bypass Enable,C-Counter-6 Odd Divide Enable,C-Counter-7 Hi Divide,C-Counter-7 Low Divide,C-Counter-7 Coarse Phase Shift,C-Counter-7 VCO Phase Tap,C-Counter-7 Input Source,C-Counter-7 Bypass Enable,C-Counter-7 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset |
| gui_parameter_values |
8,7,256,256,false,true,true,false,2,1,1,0,ph_mux_clk,false,true,4,3,1,0,ph_mux_clk,false,true,6,6,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,24,24,1,0,ph_mux_clk,false,false,48,48,1,0,ph_mux_clk,false,false,96,96,1,0,ph_mux_clk,false,false,192,192,1,0,ph_mux_clk,false,false,1,20,4000,767.999671 MHz,1546159966,gclk,glb,fb_1,ph_mux_clk,true |
| gui_mif_generate |
false |
| gui_enable_mif_dps |
false |
| gui_dps_cntr |
C0 |
| gui_dps_num |
1 |
| gui_dps_dir |
Positive |
| gui_refclk_switch |
false |
| gui_refclk1_frequency |
100.0 |
| gui_switchover_mode |
Automatic Switchover |
| gui_switchover_delay |
0 |
| gui_active_clk |
false |
| gui_clk_bad |
false |
| refclk1_frequency |
100.0 MHz |
| pll_clk_loss_sw_en |
false |
| pll_manu_clk_sw_en |
false |
| pll_auto_clk_sw_en |
false |
| pll_clkin_1_src |
clk_0 |
| pll_clk_sw_dly |
0 |
| gui_enable_cascade_out |
false |
| gui_cascade_outclk_index |
0 |
| gui_enable_cascade_in |
false |
| pll_clkin_0_src |
clk_0 |
| gui_pll_cascading_mode |
Create an adjpllin signal to connect with an upstream PLL |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |