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<br>
# SharpMZ
**Website:** [engineers@work](https://eaw.app) | **Repository:** [git.eaw.app/eaw/SharpMZ](https://git.eaw.app/eaw/SharpMZ)
---
<a name="overview" id="overview"></a>
## <font style="color: yellow;" size="6">Overview</font>
<div style="text-align: justify">
Version 1.0 of the Sharp MZ Series FPGA Emulation is a complete hardware-level recreation of the Sharp MZ computer family, implemented in VHDL and hosted on the <a href="https://git.eaw.app/eaw/SharpMZ_MiSTer">MiSTer FPGA platform</a> (Terasic DE10-Nano board). Unlike software emulators that interpret instructions, this design synthesises the actual digital logic of each Sharp MZ model inside the Cyclone V SE FPGA — the Z80 CPU, video controller, memory map, keyboard scanner, cassette interface, audio, and I/O peripherals all exist as concurrent hardware running in real time.
<br><br>
The project was created by Philip Smart and is hosted under the <a href="https://github.com/mister-devel">MiSTer-devel</a> organisation on Gitea. The source repository is <a href="https://git.eaw.app/eaw/SharpMZ_MiSTer">SharpMZ_MiSTer</a>. A successor version (v2.0) ports the design to the <a href="/tranzputer-sw-700/">tranZPUter SW-700</a> card, enabling emulation to run inside a physical Sharp MZ host machine — see the <a href="#v1-vs-v2">v1 vs v2 comparison</a> below.
<br><br>
After releasing v1.0 into the MiSTer project, I was advised that I cannot place management menus in the MiSTer binary running on the Cyclone V Cortex core. I was advised to create an FPGA instantiated management CPU and build my management code and menus into it. I disagreed with this decision as the Cyclone V Cortex core is redundant when the Emulation is running and should be dedicated to the Core if the developer chooses, so long as it provided compatible MiSTer base menus to allow the user to select another core or reboot. I spent quite some time working with the ZPU processor, which led to the creation of the <a href="/zpu-evo/">ZPU Evo(lution)</a>. In the end I lost the momentum to advance the emulation for the MiSTer project. Once the MiSTer project has stabilised and I can see a route to adding my latest developments, without creating a management CPU, I will update MiSTer with v2.0 and later changes.
</div>
<a name="summary" id="summary"></a>
## <font style="color: yellow;" size="6">Summary</font>
This project aims to provide full hardware emulation (along with extensions) of the Sharp MZ Series Computers.
The initial version is based on the Terasic DE10 Nano board and hosted under the [MiSTer_Devel](https://github.com/MiSTer_Devel) project using the HPS processor for UI operations. Work is currently under way to embed the [ZPU Evo](/zpu-evo/) into
the design to act as the UI processor such that the emulation can be hosted on different hardware as needed.
The initial version is based on the Terasic DE10 Nano board and hosted under the [MiSTer_Devel](https://github.com/MiSTer_Devel) project using the HPS processor for UI operations.
The following emulations have been written:
@@ -28,30 +46,99 @@ The current version of the emulator provides:
| Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type. |
| i8253 mono audio or Tape audio |
### Enhancements in test/under development
### <font style="color: yellow;" size="5">Enhancements in test/under development</font>
| Floppy Disk Drive/Controller 5.25" |
| Quick Disk Controller |
| Dual digital Joystick Input (MZ700) |
### Known Issues
### <font style="color: yellow;" size="5">Known Issues</font>
| Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A. |
| HDMI needs to be re-enabled in the design. |
| Need to complete the status frame buffer, used by the ZPU I/O processor for status information display - not critical to use. |
### Design Summary
<a name="design-summary" id="design-summary"></a>
### <font style="color: yellow;" size="5">Design Summary</font>
<div style="text-align: justify">
The idea of this design is to keep the emulation as independent of the HPS as possible (so it works standalone), only needing the HPS to set control registers,
read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be
someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone
wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
<br><br>
As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external
SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
</div>
<a name="fpga-architecture" id="fpga-architecture"></a>
## <font style="color: yellow;" size="6">FPGA Architecture</font>
## Installation
<div style="text-align: justify">
The emulation is written entirely in VHDL and targets the Intel (Altera) Cyclone V SE FPGA on the Terasic DE10-Nano board. The design is structured as a set of modular components that mirror the real hardware subsystems of the Sharp MZ computers. Each component runs as concurrent logic — there is no sequential software interpretation of instructions.
</div>
<a name="fpga-components" id="fpga-components"></a>
### <font style="color: yellow;" size="5">Core Components</font>
<div style="text-align: justify">
The top-level entity (<code>sharpmz.sv</code>) instantiates all the subsystems and connects them to the MiSTer framework. The key VHDL modules are:
</div>
| Module | Source | Function |
| ------ | ------ | -------- |
| **T80 CPU** | `rtl/T80/*.vhd` | Z80 CPU core — a cycle-accurate open-source Z80 implementation. Directly synthesised into FPGA logic, running at the original clock speed (2 MHz for MZ-80K, 3.5 MHz for MZ-700, 4 MHz for MZ-80B) with selectable turbo modes up to 32× (112 MHz for MZ-700). |
| **Machine Controller** | `rtl/mctrl.vhd` | Central state machine that implements the memory map, I/O port decoding, and bank switching logic for each Sharp MZ model. Selects which peripherals are active based on the configured machine type. |
| **Video Controller** | `rtl/video.vhd` | Character-based display with 40×25 and 80×25 modes, colour/mono output, VGA sync generation and scaling. Uses double-buffered rendering — VRAM is expanded to pixels during vertical blanking to eliminate snow/tearing. |
| **MZ-80B Video** | `rtl/mz80b/mz80b_video.vhd` | Extended video controller for MZ-80B/MZ-2000 models with their different video architecture and 640×200 monochrome graphics. |
| **CMT (Cassette)** | `rtl/cmt.vhd`, `rtl/mz80b/cmt.vhd` | Cassette Magnetic Tape interface. Emulates the tape hardware signals using a 64K RAM cache that holds a complete tape image. Supports 1×–32× fast mode and APSS (Automated Programme Search System) for MZ-80B/MZ-2000. |
| **i8253 Timer** | `rtl/i8253/*.vhd` | Intel 8253 Programmable Interval Timer — provides system timing and mono audio generation, matching the real IC used in Sharp MZ hardware. |
| **i8255 PPI** | `rtl/i8255/i8255.vhd` | Intel 8255 Programmable Peripheral Interface — handles keyboard scanning, cassette control signals, and general-purpose I/O, as per the original Sharp MZ design. |
| **Z80 PIO (z8420)** | `rtl/z8420/*.vhd` | Z80 Parallel I/O controller used in MZ-80B/MZ-2000 models for additional peripheral interfacing. |
| **Keyboard Matrix** | `rtl/keymatrix.vhd` | Converts PS/2 keyboard input into the Sharp MZ key matrix format. Uses configurable ROM-based key mapping tables that can be uploaded per machine model. |
| **Clock Generator** | `rtl/clkgen.vhd`, `rtl/clk_div.vhd` | PLL-based clock synthesis from the DE10-Nano's 50 MHz oscillator. Generates all required clock domains — CPU clock (with selectable turbo multiplier), video dot clock, and peripheral timing. |
| **MZ-80B/2000 Logic** | `rtl/mz80b/mz80b.vhd` | Complete glue logic and memory map for MZ-80B and MZ-2000 models, including floppy controller interface (`mb8876.vhd`, `fd55b.vhd`), system control (`sysctrl.vhd`), and extended I/O. |
| **MZ-80K/C Logic** | `rtl/mz80c/mz80c.vhd` | Glue logic and memory map for the MZ-80K, MZ-80C, MZ-1200, MZ-80A, and MZ-700 family of machines. |
| **Bridge** | `rtl/bridge.vhd` | Interface between the FPGA emulation logic and the MiSTer HPS (ARM processor). Handles control register access, ROM/tape image uploads, and the OSD menu communication channel. |
| **Config Package** | `rtl/config_pkg.vhd` | VHDL package containing all configuration constants, machine-specific parameters, memory addresses, and I/O port definitions. |
| **SPI Master** | `rtl/spi_master.vhd` | SPI bus controller for SD card access (tape and floppy image storage). |
<a name="fpga-memory" id="fpga-memory"></a>
### <font style="color: yellow;" size="5">Memory Architecture</font>
<div style="text-align: justify">
The Cyclone V SE provides 5.5 Mbits of embedded block RAM, and the design exploits this to keep nearly all emulated memory on-chip for deterministic single-cycle access. The memory layout includes:
</div>
| Memory | Size | Purpose |
| ------ | ---- | ------- |
| Main RAM | 48K / 64K | System RAM — 48K for MZ-80K/C/1200/A, 64K for MZ-700/80B. Directly accessible by the T80 CPU core. |
| Video RAM | 2K + 2K | Character VRAM (2K) and Attribute RAM (2K) for colour information. |
| Character Generator ROM | per model | Built-in CGROM for each machine model, plus a switchable CGRAM for PCG-8000/PCG-1200 compatibility (2K). |
| Monitor ROMs | per model | Complete set of monitor ROMs for all emulated machines (SA-1510, SP-1002, etc.), concatenated into a single ROM bank. |
| Key Mapping ROM | per model | Keyboard translation tables for each machine, supporting custom uploads for Japanese layouts (MZ-1200) and other variants. |
| CMT Cache | 64K | Full tape image cache — an entire MZF program (header + data) is loaded here by the HPS, then fed to the CMT hardware emulation as a bit stream. |
| Graphics Frame Buffer | 3 × 16K | Red, Green, and Blue pixel planes for 640×200 / 320×200 8-colour graphics display. Directly addressable by the CPU at C000H–FFFFH via bank switching. |
| Status Frame Buffer | ~8K | Pixel-mapped overlay for OSD menu and status indicators (Record, Play, Floppy activity), outside the main display area. |
<a name="fpga-hps" id="fpga-hps"></a>
### <font style="color: yellow;" size="5">HPS Integration</font>
<div style="text-align: justify">
The DE10-Nano contains a dual-core ARM Cortex-A9 Hard Processor System (HPS) alongside the FPGA fabric. In the MiSTer architecture, the HPS runs a Linux system that provides:
</div>
- **OSD Menu System** — The F12 on-screen display for machine selection, tape/floppy operations, display settings, ROM management, and debugging. Menu state is communicated to the FPGA via the bridge module's control registers.
- **SD Card Access** — MZF tape images and DSK floppy images are stored on the MiSTer SD card. The HPS reads files from the FAT filesystem and transfers complete images into the FPGA's CMT cache RAM via the bridge.
- **Control Registers** — Machine model selection, CPU speed, display mode, audio settings, and debug configuration are all set by the HPS writing to memory-mapped registers in the bridge module.
- **ROM Upload** — Custom monitor ROMs, character generator ROMs, key mapping tables, user ROMs, and floppy disk ROMs can be uploaded from SD card files at startup via the bridge.
<div style="text-align: justify; padding-top: 0.8em;">
Crucially, the emulation itself is self-contained in the FPGA — the HPS only provides configuration and file I/O services. The T80 CPU, video, audio, keyboard, and tape logic all run independently of the ARM processor once configured. This separation was a deliberate design decision to facilitate porting to other FPGA platforms where no HPS is available.
</div>
<a name="installation" id="installation"></a>
## <font style="color: yellow;" size="6">Installation</font>
|1. |Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide |
|2. |Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:- |
@@ -68,14 +155,17 @@ SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT
|8. |Press F12 to change the configuration, select Save Config to store it. |
## Using the Emulator
<a name="using-the-emulator" id="using-the-emulator"></a>
## <font style="color: yellow;" size="6">Using the Emulator</font>
### Menu System
<a name="menu-system" id="menu-system"></a>
### <font style="color: yellow;" size="5">Menu System</font>
The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the
display parameters, debugging and access to the MiSTer control menu.
#### Tape Storage
<a name="tape-storage" id="tape-storage"></a>
#### <font style="color: yellow;" size="4">Tape Storage</font>
In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved
on to Floppy/Quick Disks.
@@ -132,7 +222,8 @@ This menu controls the hardware CMT unit and has the following choices:
MiSTer Main binary which then uses that name to create a file on the SD card.*
#### Machine
<a name="machine" id="machine"></a>
#### <font style="color: yellow;" size="4">Machine</font>
The emulation emulates several Sharp MZ computers and this menu allows you to choose the desired Sharp Model to be emulated.
- Machine Model
@@ -189,7 +280,8 @@ The emulation emulates several Sharp MZ computers and this menu allows you to ch
made to create an 80x25 display. The emulation is capable of both modes but in order to run correctly, a different Monitor Rom for 80x25 display is needed.
#### Display
<a name="display" id="display"></a>
#### <font style="color: yellow;" size="4">Display</font>
The display on the Sharp MZ computers was originally quite simplistic. In order to cater for enhancements made in each model and by external vendors, the emulation has several configurable parameters which are grouped under this menu.
@@ -218,7 +310,7 @@ The display on the Sharp MZ computers was originally quite simplistic. In order
these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
- Graphics Addr
As the emulation is catering for several Sharp MZ models in addition to adding graphics onto machines which originally didnt have graphics there can be a clash of I/O address for selecting the graphics mode and options. This option sets the default
As the emulation is catering for several Sharp MZ models in addition to adding graphics onto machines which originally didn't have graphics there can be a clash of I/O address for selecting the graphics mode and options. This option sets the default
IO address for accessing the graphics control registers.
- VRAM CPU Wait
@@ -244,11 +336,12 @@ The display on the Sharp MZ computers was originally quite simplistic. In order
<br>*NB: Aspect Ratio and Scandoubler are currently disabled due to the inclusion of the VGA Scaling hardware. When HDMI output is compiled into the design in the near future they will be re-enabled.*
#### Debugging
<a name="debugging" id="debugging"></a>
#### <font style="color: yellow;" size="4">Debugging</font>
*Debugging has now been made a compile time option. If debugging logic has been enabled in the RTL and Main MiSTer binary, the debugging options below will be available.*
In FPGA's, all the signals are internal and unless brought out to valuable IO pins, the signals are not easily evaluated on say a trusty Oscilloscope. Altera do have an on-chip solution in the form of it's Signal Tap analyser which adds logic into your
In FPGAs, all the signals are internal and unless brought out to valuable IO pins, the signals are not easily evaluated on say a trusty Oscilloscope. Altera do have an on-chip solution in the form of its Signal Tap analyser which adds logic into your
design to record signal states which are read to a PC realtime but this requires forethought in setting up the taps, the triggers, edges, compiling and hoping you have considered the correct points and have enough free memory and spare logic (generally you do).
In saying this, there is something magic about seeing signals real-time and probing them with an oscilloscope and to this end i’ve added a debugging mode which can be used at any time without affecting the emulation (unless you choose a debug frequency in
which case the emulation will run at the selected frequency).
@@ -324,25 +417,28 @@ To use the debug mode, press F12 to enter the MiSTer menu, then select Debug and
| MZ80B I | = | Not yet defined. | | | | | |
| MZ80B II | = | Not yet defined. | | | | | |
#### System
<a name="system" id="system"></a>
#### <font style="color: yellow;" size="4">System</font>
This is the MiSTer main control menu which allows you to select a core, map keys, set bluetooth, view IP address etc.
#### Control Options
<a name="control-options" id="control-options"></a>
#### <font style="color: yellow;" size="4">Control Options</font>
The menu system presents additional control options whose function is detailed below:
| Option | Description |
| ------ | ----------- |
| Boot Reset | Perform an IPL reset on the Emulator when running in MZ80B/MZ2000 mode, ie. the boot switch you would press to bring up the IPL and load the initial program. |
| Reset | Reset the emulation, ie. toggle it's reset line. |
| Reset | Reset the emulation, ie. toggle its reset line. |
| Reload config | Reload the configuration saved previously. Any change made in these menus can be stored for future use, if additional changes are unwanted, use this option to reload your last good configuration. |
| Save config | Save the configuration to SD card. Any changes you made in the Menu system will be saved. |
| Reset config | Reset the configuration to standard defaults. |
### Graphics Frame Buffer
<a name="graphics-frame-buffer" id="graphics-frame-buffer"></a>
### <font style="color: yellow;" size="5">Graphics Frame Buffer</font>
An addition to the original design is a 640x200/320x200 8 colour Graphics frame buffer. There were many additions to the Sharp MZ series to allow graphics (ie. MZ80B comes with standard mono graphics) display and as I don’t have detailed
information of these 3rd party upgrades to date, I designed my own extension compatible with the standard Sharp MZ series video and graphics logic with the intention of adding hardware abstraction layers at a later date to add compatibility
@@ -359,7 +455,8 @@ In order to speed up the display, there is a Colour Write register, so that a wr
The programmable registers details are outlined below.
#### Switching Graphics RAM Banks into Z80 CPU Address Range
<a name="switching-graphics" id="switching-graphics"></a>
#### <font style="color: yellow;" size="4">Switching Graphics RAM Banks into Z80 CPU Address Range</font>
##### Graphics Bank Switch Set Register: I/O Address: E8H (232 decimal)
@@ -370,7 +467,7 @@ The programmable registers details are outlined below.
A read from this address switches out the Graphics RAM and returns to previous memory state.
#### Control Register (0xEA - 234 decimal)
#### <font style="color: yellow;" size="4">Control Register (0xEA - 234 decimal)</font>
| Bits | Description |
| ---- | ----------- |
@@ -380,7 +477,8 @@ The programmable registers details are outlined below.
| 5 | GRAM Output. 0=Enable, 1=Disable. Output Graphics RAM to the display. |
| 7:6 | Blend Operator (00=OR ,01=AND, 10=NAND, 11=XOR). Operator to blend Character display with Graphics Display. |
#### Colour Writer Registers (0xEB - 235 decimal to 0xED - 237 decimal )
<a name="colour-writer" id="colour-writer"></a>
#### <font style="color: yellow;" size="4">Colour Writer Registers (0xEB - 235 decimal to 0xED - 237 decimal )</font>
| Bit | Pixel | I/O Addr | Colour | Description |
| --- | ----- | -------- | ------ | ----------- |
@@ -412,11 +510,12 @@ The programmable registers details are outlined below.
For Indirect mode (Control Register bits 3/2 set to 11), a write to the Graphics RAM when mapped into CPU address space C000H – FFFFH will see the byte masked by the Red Colour Writer Register and written to the Red Bank with the same operation
for Green and Blue. This allows rapid setting of a colour across the 3 banks.
### Status Frame Buffer
<a name="status-frame-buffer" id="status-frame-buffer"></a>
### <font style="color: yellow;" size="5">Status Frame Buffer</font>
As part of the changes being made to the emulator with the intended onboarding of an I/O processor into the design, I have added an additional frame buffer which occupies the vertical lines outside of the normal screen rendering. ie. For a 640x480 VGA display, there are 80 rows
available that can be seen on the screen, 40 above the main display and 40 below. This increases to 100 above and 100 below for 800x600 SVGA mode. The status frame buffer also overlays (programmable OR, XOR, AND & NAND bit blending) a block of video RAM
on the main display to bring up a MiSTer style menu, the width and height varying according to the graphics mode selected. The menu is 256pixels hortizontal x 128pixels vertical.
available that can be seen on the screen but are outside the normal display (ie. 80x25 character display = 80x8 horizontal = 640 pixels, 25*8*2 vertical = 400 pixels so 80 free), 40 above the main display and 40 below. This increases to 100 above and 100 below for 800x600 SVGA mode.
The status frame buffer also overlays (programmable OR, XOR, AND & NAND bit blending) a block of video RAM on the main display to bring up a MiSTer style menu, the width and height varying according to the graphics mode selected. The menu is 256pixels hortizontal x 128pixels vertical.
The purpose of this status frame buffer is to allow the on board IO processor to have the ability to superimpose its own menu system without affecting the underlying emulator and to also display valued information, such as: Record, Play, QuickDisk, Floppy activity lights and status etc.
This will then allow the emulator to be fully standalone and thus reducing the requirements from the MiSTer Main binary and increase its ability to run on various other FPGA development boards.
@@ -469,7 +568,78 @@ For both the Status RAM and Menu RAM the memory width is 24 bits wide for 8 pixe
## Links
<a name="v1-vs-v2" id="v1-vs-v2"></a>
## <font style="color: yellow;" size="6">v1.0 vs v2.0 — Key Differences</font>
<div style="text-align: justify">
Version 2.0 takes the v1.0 Sharp MZ Series FPGA emulation and ports it from the standalone MiSTer DE10-Nano platform to the <a href="/tranzputer-sw-700/">tranZPUter SW-700</a> expansion card, which plugs directly into a physical Sharp MZ-700 or MZ-2000 host machine. This fundamentally changes the relationship between the emulator and the real hardware — instead of a self-contained FPGA board with synthetic peripherals, the v2.0 emulator runs inside an actual Sharp MZ computer and can use its physical keyboard, cassette drive, sound hardware, and display alongside the FPGA-emulated equivalents.
</div>
<a name="v1v2-platform" id="v1v2-platform"></a>
### <font style="color: yellow;" size="5">Platform Differences</font>
| Aspect | v1.0 — MiSTer (DE10-Nano) | v2.0 — tranZPUter SW-700 |
| ------ | -------------------------- | ------------------------ |
| **FPGA** | Intel Cyclone V SE (DE10-Nano) | Intel Cyclone V (tranZPUter SW-700 board) |
| **Host** | Standalone — no Sharp MZ hardware required | Plugs into a physical MZ-700 or MZ-2000 via the Z80 CPU socket |
| **I/O Processor** | ARM Cortex-A9 HPS (Linux) — part of DE10-Nano SoC | ARM Cortex-M4 (K64F on tranZPUter board), with ZPU Evolution as a planned replacement |
| **Video Output** | VGA from FPGA I/O pins; HDMI via MiSTer add-on board | Direct connection to the host MZ-700/2000's CRT or external VGA via the Video Module |
| **Keyboard** | PS/2 keyboard via MiSTer I/O board | Physical Sharp MZ keyboard (directly wired) or PS/2 via SharpKey interface |
| **Audio** | Audio DAC on MiSTer I/O board | Physical Sharp MZ speaker and/or audio output jack |
| **Cassette** | Emulated only — MZF files from MiSTer SD card | Choice of physical CMT tape drive or FPGA-emulated drive with MZF files from SD card |
| **Storage** | MiSTer SD card (Linux filesystem) | SD card on tranZPUter (FAT32) |
| **Menu System** | MiSTer F12 OSD (rendered by HPS ARM Linux binary) | Built-in OSD (rendered by ARM Cortex-M4 or ZPU on the tranZPUter), invoked via TZFS `mz` command |
<a name="v1v2-architecture" id="v1v2-architecture"></a>
### <font style="color: yellow;" size="5">Architectural Differences</font>
<div style="text-align: justify">
<b>Modularisation</b> — v2.0 restructures the VHDL into finer-grained modules so that physical and emulated resources can be mixed. For example, the video controller can drive the host machine's CRT for native display modes while simultaneously providing enhanced modes (80-column, colour, graphics) through the Video Module. In v1.0, all peripherals are always emulated.
<br><br>
<b>I/O Processor Independence</b> — v1.0 relies on the MiSTer HPS (ARM Cortex-A9 running Linux) for OSD menus, SD card file I/O, and configuration. The MiSTer Main binary handles all user interaction, which ties the emulation to the MiSTer ecosystem. v2.0 embeds the I/O processor (initially the K64F ARM Cortex-M4, later the ZPU Evolution soft-core) inside the FPGA design itself. The OSD, file browser, tape queueing, and configuration are all handled by firmware running on this embedded processor, making the emulation fully self-contained and portable to any FPGA platform.
<br><br>
<b>Host Hardware Integration</b> — The most significant difference in v2.0 is the ability to use the real hardware of the host machine. When the emulation runs on an MZ-700 via the tranZPUter SW-700, the user can choose between the physical CMT tape drive (loading and saving to real cassettes) or the FPGA-emulated drive (loading MZF files from SD card). The physical keyboard is used directly. The host machine's memory, ROM, and I/O ports remain accessible alongside the emulated resources, controlled by the tranZPUter's bus arbitration logic.
<br><br>
<b>Video Module Enhancements</b> — v2.0 incorporates the improved <a href="/sharpmz-upgrades-video/">Video Module</a> design developed for the tranZPUter project. This provides more accurate video timing per machine model, palette-based colour (including the v2.0 programmable palette registers for 8-bit colour), and a 32-bit interface when driven by the ZPU. The v1.0 video controller is simpler — it targets VGA output with scaling and does not have the palette enhancements.
<br><br>
<b>Emulation Accuracy</b> — Work on physical Sharp MZ machines during the tranZPUter project revealed timing inaccuracies in the v1.0 emulation. v2.0 incorporates corrections based on measurements from real hardware, particularly in video timing, memory wait states, and I/O port behaviour for the MZ-80B and MZ-2000 models.
</div>
<a name="v1v2-features" id="v1v2-features"></a>
### <font style="color: yellow;" size="5">Feature Comparison</font>
| Feature | v1.0 | v2.0 |
| ------- | ---- | ---- |
| MZ-80K/C/1200/A emulation | Yes | Yes |
| MZ-700 emulation | Yes | Yes |
| MZ-80B emulation | Yes | Yes (improved accuracy) |
| MZ-2000 emulation | Partial | Yes (improved accuracy) |
| MZ-800 emulation | Under development | Under development |
| Physical tape drive | No | Yes — real CMT or emulated, selectable |
| Physical keyboard | No (PS/2 only) | Yes — native Sharp MZ keyboard |
| Turbo mode (up to 32×) | Yes | Yes |
| PCG (Programmable Character Generator) | Yes | Yes |
| 8-colour graphics (320×200 / 640×200) | Yes | Yes |
| Programmable colour palette | No | Yes (Video Module v2.0) |
| Custom ROM upload | Yes | Yes |
| APSS tape drive (MZ-80B/2000) | Yes | Yes |
| OSD menu system | MiSTer F12 menu | Built-in OSD with file browser |
| I/O processor | HPS (external to FPGA) | Embedded (K64F / ZPU, inside the design) |
| HDMI output | Via MiSTer add-on board | Not applicable (CRT or VGA) |
| Floppy disk | Under development | Under development |
| Quick disk | Under development | Under development |
| Standalone operation | Requires MiSTer framework | Self-contained on tranZPUter SW-700 |
| Host platform | DE10-Nano only | tranZPUter SW-700 in MZ-700/2000; future DE10-Nano return planned |
<a name="v1v2-roadmap" id="v1v2-roadmap"></a>
### <font style="color: yellow;" size="5">Migration Roadmap</font>
<div style="text-align: justify">
The long-term plan is to bring the v2.0 improvements back to the MiSTer platform. Once the ZPU Evolution I/O processor replaces the K64F in the tranZPUter design, the same VHDL — including the embedded I/O processor, OSD, and all peripherals — can be synthesised for the DE10-Nano without requiring the MiSTer HPS ARM binary for menu support. This will make the Sharp MZ Series core fully self-contained on MiSTer and significantly reduce the maintenance burden of tracking MiSTer framework changes. Additional machine emulations (MZ-1500, MZ-2200, MZ-2500) are planned for both platforms.
</div>
<a name="links" id="links"></a>
## <font style="color: yellow;" size="6">Links</font>
The Sharp MZ Series Computers were not as wide spread as Commodore, Atari or Sinclair but they had a dedicated following. Given their open design it was very easy to modify and extend applications such as the BASIC interpreters and likewise easy
to add hardware extension. As such, a look round the web finds some very comprehensive User Groups with invaluable resources. If you need manuals, programs, information then please look (for starters) at the following sites:
@@ -484,7 +654,8 @@ to add hardware extension. As such, a look round the web finds some very compreh
| [SharpMZ Forum](http://forum.sharpmz.org) | Active Sharp MZ forum for all models. |
| [SCAV](http://www.scav.cz/uvod.htm) | Czech site for Sharp information and downloads, use chrome to auto translate Czech |
## Credits
<a name="credits" id="credits"></a>
## <font style="color: yellow;" size="6">Credits</font>
My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer
project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab
@@ -492,11 +663,12 @@ and his excellent work. Also credit to Sorgelig for his hard work in creating th
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. All 3rd party software, to my knowledge and research, is open source and freely useable,
if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.
## Licenses
<a name="licenses" id="licenses"></a>
## <font style="color: yellow;" size="6">Licenses</font>
This design, hardware and software, is licensed under the GNU Public Licence v3.
### The Gnu Public License v3
### <font style="color: yellow;" size="5">The Gnu Public License v3</font>
The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.