175 lines
6.3 KiB
VHDL
Vendored
175 lines
6.3 KiB
VHDL
Vendored
---------------------------------------------------------------------------------------------------------
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--
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-- Name: sfd700_pkg.vhd
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-- Created: July 2023
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-- Author(s): Philip Smart
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-- Description: SFD700 CPLD package file.
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--
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-- This module contains static declarations and functions for the SFD700 Floopy Disk
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-- Interface project.
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--
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-- Credits:
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-- Copyright: (c) 2018-23 Philip Smart <philip.smart@net2net.org>
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--
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-- History: July 2023 - Initial write.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library ieee;
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library pkgs;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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package sfd700_pkg is
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------------------------------------------------------------
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-- Constants
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------------------------------------------------------------
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-- Potential logic state constants.
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constant YES : std_logic := '1';
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constant NO : std_logic := '0';
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constant HI : std_logic := '1';
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constant LO : std_logic := '0';
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constant ONE : std_logic := '1';
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constant ZERO : std_logic := '0';
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constant HIZ : std_logic := 'Z';
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-- Target hardware modes.
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constant MODE_MZ1200 : integer := 0;
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constant MODE_MZ80A : integer := 0;
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constant MODE_MZ700 : integer := 1;
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constant MODE_MZ80B : integer := 2;
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constant MODE_MZ800 : integer := 3;
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constant MODE_MZ1500 : integer := 4;
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constant MODE_MZ2000 : integer := 5;
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constant MODE_MZ2200 : integer := 6;
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------------------------------------------------------------
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-- Configurable parameters.
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------------------------------------------------------------
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-- Version of hdl.
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constant CPLD_VERSION : integer := 1;
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------------------------------------------------------------
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-- Function prototypes
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------------------------------------------------------------
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-- Find the maximum of two integers.
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function IntMax(a : in integer; b : in integer) return integer;
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-- Find the number of bits required to represent an integer.
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function log2ceil(arg : positive) return natural;
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-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
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function clockTicks(period : in integer; clock : in integer) return integer;
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-- Function to reverse the order of the bits in a standard logic vector.
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-- ie. 1010 becomes 0101
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function reverse_vector(slv:std_logic_vector) return std_logic_vector;
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-- Function to convert an integer (0 or 1) into std_logic.
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--
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function to_std_logic(i : in integer) return std_logic;
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-- Function to return the value of a bit as an integer for array indexing etc.
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function bit_to_integer( s : std_logic ) return natural;
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------------------------------------------------------------
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-- Records
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------------------------------------------------------------
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------------------------------------------------------------
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-- Components
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------------------------------------------------------------
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end sfd700_pkg;
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------------------------------------------------------------
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-- Function definitions.
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------------------------------------------------------------
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package body sfd700_pkg is
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-- Find the maximum of two integers.
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function IntMax(a : in integer; b : in integer) return integer is
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begin
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if a > b then
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return a;
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else
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return b;
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end if;
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return a;
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end function IntMax;
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-- Find the number of bits required to represent an integer.
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function log2ceil(arg : positive) return natural is
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variable tmp : positive := 1;
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variable log : natural := 0;
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begin
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if arg = 1 then
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return 0;
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end if;
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while arg > tmp loop
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tmp := tmp * 2;
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log := log + 1;
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end loop;
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return log;
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end function;
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-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
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function clockTicks(period : in integer; clock : in integer) return integer is
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variable ticks : real;
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variable fracTicks : real;
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begin
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ticks := (Real(period) * Real(clock)) / 1000000000.0;
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fracTicks := ticks - CEIL(ticks);
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if fracTicks > 0.0001 then
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return Integer(CEIL(ticks + 1.0));
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else
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return Integer(CEIL(ticks));
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end if;
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end function;
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function reverse_vector(slv:std_logic_vector) return std_logic_vector is
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variable target : std_logic_vector(slv'high downto slv'low);
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begin
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for idx in slv'high downto slv'low loop
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target(idx) := slv(slv'low + (slv'high-idx));
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end loop;
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return target;
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end reverse_vector;
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function to_std_logic(i : in integer) return std_logic is
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begin
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if i = 0 then
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return '0';
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end if;
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return '1';
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end function;
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-- Function to return the value of a bit as an integer for array indexing etc.
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function bit_to_integer( s : std_logic ) return natural is
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begin
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if s = '1' then
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return 1;
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else
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return 0;
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end if;
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end function;
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end package body;
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