Name     SFD700 ;
PartNo   GAL26CV12 ;
Date     24/04/2023 ;
Revision 01 ;
Designer Philip Smart ;
Company  engineers@work ;
Assembly SFD700 ;
Location  ;
Device   g26cv12 ;

/* *************** CONSTANTS ********************** */
$DEFINE ON  'b'1
$DEFINE OFF 'b'0

/* *************** INPUT PINS ********************* */
PIN  1       = A0                                    ; /* Address bus A0                                                  */ 
PIN  2       = A1                                    ; /*             A1                                                  */ 
PIN  3       = A2                                    ; /*             A2                                                  */ 
PIN  4       = A3                                    ; /*             A3                                                  */ 
PIN  5       = A4                                    ; /*             A4                                                  */ 
PIN  6       = A5                                    ; /*             A5                                                  */ 
PIN  8       = A6                                    ; /*             A6                                                  */ 
PIN  9       = A7                                    ; /*             A7                                                  */ 
PIN 10       = A12                                   ; /*             A12                                                 */ 
PIN 11       = A13                                   ; /*             A13                                                 */ 
PIN 12       = A14                                   ; /*             A14                                                 */ 
PIN 13       = A15                                   ; /*             A15                                                 */ 
PIN 14       = !MREQn                                ; /* Z80 MREQ active low                                             */ 
PIN 15       = !IORQn                                ; /* Z80 IORQ active low                                             */ 
PIN 16       = !WRn                                  ; /* Z80 WR active low                                               */ 
PIN 17       = !RDn                                  ; /* Z80 RD active low                                               */ 
PIN 28       = RESET                                 ; /* System Reset active high                                        */ 

/* *************** OUTPUT PINS ******************** */
PIN 22       = !BUSENn                               ; /* BUS direction, low = read into Z80, high = write to card.       */ 
PIN 20       = !IOBUSDIRn                            ; /* I/O BUS direction, low = read into Z80, high = write to FD IC's */ 
PIN 27       = !FDCn                                 ; /* WD1773 Chip Select active low I/O - Address 0xD8 .. 0xDB        */ 
PIN 26       = !DRIVEn                               ; /* Disk Drive Select active low - Address 0xDC                     */ 
PIN 25       = !DDENn                                ; /* Drive Density select active low - Address 0xDE                  */ 
PIN 24       = !FDCRESETn                            ; /* Peripheral Reset active low                                     */ 
PIN 23       = !SIDEn                                ; /* Disk Head Select active low - Address 0xDD                      */ 
PIN 19       = !INTEN                                ; /* Interrupt enable.                                               */
PIN 18       = !ROMn                                 ; /* ROM Select.                                                     */

/* Decoder equations. */
FIELD IOADDR = [A7..0]                               ; /* Address lines considered for I/O devices.                       */
FIELD HIADDR = [A15..12]                             ; /* Address lines considered for ROM device.                        */
WD1773SELR   = IORQn & RDn & IOADDR:[D8..DB]         ; /* FDC select.                                                     */
WD1773SELW   = IORQn & WRn & IOADDR:[D8..DB]         ; /* FDC select.                                                     */
SIDESEL      = IORQn & WRn & IOADDR:[DD..DD]         ; /* Drive side select.                                              */
DRIVESEL     = IORQn & WRn & IOADDR:[DC..DC]         ; /* Drive number select.                                            */
DDENSEL      = IORQn & WRn & IOADDR:[DE..DE]         ; /* Drive Double Density select.                                    */
ROMSEL       = MREQn & RDn & HIADDR:[F000..F7FF]     ; /* Rom Select.                                                     */
DRAMENSEL    = IORQn & WRn & IOADDR:[E1];

/* Assign output pins based on equations. */
IOBUSDIRn    = WD1773SELR                            ;
BUSENn       = ROMSEL # WD1773SELR # WD1773SELW #
               SIDESEL # DRIVESEL # DDENSEL          ;
FDCRESETn    = RESET                                 ;
FDCn         = WD1773SELR # WD1773SELW               ;
SIDEn        = SIDESEL                               ;
DRIVEn       = DRIVESEL                              ;
DDENn        = DDENSEL                               ;
ROMn         = ROMSEL                                ;
INTEN.sp     = DRAMENSEL                             ;
INTEN.ar     = RESET ;
