# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32  June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		tzpuFusionX_MZ700.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY sfd700
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32  JULY 27, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL


# Z80 Address Bus
# ===============
set_location_assignment PIN_4 -to Z80_ADDR[0]
set_location_assignment PIN_5 -to Z80_ADDR[1]
set_location_assignment PIN_6 -to Z80_ADDR[2]
set_location_assignment PIN_8 -to Z80_ADDR[3]
set_location_assignment PIN_9 -to Z80_ADDR[4]
set_location_assignment PIN_10 -to Z80_ADDR[5]
set_location_assignment PIN_11 -to Z80_ADDR[6]
set_location_assignment PIN_15 -to Z80_ADDR[7]
set_location_assignment PIN_16 -to Z80_ADDR[8]
set_location_assignment PIN_17 -to Z80_ADDR[9]
set_location_assignment PIN_18 -to Z80_ADDR[10]
set_location_assignment PIN_20 -to Z80_ADDR[11]
set_location_assignment PIN_21 -to Z80_ADDR[12]
set_location_assignment PIN_22 -to Z80_ADDR[13]
set_location_assignment PIN_24 -to Z80_ADDR[14]
set_location_assignment PIN_25 -to Z80_ADDR[15]

# Z80 Data Bus
# ============
set_location_assignment PIN_27 -to Z80_DATA[0]
set_location_assignment PIN_28 -to Z80_DATA[1]
set_location_assignment PIN_29 -to Z80_DATA[2]
set_location_assignment PIN_30 -to Z80_DATA[3]
set_location_assignment PIN_31 -to Z80_DATA[4]
set_location_assignment PIN_33 -to Z80_DATA[5]
set_location_assignment PIN_34 -to Z80_DATA[6]
set_location_assignment PIN_35 -to Z80_DATA[7]

# Z80 Control signals.
# ====================
set_location_assignment PIN_36 -to Z80_M1n
set_location_assignment PIN_37 -to Z80_RDn
set_location_assignment PIN_39 -to Z80_WRn
set_location_assignment PIN_40 -to Z80_IORQn
set_location_assignment PIN_41 -to Z80_MREQn
set_location_assignment PIN_44 -to Z80_INT
set_location_assignment PIN_45 -to Z80_EXWAITn

# Mode Select
# ===========
set_location_assignment PIN_49 -to MODE[0]
set_location_assignment PIN_48 -to MODE[1]
set_location_assignment PIN_50 -to MODE[2]

# Inverted Data Bus
# =================
set_location_assignment PIN_74 -to ID[0]
set_location_assignment PIN_73 -to ID[1]
set_location_assignment PIN_70 -to ID[2]
set_location_assignment PIN_69 -to ID[3]
set_location_assignment PIN_68 -to ID[4]
set_location_assignment PIN_67 -to ID[5]
set_location_assignment PIN_65 -to ID[6]
set_location_assignment PIN_64 -to ID[7]

# FDC Control Signals
# ===================
set_location_assignment PIN_63 -to FDCn
set_location_assignment PIN_61 -to INTRQ
set_location_assignment PIN_60 -to DRQ
set_location_assignment PIN_58 -to DDENn
set_location_assignment PIN_57 -to SIDE1
set_location_assignment PIN_56 -to MOTOR
set_location_assignment PIN_55 -to DRVSAn
set_location_assignment PIN_54 -to DRVSBn
set_location_assignment PIN_52 -to DRVSCn
set_location_assignment PIN_51 -to DRVSDn

# Memory Control Signals
# ======================
set_location_assignment PIN_80 -to ROM_A10
set_location_assignment PIN_79 -to RAM_A10
set_location_assignment PIN_77 -to ROM_CSn
set_location_assignment PIN_76 -to RAM_CSn
set_location_assignment PIN_75 -to RSV

# Clocks
# ======
set_location_assignment PIN_81 -to CLK_FDC
set_location_assignment PIN_83 -to CLK_16M
set_location_assignment PIN_2 -to CLK_BUS0

set_global_assignment -name VHDL_FILE ../sfd700_Toplevel.vhd
set_global_assignment -name VHDL_FILE ../sfd700_pkg.vhd
set_global_assignment -name VHDL_FILE ../sfd700.vhd
set_global_assignment -name SDC_FILE sfd700_constraints.sdc

set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF

set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF
set_global_assignment -name AUTO_LCELL_INSERTION ON

set_global_assignment -name CDF_FILE output_files/sfd700.cdf

set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
