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Updates and bug fixes. DASM fix still outstanding

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This commit is contained in:
Philip Smart
2026-01-07 09:17:16 +00:00
parent a0bcabb125
commit 517ee7cf88
29 changed files with 1838 additions and 1111 deletions
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21
asm/include/macros.asm
View File

@@ -46,13 +46,21 @@ HWSEL1: LD A,(BNKCTRLRST)
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
ENDIF ; 22 bytes.
; MODE_MZ1200 0
; MODE_MZ80A 0
; MODE_MZ700 1
; MODE_MZ80B 2
; MODE_MZ800 3
; MODE_MZ1500 4
; MODE_MZ2000 5
; MODE_MZ2200 6
IF BUILD_SFD700 = 1
IN A,(SFD700_MODE)
OR A
LD A,BNKDEFMROM_MZ80A ; Setup default MROM for an MZ80A, this is a 4K Window into the UROM at F000.
JR HWSEL11
HWSEL11: LD A,BNKDEFMROM_MZ700 ; Setup default MROM for an MZ700, this is a 4K Window into the UROM at F000.
OUT (REG_FXXX),A
JR Z, HWSEL11
LD A,BNKDEFMROM_MZ700 ; Setup default MROM for an MZ700, this is a 4K Window into the UROM at F000.
HWSEL11: OUT (REG_FXXX),A
LD (ROMBK1),A
LD A,BNKDEFUROM ; Setup default UROM, this is a 2K Window into the UROM at E800 and contains the RFS.
OUT (REG_EXXX),A
@@ -60,6 +68,7 @@ HWSEL11: LD A,BNKDEFMROM_MZ700 ; Setup default MROM
NOP
ENDIF
ENDM
HWSELROM2: MACRO
IF BUILD_ROMDISK = 1
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
@@ -81,7 +90,7 @@ HWSEL2: LD A,(BNKCTRLRST)
IN A,(SFD700_MODE)
OR A
LD A,BNKDEFMROM_MZ80A ; Setup default MROM for an MZ80A, this is a 4K Window into the UROM at F000.
JR HWSEL21
JR Z,HWSEL21
LD A,BNKDEFMROM_MZ700 ; Setup default MROM for an MZ700, this is a 4K Window into the UROM at F000.
HWSEL21: OUT (REG_FXXX),A
LD A,BNKDEFUROM ; Setup default UROM, this is a 2K Window into the UROM at E800 and contains the RFS.
@@ -118,10 +127,10 @@ BNKSWSEL: MACRO
LD (BNKSELUSER),A
ENDIF
IF BUILD_SFD700 = 1
OUT (REG_EXXX),A ; Execute active bank switch.
OUT (REG_EXXX),A ; Execute active bank switch for E000:EFFF.
CP ROMBANK6 ; ROMBANK6/7 page in ROM from E300:FFFF
JR C,BNKSWJMP
INC A
INC A ; FXXX are 4K banks, EXXX are 2K banks.
JR BNKSWJMP2
BNKSWJMP: LD A,(ROMBK1) ; All other banks place the current active ROM into F000:FXXX space.
BNKSWJMP2: OUT (REG_FXXX),A

21
asm/include/msbasic_definitions.asm
View File

@@ -48,7 +48,7 @@
; BASIC_build.asm which configures the equates below for the correct build.
BUILD_KUMA EQU 1 ; Enable support for Kuma 40/80 column upgrade.
; NZ-80A Build
; MZ-80A Build
IF BUILD_VERSION = 0
BUILD_MZ80A EQU 1 ; Build for the standard Sharp MZ80A, no lower memory. Manually change MAXMEM above.
BUILD_RFS EQU 0 ; Build for standard RFS with SD enhancements.
@@ -124,6 +124,11 @@ CTAPESAVE EQU 4
; Debugging
ENADEBUG EQU 0 ; Enable debugging logic, 1 = enable, 0 = disable
; RFS ROM addresses.
UROMADDR EQU 0E800H ; Start of User ROM Address space.
UROMBSTBL EQU UROMADDR + 020H ; Entry point to the bank switching table.
RFSJMPTABLE EQU UROMADDR + 000B0H ; Start of jump table.
;-----------------------------------------------
; CMT Object types.
;-----------------------------------------------
@@ -151,13 +156,13 @@ QVRFY EQU 0002Dh
;-------------------------------------------------------
; Function entry points in the RFS ROM.
;-------------------------------------------------------
CMT_RDINF EQU 0E886H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU 0E889H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU 0E88CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU 0E88FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU 0E892H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU 0E895H ; UROMADDR+95H - SD directory command.
CNV_ATOS EQU 0E898H ; UROMADDR+98H - Convert an ASCII string into Sharp ASCII
CMT_RDINF EQU RFSJMPTABLE + 06H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU RFSJMPTABLE + 09H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU RFSJMPTABLE + 0CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU RFSJMPTABLE + 0FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU RFSJMPTABLE + 12H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU RFSJMPTABLE + 15H ; UROMADDR+95H - SD directory command.
CNV_ATOS EQU RFSJMPTABLE + 18H ; UROMADDR+98H - Convert an ASCII string into Sharp ASCII
;-----------------------------------------------
; BASIC ERROR CODE VALUES

14
asm/include/rfs_definitions.asm
View File

@@ -19,6 +19,9 @@
;- March 2021- Updates to accommodate the RFS v2.1 board along with back porting TZFS
;- developments.
;- May 2023 - Updates to accommodate RFS use on a FusionX board.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -62,7 +65,7 @@ FDCROMADDR EQU 0F000H
IF BUILD_SFD700 = 1
BNKDEFMROM_MZ80A EQU 0 ; Default MROM (FDC) selected, 1st 4k slot..
BNKDEFMROM_MZ700 EQU 1 ; Default MROM (FDC) selected, 1st 4k slot..
BNKDEFMROM_MZ700 EQU 1 ; Default MROM (FDC) selected, 2nd 4k slot..
BNKDEFUROM EQU 2 ; Default UROM (RFS) selected, starts at 8K.
ENDIF
@@ -373,7 +376,12 @@ MROMLOAD: EQU MROMJMPTBL + 00006H
; 8-15 are reserved for CPM code in
; the User ROM bank.
;-----------------------------------------------
MROMPAGES EQU 8
IF BUILD_ROMDISK = 1
MROMPAGES EQU 8
ENDIF
IF BUILD_SFD700 = 1
MROMPAGES EQU 12 ; 10 Pages (8 but Bank6/7 are 2 pages) + 2 pages for ROMs
ENDIF
USRROMPAGES EQU 12 ; Monitor ROM : User ROM
IF BUILD_ROMDISK = 1
ROMBANK0 EQU 0 ; MROM SA1510 40 Char : RFS Bank 0 - Main RFS Entry point and functions.
@@ -398,7 +406,7 @@ ROMBANK4 EQU 4 + BNKDEFUROM ;
ROMBANK5 EQU 5 + BNKDEFUROM ; : RFS Bank 5
ROMBANK6 EQU 6 + BNKDEFUROM ; : RFS Bank 6
ROMBANK7 EQU 8 + BNKDEFUROM ; : RFS Bank 7 - Memory and timer test utilities.
ROMBANK8 EQU 10 + BNKDEFUROM ; : CBIOS Bank 1 - Utilities
ROMBANK8 EQU 10 + BNKDEFUROM ; : CBIOS Bank 1 - Utilities
ROMBANK9 EQU 11 + BNKDEFUROM ; : CBIOS Bank 2 - Screen / ANSI Terminal
ROMBANK10 EQU 12 + BNKDEFUROM ; : CBIOS Bank 3 - SD Card
ROMBANK11 EQU 13 + BNKDEFUROM ; : CBIOS Bank 4 - Floppy disk controller.

534
asm/mz-1e05.asm Normal file
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@@ -0,0 +1,534 @@
; V1.10
;
; To compile use:
;
; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor.
;
; Available from:
; - http://www.falstaff.demon.co.uk/cross.html
; - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip
; - and many Simtel mirrors.
;
; as80 -i -l -n -x2 -v -z mz-1e05.asm
; Bring in additional resources.
INCLUDE "rfs_definitions.asm"
INCLUDE "macros.asm"
;
;----< MFM Minifloppy control >----
;
;
; Call condition
;
; Case of disk initialize
; Drive N = IX+0 (0 - 3)
;
;
; Case of sequential read & write
; Drive N = IX+0 (0 - 3)
;
; Sector addrs = IX+1,2 (0 - $045F) H C S
; (0 - 1119) -> 70 x 16 sectors -> 2 x 35 x 16
; Byte size = IX+3,4
; Address = IX+5,6
; Next track = IX+7
; Next sector = IX+8
; Start track = IX+9
; Start sector = IX+10
;
;
; I/O Port address
;
;
; Subroutine work
;
BPRO EQU 0CF00H
BUF EQU 011A3H
BPARA EQU BPRO - 23 ; BootPARAmeter
CMD EQU BPARA + 11 ; CoMmanD
MTFG EQU CMD + 1 ; MoTorFlaG
CLBF0 EQU MTFG + 1
CLBF1 EQU CLBF0 + 1
CLBF2 EQU CLBF1 + 1
CLBF3 EQU CLBF2 + 1
VRFCNT EQU CLBF3 + 1 ; VeRiFyCouNT
STAFG EQU VRFCNT + 1 ; STAtusFlaG
;
;
;--------< Ercode map >--------
;
; 50 : Not ready
; 41 : Data error
; Track 80 err
; Write protect err
; Seek err
; CRC err
; Lost data
; 54 : Unformat
; Recode not found
; 56 : Invalid data
;
;
ORG 0F000H
MZ_1E05: NOP
LD HL,000ADH
JR L_F007
FDX: EX (SP),HL
L_F007: LD (BPARA + 21),HL
XOR A
LD DE,0
CALL ?TMST
CALL FDCC ; FD i/o check
JP NZ,NOTIO
LD DE,BPARA ; destination address
LD HL,BOOT ; source address
LD BC,11 ; 11 bytes
LDIR ; copy
SJP: LD IX,BPARA
CALL BREAD ; read from drive 0, sector 0,
;
LD HL,BPRO ; compare this address
LD DE,IPLMC ; with the IPL MasterCode
LD B,7 ; this are 7 bytes : 3,'IPLPRO'
MCHECK: LD C,(HL)
LD A,(DE)
CP C
JP NZ,MASTE ; not equal than MasterError
INC HL
INC DE
DJNZ MCHECK
; else Master was found
LD DE,IPLM0 ; 'IPL IS LOADING'
RST 018H
LD DE,BPRO + 7 ; NAME
RST 018H
LD HL,(BPRO + 016H) ; TARGETADDRESS from BootBlock
LD A,H
OR L
JR NZ,L_F051 ; if it is != 0 than normal file
LD HL,(BPRO + 018H) ; TARGETADDRESS from BootBlock
LD A,H
OR L
JR Z,L_F057 ; if it is also 0 than ROM replace file
L_F051: XOR A ; else normal file,
LD HL,(BPRO + 018H) ; TARGETADDRESS from BootBlock
JR L_F05C
L_F057: LD A,0FFH ; target is at $0000, bankswitching is needed
LD HL,01200H ; for now use temporary buffer at $1200
L_F05C: LD (0CEFDH),A
LD (IX + 5),L ; set the TargetAddress
LD (IX + 6),H
LD HL,(BPRO + 014H) ; BYTE SIZE from BootBlock
LD (IX + 3),L
LD (IX + 4),H
LD HL,(BPRO + 01EH) ; START SECTOR from BootBlock
LD (IX + 1),L
LD (IX + 2),H
;
CALL BREAD
CALL MOFF
LD A,(0CEFDH)
CP 0FFH
JR NZ,L_F093
OUT (0E0H),A
LD HL,01200H ; SourceAddress
LD DE,(BPRO + 016H) ; TargetAddress
LD BC,(BPRO + 014H) ; ByteCounter
LDIR ; copy
L_F093: LD BC,00200H ; Default code
LD HL,(BPRO + 018H) ; TARGET/EXECUTION ADDRESS from BootBlock
JP (HL)
MASTE: CALL MOFF
LD DE,ERRM1 ; 'NOT MASTER'
JR ERRTR1
ERRTRT: CP 50
NOTIO: LD DE,IPLM3 ; 'MAKE READY FD'
JR Z,ERRTR1
LD DE,ERRM0 ; 'FD:LOADING ERROR'
ERRTR1: CALL 00009H
RST 018H
LD SP,010EEH
LD HL,(BPARA + 21)
EX (SP),HL
RET
;
;
; PARAMETER SETTING
;
IPLMC: DB 003H ; IPL MASTER FLAG
DB "IPLPRO"
BOOT: DB 000H ; DRIVE NO.
DW 00000H ; SECTOR ADDR.
DW 00100H ; IFM BYTE SIZE
DW BPRO ; IFM LOADING ADDR.
DW 00000H ; IX+7,8 (track 0, sector 0)
ERRM1: DB "FD:NOT MASTER",00DH
IPLM0: DB "IPL IS LOADING ",00DH
IPLM3: DB "MAKE READY FD",00DH
ERRM0: DB "FD:LOADING ERROR",00DH
FDCC: LD A,0A5H
LD B,A
OUT (FDC_TRACK),A
CALL DLY80U
IN A,(FDC_TRACK)
CP B
RET
L_F111: DB 000H, 000H
;
;
; READY CHECK
;
READY: LD A,(MTFG)
RRCA
CALL NC,MTON
LD A,(IX + 0) ; DRIVE NO SET
OR 084H
OUT (FDC_DRIVE),A ; DRIVE SELECT MOTON
XOR A
LD (CMD),A
CALL DLY60M
LD HL,0
REDY0: DEC HL
LD A,H
OR L
JR Z,REDY1
IN A,(FDC_CMD) ; STATUS GET
CPL
RLCA
JR C,REDY0
LD C,(IX + 0)
LD HL,CLBF0
LD B,000H
ADD HL,BC
BIT 0,(HL)
JR NZ,REDY2
CALL RCLB
SET 0,(HL)
REDY2: RET
REDY1: LD A,032H
JP ERJMP
;
;
; MOTOR ON
;
MTON: LD A,080H
OUT (FDC_DRIVE),A
LD B,16
MTD1: CALL DLY60M
DJNZ MTD1
LD A,1
LD (MTFG),A
RET
;
;
; SEEK TREATMENT
;
SEEK: LD A,01BH ; 1x = SEEK,
CALL CMDOT1 ; load head, no verify, max stepping rate
AND 099H
RET
;
;
; MOTOR OFF
;
MOFF: PUSH AF
CALL DLY1M ; 1000 US DELAY
XOR A
OUT (FDC_DRIVE),A
LD (CLBF0),A
LD (CLBF1),A
LD (CLBF2),A
LD (CLBF3),A
LD (MTFG),A
POP AF
RET
;
;
; RECALIBRATION
;
RCLB: LD A,00BH ; 0x = RESTORE (seek track 0)
CALL CMDOT1 ; load head, no verify, max stepping rate
AND 085H
XOR 004H
RET Z
L_F189: JP ERRORX
;
;
; COMMAND OUT ROUTINE
;
CMDOT1: LD (CMD),A
CPL
OUT (FDC_CMD),A
CALL BSYON
CALL DLY60M
IN A,(FDC_CMD)
CPL
LD (STAFG),A
RET
;
;
; BUSY AND WAIT
;
BSYON: PUSH DE
PUSH HL
CALL BSY0
BSYON2: LD HL,00000H
BSYON0: DEC HL
LD A,H
OR L
JR Z,BSYON1
IN A,(FDC_CMD)
RRCA
JR NC,BSYON0
POP HL
POP DE
RET
;
BSYON1: DEC E
JR NZ,BSYON2
BSYONE: LD A,029H
POP HL
POP DE
JP ERJMP
;
BSYOFF: PUSH DE
PUSH HL
CALL BSY0
BSYOF2: LD HL,00000H
BSYOF0: DEC HL
LD A,H
OR L
JR Z,BSYOF1
IN A,(FDC_CMD) ; Status Register
RRCA
JR C,BSYOF0
POP HL
POP DE
RET
;
BSYOF1: DEC E
JR NZ,BSYOF2
JR BSYONE
;
BSY0: CALL DLY80U
LD E,007H
RET
;
;
; SEQUENTIAL READ
;
BREAD: CALL CNVRT
CALL PARST1 ; HL = IX + 5,6 (TargetAddress)
RE8: CALL SIDST
CALL SEEK
JP NZ,ERJMP
CALL PARST2 ; C = DataRegister
DI ; disable interrupts
LD A,094H ; 9x = READ SECTOR, multiple records
CALL CMDOT2 ; compare for side 0, 15ms delay,
RE6: ; disable side select compare
LD B,0 ; ByteCounter = 0, to load 256 bytes of the sector
RE4: IN A,(FDC_CMD)
RRCA
JR C,RE3
RRCA
JR C,RE4
INI ; (HL) = in(C), B = B - 1 , HL = HL + 1
JR NZ,RE4
INC (IX + 8) ; NextSector = NextSector + 1
LD A,(IX + 8)
CP 011H ; if NextSector = 17
JR Z,L_F213 ; than end
DEC D ; else SectorCounter = SectorCounter - 1
JR NZ,RE6 ; if SectorCounter = 0
JR L_F214 ; than end
L_F213: DEC D
L_F214: CALL INTER
RE3: EI ; enable interrupts
IN A,(FDC_CMD)
CPL
LD (STAFG),A
AND 0FFH
JR NZ,ERRORX
CALL ADJ ; adjust sector and track
JP Z,REND
LD A,(IX + 7) ; track
JR RE8
REND: LD A,080H
OUT (FDC_DRIVE),A ; motor on
RET
;
;
; PARAMETER SET
;
;
PARST1: CALL READY
LD D,(IX + 4) ; D = bytes to read (highbyte) (256 bytes)
LD A,(IX + 3) ; A = bytes to read (lowbyte)
OR A ; if A = 0
JR Z,L_F23F ; than it's ok
INC D ; else read 256 bytes more (1 sector)
L_F23F: LD A,(IX + 10) ; NextSector = StartSector
LD (IX + 8),A
LD A,(IX + 9) ; NextTrack = StartTrack
LD (IX + 7),A
LD L,(IX + 5) ; HL = TargetAddress
LD H,(IX + 6)
RET
;
;
; SIZE SEEK SET
;
SIDST: SRL A
CPL
OUT (FDC_DATA),A
JR NC,L_F25D ; NC than Head 0
LD A,1 ; else Head 1
JR L_F25E
L_F25D: XOR A
L_F25E: CPL
OUT (FDC_SIDE),A ; set HeadSelect
RET
;
;
; TRACK & SECTOR SET
;
PARST2: LD C,FDC_DATA
LD A,(IX + 7) ; A = NextTrack
SRL A
CPL
OUT (FDC_TRACK),A
LD A,(IX + 8) ; A = NextSector
CPL
OUT (FDC_SECTOR),A
RET
;
;
; ADJUST SECT & TRACK
;
ADJ: LD A,(IX + 8) ; A = NextSector
CP 17 ; if NextSector = 17
JR NZ,L_F282 ; than the border is not reached
LD A,001H ; else
LD (IX + 8),A ; NextSector = 1
INC (IX + 7) ; NextTrack = NextTrack + 1
L_F282: LD A,D
OR A
RET
;
;
; COMMAND OUT & WAIT
;
CMDOT2: LD (CMD),A
CPL
OUT (FDC_CMD),A
CALL BSYOFF
RET
;
;
; FORCE INTERRUPT
;
INTER: LD A,0D8H
CPL
OUT (FDC_CMD),A
CALL BSYON
RET
;
;
; STATUS CHECK
;
ERRORX: LD A,(CMD)
CP 00BH ; Restore (seek track 0)
JR Z,ERCK1
CP 01BH ; Seek
JR Z,ERCK1
CP 0F4H ; Write track
JR Z,ERCK1
LD A,(STAFG)
BIT 7,A
JR NZ,ERRET
BIT 6,A
JR NZ,ERRET1
BIT 4,A
LD A,54
JR NZ,ERJMP
JR ERRET1
ERCK1: LD A,(STAFG)
BIT 7,A
JR NZ,ERRET
ERRET1: LD A,41
JR ERJMP
ERRET: LD A,50
ERJMP: CALL MOFF
JP ERRTRT
;
;
; SECTOR TO TRACK & SECTOR CONVERT
;
CNVRT: LD B,0 ; TrackCounter = 0
LD DE,16 ; 16 sectors per track
LD L,(IX + 1) ; HL = SectorAddress
LD H,(IX + 2)
XOR A
TRANS0: SBC HL,DE ; SectorAddress - SectorPerTrack
JR C,TRANS1 ; if < 0 than ready
INC B ; else TrackCounter = TrackCounter + 1
JR TRANS0 ; next try
TRANS1: ADD HL,DE ; undo the last substraction
LD H,B
INC L ; adjust sector (sector is 1..16 and not 0..15)
LD (IX + 9),H ; set StartTrack
LD (IX + 10),L ; set StartSector
RET
;
;
; TIME DELAY ( 1m & 60m & 80u )
;
DLY80U: PUSH DE
LD DE,15
JP DLYT
DLY1M: PUSH DE
LD DE,160
JP DLYT
DLY60M: PUSH DE
LD DE,8230
DLYT: DEC DE
LD A,E
OR D
JR NZ,DLYT
POP DE
RET
ALIGN 0FFF0H
ORG 0FFF0H
DB " 84.03.14 V1.0A"

2
asm/mz80afi.asm
View File

@@ -7,7 +7,7 @@
;
; on Thursday, 06 of February 2020 at 01:38 PM
;
i ; Bring in additional resources.
; Bring in additional resources.
INCLUDE "rfs_definitions.asm"
INCLUDE "macros.asm"
SS: EQU 00089h

77
asm/rfs.asm
View File

@@ -11,20 +11,22 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: v1.0 July 2019 - Merged 2 utilities to create this compilation.
; v2.0 May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; v2.0 July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
; or without the K64 I/O processor. RFS wont use the K64 processor all
; operations are done by the Z80 under RFS.
;- v2.0 May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- v2.0 July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
;- or without the K64 I/O processor. RFS wont use the K64 processor all
;- operations are done by the Z80 under RFS.
;- v2.1 April 2021- Updates for the v2.1 RFS board.
;- v2.2 June 2023 - Updates for the Kuma 40/80 upgrade and FusionX.
;- v2.3 Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;- v2.31 Dec 2025 - Bug fixes. Disabled internal floppy control logic for SFD700 as it is not
;- needed, AFI ROM always needs to be present, especially for MZ-80A.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -49,7 +51,7 @@
ALIGN 0E300H
ENDIF
; Monitor command table. This table contains the list of recognised commands along with the
; Monitor command table (SFD700). This table contains the list of recognised commands along with the
; handler function and bank in which it is located.
;
; 7 6 5:3 2:0
@@ -80,10 +82,7 @@ CMDTABLE2: IF BUILD_SFD700 = 1
DB 'D' ; Dump Memory.
DW DUMPX
DB 000H | 000H | 008H | 001H
DB 'F' ; RFS Floppy boot code.
DW FLOPPY
DB 000H | 000H | 008H | 001H
DB 0AAH ; Original Floppy boot code.
DB 'F' ; 'F' RFS Floppy boot code.
DW FDCK
DB 000H | 000H | 030H | 001H
DB 'H' ; Help screen.
@@ -388,7 +387,7 @@ CMDCMP: XOR A ; Clear
LD HL,CMDTABLE
ENDIF
IF BUILD_SFD700 = 1
LD HL,CMDTABLE2
LD HL,CMDTABLE2 ; SFD700 Command table located in lower location.
ENDIF
CMDCMP0: LD DE,BUFER+1 ; First command byte after the * prompt.
LD A,(HL)
@@ -419,9 +418,9 @@ CMDCMP3: LD A,(HL) ; Comma
INC HL
LD H,(HL)
LD L,A
PUSH HL
PUSH HL ; Push the address of the function to be called.
LD (TMPADR),DE ; Store the key buffer location where arguments start.
LD A,C
LD A,C ; Get back command properties, ie. bank number
SRL A
SRL A
SRL A
@@ -433,7 +432,7 @@ CMDCMP3: LD A,(HL) ; Comma
LD DE,BKSW0to1 - BKSW0to0 ; DE is the number of bytes between bank switch calls.
OR A
JR Z,CMDCMP5
CMDCMP4: ADD HL,DE
CMDCMP4: ADD HL,DE ; Basically adding the bank size to the address to get ROM location.
DJNZ CMDCMP4
CMDCMP5: EX DE,HL ; Address of bank switch function into DE.
POP HL ; Get address of command into HL.
@@ -441,7 +440,7 @@ CMDCMP5: EX DE,HL ; Addre
PUSH BC ; Address to return to after command is executed.
PUSH DE ; Now jump to DE which will switch to the correct bank and execute function at HL.
LD DE,(TMPADR)
RET
RET ; Return to address in DE, which is the required bank.
CMDCMP6: LD DE,CMDCMPEND ; Put return address onto stack.
PUSH DE
LD DE,(TMPADR) ; For the current bank, just jump to the function.
@@ -461,7 +460,7 @@ CMDCMPEND: LD A,(RESULT)
LD HL,(EXADR)
JP (HL)
; Monitor command table. This table contains the list of recognised commands along with the
; Monitor command table (ROMDISK). This table contains the list of recognised commands along with the
; handler function and bank in which it is located.
;
; 7 6 5:3 2:0
@@ -501,10 +500,10 @@ CMDTABLE: IF BUILD_ROMDISK = 1
DB "EC" ; Erase file.
DW ERASESD
DB 000H | 000H | 008H | 001H
DB 'F' ; RFS Floppy boot code.
DB 'F' ; 'F' RFS Floppy boot code.
DW FLOPPY
DB 000H | 000H | 008H | 001H
DB 0AAH ; Original Floppy boot code.
DB 0AAH ; 'f' Original Floppy boot code.
DW FDCK
DB 000H | 000H | 030H | 001H
DB 'H' ; Help screen.
@@ -617,7 +616,7 @@ HIROM: IF BUILD_ROMDISK = 1
LD A, (MEMSW) ; Swap ROM into high range slot.
LD A, ROMBANK2
LD (ROMBK1),A ; Save bank being enabled.
HWSELMROM ; Switch to the hiload rom in bank 2.
HWSELMROM ; Switch to the hiload rom in bank 2.
JP 0C000H
ENDIF
@@ -874,7 +873,6 @@ PRTMZF4: OR A
POP BC
RET
; Method to list the directory of the ROM devices.
;
DIRROM: ;DI ; Disable interrupts as we are switching out the main rom.
@@ -903,7 +901,7 @@ DIRROM: ;DI ; Disab
; B = Bank Page
; C = Block in page
;
LD B,MROMPAGES ; First 8 pages are reserved in MROM bank.
LD B,MROMPAGES ; First set of pages are reserved in MROM bank.
LD C,0 ; Block in page.
;
DIRNXTPG: LD A,B
@@ -970,7 +968,7 @@ FINDMZF: PUSH DE
; C = Block in page
;
FINDMZF0: POP DE ; Get file sequence number in D.
LD B,MROMPAGES ; First 4 pages are reserved in User ROM bank.
LD B,MROMPAGES ; First set of pages are reserved in User ROM bank.
LD C,0 ; Block in page.
FINDMZF1: LD A,B
LD (WRKROMBK1), A
@@ -1051,17 +1049,18 @@ LOADROM1: ;DI
PUSH HL ; Preserve execute flag.
EX DE,HL ; User ROM expects HL to have the filename pointer.
PUSH HL ; Save pointer to filename for FINDMZF in Monitor ROM.
; D = File sequence number.
LD D,0 ; File numbering start.
;
LD A,ROMBANK3 ; Activate the RFS Utilities MROM bank.
LD (WRKROMBK1), A
HWSELMROM
CALL MFINDMZF ; Try and find the file in User ROM via MROM utility.
POP HL
JR Z,MROMLOAD0
IF BUILD_ROMDISK = 1
PUSH HL ; Save pointer to filename for FINDMZF in Monitor ROM.
LD A,ROMBANK3 ; Activate the RFS Utilities MROM bank.
LD (WRKROMBK1), A
HWSELMROM
CALL MFINDMZF ; Try and find the file in User ROM via MROM utility.
POP HL
JR Z,MROMLOAD0
ENDIF
;
CALL FINDMZF ; Find the bank and block where the file resides. HL = filename.
JR Z, LROMLOAD
@@ -1098,7 +1097,7 @@ LOADROMEND:;EI
;
LROMLOAD: PUSH BC
;
PUSH BC
PUSH BC ; Print Loading <file>
LD DE,MSGLOAD+1
LD BC,NAME
LD HL,PRINTMSG
@@ -1110,7 +1109,7 @@ LROMLOAD: PUSH BC
HWSELMROM
;
LD DE, IBUFE ; Copy the header into the work area.
LD HL, 00000h ; Add block offset to get the valid block.
LD HL, MROMSTART ; Add block offset to get the valid block.
LD A,C
IF RFSSECTSZ >= 512
RLCA
@@ -1141,7 +1140,7 @@ LROMLOAD2: LD A, B
HWSELMROM
LROMLOAD3: PUSH BC
LD HL, 00000h
LD HL, MROMSTART
LD A, C
IF RFSSECTSZ >= 512
RLCA
@@ -1483,6 +1482,10 @@ DEFAULTFNE: EQU $
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0AAh
IF BUILD_SFD700 = 1
ALIGN 0F000H
ENDIF
MEND:
;

687
asm/rfs_bank1.asm
View File

@@ -11,13 +11,16 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; Mar 2023 - Fixed Floppy bug where the driver letter entered wasnt recognised.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Mar 2023 - Fixed Floppy bug where the driver letter entered wasnt recognised.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -34,19 +37,19 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK1"
ALIGN UROMADDR
ENDIF
ENDIF
;============================================================
;
; USER ROM BANK 1 - Floppy Disk Controller functions.
;
;============================================================
ORG UROMADDR
ORG UROMADDR
;--------------------------------
; Common code spanning all banks.
@@ -136,369 +139,371 @@ FDCKROM: LD A,(0F000h)
OR A
RET
FLOPPY: PUSH DE ; Preserve pointer to input buffer.
LD DE,BPARA ; Copy disk parameter block into RAM work area. (From)
LD HL,PRMBLK ; (To)
LD BC,0000BH ; 11 bytes of config data.
LDIR ; BC=0, HL=F0E8, DE=1013
POP DE ; init 1001-1005, port $DC mit $00
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
CP 00Dh ;
JR NZ,GETBOOTDSK ;
CALL DSKINIT ; Initialise disk and flags.
L000F: LD DE,MSGBOOTDRV ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,011A3H ;
CALL GETL ;
LD A,(DE) ;
CP 01BH ; BREAK pressed?
JP Z,ST1X ;
LD HL,19 ; Check input value is in range 1-4.
ADD HL,DE ;
LD A,(HL) ;
CP 00DH ;
JR Z,L003A ;
GETBOOTDSK:CALL HEX ; Convert number to binary
JR C,L000F ; If illegal, loop back and re-prompt.
DEC A ;
CP 004H ; Check in range, if not loop back.
JR NC,L000F ;
LD (BPARA),A ; Store in parameter block.
L003A: LD IX,BPARA ; Point to drive number.,
CALL DSKREAD ; Read sector 1 of trk 0
LD HL,0CE00H ; Now compare the first 7 bytes of what was read to see if this is a bootable disk.
LD DE,DSKID ;
LD B,007H ;
L0049: LD C,(HL) ;
LD A,(DE) ;
CP C ;
JP NZ,L008C ; If NZ then this is not a master disk, ie not bootable, so error exit with message.
INC HL ;
INC DE ;
DJNZ L0049 ;
LD DE,MSGIPLLOAD ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,0CE07H ; Program name stored at 8th byte in boot sector.
LD HL,PRTFN
CALL BKSW1to6
LD HL,(0CE16H) ; Get the load address
LD (IX+005H),L ; And store in parameter block at 100D/100E
LD (IX+006H),H ;
INC HL
DEC HL
JR NZ, NOTCPM ; If load address is 0 then where loading CPM.
; LD A,(MEMSW) ; Page out ROM.
NOTCPM: LD HL,(0CE14H) ; Get the size
LD (IX+003H),L ; And store in parameter block at 100B/100C
LD (IX+004H),H ;
LD HL,(0CE1EH) ; Get logical sector number
LD (IX+001H),L ; And store in parameter block at 1009/100A
LD (IX+002H),H ;
CALL DSKREAD ; Read the required data and store in memory.
CALL DSKINIT ; Reset the disk ready for next operation.
LD HL,(0CE18H) ; Get the execution address
JP (HL) ; And execute.
FLOPPY: IF BUILD_ROMDISK = 1
PUSH DE ; Preserve pointer to input buffer.
LD DE,BPARA ; Copy disk parameter block into RAM work area. (From)
LD HL,PRMBLK ; (To)
LD BC,0000BH ; 11 bytes of config data.
LDIR ; BC=0, HL=F0E8, DE=1013
POP DE ; init 1001-1005, port $DC mit $00
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
CP 00Dh ;
JR NZ,GETBOOTDSK ;
CALL DSKINIT ; Initialise disk and flags.
L000F: LD DE,MSGBOOTDRV ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,011A3H ;
CALL GETL ;
LD A,(DE) ;
CP 01BH ; BREAK pressed?
JP Z,ST1X ;
LD HL,19 ; Check input value is in range 1-4.
ADD HL,DE ;
LD A,(HL) ;
CP 00DH ;
JR Z,L003A ;
GETBOOTDSK: CALL HEX ; Convert number to binary
JR C,L000F ; If illegal, loop back and re-prompt.
DEC A ;
CP 004H ; Check in range, if not loop back.
JR NC,L000F ;
LD (BPARA),A ; Store in parameter block.
L003A: LD IX,BPARA ; Point to drive number.,
CALL DSKREAD ; Read sector 1 of trk 0
LD HL,0CE00H ; Now compare the first 7 bytes of what was read to see if this is a bootable disk.
LD DE,DSKID ;
LD B,007H ;
L0049: LD C,(HL) ;
LD A,(DE) ;
CP C ;
JP NZ,L008C ; If NZ then this is not a master disk, ie not bootable, so error exit with message.
INC HL ;
INC DE ;
DJNZ L0049 ;
LD DE,MSGIPLLOAD ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,0CE07H ; Program name stored at 8th byte in boot sector.
LD HL,PRTFN
CALL BKSW1to6
LD HL,(0CE16H) ; Get the load address
LD (IX+005H),L ; And store in parameter block at 100D/100E
LD (IX+006H),H ;
INC HL
DEC HL
JR NZ, NOTCPM ; If load address is 0 then where loading CPM.
;LD A,(MEMSW) ; Page out ROM.
NOTCPM: LD HL,(0CE14H) ; Get the size
LD (IX+003H),L ; And store in parameter block at 100B/100C
LD (IX+004H),H ;
LD HL,(0CE1EH) ; Get logical sector number
LD (IX+001H),L ; And store in parameter block at 1009/100A
LD (IX+002H),H ;
CALL DSKREAD ; Read the required data and store in memory.
CALL DSKINIT ; Reset the disk ready for next operation.
LD HL,(0CE18H) ; Get the execution address
JP (HL) ; And execute.
DSKLOADERR:LD DE,MSGLOADERR ; Loading error message
JR L008F ; (+003h)
DSKLOADERR: LD DE,MSGLOADERR ; Loading error message
JR L008F ; (+003h)
L008C: LD DE,MSGDSKNOTMST ; This is not a boot/master disk message.
L008F: LD HL,PRINTMSG
CALL BKSW1to6
LD DE,ERRTONE ; Play error tone.
CALL MELDY
;
LD SP,(TMPSTACKP) ; Recover the correct stack pointer before exit.
RET ; JP SS
L008C: LD DE,MSGDSKNOTMST ; This is not a boot/master disk message.
L008F: LD HL,PRINTMSG
CALL BKSW1to6
LD DE,ERRTONE ; Play error tone.
CALL MELDY
;
LD SP,(TMPSTACKP) ; Recover the correct stack pointer before exit.
RET ; JP SS
L0104: LD A,(MOTON) ; motor on flag
RRCA ; motor off?
CALL NC,DSKMOTORON ; yes, set motor on and wait
LD A,(IX+000H) ;drive no
OR 084H ;
OUT (0DCH),A ; Motor on for drive 0-3
XOR A ;
LD (FDCCMD),A ; clr latest FDC command byte
LD HL,00000H ;
L0119: DEC HL ;
LD A,H ;
OR L ;
JP Z,DSKERR ; Reset and print message that this is not a bootable disk.
IN A,(0D8H) ; Status register.
CPL ;
RLCA ;
JR C,L0119 ; Wait on motor off (bit 7)
LD C,(IX+000H) ; Drive number
LD HL,TRK0FD1 ; 1 track 0 flag for each drive
LD B,000H ;
ADD HL,BC ; Compute related flag 1002/1003/1004/1005
BIT 0,(HL) ;
JR NZ,L0137 ;
CALL DSKSEEKTK0 ; Seek track 0.
SET 0,(HL) ; Set bit 0 of trk 0 flag
L0137: RET
L0104: LD A,(MOTON) ; motor on flag
RRCA ; motor off?
CALL NC,DSKMOTORON ; yes, set motor on and wait
LD A,(IX+000H) ;drive no
OR 084H ;
OUT (0DCH),A ; Motor on for drive 0-3
XOR A ;
LD (FDCCMD),A ; clr latest FDC command byte
LD HL,00000H ;
L0119: DEC HL ;
LD A,H ;
OR L ;
JP Z,DSKERR ; Reset and print message that this is not a bootable disk.
IN A,(0D8H) ; Status register.
CPL ;
RLCA ;
JR C,L0119 ; Wait on motor off (bit 7)
LD C,(IX+000H) ; Drive number
LD HL,TRK0FD1 ; 1 track 0 flag for each drive
LD B,000H ;
ADD HL,BC ; Compute related flag 1002/1003/1004/1005
BIT 0,(HL) ;
JR NZ,L0137 ;
CALL DSKSEEKTK0 ; Seek track 0.
SET 0,(HL) ; Set bit 0 of trk 0 flag
L0137: RET
; Turn disk motor on.
DSKMOTORON:LD A,080H
OUT (0DCH),A ; Motor on
LD B,010H ;
L013E: CALL L02C7 ;
DJNZ L013E ; Wait until becomes ready.
LD A,001H ; Set motor on flag.
LD (MOTON),A ;
RET
; Turn disk motor on.
DSKMOTORON: LD A,080H
OUT (0DCH),A ; Motor on
LD B,010H ;
L013E: CALL L02C7 ;
DJNZ L013E ; Wait until becomes ready.
LD A,001H ; Set motor on flag.
LD (MOTON),A ;
RET
L0149: LD A,01BH
CALL DSKCMD
AND 099H
RET
L0149: LD A,01BH
CALL DSKCMD
AND 099H
RET
; Initialise drive and reset flags, Set motor off
DSKINIT: XOR A
OUT (0DCH),A ; Motor on/off
LD (TRK0FD1),A ; Track 0 flag drive 1
LD (TRK0FD2),A ; Track 0 flag drive 2
LD (TRK0FD3),A ; Track 0 flag drive 3
LD (TRK0FD4),A ; Track 0 flag drive 4
LD (MOTON),A ; Motor on flag
RET
; Initialise drive and reset flags, Set motor off
DSKINIT: XOR A
OUT (0DCH),A ; Motor on/off
LD (TRK0FD1),A ; Track 0 flag drive 1
LD (TRK0FD2),A ; Track 0 flag drive 2
LD (TRK0FD3),A ; Track 0 flag drive 3
LD (TRK0FD4),A ; Track 0 flag drive 4
LD (MOTON),A ; Motor on flag
RET
DSKSEEKTK0:LD A,00BH ; Restore command, seek track 0.
CALL DSKCMD ; Send command to FDC.
AND 085H ; Process result.
XOR 004H
RET Z
JP DSKERR
DSKSEEKTK0: LD A,00BH ; Restore command, seek track 0.
CALL DSKCMD ; Send command to FDC.
AND 085H ; Process result.
XOR 004H
RET Z
JP DSKERR
DSKCMD: LD (FDCCMD),A ; Store latest FDC command.
CPL ; Compliment it (FDC bit value is reversed).
OUT (0D8H),A ; Send command to FDC.
CALL L017E ; Wait to become ready.
IN A,(0D8H) ; Get status register.
CPL ; Inverse (FDC is reverse bit logic).
RET
DSKCMD: LD (FDCCMD),A ; Store latest FDC command.
CPL ; Compliment it (FDC bit value is reversed).
OUT (0D8H),A ; Send command to FDC.
CALL L017E ; Wait to become ready.
IN A,(0D8H) ; Get status register.
CPL ; Inverse (FDC is reverse bit logic).
RET
L017E: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L0185: LD HL,00000H
L0188: DEC HL
LD A,H
OR L
JR Z,L0196 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR C,L0188 ; (-00bh)
POP HL
POP DE
RET
L017E: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L0185: LD HL,00000H
L0188: DEC HL
LD A,H
OR L
JR Z,L0196 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR C,L0188 ; (-00bh)
POP HL
POP DE
RET
L0196: DEC E
JR NZ,L0185 ; (-014h)
JP DSKERR
L0196: DEC E
JR NZ,L0185 ; (-014h)
JP DSKERR
L019C: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L01A3: LD HL,00000H
L01A6: DEC HL
LD A,H
OR L
JR Z,L01B4 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR NC,L01A6 ; (-00bh)
POP HL
POP DE
RET
L019C: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L01A3: LD HL,00000H
L01A6: DEC HL
LD A,H
OR L
JR Z,L01B4 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR NC,L01A6 ; (-00bh)
POP HL
POP DE
RET
L01B4: DEC E
JR NZ,L01A3 ; (-014h)
JP DSKERR
L01B4: DEC E
JR NZ,L01A3 ; (-014h)
JP DSKERR
; Read disk starting at the first logical sector in param block 1009/100A
; Continue reading for the given size 100B/100C and store in the location
; Pointed to by the address stored in the parameter block. 100D/100E
DSKREAD: CALL L0220 ; Compute logical sector-no to track-no & sector-no, retries=10
L01BD: CALL L0229 ; Set current track & sector, get load address to HL
L01C0: CALL L0249 ; Set side reg
CALL L0149 ; Command 1b output (seek)
JR NZ,L0216 ;
CALL L0259 ; Set track & sector reg
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As below. L03FE
LD IY,L01DF ; Read sector into memory.
;DI
LD A,094H ; Latest FDC command byte
CALL L028A
L01DB: LD B,000H
JP (IX)
; Read disk starting at the first logical sector in param block 1009/100A
; Continue reading for the given size 100B/100C and store in the location
; Pointed to by the address stored in the parameter block. 100D/100E
DSKREAD: CALL L0220 ; Compute logical sector-no to track-no & sector-no, retries=10
L01BD: CALL L0229 ; Set current track & sector, get load address to HL
L01C0: CALL L0249 ; Set side reg
CALL L0149 ; Command 1b output (seek)
JR NZ,L0216 ;
CALL L0259 ; Set track & sector reg
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As below. L03FE
LD IY,L01DF ; Read sector into memory.
;DI
LD A,094H ; Latest FDC command byte
CALL L028A
L01DB: LD B,000H
JP (IX)
; Get data from disk sector to staging area (CE00).
L01DF: INI
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
JP NZ, 0F3FEH ; This is crucial, as the Z80 is running at 2MHz it is not fast enough so needs
; Get data from disk sector to staging area (CE00).
L01DF: INI
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
JP NZ, 0F3FEH ; This is crucial, as the Z80 is running at 2MHz it is not fast enough so needs
; hardware acceleration in the form of a banked ROM, if disk not ready jumps to IX, if
; data ready, jumps to IY. L03FE
POP IX
INC (IX+008H) ; Increment current sector number
LD A,(IX+008H) ; Load current sector number
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As above. L03FE
CP 011H ; Sector 17? Need to loop to next track.
JR Z,L01FB
DEC D
JR NZ,L01DB
JR L01FC ; (+001h)
POP IX
INC (IX+008H) ; Increment current sector number
LD A,(IX+008H) ; Load current sector number
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As above. L03FE
CP 011H ; Sector 17? Need to loop to next track.
JR Z,L01FB
DEC D
JR NZ,L01DB
JR L01FC ; (+001h)
L01FB: DEC D
L01FC: CALL L0294
CALL L02D2
POP IX
IN A,(0D8H)
CPL
AND 0FFH
JR NZ,L0216 ; (+00bh)
CALL L0278
JP Z,L021B
LD A,(IX+007H)
JR L01C0 ; (-056h)
L01FB: DEC D
L01FC: CALL L0294
CALL L02D2
POP IX
IN A,(0D8H)
CPL
AND 0FFH
JR NZ,L0216 ; (+00bh)
CALL L0278
JP Z,L021B
LD A,(IX+007H)
JR L01C0 ; (-056h)
L0216: CALL L026A
JR L01BD ; (-05eh)
L0216: CALL L026A
JR L01BD ; (-05eh)
L021B: LD A,080H
OUT (0DCH),A ; Motor on
RET
L021B: LD A,080H
OUT (0DCH),A ; Motor on
RET
L0220: CALL L02A3 ; compute logical sector no to track no & sector no
LD A,00AH ; 10 retries
LD (RETRIES),A
RET
L0220: CALL L02A3 ; compute logical sector no to track no & sector no
LD A,00AH ; 10 retries
LD (RETRIES),A
RET
; Set current track & sector, get load address to HL
L0229: CALL L0104
LD D,(IX+004H) ; Number of sectors to read
LD A,(IX+003H) ; Bytes to read
OR A ; 0?
JR Z,L0236 ; Yes
INC D ; Number of sectors to read + 1
L0236: LD A,(IX+00AH) ; Start sector number
LD (IX+008H),A ; To current sector number
LD A,(IX+009H) ; Start track number
LD (IX+007H),A ; To current track number
LD L,(IX+005H) ; Load address low byte
LD H,(IX+006H) ; Load address high byte
RET
; Set current track & sector, get load address to HL
L0229: CALL L0104
LD D,(IX+004H) ; Number of sectors to read
LD A,(IX+003H) ; Bytes to read
OR A ; 0?
JR Z,L0236 ; Yes
INC D ; Number of sectors to read + 1
L0236: LD A,(IX+00AH) ; Start sector number
LD (IX+008H),A ; To current sector number
LD A,(IX+009H) ; Start track number
LD (IX+007H),A ; To current track number
LD L,(IX+005H) ; Load address low byte
LD H,(IX+006H) ; Load address high byte
RET
; Compute side/head.
L0249: SRL A ; Track number even?
CPL ;
OUT (0DBH),A ; Output track no.
JR NC,L0254 ; Yes, even, set side/head 1
LD A,001H ; No, odd, set side/head 0
JR L0255
; Compute side/head.
L0249: SRL A ; Track number even?
CPL ;
OUT (0DBH),A ; Output track no.
JR NC,L0254 ; Yes, even, set side/head 1
LD A,001H ; No, odd, set side/head 0
JR L0255
; Set side/head register.
L0254: XOR A ; Side 0
L0255: CPL ; Side 1
OUT (0DDH),A ; Side/head register.
RET
; Set side/head register.
L0254: XOR A ; Side 0
L0255: CPL ; Side 1
OUT (0DDH),A ; Side/head register.
RET
; Set track and sector register.
L0259: LD C,0DBH
LD A,(IX+007H) ; Current track number
SRL A
CPL
OUT (0D9H),A ; Track reg
LD A,(IX+008H) ; Current sector number
CPL
OUT (0DAH),A ; Sector reg
RET
; Set track and sector register.
L0259: LD C,0DBH
LD A,(IX+007H) ; Current track number
SRL A
CPL
OUT (0D9H),A ; Track reg
LD A,(IX+008H) ; Current sector number
CPL
OUT (0DAH),A ; Sector reg
RET
L026A: LD A,(RETRIES)
DEC A
LD (RETRIES),A
JP Z,DSKERR
CALL DSKSEEKTK0
RET
L026A: LD A,(RETRIES)
DEC A
LD (RETRIES),A
JP Z,DSKERR
CALL DSKSEEKTK0
RET
L0278: LD A,(IX+008H)
CP 011H
JR NZ,L0287 ; (+008h)
LD A,001H
LD (IX+008H),A
INC (IX+007H)
L0287: LD A,D
OR A
RET
L0278: LD A,(IX+008H)
CP 011H
JR NZ,L0287 ; (+008h)
LD A,001H
LD (IX+008H),A
INC (IX+007H)
L0287: LD A,D
OR A
RET
L028A: LD (FDCCMD),A
CPL
OUT (0D8H),A
CALL L019C
RET
L028A: LD (FDCCMD),A
CPL
OUT (0D8H),A
CALL L019C
RET
L0294: LD A,0D8H
CPL
OUT (0D8H),A
CALL L017E
RET
L0294: LD A,0D8H
CPL
OUT (0D8H),A
CALL L017E
RET
DSKERR: CALL DSKINIT
JP DSKLOADERR
DSKERR: CALL DSKINIT
JP DSKLOADERR
; Logical sector number to physical track and sector.
L02A3: LD B,000H
LD DE,00010H ; No of sectors per trk (16)
LD L,(IX+001H) ; Logical sector number
LD H,(IX+002H) ; 2 bytes in length
XOR A
L02AF: SBC HL,DE ; Subtract 16 sectors/trk
JR C,L02B6 ; Yes, negative value
INC B ; Count track
JR L02AF ; Loop
L02B6: ADD HL,DE ; Reset HL to the previous
LD H,B ; Track
INC L ; Correction +1
LD (IX+009H),H ; Start track no
LD (IX+00AH),L ; Start sector no
RET
; Logical sector number to physical track and sector.
L02A3: LD B,000H
LD DE,00010H ; No of sectors per trk (16)
LD L,(IX+001H) ; Logical sector number
LD H,(IX+002H) ; 2 bytes in length
XOR A
L02AF: SBC HL,DE ; Subtract 16 sectors/trk
JR C,L02B6 ; Yes, negative value
INC B ; Count track
JR L02AF ; Loop
L02B6: ADD HL,DE ; Reset HL to the previous
LD H,B ; Track
INC L ; Correction +1
LD (IX+009H),H ; Start track no
LD (IX+00AH),L ; Start sector no
RET
L02C0: PUSH DE
LD DE,00007H
JP L02CB
L02C0: PUSH DE
LD DE,00007H
JP L02CB
L02C7: PUSH DE
LD DE,01013H
L02CB: DEC DE
LD A,E
OR D
JR NZ,L02CB ; (-005h)
POP DE
RET
L02C7: PUSH DE
LD DE,01013H
L02CB: DEC DE
LD A,E
OR D
JR NZ,L02CB ; (-005h)
POP DE
RET
L02D2: PUSH AF
LD A,(0119CH)
CP 0F0H
JR NZ,L02DB ; (+001h)
;EI
L02DB: POP AF
RET
L02D2: PUSH AF
LD A,(0119CH)
CP 0F0H
JR NZ,L02DB ; (+001h)
;EI
L02DB: POP AF
RET
;wait on bit 0 and bit 1 = 0 of state reg
L0300: IN A,(0D8H) ; State reg
RRCA
JR C,L0300 ; Wait on not busy
RRCA
JR C,L0300 ; Wait on data reg ready
JP (IY) ; to f1df
;wait on bit 0 and bit 1 = 0 of state reg
L0300: IN A,(0D8H) ; State reg
RRCA
JR C,L0300 ; Wait on not busy
RRCA
JR C,L0300 ; Wait on data reg ready
JP (IY) ; to f1df
ENDIF
;-------------------------------------------------------------------------------
; END OF FLOPPY DISK CONTROLLER FUNCTIONALITY

33
asm/rfs_bank2.asm
View File

@@ -11,16 +11,19 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; July 2020 - Bug fixes and additions.
; July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
; or without the K64 I/O processor. RFS wont use the K64 processor all
; operations are done by the Z80 under RFS.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- July 2020 - Bug fixes and additions.
;- July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
;- or without the K64 I/O processor. RFS wont use the K64 processor all
;- operations are done by the Z80 under RFS.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -37,9 +40,11 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN UROMADDR
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK2"
ALIGN UROMADDR
ENDIF
;===========================================================
@@ -1591,5 +1596,5 @@ SAVESD9: LD DE,MSGSVFAIL ; Fail,
ENDIF
IF BUILD_SFD700 = 1
ALIGN 0F000H
ALIGN 0F000H
ENDIF

25
asm/rfs_bank3.asm
View File

@@ -11,12 +11,15 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -38,11 +41,11 @@ COLW EQU 40
SCRNSZ EQU COLW * ROW
MODE80C EQU 0
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN UROMADDR
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK3"
ALIGN UROMADDR
ENDIF
;===========================================================

25
asm/rfs_bank4.asm
View File

@@ -11,12 +11,15 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -33,11 +36,11 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN UROMADDR
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK4"
ALIGN UROMADDR
ENDIF
;===========================================================

27
asm/rfs_bank5.asm
View File

@@ -11,13 +11,16 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; Mar 2021 - Add mapping utilities for Sharp<->ASCII conversion.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Mar 2021 - Add mapping utilities for Sharp<->ASCII conversion.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -34,11 +37,11 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN UROMADDR
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK5"
ALIGN UROMADDR
ENDIF
;======================================

36
asm/rfs_bank6.asm
View File

@@ -11,15 +11,18 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
; or without the K64 I/O processor. RFS wont use the K64 processor all
; operations are done by the Z80 under RFS.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
;- or without the K64 I/O processor. RFS wont use the K64 processor all
;- operations are done by the Z80 under RFS.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -36,11 +39,11 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN UROMADDR
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK6"
ALIGN UROMADDR
ENDIF
;======================================
@@ -319,8 +322,7 @@ HELPSCR: IF BUILD_ROMDISK = 1
DB "DXXXX[YYYY] - dump mem XXXX to YYYY.", 00DH
DB "DASMXXXX[YYYY]", 00DH
DB " disassemble XXXX to YYYY", 00DH
DB "F[X] - boot fd drive X.", 00DH
DB "f - boot fd original rom.", 00DH
DB "F - boot fd.", 00DH
DB "H - this help screen.", 00DH
DB "IR - rfs rom dir listing.", 00DH
DB "JXXXX - jump to location XXXX.", 00DH
@@ -478,7 +480,7 @@ ATBL: DB 0CCH ; NUL '\0' (null character)
;
;--------------------------------------
MSGSONTZ: DB "+ TZ" ; Version 2.x with version 2.1+ of tranZPUter board installed.
MSGSON: DB "+ RFS ", 0ABh, "2.3 **", 00DH, 000H ; Version 2.x-> as we are now using the v2.x PCB with 4 devices on-board
MSGSON: DB "+ RFS ", 0ABh, "2.31a **", 00DH, 000H ; Version 2.x-> as we are now using the v2.x PCB with 4 devices on-board
MSGNOTFND: DB "Not Found", 00DH, 000H
MSGRDIRLST: DB "ROM Directory:", 00DH, 000H
MSGTRM: DB 00DH, 000H

24
asm/rfs_bank7.asm
View File

@@ -1,6 +1,6 @@
;--------------------------------------------------------------------------------------------------------
;-
;- Name: rfs_bank4.asm
;- Name: rfs_bank7.asm
;- Created: July 2019
;- Author(s): Philip Smart
;- Description: Sharp MZ series Rom Filing System.
@@ -11,12 +11,15 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -40,11 +43,11 @@ ADDR:
ADDR_LO: DS virtual 1
ADDR_HI: DS virtual 1
ASM_ADDR: DS virtual 8 ; Assembler Destination address
ASM_BUF: DS virtual 16 ; 16 byte ASM Input Buffer
ASM_BUF: DS virtual 12 ; 16 byte ASM Input Buffer
OUT_BUF: DS virtual 4 ; 4 byte test buffer(last part of ASM_BUF)
INS_BUF: DS virtual 4 ; 4 Byte Instruction Buffer
PARM_BUF: DS virtual 7 ; 7 Byte Parm Buffer
VAL_BUF: ; 5 Byte Value Buffer
VAL_BUF: ;DS virtual 5 ; 5 Byte Value Buffer
VAL_BUF_HI: DS virtual 2 ; 2 Hi Bytes in Value Buffer
VAL_BUF_LO: DS virtual 2 ; 2 Lo Bytes in Value Buffer
DS virtual 1
@@ -59,6 +62,7 @@ ML_BUF: DS virtual 2 ; 3 byte ML buffer
ML_BTCOUNT: DS virtual 1 ; Last byte of ML buffer(byte count)
VAL_LO: DS virtual 1 ; Converted value LO
VAL_HI: DS virtual 1 ; Converted value Hi
BUF_END:
ORG 0E000H
@@ -117,7 +121,7 @@ DASM_LOOP1: CALL NL ; Print CR & LF
LD HL,ASM_BUF ; Clear ASM_BUF, INS_BUF, PARM_BUF & VAL_BUF
LD A,020H
LD B,26 ; (Set to all spaces)
LD B,BUF_END-ASM_BUF; (Set to all spaces)
DASM_FILL: LD (HL),A
INC HL
DEC B

15
asm/rfs_mrom.asm
View File

@@ -13,12 +13,15 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: Sep 2019 - Initial version.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify

24
asm/sa-5510_rfs.asm
View File

@@ -96,13 +96,23 @@ ONTYO EQU 0119FH
OCTV EQU 011A0H
RATIO EQU 011A1H
BUFER EQU 011A3H
CMT_RDINF EQU 0E886H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU 0E889H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU 0E88CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU 0E88FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU 0E892H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU 0E895H ; UROMADDR+95H - SD directory command.
PRGSTART EQU 011FDH ; Build includes the tape copy code under original build.
; RFS ROM addresses.
UROMADDR EQU 0E800H ; Start of User ROM Address space.
UROMBSTBL EQU UROMADDR + 020H ; Entry point to the bank switching table.
RFSJMPTABLE EQU UROMADDR + 000B0H ; Start of jump table.
;-------------------------------------------------------
; Function entry points in the RFS ROM.
;-------------------------------------------------------
CMT_RDINF EQU RFSJMPTABLE + 06H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU RFSJMPTABLE + 09H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU RFSJMPTABLE + 0CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU RFSJMPTABLE + 0FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU RFSJMPTABLE + 12H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU RFSJMPTABLE + 15H ; UROMADDR+95H - SD directory command.
CNV_ATOS EQU RFSJMPTABLE + 18H ; UROMADDR+98H - Convert an ASCII string into Sharp ASCII
PRGSTART EQU 011FDH ; Build includes the tape copy code under original build.
; Original build set the tape handlers to original.
IF BUILD_ORIG = 1